drivers/gpu/drm/i915/display/intel_dp_mst.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *             2014 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  21  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  22  * IN THE SOFTWARE.
  23  *
  24  */
  25
  26 #include <drm/drm_atomic.h>
  27 #include <drm/drm_atomic_helper.h>
  28 #include <drm/drm_edid.h>
  29 #include <drm/drm_fixed.h>
  30 #include <drm/drm_probe_helper.h>
  31
  32 #include "i915_drv.h"
  33 #include "i915_reg.h"
  34 #include "intel_atomic.h"
  35 #include "intel_audio.h"
  36 #include "intel_connector.h"
  37 #include "intel_crtc.h"
  38 #include "intel_ddi.h"
  39 #include "intel_de.h"
  40 #include "intel_display_driver.h"
  41 #include "intel_display_types.h"
  42 #include "intel_dp.h"
  43 #include "intel_dp_hdcp.h"
  44 #include "intel_dp_mst.h"
  45 #include "intel_dp_tunnel.h"
  46 #include "intel_dpio_phy.h"
  47 #include "intel_hdcp.h"
  48 #include "intel_hotplug.h"
  49 #include "intel_link_bw.h"
  50 #include "intel_psr.h"
  51 #include "intel_vdsc.h"
  52 #include "skl_scaler.h"
  53
  54 static int intel_dp_mst_max_dpt_bpp(const struct intel_crtc_state *crtc_state,
  55                                     bool dsc)
  56 {
  57         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
  58         const struct drm_display_mode *adjusted_mode =
  59                 &crtc_state->hw.adjusted_mode;
  60
  61         if (!intel_dp_is_uhbr(crtc_state) || DISPLAY_VER(i915) >= 20 || !dsc)
  62                 return INT_MAX;
  63
  64         /*
  65          * DSC->DPT interface width:
  66          *   ICL-MTL: 72 bits (each branch has 72 bits, only left branch is used)
  67          *   LNL+:    144 bits (not a bottleneck in any config)
  68          *
  69          * Bspec/49259 suggests that the FEC overhead needs to be
  70          * applied here, though HW people claim that neither this FEC
  71          * or any other overhead is applicable here (that is the actual
  72          * available_bw is just symbol_clock * 72). However based on
  73          * testing on MTL-P the
  74          * - DELL U3224KBA display
  75          * - Unigraf UCD-500 CTS test sink
  76          * devices the
  77          * - 5120x2880/995.59Mhz
  78          * - 6016x3384/1357.23Mhz
  79          * - 6144x3456/1413.39Mhz
  80          * modes (all the ones having a DPT limit on the above devices),
  81          * both the channel coding efficiency and an additional 3%
  82          * overhead needs to be accounted for.
  83          */
  84         return div64_u64(mul_u32_u32(intel_dp_link_symbol_clock(crtc_state->port_clock) * 72,
  85                                      drm_dp_bw_channel_coding_efficiency(true)),
  86                          mul_u32_u32(adjusted_mode->crtc_clock, 1030000));
  87 }
  88
  89 static int intel_dp_mst_bw_overhead(const struct intel_crtc_state *crtc_state,
  90                                     const struct intel_connector *connector,
  91                                     bool ssc, bool dsc, int bpp_x16)
  92 {
  93         const struct drm_display_mode *adjusted_mode =
  94                 &crtc_state->hw.adjusted_mode;
  95         unsigned long flags = DRM_DP_BW_OVERHEAD_MST;
  96         int dsc_slice_count = 0;
  97         int overhead;
  98
  99         flags |= intel_dp_is_uhbr(crtc_state) ? DRM_DP_BW_OVERHEAD_UHBR : 0;
 100         flags |= ssc ? DRM_DP_BW_OVERHEAD_SSC_REF_CLK : 0;
 101         flags |= crtc_state->fec_enable ? DRM_DP_BW_OVERHEAD_FEC : 0;
 102
 103         if (dsc) {
 104                 flags |= DRM_DP_BW_OVERHEAD_DSC;
 105                 dsc_slice_count = intel_dp_dsc_get_slice_count(connector,
 106                                                                adjusted_mode->clock,
 107                                                                adjusted_mode->hdisplay,
 108                                                                crtc_state->bigjoiner_pipes);
 109         }
 110
 111         overhead = drm_dp_bw_overhead(crtc_state->lane_count,
 112                                       adjusted_mode->hdisplay,
 113                                       dsc_slice_count,
 114                                       bpp_x16,
 115                                       flags);
 116
 117         /*
 118          * TODO: clarify whether a minimum required by the fixed FEC overhead
 119          * in the bspec audio programming sequence is required here.
 120          */
 121         return max(overhead, intel_dp_bw_fec_overhead(crtc_state->fec_enable));
 122 }
 123
 124 static void intel_dp_mst_compute_m_n(const struct intel_crtc_state *crtc_state,
 125                                      const struct intel_connector *connector,
 126                                      int overhead,
 127                                      int bpp_x16,
 128                                      struct intel_link_m_n *m_n)
 129 {
 130         const struct drm_display_mode *adjusted_mode =
 131                 &crtc_state->hw.adjusted_mode;
 132
 133         /* TODO: Check WA 14013163432 to set data M/N for full BW utilization. */
 134         intel_link_compute_m_n(bpp_x16, crtc_state->lane_count,
 135                                adjusted_mode->crtc_clock,
 136                                crtc_state->port_clock,
 137                                overhead,
 138                                m_n);
 139
 140         m_n->tu = DIV_ROUND_UP_ULL(mul_u32_u32(m_n->data_m, 64), m_n->data_n);
 141 }
 142
 143 static int intel_dp_mst_calc_pbn(int pixel_clock, int bpp_x16, int bw_overhead)
 144 {
 145         int effective_data_rate =
 146                 intel_dp_effective_data_rate(pixel_clock, bpp_x16, bw_overhead);
 147
 148         /*
 149          * TODO: Use drm_dp_calc_pbn_mode() instead, once it's converted
 150          * to calculate PBN with the BW overhead passed to it.
 151          */
 152         return DIV_ROUND_UP(effective_data_rate * 64, 54 * 1000);
 153 }
 154
 155 static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
 156                                                 struct intel_crtc_state *crtc_state,
 157                                                 int max_bpp,
 158                                                 int min_bpp,
 159                                                 struct link_config_limits *limits,
 160                                                 struct drm_connector_state *conn_state,
 161                                                 int step,
 162                                                 bool dsc)
 163 {
 164         struct drm_atomic_state *state = crtc_state->uapi.state;
 165         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 166         struct intel_dp *intel_dp = &intel_mst->primary->dp;
 167         struct drm_dp_mst_topology_state *mst_state;
 168         struct intel_connector *connector =
 169                 to_intel_connector(conn_state->connector);
 170         struct drm_i915_private *i915 = to_i915(connector->base.dev);
 171         const struct drm_display_mode *adjusted_mode =
 172                 &crtc_state->hw.adjusted_mode;
 173         int bpp, slots = -EINVAL;
 174         int max_dpt_bpp;
 175         int ret = 0;
 176
 177         mst_state = drm_atomic_get_mst_topology_state(state, &intel_dp->mst_mgr);
 178         if (IS_ERR(mst_state))
 179                 return PTR_ERR(mst_state);
 180
 181         crtc_state->lane_count = limits->max_lane_count;
 182         crtc_state->port_clock = limits->max_rate;
 183
 184         if (dsc) {
 185                 if (!intel_dp_supports_fec(intel_dp, connector, crtc_state))
 186                         return -EINVAL;
 187
 188                 crtc_state->fec_enable = !intel_dp_is_uhbr(crtc_state);
 189         }
 190
 191         mst_state->pbn_div = drm_dp_get_vc_payload_bw(&intel_dp->mst_mgr,
 192                                                       crtc_state->port_clock,
 193                                                       crtc_state->lane_count);
 194
 195         max_dpt_bpp = intel_dp_mst_max_dpt_bpp(crtc_state, dsc);
 196         if (max_bpp > max_dpt_bpp) {
 197                 drm_dbg_kms(&i915->drm, "Limiting bpp to max DPT bpp (%d -> %d)\n",
 198                             max_bpp, max_dpt_bpp);
 199                 max_bpp = max_dpt_bpp;
 200         }
 201
 202         drm_dbg_kms(&i915->drm, "Looking for slots in range min bpp %d max bpp %d\n",
 203                     min_bpp, max_bpp);
 204
 205         for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) {
 206                 int local_bw_overhead;
 207                 int remote_bw_overhead;
 208                 int link_bpp_x16;
 209                 int remote_tu;
 210
 211                 drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp);
 212
 213                 link_bpp_x16 = to_bpp_x16(dsc ? bpp :
 214                                           intel_dp_output_bpp(crtc_state->output_format, bpp));
 215
 216                 local_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, connector,
 217                                                              false, dsc, link_bpp_x16);
 218                 remote_bw_overhead = intel_dp_mst_bw_overhead(crtc_state, connector,
 219                                                               true, dsc, link_bpp_x16);
 220
 221                 intel_dp_mst_compute_m_n(crtc_state, connector,
 222                                          local_bw_overhead,
 223                                          link_bpp_x16,
 224                                          &crtc_state->dp_m_n);
 225
 226                 /*
 227                  * The TU size programmed to the HW determines which slots in
 228                  * an MTP frame are used for this stream, which needs to match
 229                  * the payload size programmed to the first downstream branch
 230                  * device's payload table.
 231                  *
 232                  * Note that atm the payload's PBN value DRM core sends via
 233                  * the ALLOCATE_PAYLOAD side-band message matches the payload
 234                  * size (which it calculates from the PBN value) it programs
 235                  * to the first branch device's payload table. The allocation
 236                  * in the payload table could be reduced though (to
 237                  * crtc_state->dp_m_n.tu), provided that the driver doesn't
 238                  * enable SSC on the corresponding link.
 239                  */
 240                 crtc_state->pbn = intel_dp_mst_calc_pbn(adjusted_mode->crtc_clock,
 241                                                         link_bpp_x16,
 242                                                         remote_bw_overhead);
 243
 244                 remote_tu = DIV_ROUND_UP(dfixed_const(crtc_state->pbn), mst_state->pbn_div.full);
 245
 246                 drm_WARN_ON(&i915->drm, remote_tu < crtc_state->dp_m_n.tu);
 247                 crtc_state->dp_m_n.tu = remote_tu;
 248
 249                 slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
 250                                                       connector->port,
 251                                                       crtc_state->pbn);
 252                 if (slots == -EDEADLK)
 253                         return slots;
 254
 255                 if (slots >= 0) {
 256                         drm_WARN_ON(&i915->drm, slots != crtc_state->dp_m_n.tu);
 257
 258                         break;
 259                 }
 260         }
 261
 262         /* We failed to find a proper bpp/timeslots, return error */
 263         if (ret)
 264                 slots = ret;
 265
 266         if (slots < 0) {
 267                 drm_dbg_kms(&i915->drm, "failed finding vcpi slots:%d\n",
 268                             slots);
 269         } else {
 270                 if (!dsc)
 271                         crtc_state->pipe_bpp = bpp;
 272                 else
 273                         crtc_state->dsc.compressed_bpp_x16 = to_bpp_x16(bpp);
 274                 drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d dsc %d\n", slots, bpp, dsc);
 275         }
 276
 277         return slots;
 278 }
 279
 280 static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
 281                                             struct intel_crtc_state *crtc_state,
 282                                             struct drm_connector_state *conn_state,
 283                                             struct link_config_limits *limits)
 284 {
 285         int slots = -EINVAL;
 286
 287         /*
 288          * FIXME: allocate the BW according to link_bpp, which in the case of
 289          * YUV420 is only half of the pipe bpp value.
 290          */
 291         slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
 292                                                      to_bpp_int(limits->link.max_bpp_x16),
 293                                                      to_bpp_int(limits->link.min_bpp_x16),
 294                                                      limits,
 295                                                      conn_state, 2 * 3, false);
 296
 297         if (slots < 0)
 298                 return slots;
 299
 300         return 0;
 301 }
 302
 303 static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
 304                                                 struct intel_crtc_state *crtc_state,
 305                                                 struct drm_connector_state *conn_state,
 306                                                 struct link_config_limits *limits)
 307 {
 308         struct intel_connector *connector =
 309                 to_intel_connector(conn_state->connector);
 310         struct drm_i915_private *i915 = to_i915(connector->base.dev);
 311         int slots = -EINVAL;
 312         int i, num_bpc;
 313         u8 dsc_bpc[3] = {};
 314         int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp;
 315         u8 dsc_max_bpc;
 316         int min_compressed_bpp, max_compressed_bpp;
 317
 318         /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */
 319         if (DISPLAY_VER(i915) >= 12)
 320                 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc);
 321         else
 322                 dsc_max_bpc = min_t(u8, 10, conn_state->max_requested_bpc);
 323
 324         max_bpp = min_t(u8, dsc_max_bpc * 3, limits->pipe.max_bpp);
 325         min_bpp = limits->pipe.min_bpp;
 326
 327         num_bpc = drm_dp_dsc_sink_supported_input_bpcs(connector->dp.dsc_dpcd,
 328                                                        dsc_bpc);
 329
 330         drm_dbg_kms(&i915->drm, "DSC Source supported min bpp %d max bpp %d\n",
 331                     min_bpp, max_bpp);
 332
 333         sink_max_bpp = dsc_bpc[0] * 3;
 334         sink_min_bpp = sink_max_bpp;
 335
 336         for (i = 1; i < num_bpc; i++) {
 337                 if (sink_min_bpp > dsc_bpc[i] * 3)
 338                         sink_min_bpp = dsc_bpc[i] * 3;
 339                 if (sink_max_bpp < dsc_bpc[i] * 3)
 340                         sink_max_bpp = dsc_bpc[i] * 3;
 341         }
 342
 343         drm_dbg_kms(&i915->drm, "DSC Sink supported min bpp %d max bpp %d\n",
 344                     sink_min_bpp, sink_max_bpp);
 345
 346         if (min_bpp < sink_min_bpp)
 347                 min_bpp = sink_min_bpp;
 348
 349         if (max_bpp > sink_max_bpp)
 350                 max_bpp = sink_max_bpp;
 351
 352         max_compressed_bpp = intel_dp_dsc_sink_max_compressed_bpp(connector,
 353                                                                   crtc_state,
 354                                                                   max_bpp / 3);
 355         max_compressed_bpp = min(max_compressed_bpp,
 356                                  to_bpp_int(limits->link.max_bpp_x16));
 357
 358         min_compressed_bpp = intel_dp_dsc_sink_min_compressed_bpp(crtc_state);
 359         min_compressed_bpp = max(min_compressed_bpp,
 360                                  to_bpp_int_roundup(limits->link.min_bpp_x16));
 361
 362         drm_dbg_kms(&i915->drm, "DSC Sink supported compressed min bpp %d compressed max bpp %d\n",
 363                     min_compressed_bpp, max_compressed_bpp);
 364
 365         /* Align compressed bpps according to our own constraints */
 366         max_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, max_compressed_bpp,
 367                                                             crtc_state->pipe_bpp);
 368         min_compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, min_compressed_bpp,
 369                                                             crtc_state->pipe_bpp);
 370
 371         slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_compressed_bpp,
 372                                                      min_compressed_bpp, limits,
 373                                                      conn_state, 1, true);
 374
 375         if (slots < 0)
 376                 return slots;
 377
 378         return 0;
 379 }
 380 static int intel_dp_mst_update_slots(struct intel_encoder *encoder,
 381                                      struct intel_crtc_state *crtc_state,
 382                                      struct drm_connector_state *conn_state)
 383 {
 384         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 385         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 386         struct intel_dp *intel_dp = &intel_mst->primary->dp;
 387         struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;
 388         struct drm_dp_mst_topology_state *topology_state;
 389         u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ?
 390                 DP_CAP_ANSI_128B132B : DP_CAP_ANSI_8B10B;
 391
 392         topology_state = drm_atomic_get_mst_topology_state(conn_state->state, mgr);
 393         if (IS_ERR(topology_state)) {
 394                 drm_dbg_kms(&i915->drm, "slot update failed\n");
 395                 return PTR_ERR(topology_state);
 396         }
 397
 398         drm_dp_mst_update_slots(topology_state, link_coding_cap);
 399
 400         return 0;
 401 }
 402
 403 static bool
 404 intel_dp_mst_dsc_source_support(const struct intel_crtc_state *crtc_state)
 405 {
 406         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
 407
 408         /*
 409          * FIXME: Enabling DSC on ICL results in blank screen and FIFO pipe /
 410          * transcoder underruns, re-enable DSC after fixing this issue.
 411          */
 412         return DISPLAY_VER(i915) >= 12 && intel_dsc_source_support(crtc_state);
 413 }
 414
 415 static int mode_hblank_period_ns(const struct drm_display_mode *mode)
 416 {
 417         return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(mode->htotal - mode->hdisplay,
 418                                                  NSEC_PER_SEC / 1000),
 419                                      mode->crtc_clock);
 420 }
 421
 422 static bool
 423 hblank_expansion_quirk_needs_dsc(const struct intel_connector *connector,
 424                                  const struct intel_crtc_state *crtc_state,
 425                                  const struct link_config_limits *limits)
 426 {
 427         const struct drm_display_mode *adjusted_mode =
 428                 &crtc_state->hw.adjusted_mode;
 429         bool is_uhbr_sink = connector->mst_port &&
 430                             drm_dp_128b132b_supported(connector->mst_port->dpcd);
 431         int hblank_limit = is_uhbr_sink ? 500 : 300;
 432
 433         if (!connector->dp.dsc_hblank_expansion_quirk)
 434                 return false;
 435
 436         if (is_uhbr_sink && !drm_dp_is_uhbr_rate(limits->max_rate))
 437                 return false;
 438
 439         if (mode_hblank_period_ns(adjusted_mode) > hblank_limit)
 440                 return false;
 441
 442         return true;
 443 }
 444
 445 static bool
 446 adjust_limits_for_dsc_hblank_expansion_quirk(const struct intel_connector *connector,
 447                                              const struct intel_crtc_state *crtc_state,
 448                                              struct link_config_limits *limits,
 449                                              bool dsc)
 450 {
 451         struct drm_i915_private *i915 = to_i915(connector->base.dev);
 452         const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 453         int min_bpp_x16 = limits->link.min_bpp_x16;
 454
 455         if (!hblank_expansion_quirk_needs_dsc(connector, crtc_state, limits))
 456                 return true;
 457
 458         if (!dsc) {
 459                 if (intel_dp_mst_dsc_source_support(crtc_state)) {
 460                         drm_dbg_kms(&i915->drm,
 461                                     "[CRTC:%d:%s][CONNECTOR:%d:%s] DSC needed by hblank expansion quirk\n",
 462                                     crtc->base.base.id, crtc->base.name,
 463                                     connector->base.base.id, connector->base.name);
 464                         return false;
 465                 }
 466
 467                 drm_dbg_kms(&i915->drm,
 468                             "[CRTC:%d:%s][CONNECTOR:%d:%s] Increasing link min bpp to 24 due to hblank expansion quirk\n",
 469                             crtc->base.base.id, crtc->base.name,
 470                             connector->base.base.id, connector->base.name);
 471
 472                 if (limits->link.max_bpp_x16 < to_bpp_x16(24))
 473                         return false;
 474
 475                 limits->link.min_bpp_x16 = to_bpp_x16(24);
 476
 477                 return true;
 478         }
 479
 480         drm_WARN_ON(&i915->drm, limits->min_rate != limits->max_rate);
 481
 482         if (limits->max_rate < 540000)
 483                 min_bpp_x16 = to_bpp_x16(13);
 484         else if (limits->max_rate < 810000)
 485                 min_bpp_x16 = to_bpp_x16(10);
 486
 487         if (limits->link.min_bpp_x16 >= min_bpp_x16)
 488                 return true;
 489
 490         drm_dbg_kms(&i915->drm,
 491                     "[CRTC:%d:%s][CONNECTOR:%d:%s] Increasing link min bpp to " BPP_X16_FMT " in DSC mode due to hblank expansion quirk\n",
 492                     crtc->base.base.id, crtc->base.name,
 493                     connector->base.base.id, connector->base.name,
 494                     BPP_X16_ARGS(min_bpp_x16));
 495
 496         if (limits->link.max_bpp_x16 < min_bpp_x16)
 497                 return false;
 498
 499         limits->link.min_bpp_x16 = min_bpp_x16;
 500
 501         return true;
 502 }
 503
 504 static bool
 505 intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
 506                                    const struct intel_connector *connector,
 507                                    struct intel_crtc_state *crtc_state,
 508                                    bool dsc,
 509                                    struct link_config_limits *limits)
 510 {
 511         /*
 512          * for MST we always configure max link bw - the spec doesn't
 513          * seem to suggest we should do otherwise.
 514          */
 515         limits->min_rate = limits->max_rate =
 516                 intel_dp_max_link_rate(intel_dp);
 517
 518         limits->min_lane_count = limits->max_lane_count =
 519                 intel_dp_max_lane_count(intel_dp);
 520
 521         limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
 522         /*
 523          * FIXME: If all the streams can't fit into the link with
 524          * their current pipe_bpp we should reduce pipe_bpp across
 525          * the board until things start to fit. Until then we
 526          * limit to <= 8bpc since that's what was hardcoded for all
 527          * MST streams previously. This hack should be removed once
 528          * we have the proper retry logic in place.
 529          */
 530         limits->pipe.max_bpp = min(crtc_state->pipe_bpp, 24);
 531
 532         intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
 533
 534         if (!intel_dp_compute_config_link_bpp_limits(intel_dp,
 535                                                      crtc_state,
 536                                                      dsc,
 537                                                      limits))
 538                 return false;
 539
 540         return adjust_limits_for_dsc_hblank_expansion_quirk(connector,
 541                                                             crtc_state,
 542                                                             limits,
 543                                                             dsc);
 544 }
 545
 546 static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
 547                                        struct intel_crtc_state *pipe_config,
 548                                        struct drm_connector_state *conn_state)
 549 {
 550         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 551         struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
 552         struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
 553         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 554         struct intel_dp *intel_dp = &intel_mst->primary->dp;
 555         struct intel_connector *connector =
 556                 to_intel_connector(conn_state->connector);
 557         const struct drm_display_mode *adjusted_mode =
 558                 &pipe_config->hw.adjusted_mode;
 559         struct link_config_limits limits;
 560         bool dsc_needed, joiner_needs_dsc;
 561         int ret = 0;
 562
 563         if (pipe_config->fec_enable &&
 564             !intel_dp_supports_fec(intel_dp, connector, pipe_config))
 565                 return -EINVAL;
 566
 567         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 568                 return -EINVAL;
 569
 570         if (intel_dp_need_bigjoiner(intel_dp, connector,
 571                                     adjusted_mode->crtc_hdisplay,
 572                                     adjusted_mode->crtc_clock))
 573                 pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
 574
 575         pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
 576         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 577         pipe_config->has_pch_encoder = false;
 578
 579         joiner_needs_dsc = intel_dp_joiner_needs_dsc(dev_priv, pipe_config->bigjoiner_pipes);
 580
 581         dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
 582                      !intel_dp_mst_compute_config_limits(intel_dp,
 583                                                          connector,
 584                                                          pipe_config,
 585                                                          false,
 586                                                          &limits);
 587
 588         if (!dsc_needed) {
 589                 ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
 590                                                        conn_state, &limits);
 591
 592                 if (ret == -EDEADLK)
 593                         return ret;
 594
 595                 if (ret)
 596                         dsc_needed = true;
 597         }
 598
 599         /* enable compression if the mode doesn't fit available BW */
 600         if (dsc_needed) {
 601                 drm_dbg_kms(&dev_priv->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
 602                             str_yes_no(ret), str_yes_no(joiner_needs_dsc),
 603                             str_yes_no(intel_dp->force_dsc_en));
 604
 605                 if (!intel_dp_mst_dsc_source_support(pipe_config))
 606                         return -EINVAL;
 607
 608                 if (!intel_dp_mst_compute_config_limits(intel_dp,
 609                                                         connector,
 610                                                         pipe_config,
 611                                                         true,
 612                                                         &limits))
 613                         return -EINVAL;
 614
 615                 /*
 616                  * FIXME: As bpc is hardcoded to 8, as mentioned above,
 617                  * WARN and ignore the debug flag force_dsc_bpc for now.
 618                  */
 619                 drm_WARN(&dev_priv->drm, intel_dp->force_dsc_bpc, "Cannot Force BPC for MST\n");
 620                 /*
 621                  * Try to get at least some timeslots and then see, if
 622                  * we can fit there with DSC.
 623                  */
 624                 drm_dbg_kms(&dev_priv->drm, "Trying to find VCPI slots in DSC mode\n");
 625
 626                 ret = intel_dp_dsc_mst_compute_link_config(encoder, pipe_config,
 627                                                            conn_state, &limits);
 628                 if (ret < 0)
 629                         return ret;
 630
 631                 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
 632                                                   conn_state, &limits,
 633                                                   pipe_config->dp_m_n.tu, false);
 634         }
 635
 636         if (ret)
 637                 return ret;
 638
 639         ret = intel_dp_mst_update_slots(encoder, pipe_config, conn_state);
 640         if (ret)
 641                 return ret;
 642
 643         pipe_config->limited_color_range =
 644                 intel_dp_limited_color_range(pipe_config, conn_state);
 645
 646         if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
 647                 pipe_config->lane_lat_optim_mask =
 648                         bxt_dpio_phy_calc_lane_lat_optim_mask(pipe_config->lane_count);
 649
 650         intel_dp_audio_compute_config(encoder, pipe_config, conn_state);
 651
 652         intel_ddi_compute_min_voltage_level(pipe_config);
 653
 654         intel_psr_compute_config(intel_dp, pipe_config, conn_state);
 655
 656         return intel_dp_tunnel_atomic_compute_stream_bw(state, intel_dp, connector,
 657                                                         pipe_config);
 658 }
 659
 660 /*
 661  * Iterate over all connectors and return a mask of
 662  * all CPU transcoders streaming over the same DP link.
 663  */
 664 static unsigned int
 665 intel_dp_mst_transcoder_mask(struct intel_atomic_state *state,
 666                              struct intel_dp *mst_port)
 667 {
 668         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 669         const struct intel_digital_connector_state *conn_state;
 670         struct intel_connector *connector;
 671         u8 transcoders = 0;
 672         int i;
 673
 674         if (DISPLAY_VER(dev_priv) < 12)
 675                 return 0;
 676
 677         for_each_new_intel_connector_in_state(state, connector, conn_state, i) {
 678                 const struct intel_crtc_state *crtc_state;
 679                 struct intel_crtc *crtc;
 680
 681                 if (connector->mst_port != mst_port || !conn_state->base.crtc)
 682                         continue;
 683
 684                 crtc = to_intel_crtc(conn_state->base.crtc);
 685                 crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
 686
 687                 if (!crtc_state->hw.active)
 688                         continue;
 689
 690                 transcoders |= BIT(crtc_state->cpu_transcoder);
 691         }
 692
 693         return transcoders;
 694 }
 695
 696 static u8 get_pipes_downstream_of_mst_port(struct intel_atomic_state *state,
 697                                            struct drm_dp_mst_topology_mgr *mst_mgr,
 698                                            struct drm_dp_mst_port *parent_port)
 699 {
 700         const struct intel_digital_connector_state *conn_state;
 701         struct intel_connector *connector;
 702         u8 mask = 0;
 703         int i;
 704
 705         for_each_new_intel_connector_in_state(state, connector, conn_state, i) {
 706                 if (!conn_state->base.crtc)
 707                         continue;
 708
 709                 if (&connector->mst_port->mst_mgr != mst_mgr)
 710                         continue;
 711
 712                 if (connector->port != parent_port &&
 713                     !drm_dp_mst_port_downstream_of_parent(mst_mgr,
 714                                                           connector->port,
 715                                                           parent_port))
 716                         continue;
 717
 718                 mask |= BIT(to_intel_crtc(conn_state->base.crtc)->pipe);
 719         }
 720
 721         return mask;
 722 }
 723
 724 static int intel_dp_mst_check_fec_change(struct intel_atomic_state *state,
 725                                          struct drm_dp_mst_topology_mgr *mst_mgr,
 726                                          struct intel_link_bw_limits *limits)
 727 {
 728         struct drm_i915_private *i915 = to_i915(state->base.dev);
 729         struct intel_crtc *crtc;
 730         u8 mst_pipe_mask;
 731         u8 fec_pipe_mask = 0;
 732         int ret;
 733
 734         mst_pipe_mask = get_pipes_downstream_of_mst_port(state, mst_mgr, NULL);
 735
 736         for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, mst_pipe_mask) {
 737                 struct intel_crtc_state *crtc_state =
 738                         intel_atomic_get_new_crtc_state(state, crtc);
 739
 740                 /* Atomic connector check should've added all the MST CRTCs. */
 741                 if (drm_WARN_ON(&i915->drm, !crtc_state))
 742                         return -EINVAL;
 743
 744                 if (crtc_state->fec_enable)
 745                         fec_pipe_mask |= BIT(crtc->pipe);
 746         }
 747
 748         if (!fec_pipe_mask || mst_pipe_mask == fec_pipe_mask)
 749                 return 0;
 750
 751         limits->force_fec_pipes |= mst_pipe_mask;
 752
 753         ret = intel_modeset_pipes_in_mask_early(state, "MST FEC",
 754                                                 mst_pipe_mask);
 755
 756         return ret ? : -EAGAIN;
 757 }
 758
 759 static int intel_dp_mst_check_bw(struct intel_atomic_state *state,
 760                                  struct drm_dp_mst_topology_mgr *mst_mgr,
 761                                  struct drm_dp_mst_topology_state *mst_state,
 762                                  struct intel_link_bw_limits *limits)
 763 {
 764         struct drm_dp_mst_port *mst_port;
 765         u8 mst_port_pipes;
 766         int ret;
 767
 768         ret = drm_dp_mst_atomic_check_mgr(&state->base, mst_mgr, mst_state, &mst_port);
 769         if (ret != -ENOSPC)
 770                 return ret;
 771
 772         mst_port_pipes = get_pipes_downstream_of_mst_port(state, mst_mgr, mst_port);
 773
 774         ret = intel_link_bw_reduce_bpp(state, limits,
 775                                        mst_port_pipes, "MST link BW");
 776
 777         return ret ? : -EAGAIN;
 778 }
 779
 780 /**
 781  * intel_dp_mst_atomic_check_link - check all modeset MST link configuration
 782  * @state: intel atomic state
 783  * @limits: link BW limits
 784  *
 785  * Check the link configuration for all modeset MST outputs. If the
 786  * configuration is invalid @limits will be updated if possible to
 787  * reduce the total BW, after which the configuration for all CRTCs in
 788  * @state must be recomputed with the updated @limits.
 789  *
 790  * Returns:
 791  *   - 0 if the confugration is valid
 792  *   - %-EAGAIN, if the configuration is invalid and @limits got updated
 793  *     with fallback values with which the configuration of all CRTCs in
 794  *     @state must be recomputed
 795  *   - Other negative error, if the configuration is invalid without a
 796  *     fallback possibility, or the check failed for another reason
 797  */
 798 int intel_dp_mst_atomic_check_link(struct intel_atomic_state *state,
 799                                    struct intel_link_bw_limits *limits)
 800 {
 801         struct drm_dp_mst_topology_mgr *mgr;
 802         struct drm_dp_mst_topology_state *mst_state;
 803         int ret;
 804         int i;
 805
 806         for_each_new_mst_mgr_in_state(&state->base, mgr, mst_state, i) {
 807                 ret = intel_dp_mst_check_fec_change(state, mgr, limits);
 808                 if (ret)
 809                         return ret;
 810
 811                 ret = intel_dp_mst_check_bw(state, mgr, mst_state,
 812                                             limits);
 813                 if (ret)
 814                         return ret;
 815         }
 816
 817         return 0;
 818 }
 819
 820 static int intel_dp_mst_compute_config_late(struct intel_encoder *encoder,
 821                                             struct intel_crtc_state *crtc_state,
 822                                             struct drm_connector_state *conn_state)
 823 {
 824         struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state);
 825         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 826         struct intel_dp *intel_dp = &intel_mst->primary->dp;
 827
 828         /* lowest numbered transcoder will be designated master */
 829         crtc_state->mst_master_transcoder =
 830                 ffs(intel_dp_mst_transcoder_mask(state, intel_dp)) - 1;
 831
 832         return 0;
 833 }
 834
 835 /*
 836  * If one of the connectors in a MST stream needs a modeset, mark all CRTCs
 837  * that shares the same MST stream as mode changed,
 838  * intel_modeset_pipe_config()+intel_crtc_check_fastset() will take care to do
 839  * a fastset when possible.
 840  *
 841  * On TGL+ this is required since each stream go through a master transcoder,
 842  * so if the master transcoder needs modeset, all other streams in the
 843  * topology need a modeset. All platforms need to add the atomic state
 844  * for all streams in the topology, since a modeset on one may require
 845  * changing the MST link BW usage of the others, which in turn needs a
 846  * recomputation of the corresponding CRTC states.
 847  */
 848 static int
 849 intel_dp_mst_atomic_topology_check(struct intel_connector *connector,
 850                                    struct intel_atomic_state *state)
 851 {
 852         struct drm_i915_private *dev_priv = to_i915(state->base.dev);
 853         struct drm_connector_list_iter connector_list_iter;
 854         struct intel_connector *connector_iter;
 855         int ret = 0;
 856
 857         if (!intel_connector_needs_modeset(state, &connector->base))
 858                 return 0;
 859
 860         drm_connector_list_iter_begin(&dev_priv->drm, &connector_list_iter);
 861         for_each_intel_connector_iter(connector_iter, &connector_list_iter) {
 862                 struct intel_digital_connector_state *conn_iter_state;
 863                 struct intel_crtc_state *crtc_state;
 864                 struct intel_crtc *crtc;
 865
 866                 if (connector_iter->mst_port != connector->mst_port ||
 867                     connector_iter == connector)
 868                         continue;
 869
 870                 conn_iter_state = intel_atomic_get_digital_connector_state(state,
 871                                                                            connector_iter);
 872                 if (IS_ERR(conn_iter_state)) {
 873                         ret = PTR_ERR(conn_iter_state);
 874                         break;
 875                 }
 876
 877                 if (!conn_iter_state->base.crtc)
 878                         continue;
 879
 880                 crtc = to_intel_crtc(conn_iter_state->base.crtc);
 881                 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
 882                 if (IS_ERR(crtc_state)) {
 883                         ret = PTR_ERR(crtc_state);
 884                         break;
 885                 }
 886
 887                 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base);
 888                 if (ret)
 889                         break;
 890                 crtc_state->uapi.mode_changed = true;
 891         }
 892         drm_connector_list_iter_end(&connector_list_iter);
 893
 894         return ret;
 895 }
 896
 897 static int
 898 intel_dp_mst_atomic_check(struct drm_connector *connector,
 899                           struct drm_atomic_state *_state)
 900 {
 901         struct intel_atomic_state *state = to_intel_atomic_state(_state);
 902         struct intel_connector *intel_connector =
 903                 to_intel_connector(connector);
 904         int ret;
 905
 906         ret = intel_digital_connector_atomic_check(connector, &state->base);
 907         if (ret)
 908                 return ret;
 909
 910         ret = intel_dp_mst_atomic_topology_check(intel_connector, state);
 911         if (ret)
 912                 return ret;
 913
 914         if (intel_connector_needs_modeset(state, connector)) {
 915                 ret = intel_dp_tunnel_atomic_check_state(state,
 916                                                          intel_connector->mst_port,
 917                                                          intel_connector);
 918                 if (ret)
 919                         return ret;
 920         }
 921
 922         return drm_dp_atomic_release_time_slots(&state->base,
 923                                                 &intel_connector->mst_port->mst_mgr,
 924                                                 intel_connector->port);
 925 }
 926
 927 static void clear_act_sent(struct intel_encoder *encoder,
 928                            const struct intel_crtc_state *crtc_state)
 929 {
 930         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 931
 932         intel_de_write(i915, dp_tp_status_reg(encoder, crtc_state),
 933                        DP_TP_STATUS_ACT_SENT);
 934 }
 935
 936 static void wait_for_act_sent(struct intel_encoder *encoder,
 937                               const struct intel_crtc_state *crtc_state)
 938 {
 939         struct drm_i915_private *i915 = to_i915(encoder->base.dev);
 940         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 941         struct intel_dp *intel_dp = &intel_mst->primary->dp;
 942
 943         if (intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state),
 944                                   DP_TP_STATUS_ACT_SENT, 1))
 945                 drm_err(&i915->drm, "Timed out waiting for ACT sent\n");
 946
 947         drm_dp_check_act_status(&intel_dp->mst_mgr);
 948 }
 949
 950 static void intel_mst_disable_dp(struct intel_atomic_state *state,
 951                                  struct intel_encoder *encoder,
 952                                  const struct intel_crtc_state *old_crtc_state,
 953                                  const struct drm_connector_state *old_conn_state)
 954 {
 955         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 956         struct intel_digital_port *dig_port = intel_mst->primary;
 957         struct intel_dp *intel_dp = &dig_port->dp;
 958         struct intel_connector *connector =
 959                 to_intel_connector(old_conn_state->connector);
 960         struct drm_i915_private *i915 = to_i915(connector->base.dev);
 961
 962         drm_dbg_kms(&i915->drm, "active links %d\n",
 963                     intel_dp->active_mst_links);
 964
 965         intel_hdcp_disable(intel_mst->connector);
 966
 967         intel_dp_sink_disable_decompression(state, connector, old_crtc_state);
 968 }
 969
 970 static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
 971                                       struct intel_encoder *encoder,
 972                                       const struct intel_crtc_state *old_crtc_state,
 973                                       const struct drm_connector_state *old_conn_state)
 974 {
 975         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
 976         struct intel_digital_port *dig_port = intel_mst->primary;
 977         struct intel_dp *intel_dp = &dig_port->dp;
 978         struct intel_connector *connector =
 979                 to_intel_connector(old_conn_state->connector);
 980         struct drm_dp_mst_topology_state *old_mst_state =
 981                 drm_atomic_get_old_mst_topology_state(&state->base, &intel_dp->mst_mgr);
 982         struct drm_dp_mst_topology_state *new_mst_state =
 983                 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);
 984         const struct drm_dp_mst_atomic_payload *old_payload =
 985                 drm_atomic_get_mst_payload_state(old_mst_state, connector->port);
 986         struct drm_dp_mst_atomic_payload *new_payload =
 987                 drm_atomic_get_mst_payload_state(new_mst_state, connector->port);
 988         struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
 989         struct intel_crtc *pipe_crtc;
 990         bool last_mst_stream;
 991
 992         intel_dp->active_mst_links--;
 993         last_mst_stream = intel_dp->active_mst_links == 0;
 994         drm_WARN_ON(&dev_priv->drm,
 995                     DISPLAY_VER(dev_priv) >= 12 && last_mst_stream &&
 996                     !intel_dp_mst_is_master_trans(old_crtc_state));
 997
 998         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc,
 999                                          intel_crtc_joined_pipe_mask(old_crtc_state)) {
1000                 const struct intel_crtc_state *old_pipe_crtc_state =
1001                         intel_atomic_get_old_crtc_state(state, pipe_crtc);
1002
1003                 intel_crtc_vblank_off(old_pipe_crtc_state);
1004         }
1005
1006         intel_disable_transcoder(old_crtc_state);
1007
1008         drm_dp_remove_payload_part1(&intel_dp->mst_mgr, new_mst_state, new_payload);
1009
1010         clear_act_sent(encoder, old_crtc_state);
1011
1012         intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder),
1013                      TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0);
1014
1015         wait_for_act_sent(encoder, old_crtc_state);
1016
1017         drm_dp_remove_payload_part2(&intel_dp->mst_mgr, new_mst_state,
1018                                     old_payload, new_payload);
1019
1020         intel_ddi_disable_transcoder_func(old_crtc_state);
1021
1022         for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, pipe_crtc,
1023                                          intel_crtc_joined_pipe_mask(old_crtc_state)) {
1024                 const struct intel_crtc_state *old_pipe_crtc_state =
1025                         intel_atomic_get_old_crtc_state(state, pipe_crtc);
1026
1027                 intel_dsc_disable(old_pipe_crtc_state);
1028
1029                 if (DISPLAY_VER(dev_priv) >= 9)
1030                         skl_scaler_disable(old_pipe_crtc_state);
1031                 else
1032                         ilk_pfit_disable(old_pipe_crtc_state);
1033         }
1034
1035         /*
1036          * Power down mst path before disabling the port, otherwise we end
1037          * up getting interrupts from the sink upon detecting link loss.
1038          */
1039         drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port,
1040                                      false);
1041
1042         /*
1043          * BSpec 4287: disable DIP after the transcoder is disabled and before
1044          * the transcoder clock select is set to none.
1045          */
1046         intel_dp_set_infoframes(&dig_port->base, false,
1047                                 old_crtc_state, NULL);
1048         /*
1049          * From TGL spec: "If multi-stream slave transcoder: Configure
1050          * Transcoder Clock Select to direct no clock to the transcoder"
1051          *
1052          * From older GENs spec: "Configure Transcoder Clock Select to direct
1053          * no clock to the transcoder"
1054          */
1055         if (DISPLAY_VER(dev_priv) < 12 || !last_mst_stream)
1056                 intel_ddi_disable_transcoder_clock(old_crtc_state);
1057
1058
1059         intel_mst->connector = NULL;
1060         if (last_mst_stream)
1061                 dig_port->base.post_disable(state, &dig_port->base,
1062                                                   old_crtc_state, NULL);
1063
1064         drm_dbg_kms(&dev_priv->drm, "active links %d\n",
1065                     intel_dp->active_mst_links);
1066 }
1067
1068 static void intel_mst_post_pll_disable_dp(struct intel_atomic_state *state,
1069                                           struct intel_encoder *encoder,
1070                                           const struct intel_crtc_state *old_crtc_state,
1071                                           const struct drm_connector_state *old_conn_state)
1072 {
1073         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1074         struct intel_digital_port *dig_port = intel_mst->primary;
1075         struct intel_dp *intel_dp = &dig_port->dp;
1076
1077         if (intel_dp->active_mst_links == 0 &&
1078             dig_port->base.post_pll_disable)
1079                 dig_port->base.post_pll_disable(state, encoder, old_crtc_state, old_conn_state);
1080 }
1081
1082 static void intel_mst_pre_pll_enable_dp(struct intel_atomic_state *state,
1083                                         struct intel_encoder *encoder,
1084                                         const struct intel_crtc_state *pipe_config,
1085                                         const struct drm_connector_state *conn_state)
1086 {
1087         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1088         struct intel_digital_port *dig_port = intel_mst->primary;
1089         struct intel_dp *intel_dp = &dig_port->dp;
1090
1091         if (intel_dp->active_mst_links == 0)
1092                 dig_port->base.pre_pll_enable(state, &dig_port->base,
1093                                                     pipe_config, NULL);
1094         else
1095                 /*
1096                  * The port PLL state needs to get updated for secondary
1097                  * streams as for the primary stream.
1098                  */
1099                 intel_ddi_update_active_dpll(state, &dig_port->base,
1100                                              to_intel_crtc(pipe_config->uapi.crtc));
1101 }
1102
1103 static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
1104                                     struct intel_encoder *encoder,
1105                                     const struct intel_crtc_state *pipe_config,
1106                                     const struct drm_connector_state *conn_state)
1107 {
1108         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1109         struct intel_digital_port *dig_port = intel_mst->primary;
1110         struct intel_dp *intel_dp = &dig_port->dp;
1111         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1112         struct intel_connector *connector =
1113                 to_intel_connector(conn_state->connector);
1114         struct drm_dp_mst_topology_state *mst_state =
1115                 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);
1116         int ret;
1117         bool first_mst_stream;
1118
1119         /* MST encoders are bound to a crtc, not to a connector,
1120          * force the mapping here for get_hw_state.
1121          */
1122         connector->encoder = encoder;
1123         intel_mst->connector = connector;
1124         first_mst_stream = intel_dp->active_mst_links == 0;
1125         drm_WARN_ON(&dev_priv->drm,
1126                     DISPLAY_VER(dev_priv) >= 12 && first_mst_stream &&
1127                     !intel_dp_mst_is_master_trans(pipe_config));
1128
1129         drm_dbg_kms(&dev_priv->drm, "active links %d\n",
1130                     intel_dp->active_mst_links);
1131
1132         if (first_mst_stream)
1133                 intel_dp_set_power(intel_dp, DP_SET_POWER_D0);
1134
1135         drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true);
1136
1137         intel_dp_sink_enable_decompression(state, connector, pipe_config);
1138
1139         if (first_mst_stream)
1140                 dig_port->base.pre_enable(state, &dig_port->base,
1141                                                 pipe_config, NULL);
1142
1143         intel_dp->active_mst_links++;
1144
1145         ret = drm_dp_add_payload_part1(&intel_dp->mst_mgr, mst_state,
1146                                        drm_atomic_get_mst_payload_state(mst_state, connector->port));
1147         if (ret < 0)
1148                 drm_dbg_kms(&dev_priv->drm, "Failed to create MST payload for %s: %d\n",
1149                             connector->base.name, ret);
1150
1151         /*
1152          * Before Gen 12 this is not done as part of
1153          * dig_port->base.pre_enable() and should be done here. For
1154          * Gen 12+ the step in which this should be done is different for the
1155          * first MST stream, so it's done on the DDI for the first stream and
1156          * here for the following ones.
1157          */
1158         if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream)
1159                 intel_ddi_enable_transcoder_clock(encoder, pipe_config);
1160
1161         intel_dsc_dp_pps_write(&dig_port->base, pipe_config);
1162         intel_ddi_set_dp_msa(pipe_config, conn_state);
1163 }
1164
1165 static void enable_bs_jitter_was(const struct intel_crtc_state *crtc_state)
1166 {
1167         struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1168         u32 clear = 0;
1169         u32 set = 0;
1170
1171         if (!IS_ALDERLAKE_P(i915))
1172                 return;
1173
1174         if (!IS_DISPLAY_STEP(i915, STEP_D0, STEP_FOREVER))
1175                 return;
1176
1177         /* Wa_14013163432:adlp */
1178         if (crtc_state->fec_enable || intel_dp_is_uhbr(crtc_state))
1179                 set |= DP_MST_FEC_BS_JITTER_WA(crtc_state->cpu_transcoder);
1180
1181         /* Wa_14014143976:adlp */
1182         if (IS_DISPLAY_STEP(i915, STEP_E0, STEP_FOREVER)) {
1183                 if (intel_dp_is_uhbr(crtc_state))
1184                         set |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder);
1185                 else if (crtc_state->fec_enable)
1186                         clear |= DP_MST_SHORT_HBLANK_WA(crtc_state->cpu_transcoder);
1187
1188                 if (crtc_state->fec_enable || intel_dp_is_uhbr(crtc_state))
1189                         set |= DP_MST_DPT_DPTP_ALIGN_WA(crtc_state->cpu_transcoder);
1190         }
1191
1192         if (!clear && !set)
1193                 return;
1194
1195         intel_de_rmw(i915, CHICKEN_MISC_3, clear, set);
1196 }
1197
1198 static void intel_mst_enable_dp(struct intel_atomic_state *state,
1199                                 struct intel_encoder *encoder,
1200                                 const struct intel_crtc_state *pipe_config,
1201                                 const struct drm_connector_state *conn_state)
1202 {
1203         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1204         struct intel_digital_port *dig_port = intel_mst->primary;
1205         struct intel_dp *intel_dp = &dig_port->dp;
1206         struct intel_connector *connector = to_intel_connector(conn_state->connector);
1207         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1208         struct drm_dp_mst_topology_state *mst_state =
1209                 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr);
1210         enum transcoder trans = pipe_config->cpu_transcoder;
1211         bool first_mst_stream = intel_dp->active_mst_links == 1;
1212         struct intel_crtc *pipe_crtc;
1213
1214         drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder);
1215
1216         if (intel_dp_is_uhbr(pipe_config)) {
1217                 const struct drm_display_mode *adjusted_mode =
1218                         &pipe_config->hw.adjusted_mode;
1219                 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock);
1220
1221                 intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder),
1222                                TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24));
1223                 intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder),
1224                                TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff));
1225         }
1226
1227         enable_bs_jitter_was(pipe_config);
1228
1229         intel_ddi_enable_transcoder_func(encoder, pipe_config);
1230
1231         clear_act_sent(encoder, pipe_config);
1232
1233         intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0,
1234                      TRANS_DDI_DP_VC_PAYLOAD_ALLOC);
1235
1236         drm_dbg_kms(&dev_priv->drm, "active links %d\n",
1237                     intel_dp->active_mst_links);
1238
1239         wait_for_act_sent(encoder, pipe_config);
1240
1241         if (first_mst_stream)
1242                 intel_ddi_wait_for_fec_status(encoder, pipe_config, true);
1243
1244         drm_dp_add_payload_part2(&intel_dp->mst_mgr, &state->base,
1245                                  drm_atomic_get_mst_payload_state(mst_state, connector->port));
1246
1247         if (DISPLAY_VER(dev_priv) >= 12)
1248                 intel_de_rmw(dev_priv, hsw_chicken_trans_reg(dev_priv, trans),
1249                              FECSTALL_DIS_DPTSTREAM_DPTTG,
1250                              pipe_config->fec_enable ? FECSTALL_DIS_DPTSTREAM_DPTTG : 0);
1251
1252         intel_audio_sdp_split_update(pipe_config);
1253
1254         intel_enable_transcoder(pipe_config);
1255
1256         for_each_intel_crtc_in_pipe_mask_reverse(&dev_priv->drm, pipe_crtc,
1257                                                  intel_crtc_joined_pipe_mask(pipe_config)) {
1258                 const struct intel_crtc_state *pipe_crtc_state =
1259                         intel_atomic_get_new_crtc_state(state, pipe_crtc);
1260
1261                 intel_crtc_vblank_on(pipe_crtc_state);
1262         }
1263
1264         intel_hdcp_enable(state, encoder, pipe_config, conn_state);
1265 }
1266
1267 static bool intel_dp_mst_enc_get_hw_state(struct intel_encoder *encoder,
1268                                       enum pipe *pipe)
1269 {
1270         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1271         *pipe = intel_mst->pipe;
1272         if (intel_mst->connector)
1273                 return true;
1274         return false;
1275 }
1276
1277 static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder,
1278                                         struct intel_crtc_state *pipe_config)
1279 {
1280         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1281         struct intel_digital_port *dig_port = intel_mst->primary;
1282
1283         dig_port->base.get_config(&dig_port->base, pipe_config);
1284 }
1285
1286 static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder,
1287                                                struct intel_crtc_state *crtc_state)
1288 {
1289         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder);
1290         struct intel_digital_port *dig_port = intel_mst->primary;
1291
1292         return intel_dp_initial_fastset_check(&dig_port->base, crtc_state);
1293 }
1294
1295 static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector)
1296 {
1297         struct intel_connector *intel_connector = to_intel_connector(connector);
1298         struct drm_i915_private *i915 = to_i915(intel_connector->base.dev);
1299         struct intel_dp *intel_dp = intel_connector->mst_port;
1300         const struct drm_edid *drm_edid;
1301         int ret;
1302
1303         if (drm_connector_is_unregistered(connector))
1304                 return intel_connector_update_modes(connector, NULL);
1305
1306         if (!intel_display_driver_check_access(i915))
1307                 return drm_edid_connector_add_modes(connector);
1308
1309         drm_edid = drm_dp_mst_edid_read(connector, &intel_dp->mst_mgr, intel_connector->port);
1310
1311         ret = intel_connector_update_modes(connector, drm_edid);
1312
1313         drm_edid_free(drm_edid);
1314
1315         return ret;
1316 }
1317
1318 static int
1319 intel_dp_mst_connector_late_register(struct drm_connector *connector)
1320 {
1321         struct intel_connector *intel_connector = to_intel_connector(connector);
1322         int ret;
1323
1324         ret = drm_dp_mst_connector_late_register(connector,
1325                                                  intel_connector->port);
1326         if (ret < 0)
1327                 return ret;
1328
1329         ret = intel_connector_register(connector);
1330         if (ret < 0)
1331                 drm_dp_mst_connector_early_unregister(connector,
1332                                                       intel_connector->port);
1333
1334         return ret;
1335 }
1336
1337 static void
1338 intel_dp_mst_connector_early_unregister(struct drm_connector *connector)
1339 {
1340         struct intel_connector *intel_connector = to_intel_connector(connector);
1341
1342         intel_connector_unregister(connector);
1343         drm_dp_mst_connector_early_unregister(connector,
1344                                               intel_connector->port);
1345 }
1346
1347 static const struct drm_connector_funcs intel_dp_mst_connector_funcs = {
1348         .fill_modes = drm_helper_probe_single_connector_modes,
1349         .atomic_get_property = intel_digital_connector_atomic_get_property,
1350         .atomic_set_property = intel_digital_connector_atomic_set_property,
1351         .late_register = intel_dp_mst_connector_late_register,
1352         .early_unregister = intel_dp_mst_connector_early_unregister,
1353         .destroy = intel_connector_destroy,
1354         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1355         .atomic_duplicate_state = intel_digital_connector_duplicate_state,
1356 };
1357
1358 static int intel_dp_mst_get_modes(struct drm_connector *connector)
1359 {
1360         return intel_dp_mst_get_ddc_modes(connector);
1361 }
1362
1363 static int
1364 intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
1365                             struct drm_display_mode *mode,
1366                             struct drm_modeset_acquire_ctx *ctx,
1367                             enum drm_mode_status *status)
1368 {
1369         struct drm_i915_private *dev_priv = to_i915(connector->dev);
1370         struct intel_connector *intel_connector = to_intel_connector(connector);
1371         struct intel_dp *intel_dp = intel_connector->mst_port;
1372         struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr;
1373         struct drm_dp_mst_port *port = intel_connector->port;
1374         const int min_bpp = 18;
1375         int max_dotclk = to_i915(connector->dev)->display.cdclk.max_dotclk_freq;
1376         int max_rate, mode_rate, max_lanes, max_link_clock;
1377         int ret;
1378         bool dsc = false, bigjoiner = false;
1379         u16 dsc_max_compressed_bpp = 0;
1380         u8 dsc_slice_count = 0;
1381         int target_clock = mode->clock;
1382
1383         if (drm_connector_is_unregistered(connector)) {
1384                 *status = MODE_ERROR;
1385                 return 0;
1386         }
1387
1388         *status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
1389         if (*status != MODE_OK)
1390                 return 0;
1391
1392         if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1393                 *status = MODE_H_ILLEGAL;
1394                 return 0;
1395         }
1396
1397         if (mode->clock < 10000) {
1398                 *status = MODE_CLOCK_LOW;
1399                 return 0;
1400         }
1401
1402         max_link_clock = intel_dp_max_link_rate(intel_dp);
1403         max_lanes = intel_dp_max_lane_count(intel_dp);
1404
1405         max_rate = intel_dp_max_link_data_rate(intel_dp,
1406                                                max_link_clock, max_lanes);
1407         mode_rate = intel_dp_link_required(mode->clock, min_bpp);
1408
1409         /*
1410          * TODO:
1411          * - Also check if compression would allow for the mode
1412          * - Calculate the overhead using drm_dp_bw_overhead() /
1413          *   drm_dp_bw_channel_coding_efficiency(), similarly to the
1414          *   compute config code, as drm_dp_calc_pbn_mode() doesn't
1415          *   account with all the overheads.
1416          * - Check here and during compute config the BW reported by
1417          *   DFP_Link_Available_Payload_Bandwidth_Number (or the
1418          *   corresponding link capabilities of the sink) in case the
1419          *   stream is uncompressed for it by the last branch device.
1420          */
1421         if (intel_dp_need_bigjoiner(intel_dp, intel_connector,
1422                                     mode->hdisplay, target_clock)) {
1423                 bigjoiner = true;
1424                 max_dotclk *= 2;
1425         }
1426
1427         ret = drm_modeset_lock(&mgr->base.lock, ctx);
1428         if (ret)
1429                 return ret;
1430
1431         if (mode_rate > max_rate || mode->clock > max_dotclk ||
1432             drm_dp_calc_pbn_mode(mode->clock, min_bpp << 4) > port->full_pbn) {
1433                 *status = MODE_CLOCK_HIGH;
1434                 return 0;
1435         }
1436
1437         if (HAS_DSC_MST(dev_priv) &&
1438             drm_dp_sink_supports_dsc(intel_connector->dp.dsc_dpcd)) {
1439                 /*
1440                  * TBD pass the connector BPC,
1441                  * for now U8_MAX so that max BPC on that platform would be picked
1442                  */
1443                 int pipe_bpp = intel_dp_dsc_compute_max_bpp(intel_connector, U8_MAX);
1444
1445                 if (drm_dp_sink_supports_fec(intel_connector->dp.fec_capability)) {
1446                         dsc_max_compressed_bpp =
1447                                 intel_dp_dsc_get_max_compressed_bpp(dev_priv,
1448                                                                     max_link_clock,
1449                                                                     max_lanes,
1450                                                                     target_clock,
1451                                                                     mode->hdisplay,
1452                                                                     bigjoiner,
1453                                                                     INTEL_OUTPUT_FORMAT_RGB,
1454                                                                     pipe_bpp, 64);
1455                         dsc_slice_count =
1456                                 intel_dp_dsc_get_slice_count(intel_connector,
1457                                                              target_clock,
1458                                                              mode->hdisplay,
1459                                                              bigjoiner);
1460                 }
1461
1462                 dsc = dsc_max_compressed_bpp && dsc_slice_count;
1463         }
1464
1465         if (intel_dp_joiner_needs_dsc(dev_priv, bigjoiner) && !dsc) {
1466                 *status = MODE_CLOCK_HIGH;
1467                 return 0;
1468         }
1469
1470         if (mode_rate > max_rate && !dsc) {
1471                 *status = MODE_CLOCK_HIGH;
1472                 return 0;
1473         }
1474
1475         *status = intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner);
1476         return 0;
1477 }
1478
1479 static struct drm_encoder *intel_mst_atomic_best_encoder(struct drm_connector *connector,
1480                                                          struct drm_atomic_state *state)
1481 {
1482         struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state,
1483                                                                                          connector);
1484         struct intel_connector *intel_connector = to_intel_connector(connector);
1485         struct intel_dp *intel_dp = intel_connector->mst_port;
1486         struct intel_crtc *crtc = to_intel_crtc(connector_state->crtc);
1487
1488         return &intel_dp->mst_encoders[crtc->pipe]->base.base;
1489 }
1490
1491 static int
1492 intel_dp_mst_detect(struct drm_connector *connector,
1493                     struct drm_modeset_acquire_ctx *ctx, bool force)
1494 {
1495         struct drm_i915_private *i915 = to_i915(connector->dev);
1496         struct intel_connector *intel_connector = to_intel_connector(connector);
1497         struct intel_dp *intel_dp = intel_connector->mst_port;
1498
1499         if (!intel_display_device_enabled(i915))
1500                 return connector_status_disconnected;
1501
1502         if (drm_connector_is_unregistered(connector))
1503                 return connector_status_disconnected;
1504
1505         if (!intel_display_driver_check_access(i915))
1506                 return connector->status;
1507
1508         return drm_dp_mst_detect_port(connector, ctx, &intel_dp->mst_mgr,
1509                                       intel_connector->port);
1510 }
1511
1512 static const struct drm_connector_helper_funcs intel_dp_mst_connector_helper_funcs = {
1513         .get_modes = intel_dp_mst_get_modes,
1514         .mode_valid_ctx = intel_dp_mst_mode_valid_ctx,
1515         .atomic_best_encoder = intel_mst_atomic_best_encoder,
1516         .atomic_check = intel_dp_mst_atomic_check,
1517         .detect_ctx = intel_dp_mst_detect,
1518 };
1519
1520 static void intel_dp_mst_encoder_destroy(struct drm_encoder *encoder)
1521 {
1522         struct intel_dp_mst_encoder *intel_mst = enc_to_mst(to_intel_encoder(encoder));
1523
1524         drm_encoder_cleanup(encoder);
1525         kfree(intel_mst);
1526 }
1527
1528 static const struct drm_encoder_funcs intel_dp_mst_enc_funcs = {
1529         .destroy = intel_dp_mst_encoder_destroy,
1530 };
1531
1532 static bool intel_dp_mst_get_hw_state(struct intel_connector *connector)
1533 {
1534         if (intel_attached_encoder(connector) && connector->base.state->crtc) {
1535                 enum pipe pipe;
1536                 if (!intel_attached_encoder(connector)->get_hw_state(intel_attached_encoder(connector), &pipe))
1537                         return false;
1538                 return true;
1539         }
1540         return false;
1541 }
1542
1543 static int intel_dp_mst_add_properties(struct intel_dp *intel_dp,
1544                                        struct drm_connector *connector,
1545                                        const char *pathprop)
1546 {
1547         struct drm_i915_private *i915 = to_i915(connector->dev);
1548
1549         drm_object_attach_property(&connector->base,
1550                                    i915->drm.mode_config.path_property, 0);
1551         drm_object_attach_property(&connector->base,
1552                                    i915->drm.mode_config.tile_property, 0);
1553
1554         intel_attach_force_audio_property(connector);
1555         intel_attach_broadcast_rgb_property(connector);
1556
1557         /*
1558          * Reuse the prop from the SST connector because we're
1559          * not allowed to create new props after device registration.
1560          */
1561         connector->max_bpc_property =
1562                 intel_dp->attached_connector->base.max_bpc_property;
1563         if (connector->max_bpc_property)
1564                 drm_connector_attach_max_bpc_property(connector, 6, 12);
1565
1566         return drm_connector_set_path_property(connector, pathprop);
1567 }
1568
1569 static void
1570 intel_dp_mst_read_decompression_port_dsc_caps(struct intel_dp *intel_dp,
1571                                               struct intel_connector *connector)
1572 {
1573         u8 dpcd_caps[DP_RECEIVER_CAP_SIZE];
1574
1575         if (!connector->dp.dsc_decompression_aux)
1576                 return;
1577
1578         if (drm_dp_read_dpcd_caps(connector->dp.dsc_decompression_aux, dpcd_caps) < 0)
1579                 return;
1580
1581         intel_dp_get_dsc_sink_cap(dpcd_caps[DP_DPCD_REV], connector);
1582 }
1583
1584 static bool detect_dsc_hblank_expansion_quirk(const struct intel_connector *connector)
1585 {
1586         struct drm_i915_private *i915 = to_i915(connector->base.dev);
1587         struct drm_dp_aux *aux = connector->dp.dsc_decompression_aux;
1588         struct drm_dp_desc desc;
1589         u8 dpcd[DP_RECEIVER_CAP_SIZE];
1590
1591         if (!aux)
1592                 return false;
1593
1594         /*
1595          * A logical port's OUI (at least for affected sinks) is all 0, so
1596          * instead of that the parent port's OUI is used for identification.
1597          */
1598         if (drm_dp_mst_port_is_logical(connector->port)) {
1599                 aux = drm_dp_mst_aux_for_parent(connector->port);
1600                 if (!aux)
1601                         aux = &connector->mst_port->aux;
1602         }
1603
1604         if (drm_dp_read_dpcd_caps(aux, dpcd) < 0)
1605                 return false;
1606
1607         if (drm_dp_read_desc(aux, &desc, drm_dp_is_branch(dpcd)) < 0)
1608                 return false;
1609
1610         if (!drm_dp_has_quirk(&desc,
1611                               DP_DPCD_QUIRK_HBLANK_EXPANSION_REQUIRES_DSC))
1612                 return false;
1613
1614         /*
1615          * UHBR (MST sink) devices requiring this quirk don't advertise the
1616          * HBLANK expansion support. Presuming that they perform HBLANK
1617          * expansion internally, or are affected by this issue on modes with a
1618          * short HBLANK for other reasons.
1619          */
1620         if (!drm_dp_128b132b_supported(dpcd) &&
1621             !(dpcd[DP_RECEIVE_PORT_0_CAP_0] & DP_HBLANK_EXPANSION_CAPABLE))
1622                 return false;
1623
1624         drm_dbg_kms(&i915->drm,
1625                     "[CONNECTOR:%d:%s] DSC HBLANK expansion quirk detected\n",
1626                     connector->base.base.id, connector->base.name);
1627
1628         return true;
1629 }
1630
1631 static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr,
1632                                                         struct drm_dp_mst_port *port,
1633                                                         const char *pathprop)
1634 {
1635         struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr);
1636         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1637         struct drm_device *dev = dig_port->base.base.dev;
1638         struct drm_i915_private *dev_priv = to_i915(dev);
1639         struct intel_connector *intel_connector;
1640         struct drm_connector *connector;
1641         enum pipe pipe;
1642         int ret;
1643
1644         intel_connector = intel_connector_alloc();
1645         if (!intel_connector)
1646                 return NULL;
1647
1648         intel_connector->get_hw_state = intel_dp_mst_get_hw_state;
1649         intel_connector->sync_state = intel_dp_connector_sync_state;
1650         intel_connector->mst_port = intel_dp;
1651         intel_connector->port = port;
1652         drm_dp_mst_get_port_malloc(port);
1653
1654         intel_dp_init_modeset_retry_work(intel_connector);
1655
1656         intel_connector->dp.dsc_decompression_aux = drm_dp_mst_dsc_aux_for_port(port);
1657         intel_dp_mst_read_decompression_port_dsc_caps(intel_dp, intel_connector);
1658         intel_connector->dp.dsc_hblank_expansion_quirk =
1659                 detect_dsc_hblank_expansion_quirk(intel_connector);
1660
1661         connector = &intel_connector->base;
1662         ret = drm_connector_init(dev, connector, &intel_dp_mst_connector_funcs,
1663                                  DRM_MODE_CONNECTOR_DisplayPort);
1664         if (ret) {
1665                 drm_dp_mst_put_port_malloc(port);
1666                 intel_connector_free(intel_connector);
1667                 return NULL;
1668         }
1669
1670         drm_connector_helper_add(connector, &intel_dp_mst_connector_helper_funcs);
1671
1672         for_each_pipe(dev_priv, pipe) {
1673                 struct drm_encoder *enc =
1674                         &intel_dp->mst_encoders[pipe]->base.base;
1675
1676                 ret = drm_connector_attach_encoder(&intel_connector->base, enc);
1677                 if (ret)
1678                         goto err;
1679         }
1680
1681         ret = intel_dp_mst_add_properties(intel_dp, connector, pathprop);
1682         if (ret)
1683                 goto err;
1684
1685         ret = intel_dp_hdcp_init(dig_port, intel_connector);
1686         if (ret)
1687                 drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP MST init failed, skipping.\n",
1688                             connector->name, connector->base.id);
1689
1690         return connector;
1691
1692 err:
1693         drm_connector_cleanup(connector);
1694         return NULL;
1695 }
1696
1697 static void
1698 intel_dp_mst_poll_hpd_irq(struct drm_dp_mst_topology_mgr *mgr)
1699 {
1700         struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr);
1701
1702         intel_hpd_trigger_irq(dp_to_dig_port(intel_dp));
1703 }
1704
1705 static const struct drm_dp_mst_topology_cbs mst_cbs = {
1706         .add_connector = intel_dp_add_mst_connector,
1707         .poll_hpd_irq = intel_dp_mst_poll_hpd_irq,
1708 };
1709
1710 static struct intel_dp_mst_encoder *
1711 intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe pipe)
1712 {
1713         struct intel_dp_mst_encoder *intel_mst;
1714         struct intel_encoder *intel_encoder;
1715         struct drm_device *dev = dig_port->base.base.dev;
1716
1717         intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL);
1718
1719         if (!intel_mst)
1720                 return NULL;
1721
1722         intel_mst->pipe = pipe;
1723         intel_encoder = &intel_mst->base;
1724         intel_mst->primary = dig_port;
1725
1726         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_mst_enc_funcs,
1727                          DRM_MODE_ENCODER_DPMST, "DP-MST %c", pipe_name(pipe));
1728
1729         intel_encoder->type = INTEL_OUTPUT_DP_MST;
1730         intel_encoder->power_domain = dig_port->base.power_domain;
1731         intel_encoder->port = dig_port->base.port;
1732         intel_encoder->cloneable = 0;
1733         /*
1734          * This is wrong, but broken userspace uses the intersection
1735          * of possible_crtcs of all the encoders of a given connector
1736          * to figure out which crtcs can drive said connector. What
1737          * should be used instead is the union of possible_crtcs.
1738          * To keep such userspace functioning we must misconfigure
1739          * this to make sure the intersection is not empty :(
1740          */
1741         intel_encoder->pipe_mask = ~0;
1742
1743         intel_encoder->compute_config = intel_dp_mst_compute_config;
1744         intel_encoder->compute_config_late = intel_dp_mst_compute_config_late;
1745         intel_encoder->disable = intel_mst_disable_dp;
1746         intel_encoder->post_disable = intel_mst_post_disable_dp;
1747         intel_encoder->post_pll_disable = intel_mst_post_pll_disable_dp;
1748         intel_encoder->update_pipe = intel_ddi_update_pipe;
1749         intel_encoder->pre_pll_enable = intel_mst_pre_pll_enable_dp;
1750         intel_encoder->pre_enable = intel_mst_pre_enable_dp;
1751         intel_encoder->enable = intel_mst_enable_dp;
1752         intel_encoder->audio_enable = intel_audio_codec_enable;
1753         intel_encoder->audio_disable = intel_audio_codec_disable;
1754         intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state;
1755         intel_encoder->get_config = intel_dp_mst_enc_get_config;
1756         intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check;
1757
1758         return intel_mst;
1759
1760 }
1761
1762 static bool
1763 intel_dp_create_fake_mst_encoders(struct intel_digital_port *dig_port)
1764 {
1765         struct intel_dp *intel_dp = &dig_port->dp;
1766         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
1767         enum pipe pipe;
1768
1769         for_each_pipe(dev_priv, pipe)
1770                 intel_dp->mst_encoders[pipe] = intel_dp_create_fake_mst_encoder(dig_port, pipe);
1771         return true;
1772 }
1773
1774 int
1775 intel_dp_mst_encoder_active_links(struct intel_digital_port *dig_port)
1776 {
1777         return dig_port->dp.active_mst_links;
1778 }
1779
1780 int
1781 intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id)
1782 {
1783         struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
1784         struct intel_dp *intel_dp = &dig_port->dp;
1785         enum port port = dig_port->base.port;
1786         int ret;
1787
1788         if (!HAS_DP_MST(i915) || intel_dp_is_edp(intel_dp))
1789                 return 0;
1790
1791         if (DISPLAY_VER(i915) < 12 && port == PORT_A)
1792                 return 0;
1793
1794         if (DISPLAY_VER(i915) < 11 && port == PORT_E)
1795                 return 0;
1796
1797         intel_dp->mst_mgr.cbs = &mst_cbs;
1798
1799         /* create encoders */
1800         intel_dp_create_fake_mst_encoders(dig_port);
1801         ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm,
1802                                            &intel_dp->aux, 16, 3, conn_base_id);
1803         if (ret) {
1804                 intel_dp->mst_mgr.cbs = NULL;
1805                 return ret;
1806         }
1807
1808         return 0;
1809 }
1810
1811 bool intel_dp_mst_source_support(struct intel_dp *intel_dp)
1812 {
1813         return intel_dp->mst_mgr.cbs;
1814 }
1815
1816 void
1817 intel_dp_mst_encoder_cleanup(struct intel_digital_port *dig_port)
1818 {
1819         struct intel_dp *intel_dp = &dig_port->dp;
1820
1821         if (!intel_dp_mst_source_support(intel_dp))
1822                 return;
1823
1824         drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr);
1825         /* encoders will get killed by normal cleanup */
1826
1827         intel_dp->mst_mgr.cbs = NULL;
1828 }
1829
1830 bool intel_dp_mst_is_master_trans(const struct intel_crtc_state *crtc_state)
1831 {
1832         return crtc_state->mst_master_transcoder == crtc_state->cpu_transcoder;
1833 }
1834
1835 bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state)
1836 {
1837         return crtc_state->mst_master_transcoder != INVALID_TRANSCODER &&
1838                crtc_state->mst_master_transcoder != crtc_state->cpu_transcoder;
1839 }
1840
1841 /**
1842  * intel_dp_mst_add_topology_state_for_connector - add MST topology state for a connector
1843  * @state: atomic state
1844  * @connector: connector to add the state for
1845  * @crtc: the CRTC @connector is attached to
1846  *
1847  * Add the MST topology state for @connector to @state.
1848  *
1849  * Returns 0 on success, negative error code on failure.
1850  */
1851 static int
1852 intel_dp_mst_add_topology_state_for_connector(struct intel_atomic_state *state,
1853                                               struct intel_connector *connector,
1854                                               struct intel_crtc *crtc)
1855 {
1856         struct drm_dp_mst_topology_state *mst_state;
1857
1858         if (!connector->mst_port)
1859                 return 0;
1860
1861         mst_state = drm_atomic_get_mst_topology_state(&state->base,
1862                                                       &connector->mst_port->mst_mgr);
1863         if (IS_ERR(mst_state))
1864                 return PTR_ERR(mst_state);
1865
1866         mst_state->pending_crtc_mask |= drm_crtc_mask(&crtc->base);
1867
1868         return 0;
1869 }
1870
1871 /**
1872  * intel_dp_mst_add_topology_state_for_crtc - add MST topology state for a CRTC
1873  * @state: atomic state
1874  * @crtc: CRTC to add the state for
1875  *
1876  * Add the MST topology state for @crtc to @state.
1877  *
1878  * Returns 0 on success, negative error code on failure.
1879  */
1880 int intel_dp_mst_add_topology_state_for_crtc(struct intel_atomic_state *state,
1881                                              struct intel_crtc *crtc)
1882 {
1883         struct drm_connector *_connector;
1884         struct drm_connector_state *conn_state;
1885         int i;
1886
1887         for_each_new_connector_in_state(&state->base, _connector, conn_state, i) {
1888                 struct intel_connector *connector = to_intel_connector(_connector);
1889                 int ret;
1890
1891                 if (conn_state->crtc != &crtc->base)
1892                         continue;
1893
1894                 ret = intel_dp_mst_add_topology_state_for_connector(state, connector, crtc);
1895                 if (ret)
1896                         return ret;
1897         }
1898
1899         return 0;
1900 }
1901
1902 static struct intel_connector *
1903 get_connector_in_state_for_crtc(struct intel_atomic_state *state,
1904                                 const struct intel_crtc *crtc)
1905 {
1906         struct drm_connector_state *old_conn_state;
1907         struct drm_connector_state *new_conn_state;
1908         struct drm_connector *_connector;
1909         int i;
1910
1911         for_each_oldnew_connector_in_state(&state->base, _connector,
1912                                            old_conn_state, new_conn_state, i) {
1913                 struct intel_connector *connector =
1914                         to_intel_connector(_connector);
1915
1916                 if (old_conn_state->crtc == &crtc->base ||
1917                     new_conn_state->crtc == &crtc->base)
1918                         return connector;
1919         }
1920
1921         return NULL;
1922 }
1923
1924 /**
1925  * intel_dp_mst_crtc_needs_modeset - check if changes in topology need to modeset the given CRTC
1926  * @state: atomic state
1927  * @crtc: CRTC for which to check the modeset requirement
1928  *
1929  * Check if any change in a MST topology requires a forced modeset on @crtc in
1930  * this topology. One such change is enabling/disabling the DSC decompression
1931  * state in the first branch device's UFP DPCD as required by one CRTC, while
1932  * the other @crtc in the same topology is still active, requiring a full modeset
1933  * on @crtc.
1934  */
1935 bool intel_dp_mst_crtc_needs_modeset(struct intel_atomic_state *state,
1936                                      struct intel_crtc *crtc)
1937 {
1938         const struct intel_connector *crtc_connector;
1939         const struct drm_connector_state *conn_state;
1940         const struct drm_connector *_connector;
1941         int i;
1942
1943         if (!intel_crtc_has_type(intel_atomic_get_new_crtc_state(state, crtc),
1944                                  INTEL_OUTPUT_DP_MST))
1945                 return false;
1946
1947         crtc_connector = get_connector_in_state_for_crtc(state, crtc);
1948
1949         if (!crtc_connector)
1950                 /* None of the connectors in the topology needs modeset */
1951                 return false;
1952
1953         for_each_new_connector_in_state(&state->base, _connector, conn_state, i) {
1954                 const struct intel_connector *connector =
1955                         to_intel_connector(_connector);
1956                 const struct intel_crtc_state *new_crtc_state;
1957                 const struct intel_crtc_state *old_crtc_state;
1958                 struct intel_crtc *crtc_iter;
1959
1960                 if (connector->mst_port != crtc_connector->mst_port ||
1961                     !conn_state->crtc)
1962                         continue;
1963
1964                 crtc_iter = to_intel_crtc(conn_state->crtc);
1965
1966                 new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc_iter);
1967                 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc_iter);
1968
1969                 if (!intel_crtc_needs_modeset(new_crtc_state))
1970                         continue;
1971
1972                 if (old_crtc_state->dsc.compression_enable ==
1973                     new_crtc_state->dsc.compression_enable)
1974                         continue;
1975                 /*
1976                  * Toggling the decompression flag because of this stream in
1977                  * the first downstream branch device's UFP DPCD may reset the
1978                  * whole branch device. To avoid the reset while other streams
1979                  * are also active modeset the whole MST topology in this
1980                  * case.
1981                  */
1982                 if (connector->dp.dsc_decompression_aux ==
1983                     &connector->mst_port->aux)
1984                         return true;
1985         }
1986
1987         return false;
1988 }