drivers/gpu/drm/i915/display/intel_cursor.c

   1 // SPDX-License-Identifier: MIT
   2 /*
   3  * Copyright © 2020 Intel Corporation
   4  */
   5 #include <linux/kernel.h>
   6
   7 #include <drm/drm_atomic_helper.h>
   8 #include <drm/drm_atomic_uapi.h>
   9 #include <drm/drm_blend.h>
  10 #include <drm/drm_damage_helper.h>
  11 #include <drm/drm_fourcc.h>
  12
  13 #include "i915_reg.h"
  14 #include "intel_atomic.h"
  15 #include "intel_atomic_plane.h"
  16 #include "intel_cursor.h"
  17 #include "intel_de.h"
  18 #include "intel_display.h"
  19 #include "intel_display_types.h"
  20 #include "intel_fb.h"
  21 #include "intel_fb_pin.h"
  22 #include "intel_frontbuffer.h"
  23 #include "intel_psr.h"
  24 #include "intel_psr_regs.h"
  25 #include "intel_vblank.h"
  26 #include "skl_watermark.h"
  27
  28 #include "gem/i915_gem_object.h"
  29
  30 /* Cursor formats */
  31 static const u32 intel_cursor_formats[] = {
  32         DRM_FORMAT_ARGB8888,
  33 };
  34
  35 static u32 intel_cursor_base(const struct intel_plane_state *plane_state)
  36 {
  37         struct drm_i915_private *dev_priv =
  38                 to_i915(plane_state->uapi.plane->dev);
  39         u32 base;
  40
  41         if (DISPLAY_INFO(dev_priv)->cursor_needs_physical)
  42                 base = plane_state->phys_dma_addr;
  43         else
  44                 base = intel_plane_ggtt_offset(plane_state);
  45
  46         return base + plane_state->view.color_plane[0].offset;
  47 }
  48
  49 static u32 intel_cursor_position(const struct intel_crtc_state *crtc_state,
  50                                  const struct intel_plane_state *plane_state,
  51                                  bool early_tpt)
  52 {
  53         int x = plane_state->uapi.dst.x1;
  54         int y = plane_state->uapi.dst.y1;
  55         u32 pos = 0;
  56
  57         /*
  58          * Formula from Bspec:
  59          * MAX(-1 * <Cursor vertical size from CUR_CTL base on cursor mode
  60          * select setting> + 1, CUR_POS Y Position - Update region Y position
  61          */
  62         if (early_tpt)
  63                 y = max(-1 * drm_rect_height(&plane_state->uapi.dst) + 1,
  64                         y - crtc_state->psr2_su_area.y1);
  65
  66         if (x < 0) {
  67                 pos |= CURSOR_POS_X_SIGN;
  68                 x = -x;
  69         }
  70         pos |= CURSOR_POS_X(x);
  71
  72         if (y < 0) {
  73                 pos |= CURSOR_POS_Y_SIGN;
  74                 y = -y;
  75         }
  76         pos |= CURSOR_POS_Y(y);
  77
  78         return pos;
  79 }
  80
  81 static bool intel_cursor_size_ok(const struct intel_plane_state *plane_state)
  82 {
  83         const struct drm_mode_config *config =
  84                 &plane_state->uapi.plane->dev->mode_config;
  85         int width = drm_rect_width(&plane_state->uapi.dst);
  86         int height = drm_rect_height(&plane_state->uapi.dst);
  87
  88         return width > 0 && width <= config->cursor_width &&
  89                 height > 0 && height <= config->cursor_height;
  90 }
  91
  92 static int intel_cursor_check_surface(struct intel_plane_state *plane_state)
  93 {
  94         struct drm_i915_private *dev_priv =
  95                 to_i915(plane_state->uapi.plane->dev);
  96         unsigned int rotation = plane_state->hw.rotation;
  97         int src_x, src_y;
  98         u32 offset;
  99         int ret;
 100
 101         ret = intel_plane_compute_gtt(plane_state);
 102         if (ret)
 103                 return ret;
 104
 105         if (!plane_state->uapi.visible)
 106                 return 0;
 107
 108         src_x = plane_state->uapi.src.x1 >> 16;
 109         src_y = plane_state->uapi.src.y1 >> 16;
 110
 111         intel_add_fb_offsets(&src_x, &src_y, plane_state, 0);
 112         offset = intel_plane_compute_aligned_offset(&src_x, &src_y,
 113                                                     plane_state, 0);
 114
 115         if (src_x != 0 || src_y != 0) {
 116                 drm_dbg_kms(&dev_priv->drm,
 117                             "Arbitrary cursor panning not supported\n");
 118                 return -EINVAL;
 119         }
 120
 121         /*
 122          * Put the final coordinates back so that the src
 123          * coordinate checks will see the right values.
 124          */
 125         drm_rect_translate_to(&plane_state->uapi.src,
 126                               src_x << 16, src_y << 16);
 127
 128         /* ILK+ do this automagically in hardware */
 129         if (HAS_GMCH(dev_priv) && rotation & DRM_MODE_ROTATE_180) {
 130                 const struct drm_framebuffer *fb = plane_state->hw.fb;
 131                 int src_w = drm_rect_width(&plane_state->uapi.src) >> 16;
 132                 int src_h = drm_rect_height(&plane_state->uapi.src) >> 16;
 133
 134                 offset += (src_h * src_w - 1) * fb->format->cpp[0];
 135         }
 136
 137         plane_state->view.color_plane[0].offset = offset;
 138         plane_state->view.color_plane[0].x = src_x;
 139         plane_state->view.color_plane[0].y = src_y;
 140
 141         return 0;
 142 }
 143
 144 static int intel_check_cursor(struct intel_crtc_state *crtc_state,
 145                               struct intel_plane_state *plane_state)
 146 {
 147         const struct drm_framebuffer *fb = plane_state->hw.fb;
 148         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
 149         const struct drm_rect src = plane_state->uapi.src;
 150         const struct drm_rect dst = plane_state->uapi.dst;
 151         int ret;
 152
 153         if (fb && fb->modifier != DRM_FORMAT_MOD_LINEAR) {
 154                 drm_dbg_kms(&i915->drm, "cursor cannot be tiled\n");
 155                 return -EINVAL;
 156         }
 157
 158         ret = intel_atomic_plane_check_clipping(plane_state, crtc_state,
 159                                                 DRM_PLANE_NO_SCALING,
 160                                                 DRM_PLANE_NO_SCALING,
 161                                                 true);
 162         if (ret)
 163                 return ret;
 164
 165         /* Use the unclipped src/dst rectangles, which we program to hw */
 166         plane_state->uapi.src = src;
 167         plane_state->uapi.dst = dst;
 168
 169         /* final plane coordinates will be relative to the plane's pipe */
 170         drm_rect_translate(&plane_state->uapi.dst,
 171                            -crtc_state->pipe_src.x1,
 172                            -crtc_state->pipe_src.y1);
 173
 174         ret = intel_cursor_check_surface(plane_state);
 175         if (ret)
 176                 return ret;
 177
 178         if (!plane_state->uapi.visible)
 179                 return 0;
 180
 181         ret = intel_plane_check_src_coordinates(plane_state);
 182         if (ret)
 183                 return ret;
 184
 185         return 0;
 186 }
 187
 188 static unsigned int
 189 i845_cursor_max_stride(struct intel_plane *plane,
 190                        u32 pixel_format, u64 modifier,
 191                        unsigned int rotation)
 192 {
 193         return 2048;
 194 }
 195
 196 static u32 i845_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
 197 {
 198         u32 cntl = 0;
 199
 200         if (crtc_state->gamma_enable)
 201                 cntl |= CURSOR_PIPE_GAMMA_ENABLE;
 202
 203         return cntl;
 204 }
 205
 206 static u32 i845_cursor_ctl(const struct intel_crtc_state *crtc_state,
 207                            const struct intel_plane_state *plane_state)
 208 {
 209         return CURSOR_ENABLE |
 210                 CURSOR_FORMAT_ARGB |
 211                 CURSOR_STRIDE(plane_state->view.color_plane[0].mapping_stride);
 212 }
 213
 214 static bool i845_cursor_size_ok(const struct intel_plane_state *plane_state)
 215 {
 216         int width = drm_rect_width(&plane_state->uapi.dst);
 217
 218         /*
 219          * 845g/865g are only limited by the width of their cursors,
 220          * the height is arbitrary up to the precision of the register.
 221          */
 222         return intel_cursor_size_ok(plane_state) && IS_ALIGNED(width, 64);
 223 }
 224
 225 static int i845_check_cursor(struct intel_crtc_state *crtc_state,
 226                              struct intel_plane_state *plane_state)
 227 {
 228         const struct drm_framebuffer *fb = plane_state->hw.fb;
 229         struct drm_i915_private *i915 = to_i915(plane_state->uapi.plane->dev);
 230         int ret;
 231
 232         ret = intel_check_cursor(crtc_state, plane_state);
 233         if (ret)
 234                 return ret;
 235
 236         /* if we want to turn off the cursor ignore width and height */
 237         if (!fb)
 238                 return 0;
 239
 240         /* Check for which cursor types we support */
 241         if (!i845_cursor_size_ok(plane_state)) {
 242                 drm_dbg_kms(&i915->drm,
 243                             "Cursor dimension %dx%d not supported\n",
 244                             drm_rect_width(&plane_state->uapi.dst),
 245                             drm_rect_height(&plane_state->uapi.dst));
 246                 return -EINVAL;
 247         }
 248
 249         drm_WARN_ON(&i915->drm, plane_state->uapi.visible &&
 250                     plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]);
 251
 252         switch (fb->pitches[0]) {
 253         case 256:
 254         case 512:
 255         case 1024:
 256         case 2048:
 257                 break;
 258         default:
 259                  drm_dbg_kms(&i915->drm, "Invalid cursor stride (%u)\n",
 260                              fb->pitches[0]);
 261                 return -EINVAL;
 262         }
 263
 264         plane_state->ctl = i845_cursor_ctl(crtc_state, plane_state);
 265
 266         return 0;
 267 }
 268
 269 /* TODO: split into noarm+arm pair */
 270 static void i845_cursor_update_arm(struct intel_plane *plane,
 271                                    const struct intel_crtc_state *crtc_state,
 272                                    const struct intel_plane_state *plane_state)
 273 {
 274         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 275         u32 cntl = 0, base = 0, pos = 0, size = 0;
 276
 277         if (plane_state && plane_state->uapi.visible) {
 278                 unsigned int width = drm_rect_width(&plane_state->uapi.dst);
 279                 unsigned int height = drm_rect_height(&plane_state->uapi.dst);
 280
 281                 cntl = plane_state->ctl |
 282                         i845_cursor_ctl_crtc(crtc_state);
 283
 284                 size = CURSOR_HEIGHT(height) | CURSOR_WIDTH(width);
 285
 286                 base = intel_cursor_base(plane_state);
 287                 pos = intel_cursor_position(crtc_state, plane_state, false);
 288         }
 289
 290         /* On these chipsets we can only modify the base/size/stride
 291          * whilst the cursor is disabled.
 292          */
 293         if (plane->cursor.base != base ||
 294             plane->cursor.size != size ||
 295             plane->cursor.cntl != cntl) {
 296                 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), 0);
 297                 intel_de_write_fw(dev_priv, CURBASE(PIPE_A), base);
 298                 intel_de_write_fw(dev_priv, CURSIZE(PIPE_A), size);
 299                 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
 300                 intel_de_write_fw(dev_priv, CURCNTR(PIPE_A), cntl);
 301
 302                 plane->cursor.base = base;
 303                 plane->cursor.size = size;
 304                 plane->cursor.cntl = cntl;
 305         } else {
 306                 intel_de_write_fw(dev_priv, CURPOS(PIPE_A), pos);
 307         }
 308 }
 309
 310 static void i845_cursor_disable_arm(struct intel_plane *plane,
 311                                     const struct intel_crtc_state *crtc_state)
 312 {
 313         i845_cursor_update_arm(plane, crtc_state, NULL);
 314 }
 315
 316 static bool i845_cursor_get_hw_state(struct intel_plane *plane,
 317                                      enum pipe *pipe)
 318 {
 319         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 320         enum intel_display_power_domain power_domain;
 321         intel_wakeref_t wakeref;
 322         bool ret;
 323
 324         power_domain = POWER_DOMAIN_PIPE(PIPE_A);
 325         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
 326         if (!wakeref)
 327                 return false;
 328
 329         ret = intel_de_read(dev_priv, CURCNTR(PIPE_A)) & CURSOR_ENABLE;
 330
 331         *pipe = PIPE_A;
 332
 333         intel_display_power_put(dev_priv, power_domain, wakeref);
 334
 335         return ret;
 336 }
 337
 338 static unsigned int
 339 i9xx_cursor_max_stride(struct intel_plane *plane,
 340                        u32 pixel_format, u64 modifier,
 341                        unsigned int rotation)
 342 {
 343         return plane->base.dev->mode_config.cursor_width * 4;
 344 }
 345
 346 static u32 i9xx_cursor_ctl_crtc(const struct intel_crtc_state *crtc_state)
 347 {
 348         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 349         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
 350         u32 cntl = 0;
 351
 352         if (DISPLAY_VER(dev_priv) >= 11)
 353                 return cntl;
 354
 355         if (crtc_state->gamma_enable)
 356                 cntl = MCURSOR_PIPE_GAMMA_ENABLE;
 357
 358         if (crtc_state->csc_enable)
 359                 cntl |= MCURSOR_PIPE_CSC_ENABLE;
 360
 361         if (DISPLAY_VER(dev_priv) < 5 && !IS_G4X(dev_priv))
 362                 cntl |= MCURSOR_PIPE_SEL(crtc->pipe);
 363
 364         return cntl;
 365 }
 366
 367 static u32 i9xx_cursor_ctl(const struct intel_crtc_state *crtc_state,
 368                            const struct intel_plane_state *plane_state)
 369 {
 370         struct drm_i915_private *dev_priv =
 371                 to_i915(plane_state->uapi.plane->dev);
 372         u32 cntl = 0;
 373
 374         if (IS_SANDYBRIDGE(dev_priv) || IS_IVYBRIDGE(dev_priv))
 375                 cntl |= MCURSOR_TRICKLE_FEED_DISABLE;
 376
 377         switch (drm_rect_width(&plane_state->uapi.dst)) {
 378         case 64:
 379                 cntl |= MCURSOR_MODE_64_ARGB_AX;
 380                 break;
 381         case 128:
 382                 cntl |= MCURSOR_MODE_128_ARGB_AX;
 383                 break;
 384         case 256:
 385                 cntl |= MCURSOR_MODE_256_ARGB_AX;
 386                 break;
 387         default:
 388                 MISSING_CASE(drm_rect_width(&plane_state->uapi.dst));
 389                 return 0;
 390         }
 391
 392         if (plane_state->hw.rotation & DRM_MODE_ROTATE_180)
 393                 cntl |= MCURSOR_ROTATE_180;
 394
 395         /* Wa_22012358565:adl-p */
 396         if (DISPLAY_VER(dev_priv) == 13)
 397                 cntl |= MCURSOR_ARB_SLOTS(1);
 398
 399         return cntl;
 400 }
 401
 402 static bool i9xx_cursor_size_ok(const struct intel_plane_state *plane_state)
 403 {
 404         struct drm_i915_private *dev_priv =
 405                 to_i915(plane_state->uapi.plane->dev);
 406         int width = drm_rect_width(&plane_state->uapi.dst);
 407         int height = drm_rect_height(&plane_state->uapi.dst);
 408
 409         if (!intel_cursor_size_ok(plane_state))
 410                 return false;
 411
 412         /* Cursor width is limited to a few power-of-two sizes */
 413         switch (width) {
 414         case 256:
 415         case 128:
 416         case 64:
 417                 break;
 418         default:
 419                 return false;
 420         }
 421
 422         /*
 423          * IVB+ have CUR_FBC_CTL which allows an arbitrary cursor
 424          * height from 8 lines up to the cursor width, when the
 425          * cursor is not rotated. Everything else requires square
 426          * cursors.
 427          */
 428         if (HAS_CUR_FBC(dev_priv) &&
 429             plane_state->hw.rotation & DRM_MODE_ROTATE_0) {
 430                 if (height < 8 || height > width)
 431                         return false;
 432         } else {
 433                 if (height != width)
 434                         return false;
 435         }
 436
 437         return true;
 438 }
 439
 440 static int i9xx_check_cursor(struct intel_crtc_state *crtc_state,
 441                              struct intel_plane_state *plane_state)
 442 {
 443         struct intel_plane *plane = to_intel_plane(plane_state->uapi.plane);
 444         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 445         const struct drm_framebuffer *fb = plane_state->hw.fb;
 446         enum pipe pipe = plane->pipe;
 447         int ret;
 448
 449         ret = intel_check_cursor(crtc_state, plane_state);
 450         if (ret)
 451                 return ret;
 452
 453         /* if we want to turn off the cursor ignore width and height */
 454         if (!fb)
 455                 return 0;
 456
 457         /* Check for which cursor types we support */
 458         if (!i9xx_cursor_size_ok(plane_state)) {
 459                 drm_dbg(&dev_priv->drm,
 460                         "Cursor dimension %dx%d not supported\n",
 461                         drm_rect_width(&plane_state->uapi.dst),
 462                         drm_rect_height(&plane_state->uapi.dst));
 463                 return -EINVAL;
 464         }
 465
 466         drm_WARN_ON(&dev_priv->drm, plane_state->uapi.visible &&
 467                     plane_state->view.color_plane[0].mapping_stride != fb->pitches[0]);
 468
 469         if (fb->pitches[0] !=
 470             drm_rect_width(&plane_state->uapi.dst) * fb->format->cpp[0]) {
 471                 drm_dbg_kms(&dev_priv->drm,
 472                             "Invalid cursor stride (%u) (cursor width %d)\n",
 473                             fb->pitches[0],
 474                             drm_rect_width(&plane_state->uapi.dst));
 475                 return -EINVAL;
 476         }
 477
 478         /*
 479          * There's something wrong with the cursor on CHV pipe C.
 480          * If it straddles the left edge of the screen then
 481          * moving it away from the edge or disabling it often
 482          * results in a pipe underrun, and often that can lead to
 483          * dead pipe (constant underrun reported, and it scans
 484          * out just a solid color). To recover from that, the
 485          * display power well must be turned off and on again.
 486          * Refuse the put the cursor into that compromised position.
 487          */
 488         if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_C &&
 489             plane_state->uapi.visible && plane_state->uapi.dst.x1 < 0) {
 490                 drm_dbg_kms(&dev_priv->drm,
 491                             "CHV cursor C not allowed to straddle the left screen edge\n");
 492                 return -EINVAL;
 493         }
 494
 495         plane_state->ctl = i9xx_cursor_ctl(crtc_state, plane_state);
 496
 497         return 0;
 498 }
 499
 500 static void i9xx_cursor_disable_sel_fetch_arm(struct intel_plane *plane,
 501                                               const struct intel_crtc_state *crtc_state)
 502 {
 503         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 504         enum pipe pipe = plane->pipe;
 505
 506         if (!crtc_state->enable_psr2_sel_fetch)
 507                 return;
 508
 509         intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), 0);
 510 }
 511
 512 static void wa_16021440873(struct intel_plane *plane,
 513                            const struct intel_crtc_state *crtc_state,
 514                            const struct intel_plane_state *plane_state)
 515 {
 516         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 517         u32 ctl = plane_state->ctl;
 518         int et_y_position = drm_rect_height(&crtc_state->pipe_src) + 1;
 519         enum pipe pipe = plane->pipe;
 520
 521         ctl &= ~MCURSOR_MODE_MASK;
 522         ctl |= MCURSOR_MODE_64_2B;
 523
 524         intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id), ctl);
 525
 526         intel_de_write(dev_priv, PIPE_SRCSZ_ERLY_TPT(pipe),
 527                        PIPESRC_HEIGHT(et_y_position));
 528 }
 529
 530 static void i9xx_cursor_update_sel_fetch_arm(struct intel_plane *plane,
 531                                              const struct intel_crtc_state *crtc_state,
 532                                              const struct intel_plane_state *plane_state)
 533 {
 534         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 535         enum pipe pipe = plane->pipe;
 536
 537         if (!crtc_state->enable_psr2_sel_fetch)
 538                 return;
 539
 540         if (drm_rect_height(&plane_state->psr2_sel_fetch_area) > 0) {
 541                 if (crtc_state->enable_psr2_su_region_et) {
 542                         u32 val = intel_cursor_position(crtc_state, plane_state,
 543                                 true);
 544                         intel_de_write_fw(dev_priv, CURPOS_ERLY_TPT(pipe), val);
 545                 }
 546
 547                 intel_de_write_fw(dev_priv, PLANE_SEL_FETCH_CTL(pipe, plane->id),
 548                                   plane_state->ctl);
 549         } else {
 550                 /* Wa_16021440873 */
 551                 if (crtc_state->enable_psr2_su_region_et)
 552                         wa_16021440873(plane, crtc_state, plane_state);
 553                 else
 554                         i9xx_cursor_disable_sel_fetch_arm(plane, crtc_state);
 555         }
 556 }
 557
 558 /* TODO: split into noarm+arm pair */
 559 static void i9xx_cursor_update_arm(struct intel_plane *plane,
 560                                    const struct intel_crtc_state *crtc_state,
 561                                    const struct intel_plane_state *plane_state)
 562 {
 563         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 564         enum pipe pipe = plane->pipe;
 565         u32 cntl = 0, base = 0, pos = 0, fbc_ctl = 0;
 566
 567         if (plane_state && plane_state->uapi.visible) {
 568                 int width = drm_rect_width(&plane_state->uapi.dst);
 569                 int height = drm_rect_height(&plane_state->uapi.dst);
 570
 571                 cntl = plane_state->ctl |
 572                         i9xx_cursor_ctl_crtc(crtc_state);
 573
 574                 if (width != height)
 575                         fbc_ctl = CUR_FBC_EN | CUR_FBC_HEIGHT(height - 1);
 576
 577                 base = intel_cursor_base(plane_state);
 578                 pos = intel_cursor_position(crtc_state, plane_state, false);
 579         }
 580
 581         /*
 582          * On some platforms writing CURCNTR first will also
 583          * cause CURPOS to be armed by the CURBASE write.
 584          * Without the CURCNTR write the CURPOS write would
 585          * arm itself. Thus we always update CURCNTR before
 586          * CURPOS.
 587          *
 588          * On other platforms CURPOS always requires the
 589          * CURBASE write to arm the update. Additonally
 590          * a write to any of the cursor register will cancel
 591          * an already armed cursor update. Thus leaving out
 592          * the CURBASE write after CURPOS could lead to a
 593          * cursor that doesn't appear to move, or even change
 594          * shape. Thus we always write CURBASE.
 595          *
 596          * The other registers are armed by the CURBASE write
 597          * except when the plane is getting enabled at which time
 598          * the CURCNTR write arms the update.
 599          */
 600
 601         if (DISPLAY_VER(dev_priv) >= 9)
 602                 skl_write_cursor_wm(plane, crtc_state);
 603
 604         if (plane_state)
 605                 i9xx_cursor_update_sel_fetch_arm(plane, crtc_state,
 606                                                  plane_state);
 607         else
 608                 i9xx_cursor_disable_sel_fetch_arm(plane, crtc_state);
 609
 610         if (plane->cursor.base != base ||
 611             plane->cursor.size != fbc_ctl ||
 612             plane->cursor.cntl != cntl) {
 613                 if (HAS_CUR_FBC(dev_priv))
 614                         intel_de_write_fw(dev_priv, CUR_FBC_CTL(pipe),
 615                                           fbc_ctl);
 616                 intel_de_write_fw(dev_priv, CURCNTR(pipe), cntl);
 617                 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
 618                 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
 619
 620                 plane->cursor.base = base;
 621                 plane->cursor.size = fbc_ctl;
 622                 plane->cursor.cntl = cntl;
 623         } else {
 624                 intel_de_write_fw(dev_priv, CURPOS(pipe), pos);
 625                 intel_de_write_fw(dev_priv, CURBASE(pipe), base);
 626         }
 627 }
 628
 629 static void i9xx_cursor_disable_arm(struct intel_plane *plane,
 630                                     const struct intel_crtc_state *crtc_state)
 631 {
 632         i9xx_cursor_update_arm(plane, crtc_state, NULL);
 633 }
 634
 635 static bool i9xx_cursor_get_hw_state(struct intel_plane *plane,
 636                                      enum pipe *pipe)
 637 {
 638         struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
 639         enum intel_display_power_domain power_domain;
 640         intel_wakeref_t wakeref;
 641         bool ret;
 642         u32 val;
 643
 644         /*
 645          * Not 100% correct for planes that can move between pipes,
 646          * but that's only the case for gen2-3 which don't have any
 647          * display power wells.
 648          */
 649         power_domain = POWER_DOMAIN_PIPE(plane->pipe);
 650         wakeref = intel_display_power_get_if_enabled(dev_priv, power_domain);
 651         if (!wakeref)
 652                 return false;
 653
 654         val = intel_de_read(dev_priv, CURCNTR(plane->pipe));
 655
 656         ret = val & MCURSOR_MODE_MASK;
 657
 658         if (DISPLAY_VER(dev_priv) >= 5 || IS_G4X(dev_priv))
 659                 *pipe = plane->pipe;
 660         else
 661                 *pipe = REG_FIELD_GET(MCURSOR_PIPE_SEL_MASK, val);
 662
 663         intel_display_power_put(dev_priv, power_domain, wakeref);
 664
 665         return ret;
 666 }
 667
 668 static bool intel_cursor_format_mod_supported(struct drm_plane *_plane,
 669                                               u32 format, u64 modifier)
 670 {
 671         if (!intel_fb_plane_supports_modifier(to_intel_plane(_plane), modifier))
 672                 return false;
 673
 674         return format == DRM_FORMAT_ARGB8888;
 675 }
 676
 677 static int
 678 intel_legacy_cursor_update(struct drm_plane *_plane,
 679                            struct drm_crtc *_crtc,
 680                            struct drm_framebuffer *fb,
 681                            int crtc_x, int crtc_y,
 682                            unsigned int crtc_w, unsigned int crtc_h,
 683                            u32 src_x, u32 src_y,
 684                            u32 src_w, u32 src_h,
 685                            struct drm_modeset_acquire_ctx *ctx)
 686 {
 687         struct intel_plane *plane = to_intel_plane(_plane);
 688         struct intel_crtc *crtc = to_intel_crtc(_crtc);
 689         struct drm_i915_private *i915 = to_i915(plane->base.dev);
 690         struct intel_plane_state *old_plane_state =
 691                 to_intel_plane_state(plane->base.state);
 692         struct intel_plane_state *new_plane_state;
 693         struct intel_crtc_state *crtc_state =
 694                 to_intel_crtc_state(crtc->base.state);
 695         struct intel_crtc_state *new_crtc_state;
 696         struct intel_vblank_evade_ctx evade;
 697         int ret;
 698
 699         /*
 700          * When crtc is inactive or there is a modeset pending,
 701          * wait for it to complete in the slowpath.
 702          * PSR2 selective fetch also requires the slow path as
 703          * PSR2 plane and transcoder registers can only be updated during
 704          * vblank.
 705          *
 706          * FIXME bigjoiner fastpath would be good
 707          */
 708         if (!crtc_state->hw.active ||
 709             intel_crtc_needs_modeset(crtc_state) ||
 710             intel_crtc_needs_fastset(crtc_state) ||
 711             crtc_state->bigjoiner_pipes)
 712                 goto slow;
 713
 714         /*
 715          * Don't do an async update if there is an outstanding commit modifying
 716          * the plane.  This prevents our async update's changes from getting
 717          * overridden by a previous synchronous update's state.
 718          */
 719         if (old_plane_state->uapi.commit &&
 720             !try_wait_for_completion(&old_plane_state->uapi.commit->hw_done))
 721                 goto slow;
 722
 723         /*
 724          * If any parameters change that may affect watermarks,
 725          * take the slowpath. Only changing fb or position should be
 726          * in the fastpath.
 727          */
 728         if (old_plane_state->uapi.crtc != &crtc->base ||
 729             old_plane_state->uapi.src_w != src_w ||
 730             old_plane_state->uapi.src_h != src_h ||
 731             old_plane_state->uapi.crtc_w != crtc_w ||
 732             old_plane_state->uapi.crtc_h != crtc_h ||
 733             !old_plane_state->uapi.fb != !fb)
 734                 goto slow;
 735
 736         new_plane_state = to_intel_plane_state(intel_plane_duplicate_state(&plane->base));
 737         if (!new_plane_state)
 738                 return -ENOMEM;
 739
 740         new_crtc_state = to_intel_crtc_state(intel_crtc_duplicate_state(&crtc->base));
 741         if (!new_crtc_state) {
 742                 ret = -ENOMEM;
 743                 goto out_free;
 744         }
 745
 746         drm_atomic_set_fb_for_plane(&new_plane_state->uapi, fb);
 747
 748         new_plane_state->uapi.src_x = src_x;
 749         new_plane_state->uapi.src_y = src_y;
 750         new_plane_state->uapi.src_w = src_w;
 751         new_plane_state->uapi.src_h = src_h;
 752         new_plane_state->uapi.crtc_x = crtc_x;
 753         new_plane_state->uapi.crtc_y = crtc_y;
 754         new_plane_state->uapi.crtc_w = crtc_w;
 755         new_plane_state->uapi.crtc_h = crtc_h;
 756
 757         intel_plane_copy_uapi_to_hw_state(new_plane_state, new_plane_state, crtc);
 758
 759         ret = intel_plane_atomic_check_with_state(crtc_state, new_crtc_state,
 760                                                   old_plane_state, new_plane_state);
 761         if (ret)
 762                 goto out_free;
 763
 764         ret = intel_plane_pin_fb(new_plane_state);
 765         if (ret)
 766                 goto out_free;
 767
 768         intel_frontbuffer_flush(to_intel_frontbuffer(new_plane_state->hw.fb),
 769                                 ORIGIN_CURSOR_UPDATE);
 770         intel_frontbuffer_track(to_intel_frontbuffer(old_plane_state->hw.fb),
 771                                 to_intel_frontbuffer(new_plane_state->hw.fb),
 772                                 plane->frontbuffer_bit);
 773
 774         /* Swap plane state */
 775         plane->base.state = &new_plane_state->uapi;
 776
 777         /*
 778          * We cannot swap crtc_state as it may be in use by an atomic commit or
 779          * page flip that's running simultaneously. If we swap crtc_state and
 780          * destroy the old state, we will cause a use-after-free there.
 781          *
 782          * Only update active_planes, which is needed for our internal
 783          * bookkeeping. Either value will do the right thing when updating
 784          * planes atomically. If the cursor was part of the atomic update then
 785          * we would have taken the slowpath.
 786          */
 787         crtc_state->active_planes = new_crtc_state->active_planes;
 788
 789         intel_vblank_evade_init(crtc_state, crtc_state, &evade);
 790
 791         intel_psr_lock(crtc_state);
 792
 793         if (!drm_WARN_ON(&i915->drm, drm_crtc_vblank_get(&crtc->base))) {
 794                 /*
 795                  * TODO: maybe check if we're still in PSR
 796                  * and skip the vblank evasion entirely?
 797                  */
 798                 intel_psr_wait_for_idle_locked(crtc_state);
 799
 800                 local_irq_disable();
 801
 802                 intel_vblank_evade(&evade);
 803
 804                 drm_crtc_vblank_put(&crtc->base);
 805         } else {
 806                 local_irq_disable();
 807         }
 808
 809         if (new_plane_state->uapi.visible) {
 810                 intel_plane_update_noarm(plane, crtc_state, new_plane_state);
 811                 intel_plane_update_arm(plane, crtc_state, new_plane_state);
 812         } else {
 813                 intel_plane_disable_arm(plane, crtc_state);
 814         }
 815
 816         local_irq_enable();
 817
 818         intel_psr_unlock(crtc_state);
 819
 820         intel_plane_unpin_fb(old_plane_state);
 821
 822 out_free:
 823         if (new_crtc_state)
 824                 intel_crtc_destroy_state(&crtc->base, &new_crtc_state->uapi);
 825         if (ret)
 826                 intel_plane_destroy_state(&plane->base, &new_plane_state->uapi);
 827         else
 828                 intel_plane_destroy_state(&plane->base, &old_plane_state->uapi);
 829         return ret;
 830
 831 slow:
 832         return drm_atomic_helper_update_plane(&plane->base, &crtc->base, fb,
 833                                               crtc_x, crtc_y, crtc_w, crtc_h,
 834                                               src_x, src_y, src_w, src_h, ctx);
 835 }
 836
 837 static const struct drm_plane_funcs intel_cursor_plane_funcs = {
 838         .update_plane = intel_legacy_cursor_update,
 839         .disable_plane = drm_atomic_helper_disable_plane,
 840         .destroy = intel_plane_destroy,
 841         .atomic_duplicate_state = intel_plane_duplicate_state,
 842         .atomic_destroy_state = intel_plane_destroy_state,
 843         .format_mod_supported = intel_cursor_format_mod_supported,
 844 };
 845
 846 static void intel_cursor_add_size_hints_property(struct intel_plane *plane)
 847 {
 848         struct drm_i915_private *i915 = to_i915(plane->base.dev);
 849         const struct drm_mode_config *config = &i915->drm.mode_config;
 850         struct drm_plane_size_hint hints[4];
 851         int size, max_size, num_hints = 0;
 852
 853         max_size = min(config->cursor_width, config->cursor_height);
 854
 855         /* for simplicity only enumerate the supported square+POT sizes */
 856         for (size = 64; size <= max_size; size *= 2) {
 857                 if (drm_WARN_ON(&i915->drm, num_hints >= ARRAY_SIZE(hints)))
 858                         break;
 859
 860                 hints[num_hints].width = size;
 861                 hints[num_hints].height = size;
 862                 num_hints++;
 863         }
 864
 865         drm_plane_add_size_hints_property(&plane->base, hints, num_hints);
 866 }
 867
 868 struct intel_plane *
 869 intel_cursor_plane_create(struct drm_i915_private *dev_priv,
 870                           enum pipe pipe)
 871 {
 872         struct intel_plane *cursor;
 873         int ret, zpos;
 874         u64 *modifiers;
 875
 876         cursor = intel_plane_alloc();
 877         if (IS_ERR(cursor))
 878                 return cursor;
 879
 880         cursor->pipe = pipe;
 881         cursor->i9xx_plane = (enum i9xx_plane_id) pipe;
 882         cursor->id = PLANE_CURSOR;
 883         cursor->frontbuffer_bit = INTEL_FRONTBUFFER(pipe, cursor->id);
 884
 885         if (IS_I845G(dev_priv) || IS_I865G(dev_priv)) {
 886                 cursor->max_stride = i845_cursor_max_stride;
 887                 cursor->update_arm = i845_cursor_update_arm;
 888                 cursor->disable_arm = i845_cursor_disable_arm;
 889                 cursor->get_hw_state = i845_cursor_get_hw_state;
 890                 cursor->check_plane = i845_check_cursor;
 891         } else {
 892                 cursor->max_stride = i9xx_cursor_max_stride;
 893                 cursor->update_arm = i9xx_cursor_update_arm;
 894                 cursor->disable_arm = i9xx_cursor_disable_arm;
 895                 cursor->get_hw_state = i9xx_cursor_get_hw_state;
 896                 cursor->check_plane = i9xx_check_cursor;
 897         }
 898
 899         cursor->cursor.base = ~0;
 900         cursor->cursor.cntl = ~0;
 901
 902         if (IS_I845G(dev_priv) || IS_I865G(dev_priv) || HAS_CUR_FBC(dev_priv))
 903                 cursor->cursor.size = ~0;
 904
 905         modifiers = intel_fb_plane_get_modifiers(dev_priv, INTEL_PLANE_CAP_NONE);
 906
 907         ret = drm_universal_plane_init(&dev_priv->drm, &cursor->base,
 908                                        0, &intel_cursor_plane_funcs,
 909                                        intel_cursor_formats,
 910                                        ARRAY_SIZE(intel_cursor_formats),
 911                                        modifiers,
 912                                        DRM_PLANE_TYPE_CURSOR,
 913                                        "cursor %c", pipe_name(pipe));
 914
 915         kfree(modifiers);
 916
 917         if (ret)
 918                 goto fail;
 919
 920         if (DISPLAY_VER(dev_priv) >= 4)
 921                 drm_plane_create_rotation_property(&cursor->base,
 922                                                    DRM_MODE_ROTATE_0,
 923                                                    DRM_MODE_ROTATE_0 |
 924                                                    DRM_MODE_ROTATE_180);
 925
 926         intel_cursor_add_size_hints_property(cursor);
 927
 928         zpos = DISPLAY_RUNTIME_INFO(dev_priv)->num_sprites[pipe] + 1;
 929         drm_plane_create_zpos_immutable_property(&cursor->base, zpos);
 930
 931         if (DISPLAY_VER(dev_priv) >= 12)
 932                 drm_plane_enable_fb_damage_clips(&cursor->base);
 933
 934         intel_plane_helper_add(cursor);
 935
 936         return cursor;
 937
 938 fail:
 939         intel_plane_free(cursor);
 940
 941         return ERR_PTR(ret);
 942 }