drivers/gpu/drm/i915/display/intel_crt.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <[email protected]>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30
  31 #include <drm/drm_atomic_helper.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_edid.h>
  34 #include <drm/drm_probe_helper.h>
  35
  36 #include "i915_drv.h"
  37 #include "i915_irq.h"
  38 #include "i915_reg.h"
  39 #include "intel_connector.h"
  40 #include "intel_crt.h"
  41 #include "intel_crtc.h"
  42 #include "intel_ddi.h"
  43 #include "intel_ddi_buf_trans.h"
  44 #include "intel_de.h"
  45 #include "intel_display_driver.h"
  46 #include "intel_display_types.h"
  47 #include "intel_fdi.h"
  48 #include "intel_fdi_regs.h"
  49 #include "intel_fifo_underrun.h"
  50 #include "intel_gmbus.h"
  51 #include "intel_hotplug.h"
  52 #include "intel_hotplug_irq.h"
  53 #include "intel_load_detect.h"
  54 #include "intel_pch_display.h"
  55 #include "intel_pch_refclk.h"
  56
  57 /* Here's the desired hotplug mode */
  58 #define ADPA_HOTPLUG_BITS (ADPA_CRT_HOTPLUG_PERIOD_128 |                \
  59                            ADPA_CRT_HOTPLUG_WARMUP_10MS |               \
  60                            ADPA_CRT_HOTPLUG_SAMPLE_4S |                 \
  61                            ADPA_CRT_HOTPLUG_VOLTAGE_50 |                \
  62                            ADPA_CRT_HOTPLUG_VOLREF_325MV |              \
  63                            ADPA_CRT_HOTPLUG_ENABLE)
  64
  65 struct intel_crt {
  66         struct intel_encoder base;
  67         /* DPMS state is stored in the connector, which we need in the
  68          * encoder's enable/disable callbacks */
  69         struct intel_connector *connector;
  70         bool force_hotplug_required;
  71         i915_reg_t adpa_reg;
  72 };
  73
  74 static struct intel_crt *intel_encoder_to_crt(struct intel_encoder *encoder)
  75 {
  76         return container_of(encoder, struct intel_crt, base);
  77 }
  78
  79 static struct intel_crt *intel_attached_crt(struct intel_connector *connector)
  80 {
  81         return intel_encoder_to_crt(intel_attached_encoder(connector));
  82 }
  83
  84 bool intel_crt_port_enabled(struct drm_i915_private *dev_priv,
  85                             i915_reg_t adpa_reg, enum pipe *pipe)
  86 {
  87         u32 val;
  88
  89         val = intel_de_read(dev_priv, adpa_reg);
  90
  91         /* asserts want to know the pipe even if the port is disabled */
  92         if (HAS_PCH_CPT(dev_priv))
  93                 *pipe = (val & ADPA_PIPE_SEL_MASK_CPT) >> ADPA_PIPE_SEL_SHIFT_CPT;
  94         else
  95                 *pipe = (val & ADPA_PIPE_SEL_MASK) >> ADPA_PIPE_SEL_SHIFT;
  96
  97         return val & ADPA_DAC_ENABLE;
  98 }
  99
 100 static bool intel_crt_get_hw_state(struct intel_encoder *encoder,
 101                                    enum pipe *pipe)
 102 {
 103         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 104         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 105         intel_wakeref_t wakeref;
 106         bool ret;
 107
 108         wakeref = intel_display_power_get_if_enabled(dev_priv,
 109                                                      encoder->power_domain);
 110         if (!wakeref)
 111                 return false;
 112
 113         ret = intel_crt_port_enabled(dev_priv, crt->adpa_reg, pipe);
 114
 115         intel_display_power_put(dev_priv, encoder->power_domain, wakeref);
 116
 117         return ret;
 118 }
 119
 120 static unsigned int intel_crt_get_flags(struct intel_encoder *encoder)
 121 {
 122         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 123         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 124         u32 tmp, flags = 0;
 125
 126         tmp = intel_de_read(dev_priv, crt->adpa_reg);
 127
 128         if (tmp & ADPA_HSYNC_ACTIVE_HIGH)
 129                 flags |= DRM_MODE_FLAG_PHSYNC;
 130         else
 131                 flags |= DRM_MODE_FLAG_NHSYNC;
 132
 133         if (tmp & ADPA_VSYNC_ACTIVE_HIGH)
 134                 flags |= DRM_MODE_FLAG_PVSYNC;
 135         else
 136                 flags |= DRM_MODE_FLAG_NVSYNC;
 137
 138         return flags;
 139 }
 140
 141 static void intel_crt_get_config(struct intel_encoder *encoder,
 142                                  struct intel_crtc_state *pipe_config)
 143 {
 144         pipe_config->output_types |= BIT(INTEL_OUTPUT_ANALOG);
 145
 146         pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 147
 148         pipe_config->hw.adjusted_mode.crtc_clock = pipe_config->port_clock;
 149 }
 150
 151 static void hsw_crt_get_config(struct intel_encoder *encoder,
 152                                struct intel_crtc_state *pipe_config)
 153 {
 154         lpt_pch_get_config(pipe_config);
 155
 156         hsw_ddi_get_config(encoder, pipe_config);
 157
 158         pipe_config->hw.adjusted_mode.flags &= ~(DRM_MODE_FLAG_PHSYNC |
 159                                               DRM_MODE_FLAG_NHSYNC |
 160                                               DRM_MODE_FLAG_PVSYNC |
 161                                               DRM_MODE_FLAG_NVSYNC);
 162         pipe_config->hw.adjusted_mode.flags |= intel_crt_get_flags(encoder);
 163 }
 164
 165 /* Note: The caller is required to filter out dpms modes not supported by the
 166  * platform. */
 167 static void intel_crt_set_dpms(struct intel_encoder *encoder,
 168                                const struct intel_crtc_state *crtc_state,
 169                                int mode)
 170 {
 171         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 172         struct intel_crt *crt = intel_encoder_to_crt(encoder);
 173         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 174         const struct drm_display_mode *adjusted_mode = &crtc_state->hw.adjusted_mode;
 175         u32 adpa;
 176
 177         if (DISPLAY_VER(dev_priv) >= 5)
 178                 adpa = ADPA_HOTPLUG_BITS;
 179         else
 180                 adpa = 0;
 181
 182         if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 183                 adpa |= ADPA_HSYNC_ACTIVE_HIGH;
 184         if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 185                 adpa |= ADPA_VSYNC_ACTIVE_HIGH;
 186
 187         /* For CPT allow 3 pipe config, for others just use A or B */
 188         if (HAS_PCH_LPT(dev_priv))
 189                 ; /* Those bits don't exist here */
 190         else if (HAS_PCH_CPT(dev_priv))
 191                 adpa |= ADPA_PIPE_SEL_CPT(crtc->pipe);
 192         else
 193                 adpa |= ADPA_PIPE_SEL(crtc->pipe);
 194
 195         if (!HAS_PCH_SPLIT(dev_priv))
 196                 intel_de_write(dev_priv, BCLRPAT(crtc->pipe), 0);
 197
 198         switch (mode) {
 199         case DRM_MODE_DPMS_ON:
 200                 adpa |= ADPA_DAC_ENABLE;
 201                 break;
 202         case DRM_MODE_DPMS_STANDBY:
 203                 adpa |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
 204                 break;
 205         case DRM_MODE_DPMS_SUSPEND:
 206                 adpa |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
 207                 break;
 208         case DRM_MODE_DPMS_OFF:
 209                 adpa |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
 210                 break;
 211         }
 212
 213         intel_de_write(dev_priv, crt->adpa_reg, adpa);
 214 }
 215
 216 static void intel_disable_crt(struct intel_atomic_state *state,
 217                               struct intel_encoder *encoder,
 218                               const struct intel_crtc_state *old_crtc_state,
 219                               const struct drm_connector_state *old_conn_state)
 220 {
 221         intel_crt_set_dpms(encoder, old_crtc_state, DRM_MODE_DPMS_OFF);
 222 }
 223
 224 static void pch_disable_crt(struct intel_atomic_state *state,
 225                             struct intel_encoder *encoder,
 226                             const struct intel_crtc_state *old_crtc_state,
 227                             const struct drm_connector_state *old_conn_state)
 228 {
 229 }
 230
 231 static void pch_post_disable_crt(struct intel_atomic_state *state,
 232                                  struct intel_encoder *encoder,
 233                                  const struct intel_crtc_state *old_crtc_state,
 234                                  const struct drm_connector_state *old_conn_state)
 235 {
 236         intel_disable_crt(state, encoder, old_crtc_state, old_conn_state);
 237 }
 238
 239 static void hsw_disable_crt(struct intel_atomic_state *state,
 240                             struct intel_encoder *encoder,
 241                             const struct intel_crtc_state *old_crtc_state,
 242                             const struct drm_connector_state *old_conn_state)
 243 {
 244         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 245
 246         drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
 247
 248         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
 249 }
 250
 251 static void hsw_post_disable_crt(struct intel_atomic_state *state,
 252                                  struct intel_encoder *encoder,
 253                                  const struct intel_crtc_state *old_crtc_state,
 254                                  const struct drm_connector_state *old_conn_state)
 255 {
 256         struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
 257         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 258
 259         intel_crtc_vblank_off(old_crtc_state);
 260
 261         intel_disable_transcoder(old_crtc_state);
 262
 263         intel_ddi_disable_transcoder_func(old_crtc_state);
 264
 265         ilk_pfit_disable(old_crtc_state);
 266
 267         intel_ddi_disable_transcoder_clock(old_crtc_state);
 268
 269         pch_post_disable_crt(state, encoder, old_crtc_state, old_conn_state);
 270
 271         lpt_pch_disable(state, crtc);
 272
 273         hsw_fdi_disable(encoder);
 274
 275         drm_WARN_ON(&dev_priv->drm, !old_crtc_state->has_pch_encoder);
 276
 277         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
 278 }
 279
 280 static void hsw_pre_pll_enable_crt(struct intel_atomic_state *state,
 281                                    struct intel_encoder *encoder,
 282                                    const struct intel_crtc_state *crtc_state,
 283                                    const struct drm_connector_state *conn_state)
 284 {
 285         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 286
 287         drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
 288
 289         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
 290 }
 291
 292 static void hsw_pre_enable_crt(struct intel_atomic_state *state,
 293                                struct intel_encoder *encoder,
 294                                const struct intel_crtc_state *crtc_state,
 295                                const struct drm_connector_state *conn_state)
 296 {
 297         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 298         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 299         enum pipe pipe = crtc->pipe;
 300
 301         drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
 302
 303         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
 304
 305         hsw_fdi_link_train(encoder, crtc_state);
 306
 307         intel_ddi_enable_transcoder_clock(encoder, crtc_state);
 308 }
 309
 310 static void hsw_enable_crt(struct intel_atomic_state *state,
 311                            struct intel_encoder *encoder,
 312                            const struct intel_crtc_state *crtc_state,
 313                            const struct drm_connector_state *conn_state)
 314 {
 315         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 316         struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
 317         enum pipe pipe = crtc->pipe;
 318
 319         drm_WARN_ON(&dev_priv->drm, !crtc_state->has_pch_encoder);
 320
 321         intel_ddi_enable_transcoder_func(encoder, crtc_state);
 322
 323         intel_enable_transcoder(crtc_state);
 324
 325         lpt_pch_enable(state, crtc);
 326
 327         intel_crtc_vblank_on(crtc_state);
 328
 329         intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
 330
 331         intel_crtc_wait_for_next_vblank(crtc);
 332         intel_crtc_wait_for_next_vblank(crtc);
 333         intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
 334         intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
 335 }
 336
 337 static void intel_enable_crt(struct intel_atomic_state *state,
 338                              struct intel_encoder *encoder,
 339                              const struct intel_crtc_state *crtc_state,
 340                              const struct drm_connector_state *conn_state)
 341 {
 342         intel_crt_set_dpms(encoder, crtc_state, DRM_MODE_DPMS_ON);
 343 }
 344
 345 static enum drm_mode_status
 346 intel_crt_mode_valid(struct drm_connector *connector,
 347                      struct drm_display_mode *mode)
 348 {
 349         struct drm_device *dev = connector->dev;
 350         struct drm_i915_private *dev_priv = to_i915(dev);
 351         int max_dotclk = dev_priv->display.cdclk.max_dotclk_freq;
 352         enum drm_mode_status status;
 353         int max_clock;
 354
 355         status = intel_cpu_transcoder_mode_valid(dev_priv, mode);
 356         if (status != MODE_OK)
 357                 return status;
 358
 359         if (mode->clock < 25000)
 360                 return MODE_CLOCK_LOW;
 361
 362         if (HAS_PCH_LPT(dev_priv))
 363                 max_clock = 180000;
 364         else if (IS_VALLEYVIEW(dev_priv))
 365                 /*
 366                  * 270 MHz due to current DPLL limits,
 367                  * DAC limit supposedly 355 MHz.
 368                  */
 369                 max_clock = 270000;
 370         else if (IS_DISPLAY_VER(dev_priv, 3, 4))
 371                 max_clock = 400000;
 372         else
 373                 max_clock = 350000;
 374         if (mode->clock > max_clock)
 375                 return MODE_CLOCK_HIGH;
 376
 377         if (mode->clock > max_dotclk)
 378                 return MODE_CLOCK_HIGH;
 379
 380         /* The FDI receiver on LPT only supports 8bpc and only has 2 lanes. */
 381         if (HAS_PCH_LPT(dev_priv) &&
 382             ilk_get_lanes_required(mode->clock, 270000, 24) > 2)
 383                 return MODE_CLOCK_HIGH;
 384
 385         /* HSW/BDW FDI limited to 4k */
 386         if (mode->hdisplay > 4096)
 387                 return MODE_H_ILLEGAL;
 388
 389         return MODE_OK;
 390 }
 391
 392 static int intel_crt_compute_config(struct intel_encoder *encoder,
 393                                     struct intel_crtc_state *pipe_config,
 394                                     struct drm_connector_state *conn_state)
 395 {
 396         struct drm_display_mode *adjusted_mode =
 397                 &pipe_config->hw.adjusted_mode;
 398
 399         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 400                 return -EINVAL;
 401
 402         pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
 403         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 404
 405         return 0;
 406 }
 407
 408 static int pch_crt_compute_config(struct intel_encoder *encoder,
 409                                   struct intel_crtc_state *pipe_config,
 410                                   struct drm_connector_state *conn_state)
 411 {
 412         struct drm_display_mode *adjusted_mode =
 413                 &pipe_config->hw.adjusted_mode;
 414
 415         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 416                 return -EINVAL;
 417
 418         pipe_config->has_pch_encoder = true;
 419         if (!intel_fdi_compute_pipe_bpp(pipe_config))
 420                 return -EINVAL;
 421
 422         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 423
 424         return 0;
 425 }
 426
 427 static int hsw_crt_compute_config(struct intel_encoder *encoder,
 428                                   struct intel_crtc_state *pipe_config,
 429                                   struct drm_connector_state *conn_state)
 430 {
 431         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
 432         struct drm_display_mode *adjusted_mode =
 433                 &pipe_config->hw.adjusted_mode;
 434
 435         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
 436                 return -EINVAL;
 437
 438         /* HSW/BDW FDI limited to 4k */
 439         if (adjusted_mode->crtc_hdisplay > 4096 ||
 440             adjusted_mode->crtc_hblank_start > 4096)
 441                 return -EINVAL;
 442
 443         pipe_config->has_pch_encoder = true;
 444         if (!intel_fdi_compute_pipe_bpp(pipe_config))
 445                 return -EINVAL;
 446
 447         pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
 448
 449         /* LPT FDI RX only supports 8bpc. */
 450         if (HAS_PCH_LPT(dev_priv)) {
 451                 /* TODO: Check crtc_state->max_link_bpp_x16 instead of bw_constrained */
 452                 if (pipe_config->bw_constrained && pipe_config->pipe_bpp < 24) {
 453                         drm_dbg_kms(&dev_priv->drm,
 454                                     "LPT only supports 24bpp\n");
 455                         return -EINVAL;
 456                 }
 457
 458                 pipe_config->pipe_bpp = 24;
 459         }
 460
 461         /* FDI must always be 2.7 GHz */
 462         pipe_config->port_clock = 135000 * 2;
 463
 464         pipe_config->enhanced_framing = true;
 465
 466         adjusted_mode->crtc_clock = lpt_iclkip(pipe_config);
 467
 468         return 0;
 469 }
 470
 471 static bool ilk_crt_detect_hotplug(struct drm_connector *connector)
 472 {
 473         struct drm_device *dev = connector->dev;
 474         struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
 475         struct drm_i915_private *dev_priv = to_i915(dev);
 476         u32 adpa;
 477         bool ret;
 478
 479         /* The first time through, trigger an explicit detection cycle */
 480         if (crt->force_hotplug_required) {
 481                 bool turn_off_dac = HAS_PCH_SPLIT(dev_priv);
 482                 u32 save_adpa;
 483
 484                 crt->force_hotplug_required = false;
 485
 486                 save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
 487                 drm_dbg_kms(&dev_priv->drm,
 488                             "trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 489
 490                 adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 491                 if (turn_off_dac)
 492                         adpa &= ~ADPA_DAC_ENABLE;
 493
 494                 intel_de_write(dev_priv, crt->adpa_reg, adpa);
 495
 496                 if (intel_de_wait_for_clear(dev_priv,
 497                                             crt->adpa_reg,
 498                                             ADPA_CRT_HOTPLUG_FORCE_TRIGGER,
 499                                             1000))
 500                         drm_dbg_kms(&dev_priv->drm,
 501                                     "timed out waiting for FORCE_TRIGGER");
 502
 503                 if (turn_off_dac) {
 504                         intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
 505                         intel_de_posting_read(dev_priv, crt->adpa_reg);
 506                 }
 507         }
 508
 509         /* Check the status to see if both blue and green are on now */
 510         adpa = intel_de_read(dev_priv, crt->adpa_reg);
 511         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 512                 ret = true;
 513         else
 514                 ret = false;
 515         drm_dbg_kms(&dev_priv->drm, "ironlake hotplug adpa=0x%x, result %d\n",
 516                     adpa, ret);
 517
 518         return ret;
 519 }
 520
 521 static bool valleyview_crt_detect_hotplug(struct drm_connector *connector)
 522 {
 523         struct drm_device *dev = connector->dev;
 524         struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
 525         struct drm_i915_private *dev_priv = to_i915(dev);
 526         bool reenable_hpd;
 527         u32 adpa;
 528         bool ret;
 529         u32 save_adpa;
 530
 531         /*
 532          * Doing a force trigger causes a hpd interrupt to get sent, which can
 533          * get us stuck in a loop if we're polling:
 534          *  - We enable power wells and reset the ADPA
 535          *  - output_poll_exec does force probe on VGA, triggering a hpd
 536          *  - HPD handler waits for poll to unlock dev->mode_config.mutex
 537          *  - output_poll_exec shuts off the ADPA, unlocks
 538          *    dev->mode_config.mutex
 539          *  - HPD handler runs, resets ADPA and brings us back to the start
 540          *
 541          * Just disable HPD interrupts here to prevent this
 542          */
 543         reenable_hpd = intel_hpd_disable(dev_priv, crt->base.hpd_pin);
 544
 545         save_adpa = adpa = intel_de_read(dev_priv, crt->adpa_reg);
 546         drm_dbg_kms(&dev_priv->drm,
 547                     "trigger hotplug detect cycle: adpa=0x%x\n", adpa);
 548
 549         adpa |= ADPA_CRT_HOTPLUG_FORCE_TRIGGER;
 550
 551         intel_de_write(dev_priv, crt->adpa_reg, adpa);
 552
 553         if (intel_de_wait_for_clear(dev_priv, crt->adpa_reg,
 554                                     ADPA_CRT_HOTPLUG_FORCE_TRIGGER, 1000)) {
 555                 drm_dbg_kms(&dev_priv->drm,
 556                             "timed out waiting for FORCE_TRIGGER");
 557                 intel_de_write(dev_priv, crt->adpa_reg, save_adpa);
 558         }
 559
 560         /* Check the status to see if both blue and green are on now */
 561         adpa = intel_de_read(dev_priv, crt->adpa_reg);
 562         if ((adpa & ADPA_CRT_HOTPLUG_MONITOR_MASK) != 0)
 563                 ret = true;
 564         else
 565                 ret = false;
 566
 567         drm_dbg_kms(&dev_priv->drm,
 568                     "valleyview hotplug adpa=0x%x, result %d\n", adpa, ret);
 569
 570         if (reenable_hpd)
 571                 intel_hpd_enable(dev_priv, crt->base.hpd_pin);
 572
 573         return ret;
 574 }
 575
 576 static bool intel_crt_detect_hotplug(struct drm_connector *connector)
 577 {
 578         struct drm_device *dev = connector->dev;
 579         struct drm_i915_private *dev_priv = to_i915(dev);
 580         u32 stat;
 581         bool ret = false;
 582         int i, tries = 0;
 583
 584         if (HAS_PCH_SPLIT(dev_priv))
 585                 return ilk_crt_detect_hotplug(connector);
 586
 587         if (IS_VALLEYVIEW(dev_priv))
 588                 return valleyview_crt_detect_hotplug(connector);
 589
 590         /*
 591          * On 4 series desktop, CRT detect sequence need to be done twice
 592          * to get a reliable result.
 593          */
 594
 595         if (IS_G45(dev_priv))
 596                 tries = 2;
 597         else
 598                 tries = 1;
 599
 600         for (i = 0; i < tries ; i++) {
 601                 /* turn on the FORCE_DETECT */
 602                 i915_hotplug_interrupt_update(dev_priv,
 603                                               CRT_HOTPLUG_FORCE_DETECT,
 604                                               CRT_HOTPLUG_FORCE_DETECT);
 605                 /* wait for FORCE_DETECT to go off */
 606                 if (intel_de_wait_for_clear(dev_priv, PORT_HOTPLUG_EN,
 607                                             CRT_HOTPLUG_FORCE_DETECT, 1000))
 608                         drm_dbg_kms(&dev_priv->drm,
 609                                     "timed out waiting for FORCE_DETECT to go off");
 610         }
 611
 612         stat = intel_de_read(dev_priv, PORT_HOTPLUG_STAT);
 613         if ((stat & CRT_HOTPLUG_MONITOR_MASK) != CRT_HOTPLUG_MONITOR_NONE)
 614                 ret = true;
 615
 616         /* clear the interrupt we just generated, if any */
 617         intel_de_write(dev_priv, PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
 618
 619         i915_hotplug_interrupt_update(dev_priv, CRT_HOTPLUG_FORCE_DETECT, 0);
 620
 621         return ret;
 622 }
 623
 624 static const struct drm_edid *intel_crt_get_edid(struct drm_connector *connector,
 625                                                  struct i2c_adapter *ddc)
 626 {
 627         const struct drm_edid *drm_edid;
 628
 629         drm_edid = drm_edid_read_ddc(connector, ddc);
 630
 631         if (!drm_edid && !intel_gmbus_is_forced_bit(ddc)) {
 632                 drm_dbg_kms(connector->dev,
 633                             "CRT GMBUS EDID read failed, retry using GPIO bit-banging\n");
 634                 intel_gmbus_force_bit(ddc, true);
 635                 drm_edid = drm_edid_read_ddc(connector, ddc);
 636                 intel_gmbus_force_bit(ddc, false);
 637         }
 638
 639         return drm_edid;
 640 }
 641
 642 /* local version of intel_ddc_get_modes() to use intel_crt_get_edid() */
 643 static int intel_crt_ddc_get_modes(struct drm_connector *connector,
 644                                    struct i2c_adapter *ddc)
 645 {
 646         const struct drm_edid *drm_edid;
 647         int ret;
 648
 649         drm_edid = intel_crt_get_edid(connector, ddc);
 650         if (!drm_edid)
 651                 return 0;
 652
 653         ret = intel_connector_update_modes(connector, drm_edid);
 654
 655         drm_edid_free(drm_edid);
 656
 657         return ret;
 658 }
 659
 660 static bool intel_crt_detect_ddc(struct drm_connector *connector)
 661 {
 662         struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
 663         struct drm_i915_private *dev_priv = to_i915(crt->base.base.dev);
 664         const struct drm_edid *drm_edid;
 665         bool ret = false;
 666
 667         drm_edid = intel_crt_get_edid(connector, connector->ddc);
 668
 669         if (drm_edid) {
 670                 /*
 671                  * This may be a DVI-I connector with a shared DDC
 672                  * link between analog and digital outputs, so we
 673                  * have to check the EDID input spec of the attached device.
 674                  */
 675                 if (drm_edid_is_digital(drm_edid)) {
 676                         drm_dbg_kms(&dev_priv->drm,
 677                                     "CRT not detected via DDC:0x50 [EDID reports a digital panel]\n");
 678                 } else {
 679                         drm_dbg_kms(&dev_priv->drm,
 680                                     "CRT detected via DDC:0x50 [EDID]\n");
 681                         ret = true;
 682                 }
 683         } else {
 684                 drm_dbg_kms(&dev_priv->drm,
 685                             "CRT not detected via DDC:0x50 [no valid EDID found]\n");
 686         }
 687
 688         drm_edid_free(drm_edid);
 689
 690         return ret;
 691 }
 692
 693 static enum drm_connector_status
 694 intel_crt_load_detect(struct intel_crt *crt, enum pipe pipe)
 695 {
 696         struct drm_device *dev = crt->base.base.dev;
 697         struct drm_i915_private *dev_priv = to_i915(dev);
 698         enum transcoder cpu_transcoder = (enum transcoder)pipe;
 699         u32 save_bclrpat;
 700         u32 save_vtotal;
 701         u32 vtotal, vactive;
 702         u32 vsample;
 703         u32 vblank, vblank_start, vblank_end;
 704         u32 dsl;
 705         u8 st00;
 706         enum drm_connector_status status;
 707
 708         drm_dbg_kms(&dev_priv->drm, "starting load-detect on CRT\n");
 709
 710         save_bclrpat = intel_de_read(dev_priv, BCLRPAT(cpu_transcoder));
 711         save_vtotal = intel_de_read(dev_priv, TRANS_VTOTAL(cpu_transcoder));
 712         vblank = intel_de_read(dev_priv, TRANS_VBLANK(cpu_transcoder));
 713
 714         vtotal = REG_FIELD_GET(VTOTAL_MASK, save_vtotal) + 1;
 715         vactive = REG_FIELD_GET(VACTIVE_MASK, save_vtotal) + 1;
 716
 717         vblank_start = REG_FIELD_GET(VBLANK_START_MASK, vblank) + 1;
 718         vblank_end = REG_FIELD_GET(VBLANK_END_MASK, vblank) + 1;
 719
 720         /* Set the border color to purple. */
 721         intel_de_write(dev_priv, BCLRPAT(cpu_transcoder), 0x500050);
 722
 723         if (DISPLAY_VER(dev_priv) != 2) {
 724                 u32 transconf = intel_de_read(dev_priv, TRANSCONF(cpu_transcoder));
 725
 726                 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder),
 727                                transconf | TRANSCONF_FORCE_BORDER);
 728                 intel_de_posting_read(dev_priv, TRANSCONF(cpu_transcoder));
 729                 /* Wait for next Vblank to substitue
 730                  * border color for Color info */
 731                 intel_crtc_wait_for_next_vblank(intel_crtc_for_pipe(dev_priv, pipe));
 732                 st00 = intel_de_read8(dev_priv, _VGA_MSR_WRITE);
 733                 status = ((st00 & (1 << 4)) != 0) ?
 734                         connector_status_connected :
 735                         connector_status_disconnected;
 736
 737                 intel_de_write(dev_priv, TRANSCONF(cpu_transcoder), transconf);
 738         } else {
 739                 bool restore_vblank = false;
 740                 int count, detect;
 741
 742                 /*
 743                 * If there isn't any border, add some.
 744                 * Yes, this will flicker
 745                 */
 746                 if (vblank_start <= vactive && vblank_end >= vtotal) {
 747                         u32 vsync = intel_de_read(dev_priv, TRANS_VSYNC(cpu_transcoder));
 748                         u32 vsync_start = REG_FIELD_GET(VSYNC_START_MASK, vsync) + 1;
 749
 750                         vblank_start = vsync_start;
 751                         intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder),
 752                                        VBLANK_START(vblank_start - 1) |
 753                                        VBLANK_END(vblank_end - 1));
 754                         restore_vblank = true;
 755                 }
 756                 /* sample in the vertical border, selecting the larger one */
 757                 if (vblank_start - vactive >= vtotal - vblank_end)
 758                         vsample = (vblank_start + vactive) >> 1;
 759                 else
 760                         vsample = (vtotal + vblank_end) >> 1;
 761
 762                 /*
 763                  * Wait for the border to be displayed
 764                  */
 765                 while (intel_de_read(dev_priv, PIPEDSL(pipe)) >= vactive)
 766                         ;
 767                 while ((dsl = intel_de_read(dev_priv, PIPEDSL(pipe))) <= vsample)
 768                         ;
 769                 /*
 770                  * Watch ST00 for an entire scanline
 771                  */
 772                 detect = 0;
 773                 count = 0;
 774                 do {
 775                         count++;
 776                         /* Read the ST00 VGA status register */
 777                         st00 = intel_de_read8(dev_priv, _VGA_MSR_WRITE);
 778                         if (st00 & (1 << 4))
 779                                 detect++;
 780                 } while ((intel_de_read(dev_priv, PIPEDSL(pipe)) == dsl));
 781
 782                 /* restore vblank if necessary */
 783                 if (restore_vblank)
 784                         intel_de_write(dev_priv, TRANS_VBLANK(cpu_transcoder), vblank);
 785                 /*
 786                  * If more than 3/4 of the scanline detected a monitor,
 787                  * then it is assumed to be present. This works even on i830,
 788                  * where there isn't any way to force the border color across
 789                  * the screen
 790                  */
 791                 status = detect * 4 > count * 3 ?
 792                          connector_status_connected :
 793                          connector_status_disconnected;
 794         }
 795
 796         /* Restore previous settings */
 797         intel_de_write(dev_priv, BCLRPAT(cpu_transcoder), save_bclrpat);
 798
 799         return status;
 800 }
 801
 802 static int intel_spurious_crt_detect_dmi_callback(const struct dmi_system_id *id)
 803 {
 804         DRM_DEBUG_DRIVER("Skipping CRT detection for %s\n", id->ident);
 805         return 1;
 806 }
 807
 808 static const struct dmi_system_id intel_spurious_crt_detect[] = {
 809         {
 810                 .callback = intel_spurious_crt_detect_dmi_callback,
 811                 .ident = "ACER ZGB",
 812                 .matches = {
 813                         DMI_MATCH(DMI_SYS_VENDOR, "ACER"),
 814                         DMI_MATCH(DMI_PRODUCT_NAME, "ZGB"),
 815                 },
 816         },
 817         {
 818                 .callback = intel_spurious_crt_detect_dmi_callback,
 819                 .ident = "Intel DZ77BH-55K",
 820                 .matches = {
 821                         DMI_MATCH(DMI_BOARD_VENDOR, "Intel Corporation"),
 822                         DMI_MATCH(DMI_BOARD_NAME, "DZ77BH-55K"),
 823                 },
 824         },
 825         { }
 826 };
 827
 828 static int
 829 intel_crt_detect(struct drm_connector *connector,
 830                  struct drm_modeset_acquire_ctx *ctx,
 831                  bool force)
 832 {
 833         struct drm_i915_private *dev_priv = to_i915(connector->dev);
 834         struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
 835         struct intel_encoder *intel_encoder = &crt->base;
 836         struct drm_atomic_state *state;
 837         intel_wakeref_t wakeref;
 838         int status;
 839
 840         drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s] force=%d\n",
 841                     connector->base.id, connector->name,
 842                     force);
 843
 844         if (!intel_display_device_enabled(dev_priv))
 845                 return connector_status_disconnected;
 846
 847         if (!intel_display_driver_check_access(dev_priv))
 848                 return connector->status;
 849
 850         if (dev_priv->display.params.load_detect_test) {
 851                 wakeref = intel_display_power_get(dev_priv,
 852                                                   intel_encoder->power_domain);
 853                 goto load_detect;
 854         }
 855
 856         /* Skip machines without VGA that falsely report hotplug events */
 857         if (dmi_check_system(intel_spurious_crt_detect))
 858                 return connector_status_disconnected;
 859
 860         wakeref = intel_display_power_get(dev_priv,
 861                                           intel_encoder->power_domain);
 862
 863         if (I915_HAS_HOTPLUG(dev_priv)) {
 864                 /* We can not rely on the HPD pin always being correctly wired
 865                  * up, for example many KVM do not pass it through, and so
 866                  * only trust an assertion that the monitor is connected.
 867                  */
 868                 if (intel_crt_detect_hotplug(connector)) {
 869                         drm_dbg_kms(&dev_priv->drm,
 870                                     "CRT detected via hotplug\n");
 871                         status = connector_status_connected;
 872                         goto out;
 873                 } else
 874                         drm_dbg_kms(&dev_priv->drm,
 875                                     "CRT not detected via hotplug\n");
 876         }
 877
 878         if (intel_crt_detect_ddc(connector)) {
 879                 status = connector_status_connected;
 880                 goto out;
 881         }
 882
 883         /* Load detection is broken on HPD capable machines. Whoever wants a
 884          * broken monitor (without edid) to work behind a broken kvm (that fails
 885          * to have the right resistors for HP detection) needs to fix this up.
 886          * For now just bail out. */
 887         if (I915_HAS_HOTPLUG(dev_priv)) {
 888                 status = connector_status_disconnected;
 889                 goto out;
 890         }
 891
 892 load_detect:
 893         if (!force) {
 894                 status = connector->status;
 895                 goto out;
 896         }
 897
 898         /* for pre-945g platforms use load detect */
 899         state = intel_load_detect_get_pipe(connector, ctx);
 900         if (IS_ERR(state)) {
 901                 status = PTR_ERR(state);
 902         } else if (!state) {
 903                 status = connector_status_unknown;
 904         } else {
 905                 if (intel_crt_detect_ddc(connector))
 906                         status = connector_status_connected;
 907                 else if (DISPLAY_VER(dev_priv) < 4)
 908                         status = intel_crt_load_detect(crt,
 909                                 to_intel_crtc(connector->state->crtc)->pipe);
 910                 else if (dev_priv->display.params.load_detect_test)
 911                         status = connector_status_disconnected;
 912                 else
 913                         status = connector_status_unknown;
 914                 intel_load_detect_release_pipe(connector, state, ctx);
 915         }
 916
 917 out:
 918         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
 919
 920         return status;
 921 }
 922
 923 static int intel_crt_get_modes(struct drm_connector *connector)
 924 {
 925         struct drm_device *dev = connector->dev;
 926         struct drm_i915_private *dev_priv = to_i915(dev);
 927         struct intel_crt *crt = intel_attached_crt(to_intel_connector(connector));
 928         struct intel_encoder *intel_encoder = &crt->base;
 929         intel_wakeref_t wakeref;
 930         struct i2c_adapter *ddc;
 931         int ret;
 932
 933         if (!intel_display_driver_check_access(dev_priv))
 934                 return drm_edid_connector_add_modes(connector);
 935
 936         wakeref = intel_display_power_get(dev_priv,
 937                                           intel_encoder->power_domain);
 938
 939         ret = intel_crt_ddc_get_modes(connector, connector->ddc);
 940         if (ret || !IS_G4X(dev_priv))
 941                 goto out;
 942
 943         /* Try to probe digital port for output in DVI-I -> VGA mode. */
 944         ddc = intel_gmbus_get_adapter(dev_priv, GMBUS_PIN_DPB);
 945         ret = intel_crt_ddc_get_modes(connector, ddc);
 946
 947 out:
 948         intel_display_power_put(dev_priv, intel_encoder->power_domain, wakeref);
 949
 950         return ret;
 951 }
 952
 953 void intel_crt_reset(struct drm_encoder *encoder)
 954 {
 955         struct drm_i915_private *dev_priv = to_i915(encoder->dev);
 956         struct intel_crt *crt = intel_encoder_to_crt(to_intel_encoder(encoder));
 957
 958         if (DISPLAY_VER(dev_priv) >= 5) {
 959                 u32 adpa;
 960
 961                 adpa = intel_de_read(dev_priv, crt->adpa_reg);
 962                 adpa &= ~ADPA_CRT_HOTPLUG_MASK;
 963                 adpa |= ADPA_HOTPLUG_BITS;
 964                 intel_de_write(dev_priv, crt->adpa_reg, adpa);
 965                 intel_de_posting_read(dev_priv, crt->adpa_reg);
 966
 967                 drm_dbg_kms(&dev_priv->drm, "crt adpa set to 0x%x\n", adpa);
 968                 crt->force_hotplug_required = true;
 969         }
 970
 971 }
 972
 973 /*
 974  * Routines for controlling stuff on the analog port
 975  */
 976
 977 static const struct drm_connector_funcs intel_crt_connector_funcs = {
 978         .fill_modes = drm_helper_probe_single_connector_modes,
 979         .late_register = intel_connector_register,
 980         .early_unregister = intel_connector_unregister,
 981         .destroy = intel_connector_destroy,
 982         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 983         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 984 };
 985
 986 static const struct drm_connector_helper_funcs intel_crt_connector_helper_funcs = {
 987         .detect_ctx = intel_crt_detect,
 988         .mode_valid = intel_crt_mode_valid,
 989         .get_modes = intel_crt_get_modes,
 990 };
 991
 992 static const struct drm_encoder_funcs intel_crt_enc_funcs = {
 993         .reset = intel_crt_reset,
 994         .destroy = intel_encoder_destroy,
 995 };
 996
 997 void intel_crt_init(struct drm_i915_private *dev_priv)
 998 {
 999         struct drm_connector *connector;
1000         struct intel_crt *crt;
1001         struct intel_connector *intel_connector;
1002         i915_reg_t adpa_reg;
1003         u8 ddc_pin;
1004         u32 adpa;
1005
1006         if (HAS_PCH_SPLIT(dev_priv))
1007                 adpa_reg = PCH_ADPA;
1008         else if (IS_VALLEYVIEW(dev_priv))
1009                 adpa_reg = VLV_ADPA;
1010         else
1011                 adpa_reg = ADPA;
1012
1013         adpa = intel_de_read(dev_priv, adpa_reg);
1014         if ((adpa & ADPA_DAC_ENABLE) == 0) {
1015                 /*
1016                  * On some machines (some IVB at least) CRT can be
1017                  * fused off, but there's no known fuse bit to
1018                  * indicate that. On these machine the ADPA register
1019                  * works normally, except the DAC enable bit won't
1020                  * take. So the only way to tell is attempt to enable
1021                  * it and see what happens.
1022                  */
1023                 intel_de_write(dev_priv, adpa_reg,
1024                                adpa | ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
1025                 if ((intel_de_read(dev_priv, adpa_reg) & ADPA_DAC_ENABLE) == 0)
1026                         return;
1027                 intel_de_write(dev_priv, adpa_reg, adpa);
1028         }
1029
1030         crt = kzalloc(sizeof(struct intel_crt), GFP_KERNEL);
1031         if (!crt)
1032                 return;
1033
1034         intel_connector = intel_connector_alloc();
1035         if (!intel_connector) {
1036                 kfree(crt);
1037                 return;
1038         }
1039
1040         ddc_pin = dev_priv->display.vbt.crt_ddc_pin;
1041
1042         connector = &intel_connector->base;
1043         crt->connector = intel_connector;
1044         drm_connector_init_with_ddc(&dev_priv->drm, connector,
1045                                     &intel_crt_connector_funcs,
1046                                     DRM_MODE_CONNECTOR_VGA,
1047                                     intel_gmbus_get_adapter(dev_priv, ddc_pin));
1048
1049         drm_encoder_init(&dev_priv->drm, &crt->base.base, &intel_crt_enc_funcs,
1050                          DRM_MODE_ENCODER_DAC, "CRT");
1051
1052         intel_connector_attach_encoder(intel_connector, &crt->base);
1053
1054         crt->base.type = INTEL_OUTPUT_ANALOG;
1055         crt->base.cloneable = BIT(INTEL_OUTPUT_DVO) | BIT(INTEL_OUTPUT_HDMI);
1056         if (IS_I830(dev_priv))
1057                 crt->base.pipe_mask = BIT(PIPE_A);
1058         else
1059                 crt->base.pipe_mask = ~0;
1060
1061         if (DISPLAY_VER(dev_priv) != 2)
1062                 connector->interlace_allowed = true;
1063
1064         crt->adpa_reg = adpa_reg;
1065
1066         crt->base.power_domain = POWER_DOMAIN_PORT_CRT;
1067
1068         if (I915_HAS_HOTPLUG(dev_priv) &&
1069             !dmi_check_system(intel_spurious_crt_detect)) {
1070                 crt->base.hpd_pin = HPD_CRT;
1071                 crt->base.hotplug = intel_encoder_hotplug;
1072                 intel_connector->polled = DRM_CONNECTOR_POLL_HPD;
1073         } else {
1074                 intel_connector->polled = DRM_CONNECTOR_POLL_CONNECT;
1075         }
1076         intel_connector->base.polled = intel_connector->polled;
1077
1078         if (HAS_DDI(dev_priv)) {
1079                 assert_port_valid(dev_priv, PORT_E);
1080
1081                 crt->base.port = PORT_E;
1082                 crt->base.get_config = hsw_crt_get_config;
1083                 crt->base.get_hw_state = intel_ddi_get_hw_state;
1084                 crt->base.compute_config = hsw_crt_compute_config;
1085                 crt->base.pre_pll_enable = hsw_pre_pll_enable_crt;
1086                 crt->base.pre_enable = hsw_pre_enable_crt;
1087                 crt->base.enable = hsw_enable_crt;
1088                 crt->base.disable = hsw_disable_crt;
1089                 crt->base.post_disable = hsw_post_disable_crt;
1090                 crt->base.enable_clock = hsw_ddi_enable_clock;
1091                 crt->base.disable_clock = hsw_ddi_disable_clock;
1092                 crt->base.is_clock_enabled = hsw_ddi_is_clock_enabled;
1093
1094                 intel_ddi_buf_trans_init(&crt->base);
1095         } else {
1096                 if (HAS_PCH_SPLIT(dev_priv)) {
1097                         crt->base.compute_config = pch_crt_compute_config;
1098                         crt->base.disable = pch_disable_crt;
1099                         crt->base.post_disable = pch_post_disable_crt;
1100                 } else {
1101                         crt->base.compute_config = intel_crt_compute_config;
1102                         crt->base.disable = intel_disable_crt;
1103                 }
1104                 crt->base.port = PORT_NONE;
1105                 crt->base.get_config = intel_crt_get_config;
1106                 crt->base.get_hw_state = intel_crt_get_hw_state;
1107                 crt->base.enable = intel_enable_crt;
1108         }
1109         intel_connector->get_hw_state = intel_connector_get_hw_state;
1110
1111         drm_connector_helper_add(connector, &intel_crt_connector_helper_funcs);
1112
1113         /*
1114          * TODO: find a proper way to discover whether we need to set the the
1115          * polarity and link reversal bits or not, instead of relying on the
1116          * BIOS.
1117          */
1118         if (HAS_PCH_LPT(dev_priv)) {
1119                 u32 fdi_config = FDI_RX_POLARITY_REVERSED_LPT |
1120                                  FDI_RX_LINK_REVERSAL_OVERRIDE;
1121
1122                 dev_priv->display.fdi.rx_config = intel_de_read(dev_priv,
1123                                                                 FDI_RX_CTL(PIPE_A)) & fdi_config;
1124         }
1125
1126         intel_crt_reset(&crt->base.base);
1127 }