drivers/dma/fsl-edma-common.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 //
   3 // Copyright (c) 2013-2014 Freescale Semiconductor, Inc
   4 // Copyright (c) 2017 Sysam, Angelo Dureghello  <[email protected]>
   5
   6 #include <linux/cleanup.h>
   7 #include <linux/clk.h>
   8 #include <linux/dmapool.h>
   9 #include <linux/module.h>
  10 #include <linux/slab.h>
  11 #include <linux/dma-mapping.h>
  12 #include <linux/pm_runtime.h>
  13 #include <linux/pm_domain.h>
  14
  15 #include "fsl-edma-common.h"
  16
  17 #define EDMA_CR                 0x00
  18 #define EDMA_ES                 0x04
  19 #define EDMA_ERQ                0x0C
  20 #define EDMA_EEI                0x14
  21 #define EDMA_SERQ               0x1B
  22 #define EDMA_CERQ               0x1A
  23 #define EDMA_SEEI               0x19
  24 #define EDMA_CEEI               0x18
  25 #define EDMA_CINT               0x1F
  26 #define EDMA_CERR               0x1E
  27 #define EDMA_SSRT               0x1D
  28 #define EDMA_CDNE               0x1C
  29 #define EDMA_INTR               0x24
  30 #define EDMA_ERR                0x2C
  31
  32 #define EDMA64_ERQH             0x08
  33 #define EDMA64_EEIH             0x10
  34 #define EDMA64_SERQ             0x18
  35 #define EDMA64_CERQ             0x19
  36 #define EDMA64_SEEI             0x1a
  37 #define EDMA64_CEEI             0x1b
  38 #define EDMA64_CINT             0x1c
  39 #define EDMA64_CERR             0x1d
  40 #define EDMA64_SSRT             0x1e
  41 #define EDMA64_CDNE             0x1f
  42 #define EDMA64_INTH             0x20
  43 #define EDMA64_INTL             0x24
  44 #define EDMA64_ERRH             0x28
  45 #define EDMA64_ERRL             0x2c
  46
  47 void fsl_edma_tx_chan_handler(struct fsl_edma_chan *fsl_chan)
  48 {
  49         spin_lock(&fsl_chan->vchan.lock);
  50
  51         if (!fsl_chan->edesc) {
  52                 /* terminate_all called before */
  53                 spin_unlock(&fsl_chan->vchan.lock);
  54                 return;
  55         }
  56
  57         if (!fsl_chan->edesc->iscyclic) {
  58                 list_del(&fsl_chan->edesc->vdesc.node);
  59                 vchan_cookie_complete(&fsl_chan->edesc->vdesc);
  60                 fsl_chan->edesc = NULL;
  61                 fsl_chan->status = DMA_COMPLETE;
  62                 fsl_chan->idle = true;
  63         } else {
  64                 vchan_cyclic_callback(&fsl_chan->edesc->vdesc);
  65         }
  66
  67         if (!fsl_chan->edesc)
  68                 fsl_edma_xfer_desc(fsl_chan);
  69
  70         spin_unlock(&fsl_chan->vchan.lock);
  71 }
  72
  73 static void fsl_edma3_enable_request(struct fsl_edma_chan *fsl_chan)
  74 {
  75         u32 val, flags;
  76
  77         flags = fsl_edma_drvflags(fsl_chan);
  78         val = edma_readl_chreg(fsl_chan, ch_sbr);
  79         if (fsl_chan->is_rxchan)
  80                 val |= EDMA_V3_CH_SBR_RD;
  81         else
  82                 val |= EDMA_V3_CH_SBR_WR;
  83
  84         if (fsl_chan->is_remote)
  85                 val &= ~(EDMA_V3_CH_SBR_RD | EDMA_V3_CH_SBR_WR);
  86
  87         edma_writel_chreg(fsl_chan, val, ch_sbr);
  88
  89         if (flags & FSL_EDMA_DRV_HAS_CHMUX) {
  90                 /*
  91                  * ch_mux: With the exception of 0, attempts to write a value
  92                  * already in use will be forced to 0.
  93                  */
  94                 if (!edma_readl(fsl_chan->edma, fsl_chan->mux_addr))
  95                         edma_writel(fsl_chan->edma, fsl_chan->srcid, fsl_chan->mux_addr);
  96         }
  97
  98         val = edma_readl_chreg(fsl_chan, ch_csr);
  99         val |= EDMA_V3_CH_CSR_ERQ;
 100         edma_writel_chreg(fsl_chan, val, ch_csr);
 101 }
 102
 103 static void fsl_edma_enable_request(struct fsl_edma_chan *fsl_chan)
 104 {
 105         struct edma_regs *regs = &fsl_chan->edma->regs;
 106         u32 ch = fsl_chan->vchan.chan.chan_id;
 107
 108         if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_SPLIT_REG)
 109                 return fsl_edma3_enable_request(fsl_chan);
 110
 111         if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_WRAP_IO) {
 112                 edma_writeb(fsl_chan->edma, EDMA_SEEI_SEEI(ch), regs->seei);
 113                 edma_writeb(fsl_chan->edma, ch, regs->serq);
 114         } else {
 115                 /* ColdFire is big endian, and accesses natively
 116                  * big endian I/O peripherals
 117                  */
 118                 iowrite8(EDMA_SEEI_SEEI(ch), regs->seei);
 119                 iowrite8(ch, regs->serq);
 120         }
 121 }
 122
 123 static void fsl_edma3_disable_request(struct fsl_edma_chan *fsl_chan)
 124 {
 125         u32 val = edma_readl_chreg(fsl_chan, ch_csr);
 126         u32 flags;
 127
 128         flags = fsl_edma_drvflags(fsl_chan);
 129
 130         if (flags & FSL_EDMA_DRV_HAS_CHMUX)
 131                 edma_writel(fsl_chan->edma, 0, fsl_chan->mux_addr);
 132
 133         val &= ~EDMA_V3_CH_CSR_ERQ;
 134         edma_writel_chreg(fsl_chan, val, ch_csr);
 135 }
 136
 137 void fsl_edma_disable_request(struct fsl_edma_chan *fsl_chan)
 138 {
 139         struct edma_regs *regs = &fsl_chan->edma->regs;
 140         u32 ch = fsl_chan->vchan.chan.chan_id;
 141
 142         if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_SPLIT_REG)
 143                 return fsl_edma3_disable_request(fsl_chan);
 144
 145         if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_WRAP_IO) {
 146                 edma_writeb(fsl_chan->edma, ch, regs->cerq);
 147                 edma_writeb(fsl_chan->edma, EDMA_CEEI_CEEI(ch), regs->ceei);
 148         } else {
 149                 /* ColdFire is big endian, and accesses natively
 150                  * big endian I/O peripherals
 151                  */
 152                 iowrite8(ch, regs->cerq);
 153                 iowrite8(EDMA_CEEI_CEEI(ch), regs->ceei);
 154         }
 155 }
 156
 157 static void mux_configure8(struct fsl_edma_chan *fsl_chan, void __iomem *addr,
 158                            u32 off, u32 slot, bool enable)
 159 {
 160         u8 val8;
 161
 162         if (enable)
 163                 val8 = EDMAMUX_CHCFG_ENBL | slot;
 164         else
 165                 val8 = EDMAMUX_CHCFG_DIS;
 166
 167         iowrite8(val8, addr + off);
 168 }
 169
 170 static void mux_configure32(struct fsl_edma_chan *fsl_chan, void __iomem *addr,
 171                             u32 off, u32 slot, bool enable)
 172 {
 173         u32 val;
 174
 175         if (enable)
 176                 val = EDMAMUX_CHCFG_ENBL << 24 | slot;
 177         else
 178                 val = EDMAMUX_CHCFG_DIS;
 179
 180         iowrite32(val, addr + off * 4);
 181 }
 182
 183 void fsl_edma_chan_mux(struct fsl_edma_chan *fsl_chan,
 184                        unsigned int slot, bool enable)
 185 {
 186         u32 ch = fsl_chan->vchan.chan.chan_id;
 187         void __iomem *muxaddr;
 188         unsigned int chans_per_mux, ch_off;
 189         int endian_diff[4] = {3, 1, -1, -3};
 190         u32 dmamux_nr = fsl_chan->edma->drvdata->dmamuxs;
 191
 192         if (!dmamux_nr)
 193                 return;
 194
 195         chans_per_mux = fsl_chan->edma->n_chans / dmamux_nr;
 196         ch_off = fsl_chan->vchan.chan.chan_id % chans_per_mux;
 197
 198         if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_MUX_SWAP)
 199                 ch_off += endian_diff[ch_off % 4];
 200
 201         muxaddr = fsl_chan->edma->muxbase[ch / chans_per_mux];
 202         slot = EDMAMUX_CHCFG_SOURCE(slot);
 203
 204         if (fsl_chan->edma->drvdata->flags & FSL_EDMA_DRV_CONFIG32)
 205                 mux_configure32(fsl_chan, muxaddr, ch_off, slot, enable);
 206         else
 207                 mux_configure8(fsl_chan, muxaddr, ch_off, slot, enable);
 208 }
 209
 210 static unsigned int fsl_edma_get_tcd_attr(enum dma_slave_buswidth addr_width)
 211 {
 212         u32 val;
 213
 214         if (addr_width == DMA_SLAVE_BUSWIDTH_UNDEFINED)
 215                 addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
 216
 217         val = ffs(addr_width) - 1;
 218         return val | (val << 8);
 219 }
 220
 221 void fsl_edma_free_desc(struct virt_dma_desc *vdesc)
 222 {
 223         struct fsl_edma_desc *fsl_desc;
 224         int i;
 225
 226         fsl_desc = to_fsl_edma_desc(vdesc);
 227         for (i = 0; i < fsl_desc->n_tcds; i++)
 228                 dma_pool_free(fsl_desc->echan->tcd_pool, fsl_desc->tcd[i].vtcd,
 229                               fsl_desc->tcd[i].ptcd);
 230         kfree(fsl_desc);
 231 }
 232
 233 int fsl_edma_terminate_all(struct dma_chan *chan)
 234 {
 235         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 236         unsigned long flags;
 237         LIST_HEAD(head);
 238
 239         spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
 240         fsl_edma_disable_request(fsl_chan);
 241         fsl_chan->edesc = NULL;
 242         fsl_chan->idle = true;
 243         vchan_get_all_descriptors(&fsl_chan->vchan, &head);
 244         spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 245         vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
 246
 247         if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_HAS_PD)
 248                 pm_runtime_allow(fsl_chan->pd_dev);
 249
 250         return 0;
 251 }
 252
 253 int fsl_edma_pause(struct dma_chan *chan)
 254 {
 255         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 256         unsigned long flags;
 257
 258         spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
 259         if (fsl_chan->edesc) {
 260                 fsl_edma_disable_request(fsl_chan);
 261                 fsl_chan->status = DMA_PAUSED;
 262                 fsl_chan->idle = true;
 263         }
 264         spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 265         return 0;
 266 }
 267
 268 int fsl_edma_resume(struct dma_chan *chan)
 269 {
 270         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 271         unsigned long flags;
 272
 273         spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
 274         if (fsl_chan->edesc) {
 275                 fsl_edma_enable_request(fsl_chan);
 276                 fsl_chan->status = DMA_IN_PROGRESS;
 277                 fsl_chan->idle = false;
 278         }
 279         spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 280         return 0;
 281 }
 282
 283 static void fsl_edma_unprep_slave_dma(struct fsl_edma_chan *fsl_chan)
 284 {
 285         if (fsl_chan->dma_dir != DMA_NONE)
 286                 dma_unmap_resource(fsl_chan->vchan.chan.device->dev,
 287                                    fsl_chan->dma_dev_addr,
 288                                    fsl_chan->dma_dev_size,
 289                                    fsl_chan->dma_dir, 0);
 290         fsl_chan->dma_dir = DMA_NONE;
 291 }
 292
 293 static bool fsl_edma_prep_slave_dma(struct fsl_edma_chan *fsl_chan,
 294                                     enum dma_transfer_direction dir)
 295 {
 296         struct device *dev = fsl_chan->vchan.chan.device->dev;
 297         enum dma_data_direction dma_dir;
 298         phys_addr_t addr = 0;
 299         u32 size = 0;
 300
 301         switch (dir) {
 302         case DMA_MEM_TO_DEV:
 303                 dma_dir = DMA_FROM_DEVICE;
 304                 addr = fsl_chan->cfg.dst_addr;
 305                 size = fsl_chan->cfg.dst_maxburst;
 306                 break;
 307         case DMA_DEV_TO_MEM:
 308                 dma_dir = DMA_TO_DEVICE;
 309                 addr = fsl_chan->cfg.src_addr;
 310                 size = fsl_chan->cfg.src_maxburst;
 311                 break;
 312         default:
 313                 dma_dir = DMA_NONE;
 314                 break;
 315         }
 316
 317         /* Already mapped for this config? */
 318         if (fsl_chan->dma_dir == dma_dir)
 319                 return true;
 320
 321         fsl_edma_unprep_slave_dma(fsl_chan);
 322
 323         fsl_chan->dma_dev_addr = dma_map_resource(dev, addr, size, dma_dir, 0);
 324         if (dma_mapping_error(dev, fsl_chan->dma_dev_addr))
 325                 return false;
 326         fsl_chan->dma_dev_size = size;
 327         fsl_chan->dma_dir = dma_dir;
 328
 329         return true;
 330 }
 331
 332 int fsl_edma_slave_config(struct dma_chan *chan,
 333                                  struct dma_slave_config *cfg)
 334 {
 335         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 336
 337         memcpy(&fsl_chan->cfg, cfg, sizeof(*cfg));
 338         fsl_edma_unprep_slave_dma(fsl_chan);
 339
 340         return 0;
 341 }
 342
 343 static size_t fsl_edma_desc_residue(struct fsl_edma_chan *fsl_chan,
 344                 struct virt_dma_desc *vdesc, bool in_progress)
 345 {
 346         struct fsl_edma_desc *edesc = fsl_chan->edesc;
 347         enum dma_transfer_direction dir = edesc->dirn;
 348         dma_addr_t cur_addr, dma_addr, old_addr;
 349         size_t len, size;
 350         u32 nbytes = 0;
 351         int i;
 352
 353         /* calculate the total size in this desc */
 354         for (len = i = 0; i < fsl_chan->edesc->n_tcds; i++) {
 355                 nbytes = fsl_edma_get_tcd_to_cpu(fsl_chan, edesc->tcd[i].vtcd, nbytes);
 356                 if (nbytes & (EDMA_V3_TCD_NBYTES_DMLOE | EDMA_V3_TCD_NBYTES_SMLOE))
 357                         nbytes = EDMA_V3_TCD_NBYTES_MLOFF_NBYTES(nbytes);
 358                 len += nbytes * fsl_edma_get_tcd_to_cpu(fsl_chan, edesc->tcd[i].vtcd, biter);
 359         }
 360
 361         if (!in_progress)
 362                 return len;
 363
 364         /* 64bit read is not atomic, need read retry when high 32bit changed */
 365         do {
 366                 if (dir == DMA_MEM_TO_DEV) {
 367                         old_addr = edma_read_tcdreg(fsl_chan, saddr);
 368                         cur_addr = edma_read_tcdreg(fsl_chan, saddr);
 369                 } else {
 370                         old_addr = edma_read_tcdreg(fsl_chan, daddr);
 371                         cur_addr = edma_read_tcdreg(fsl_chan, daddr);
 372                 }
 373         } while (upper_32_bits(cur_addr) != upper_32_bits(old_addr));
 374
 375         /* figure out the finished and calculate the residue */
 376         for (i = 0; i < fsl_chan->edesc->n_tcds; i++) {
 377                 nbytes = fsl_edma_get_tcd_to_cpu(fsl_chan, edesc->tcd[i].vtcd, nbytes);
 378                 if (nbytes & (EDMA_V3_TCD_NBYTES_DMLOE | EDMA_V3_TCD_NBYTES_SMLOE))
 379                         nbytes = EDMA_V3_TCD_NBYTES_MLOFF_NBYTES(nbytes);
 380
 381                 size = nbytes * fsl_edma_get_tcd_to_cpu(fsl_chan, edesc->tcd[i].vtcd, biter);
 382
 383                 if (dir == DMA_MEM_TO_DEV)
 384                         dma_addr = fsl_edma_get_tcd_to_cpu(fsl_chan, edesc->tcd[i].vtcd, saddr);
 385                 else
 386                         dma_addr = fsl_edma_get_tcd_to_cpu(fsl_chan, edesc->tcd[i].vtcd, daddr);
 387
 388                 len -= size;
 389                 if (cur_addr >= dma_addr && cur_addr < dma_addr + size) {
 390                         len += dma_addr + size - cur_addr;
 391                         break;
 392                 }
 393         }
 394
 395         return len;
 396 }
 397
 398 enum dma_status fsl_edma_tx_status(struct dma_chan *chan,
 399                 dma_cookie_t cookie, struct dma_tx_state *txstate)
 400 {
 401         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 402         struct virt_dma_desc *vdesc;
 403         enum dma_status status;
 404         unsigned long flags;
 405
 406         status = dma_cookie_status(chan, cookie, txstate);
 407         if (status == DMA_COMPLETE)
 408                 return status;
 409
 410         if (!txstate)
 411                 return fsl_chan->status;
 412
 413         spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
 414         vdesc = vchan_find_desc(&fsl_chan->vchan, cookie);
 415         if (fsl_chan->edesc && cookie == fsl_chan->edesc->vdesc.tx.cookie)
 416                 txstate->residue =
 417                         fsl_edma_desc_residue(fsl_chan, vdesc, true);
 418         else if (vdesc)
 419                 txstate->residue =
 420                         fsl_edma_desc_residue(fsl_chan, vdesc, false);
 421         else
 422                 txstate->residue = 0;
 423
 424         spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 425
 426         return fsl_chan->status;
 427 }
 428
 429 static void fsl_edma_set_tcd_regs(struct fsl_edma_chan *fsl_chan, void *tcd)
 430 {
 431         u16 csr = 0;
 432
 433         /*
 434          * TCD parameters are stored in struct fsl_edma_hw_tcd in little
 435          * endian format. However, we need to load the TCD registers in
 436          * big- or little-endian obeying the eDMA engine model endian,
 437          * and this is performed from specific edma_write functions
 438          */
 439         edma_write_tcdreg(fsl_chan, 0, csr);
 440
 441         edma_cp_tcd_to_reg(fsl_chan, tcd, saddr);
 442         edma_cp_tcd_to_reg(fsl_chan, tcd, daddr);
 443
 444         edma_cp_tcd_to_reg(fsl_chan, tcd, attr);
 445         edma_cp_tcd_to_reg(fsl_chan, tcd, soff);
 446
 447         edma_cp_tcd_to_reg(fsl_chan, tcd, nbytes);
 448         edma_cp_tcd_to_reg(fsl_chan, tcd, slast);
 449
 450         edma_cp_tcd_to_reg(fsl_chan, tcd, citer);
 451         edma_cp_tcd_to_reg(fsl_chan, tcd, biter);
 452         edma_cp_tcd_to_reg(fsl_chan, tcd, doff);
 453
 454         edma_cp_tcd_to_reg(fsl_chan, tcd, dlast_sga);
 455
 456         csr = fsl_edma_get_tcd_to_cpu(fsl_chan, tcd, csr);
 457
 458         if (fsl_chan->is_sw) {
 459                 csr |= EDMA_TCD_CSR_START;
 460                 fsl_edma_set_tcd_to_le(fsl_chan, tcd, csr, csr);
 461         }
 462
 463         /*
 464          * Must clear CHn_CSR[DONE] bit before enable TCDn_CSR[ESG] at EDMAv3
 465          * eDMAv4 have not such requirement.
 466          * Change MLINK need clear CHn_CSR[DONE] for both eDMAv3 and eDMAv4.
 467          */
 468         if (((fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_CLEAR_DONE_E_SG) &&
 469                 (csr & EDMA_TCD_CSR_E_SG)) ||
 470             ((fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_CLEAR_DONE_E_LINK) &&
 471                 (csr & EDMA_TCD_CSR_E_LINK)))
 472                 edma_writel_chreg(fsl_chan, edma_readl_chreg(fsl_chan, ch_csr), ch_csr);
 473
 474
 475         edma_cp_tcd_to_reg(fsl_chan, tcd, csr);
 476 }
 477
 478 static inline
 479 void fsl_edma_fill_tcd(struct fsl_edma_chan *fsl_chan,
 480                        struct fsl_edma_hw_tcd *tcd, dma_addr_t src, dma_addr_t dst,
 481                        u16 attr, u16 soff, u32 nbytes, dma_addr_t slast, u16 citer,
 482                        u16 biter, u16 doff, dma_addr_t dlast_sga, bool major_int,
 483                        bool disable_req, bool enable_sg)
 484 {
 485         struct dma_slave_config *cfg = &fsl_chan->cfg;
 486         u16 csr = 0;
 487         u32 burst;
 488
 489         /*
 490          * eDMA hardware SGs require the TCDs to be stored in little
 491          * endian format irrespective of the register endian model.
 492          * So we put the value in little endian in memory, waiting
 493          * for fsl_edma_set_tcd_regs doing the swap.
 494          */
 495         fsl_edma_set_tcd_to_le(fsl_chan, tcd, src, saddr);
 496         fsl_edma_set_tcd_to_le(fsl_chan, tcd, dst, daddr);
 497
 498         fsl_edma_set_tcd_to_le(fsl_chan, tcd, attr, attr);
 499
 500         fsl_edma_set_tcd_to_le(fsl_chan, tcd, soff, soff);
 501
 502         if (fsl_chan->is_multi_fifo) {
 503                 /* set mloff to support multiple fifo */
 504                 burst = cfg->direction == DMA_DEV_TO_MEM ?
 505                                 cfg->src_maxburst : cfg->dst_maxburst;
 506                 nbytes |= EDMA_V3_TCD_NBYTES_MLOFF(-(burst * 4));
 507                 /* enable DMLOE/SMLOE */
 508                 if (cfg->direction == DMA_MEM_TO_DEV) {
 509                         nbytes |= EDMA_V3_TCD_NBYTES_DMLOE;
 510                         nbytes &= ~EDMA_V3_TCD_NBYTES_SMLOE;
 511                 } else {
 512                         nbytes |= EDMA_V3_TCD_NBYTES_SMLOE;
 513                         nbytes &= ~EDMA_V3_TCD_NBYTES_DMLOE;
 514                 }
 515         }
 516
 517         fsl_edma_set_tcd_to_le(fsl_chan, tcd, nbytes, nbytes);
 518         fsl_edma_set_tcd_to_le(fsl_chan, tcd, slast, slast);
 519
 520         fsl_edma_set_tcd_to_le(fsl_chan, tcd, EDMA_TCD_CITER_CITER(citer), citer);
 521         fsl_edma_set_tcd_to_le(fsl_chan, tcd, doff, doff);
 522
 523         fsl_edma_set_tcd_to_le(fsl_chan, tcd, dlast_sga, dlast_sga);
 524
 525         fsl_edma_set_tcd_to_le(fsl_chan, tcd, EDMA_TCD_BITER_BITER(biter), biter);
 526
 527         if (major_int)
 528                 csr |= EDMA_TCD_CSR_INT_MAJOR;
 529
 530         if (disable_req)
 531                 csr |= EDMA_TCD_CSR_D_REQ;
 532
 533         if (enable_sg)
 534                 csr |= EDMA_TCD_CSR_E_SG;
 535
 536         if (fsl_chan->is_rxchan)
 537                 csr |= EDMA_TCD_CSR_ACTIVE;
 538
 539         if (fsl_chan->is_sw)
 540                 csr |= EDMA_TCD_CSR_START;
 541
 542         fsl_edma_set_tcd_to_le(fsl_chan, tcd, csr, csr);
 543
 544         trace_edma_fill_tcd(fsl_chan, tcd);
 545 }
 546
 547 static struct fsl_edma_desc *fsl_edma_alloc_desc(struct fsl_edma_chan *fsl_chan,
 548                 int sg_len)
 549 {
 550         struct fsl_edma_desc *fsl_desc;
 551         int i;
 552
 553         fsl_desc = kzalloc(struct_size(fsl_desc, tcd, sg_len), GFP_NOWAIT);
 554         if (!fsl_desc)
 555                 return NULL;
 556
 557         fsl_desc->echan = fsl_chan;
 558         fsl_desc->n_tcds = sg_len;
 559         for (i = 0; i < sg_len; i++) {
 560                 fsl_desc->tcd[i].vtcd = dma_pool_alloc(fsl_chan->tcd_pool,
 561                                         GFP_NOWAIT, &fsl_desc->tcd[i].ptcd);
 562                 if (!fsl_desc->tcd[i].vtcd)
 563                         goto err;
 564         }
 565         return fsl_desc;
 566
 567 err:
 568         while (--i >= 0)
 569                 dma_pool_free(fsl_chan->tcd_pool, fsl_desc->tcd[i].vtcd,
 570                                 fsl_desc->tcd[i].ptcd);
 571         kfree(fsl_desc);
 572         return NULL;
 573 }
 574
 575 struct dma_async_tx_descriptor *fsl_edma_prep_dma_cyclic(
 576                 struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
 577                 size_t period_len, enum dma_transfer_direction direction,
 578                 unsigned long flags)
 579 {
 580         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 581         struct fsl_edma_desc *fsl_desc;
 582         dma_addr_t dma_buf_next;
 583         bool major_int = true;
 584         int sg_len, i;
 585         dma_addr_t src_addr, dst_addr, last_sg;
 586         u16 soff, doff, iter;
 587         u32 nbytes;
 588
 589         if (!is_slave_direction(direction))
 590                 return NULL;
 591
 592         if (!fsl_edma_prep_slave_dma(fsl_chan, direction))
 593                 return NULL;
 594
 595         sg_len = buf_len / period_len;
 596         fsl_desc = fsl_edma_alloc_desc(fsl_chan, sg_len);
 597         if (!fsl_desc)
 598                 return NULL;
 599         fsl_desc->iscyclic = true;
 600         fsl_desc->dirn = direction;
 601
 602         dma_buf_next = dma_addr;
 603         if (direction == DMA_MEM_TO_DEV) {
 604                 fsl_chan->attr =
 605                         fsl_edma_get_tcd_attr(fsl_chan->cfg.dst_addr_width);
 606                 nbytes = fsl_chan->cfg.dst_addr_width *
 607                         fsl_chan->cfg.dst_maxburst;
 608         } else {
 609                 fsl_chan->attr =
 610                         fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width);
 611                 nbytes = fsl_chan->cfg.src_addr_width *
 612                         fsl_chan->cfg.src_maxburst;
 613         }
 614
 615         iter = period_len / nbytes;
 616
 617         for (i = 0; i < sg_len; i++) {
 618                 if (dma_buf_next >= dma_addr + buf_len)
 619                         dma_buf_next = dma_addr;
 620
 621                 /* get next sg's physical address */
 622                 last_sg = fsl_desc->tcd[(i + 1) % sg_len].ptcd;
 623
 624                 if (direction == DMA_MEM_TO_DEV) {
 625                         src_addr = dma_buf_next;
 626                         dst_addr = fsl_chan->dma_dev_addr;
 627                         soff = fsl_chan->cfg.dst_addr_width;
 628                         doff = fsl_chan->is_multi_fifo ? 4 : 0;
 629                 } else if (direction == DMA_DEV_TO_MEM) {
 630                         src_addr = fsl_chan->dma_dev_addr;
 631                         dst_addr = dma_buf_next;
 632                         soff = fsl_chan->is_multi_fifo ? 4 : 0;
 633                         doff = fsl_chan->cfg.src_addr_width;
 634                 } else {
 635                         /* DMA_DEV_TO_DEV */
 636                         src_addr = fsl_chan->cfg.src_addr;
 637                         dst_addr = fsl_chan->cfg.dst_addr;
 638                         soff = doff = 0;
 639                         major_int = false;
 640                 }
 641
 642                 fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr, dst_addr,
 643                                   fsl_chan->attr, soff, nbytes, 0, iter,
 644                                   iter, doff, last_sg, major_int, false, true);
 645                 dma_buf_next += period_len;
 646         }
 647
 648         return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags);
 649 }
 650
 651 struct dma_async_tx_descriptor *fsl_edma_prep_slave_sg(
 652                 struct dma_chan *chan, struct scatterlist *sgl,
 653                 unsigned int sg_len, enum dma_transfer_direction direction,
 654                 unsigned long flags, void *context)
 655 {
 656         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 657         struct fsl_edma_desc *fsl_desc;
 658         struct scatterlist *sg;
 659         dma_addr_t src_addr, dst_addr, last_sg;
 660         u16 soff, doff, iter;
 661         u32 nbytes;
 662         int i;
 663
 664         if (!is_slave_direction(direction))
 665                 return NULL;
 666
 667         if (!fsl_edma_prep_slave_dma(fsl_chan, direction))
 668                 return NULL;
 669
 670         fsl_desc = fsl_edma_alloc_desc(fsl_chan, sg_len);
 671         if (!fsl_desc)
 672                 return NULL;
 673         fsl_desc->iscyclic = false;
 674         fsl_desc->dirn = direction;
 675
 676         if (direction == DMA_MEM_TO_DEV) {
 677                 fsl_chan->attr =
 678                         fsl_edma_get_tcd_attr(fsl_chan->cfg.dst_addr_width);
 679                 nbytes = fsl_chan->cfg.dst_addr_width *
 680                         fsl_chan->cfg.dst_maxburst;
 681         } else {
 682                 fsl_chan->attr =
 683                         fsl_edma_get_tcd_attr(fsl_chan->cfg.src_addr_width);
 684                 nbytes = fsl_chan->cfg.src_addr_width *
 685                         fsl_chan->cfg.src_maxburst;
 686         }
 687
 688         for_each_sg(sgl, sg, sg_len, i) {
 689                 if (direction == DMA_MEM_TO_DEV) {
 690                         src_addr = sg_dma_address(sg);
 691                         dst_addr = fsl_chan->dma_dev_addr;
 692                         soff = fsl_chan->cfg.dst_addr_width;
 693                         doff = 0;
 694                 } else if (direction == DMA_DEV_TO_MEM) {
 695                         src_addr = fsl_chan->dma_dev_addr;
 696                         dst_addr = sg_dma_address(sg);
 697                         soff = 0;
 698                         doff = fsl_chan->cfg.src_addr_width;
 699                 } else {
 700                         /* DMA_DEV_TO_DEV */
 701                         src_addr = fsl_chan->cfg.src_addr;
 702                         dst_addr = fsl_chan->cfg.dst_addr;
 703                         soff = 0;
 704                         doff = 0;
 705                 }
 706
 707                 /*
 708                  * Choose the suitable burst length if sg_dma_len is not
 709                  * multiple of burst length so that the whole transfer length is
 710                  * multiple of minor loop(burst length).
 711                  */
 712                 if (sg_dma_len(sg) % nbytes) {
 713                         u32 width = (direction == DMA_DEV_TO_MEM) ? doff : soff;
 714                         u32 burst = (direction == DMA_DEV_TO_MEM) ?
 715                                                 fsl_chan->cfg.src_maxburst :
 716                                                 fsl_chan->cfg.dst_maxburst;
 717                         int j;
 718
 719                         for (j = burst; j > 1; j--) {
 720                                 if (!(sg_dma_len(sg) % (j * width))) {
 721                                         nbytes = j * width;
 722                                         break;
 723                                 }
 724                         }
 725                         /* Set burst size as 1 if there's no suitable one */
 726                         if (j == 1)
 727                                 nbytes = width;
 728                 }
 729                 iter = sg_dma_len(sg) / nbytes;
 730                 if (i < sg_len - 1) {
 731                         last_sg = fsl_desc->tcd[(i + 1)].ptcd;
 732                         fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr,
 733                                           dst_addr, fsl_chan->attr, soff,
 734                                           nbytes, 0, iter, iter, doff, last_sg,
 735                                           false, false, true);
 736                 } else {
 737                         last_sg = 0;
 738                         fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[i].vtcd, src_addr,
 739                                           dst_addr, fsl_chan->attr, soff,
 740                                           nbytes, 0, iter, iter, doff, last_sg,
 741                                           true, true, false);
 742                 }
 743         }
 744
 745         return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags);
 746 }
 747
 748 struct dma_async_tx_descriptor *fsl_edma_prep_memcpy(struct dma_chan *chan,
 749                                                      dma_addr_t dma_dst, dma_addr_t dma_src,
 750                                                      size_t len, unsigned long flags)
 751 {
 752         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 753         struct fsl_edma_desc *fsl_desc;
 754
 755         fsl_desc = fsl_edma_alloc_desc(fsl_chan, 1);
 756         if (!fsl_desc)
 757                 return NULL;
 758         fsl_desc->iscyclic = false;
 759
 760         fsl_chan->is_sw = true;
 761
 762         /* To match with copy_align and max_seg_size so 1 tcd is enough */
 763         fsl_edma_fill_tcd(fsl_chan, fsl_desc->tcd[0].vtcd, dma_src, dma_dst,
 764                         fsl_edma_get_tcd_attr(DMA_SLAVE_BUSWIDTH_32_BYTES),
 765                         32, len, 0, 1, 1, 32, 0, true, true, false);
 766
 767         return vchan_tx_prep(&fsl_chan->vchan, &fsl_desc->vdesc, flags);
 768 }
 769
 770 void fsl_edma_xfer_desc(struct fsl_edma_chan *fsl_chan)
 771 {
 772         struct virt_dma_desc *vdesc;
 773
 774         lockdep_assert_held(&fsl_chan->vchan.lock);
 775
 776         vdesc = vchan_next_desc(&fsl_chan->vchan);
 777         if (!vdesc)
 778                 return;
 779         fsl_chan->edesc = to_fsl_edma_desc(vdesc);
 780         fsl_edma_set_tcd_regs(fsl_chan, fsl_chan->edesc->tcd[0].vtcd);
 781         fsl_edma_enable_request(fsl_chan);
 782         fsl_chan->status = DMA_IN_PROGRESS;
 783         fsl_chan->idle = false;
 784 }
 785
 786 void fsl_edma_issue_pending(struct dma_chan *chan)
 787 {
 788         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 789         unsigned long flags;
 790
 791         spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
 792
 793         if (unlikely(fsl_chan->pm_state != RUNNING)) {
 794                 spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 795                 /* cannot submit due to suspend */
 796                 return;
 797         }
 798
 799         if (vchan_issue_pending(&fsl_chan->vchan) && !fsl_chan->edesc)
 800                 fsl_edma_xfer_desc(fsl_chan);
 801
 802         spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 803 }
 804
 805 int fsl_edma_alloc_chan_resources(struct dma_chan *chan)
 806 {
 807         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 808
 809         if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_HAS_CHCLK)
 810                 clk_prepare_enable(fsl_chan->clk);
 811
 812         fsl_chan->tcd_pool = dma_pool_create("tcd_pool", chan->device->dev,
 813                                 fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_TCD64 ?
 814                                 sizeof(struct fsl_edma_hw_tcd64) : sizeof(struct fsl_edma_hw_tcd),
 815                                 32, 0);
 816         return 0;
 817 }
 818
 819 void fsl_edma_free_chan_resources(struct dma_chan *chan)
 820 {
 821         struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
 822         struct fsl_edma_engine *edma = fsl_chan->edma;
 823         unsigned long flags;
 824         LIST_HEAD(head);
 825
 826         spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
 827         fsl_edma_disable_request(fsl_chan);
 828         if (edma->drvdata->dmamuxs)
 829                 fsl_edma_chan_mux(fsl_chan, 0, false);
 830         fsl_chan->edesc = NULL;
 831         vchan_get_all_descriptors(&fsl_chan->vchan, &head);
 832         fsl_edma_unprep_slave_dma(fsl_chan);
 833         spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
 834
 835         vchan_dma_desc_free_list(&fsl_chan->vchan, &head);
 836         dma_pool_destroy(fsl_chan->tcd_pool);
 837         fsl_chan->tcd_pool = NULL;
 838         fsl_chan->is_sw = false;
 839         fsl_chan->srcid = 0;
 840         if (fsl_edma_drvflags(fsl_chan) & FSL_EDMA_DRV_HAS_CHCLK)
 841                 clk_disable_unprepare(fsl_chan->clk);
 842 }
 843
 844 void fsl_edma_cleanup_vchan(struct dma_device *dmadev)
 845 {
 846         struct fsl_edma_chan *chan, *_chan;
 847
 848         list_for_each_entry_safe(chan, _chan,
 849                                 &dmadev->channels, vchan.chan.device_node) {
 850                 list_del(&chan->vchan.chan.device_node);
 851                 tasklet_kill(&chan->vchan.task);
 852         }
 853 }
 854
 855 /*
 856  * On the 32 channels Vybrid/mpc577x edma version, register offsets are
 857  * different compared to ColdFire mcf5441x 64 channels edma.
 858  *
 859  * This function sets up register offsets as per proper declared version
 860  * so must be called in xxx_edma_probe() just after setting the
 861  * edma "version" and "membase" appropriately.
 862  */
 863 void fsl_edma_setup_regs(struct fsl_edma_engine *edma)
 864 {
 865         bool is64 = !!(edma->drvdata->flags & FSL_EDMA_DRV_EDMA64);
 866
 867         edma->regs.cr = edma->membase + EDMA_CR;
 868         edma->regs.es = edma->membase + EDMA_ES;
 869         edma->regs.erql = edma->membase + EDMA_ERQ;
 870         edma->regs.eeil = edma->membase + EDMA_EEI;
 871
 872         edma->regs.serq = edma->membase + (is64 ? EDMA64_SERQ : EDMA_SERQ);
 873         edma->regs.cerq = edma->membase + (is64 ? EDMA64_CERQ : EDMA_CERQ);
 874         edma->regs.seei = edma->membase + (is64 ? EDMA64_SEEI : EDMA_SEEI);
 875         edma->regs.ceei = edma->membase + (is64 ? EDMA64_CEEI : EDMA_CEEI);
 876         edma->regs.cint = edma->membase + (is64 ? EDMA64_CINT : EDMA_CINT);
 877         edma->regs.cerr = edma->membase + (is64 ? EDMA64_CERR : EDMA_CERR);
 878         edma->regs.ssrt = edma->membase + (is64 ? EDMA64_SSRT : EDMA_SSRT);
 879         edma->regs.cdne = edma->membase + (is64 ? EDMA64_CDNE : EDMA_CDNE);
 880         edma->regs.intl = edma->membase + (is64 ? EDMA64_INTL : EDMA_INTR);
 881         edma->regs.errl = edma->membase + (is64 ? EDMA64_ERRL : EDMA_ERR);
 882
 883         if (is64) {
 884                 edma->regs.erqh = edma->membase + EDMA64_ERQH;
 885                 edma->regs.eeih = edma->membase + EDMA64_EEIH;
 886                 edma->regs.errh = edma->membase + EDMA64_ERRH;
 887                 edma->regs.inth = edma->membase + EDMA64_INTH;
 888         }
 889 }
 890
 891 MODULE_LICENSE("GPL v2");