drivers/crypto/n2_core.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /* n2_core.c: Niagara2 Stream Processing Unit (SPU) crypto support.
   3  *
   4  * Copyright (C) 2010, 2011 David S. Miller <[email protected]>
   5  */
   6
   7 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
   8
   9 #include <linux/kernel.h>
  10 #include <linux/module.h>
  11 #include <linux/of.h>
  12 #include <linux/of_address.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/cpumask.h>
  15 #include <linux/slab.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/crypto.h>
  18 #include <crypto/md5.h>
  19 #include <crypto/sha1.h>
  20 #include <crypto/sha2.h>
  21 #include <crypto/aes.h>
  22 #include <crypto/internal/des.h>
  23 #include <linux/mutex.h>
  24 #include <linux/delay.h>
  25 #include <linux/sched.h>
  26
  27 #include <crypto/internal/hash.h>
  28 #include <crypto/internal/skcipher.h>
  29 #include <crypto/scatterwalk.h>
  30 #include <crypto/algapi.h>
  31
  32 #include <asm/hypervisor.h>
  33 #include <asm/mdesc.h>
  34
  35 #include "n2_core.h"
  36
  37 #define DRV_MODULE_NAME         "n2_crypto"
  38 #define DRV_MODULE_VERSION      "0.2"
  39 #define DRV_MODULE_RELDATE      "July 28, 2011"
  40
  41 static const char version[] =
  42         DRV_MODULE_NAME ".c:v" DRV_MODULE_VERSION " (" DRV_MODULE_RELDATE ")\n";
  43
  44 MODULE_AUTHOR("David S. Miller <[email protected]>");
  45 MODULE_DESCRIPTION("Niagara2 Crypto driver");
  46 MODULE_LICENSE("GPL");
  47 MODULE_VERSION(DRV_MODULE_VERSION);
  48
  49 #define N2_CRA_PRIORITY         200
  50
  51 static DEFINE_MUTEX(spu_lock);
  52
  53 struct spu_queue {
  54         cpumask_t               sharing;
  55         unsigned long           qhandle;
  56
  57         spinlock_t              lock;
  58         u8                      q_type;
  59         void                    *q;
  60         unsigned long           head;
  61         unsigned long           tail;
  62         struct list_head        jobs;
  63
  64         unsigned long           devino;
  65
  66         char                    irq_name[32];
  67         unsigned int            irq;
  68
  69         struct list_head        list;
  70 };
  71
  72 struct spu_qreg {
  73         struct spu_queue        *queue;
  74         unsigned long           type;
  75 };
  76
  77 static struct spu_queue **cpu_to_cwq;
  78 static struct spu_queue **cpu_to_mau;
  79
  80 static unsigned long spu_next_offset(struct spu_queue *q, unsigned long off)
  81 {
  82         if (q->q_type == HV_NCS_QTYPE_MAU) {
  83                 off += MAU_ENTRY_SIZE;
  84                 if (off == (MAU_ENTRY_SIZE * MAU_NUM_ENTRIES))
  85                         off = 0;
  86         } else {
  87                 off += CWQ_ENTRY_SIZE;
  88                 if (off == (CWQ_ENTRY_SIZE * CWQ_NUM_ENTRIES))
  89                         off = 0;
  90         }
  91         return off;
  92 }
  93
  94 struct n2_request_common {
  95         struct list_head        entry;
  96         unsigned int            offset;
  97 };
  98 #define OFFSET_NOT_RUNNING      (~(unsigned int)0)
  99
 100 /* An async job request records the final tail value it used in
 101  * n2_request_common->offset, test to see if that offset is in
 102  * the range old_head, new_head, inclusive.
 103  */
 104 static inline bool job_finished(struct spu_queue *q, unsigned int offset,
 105                                 unsigned long old_head, unsigned long new_head)
 106 {
 107         if (old_head <= new_head) {
 108                 if (offset > old_head && offset <= new_head)
 109                         return true;
 110         } else {
 111                 if (offset > old_head || offset <= new_head)
 112                         return true;
 113         }
 114         return false;
 115 }
 116
 117 /* When the HEAD marker is unequal to the actual HEAD, we get
 118  * a virtual device INO interrupt.  We should process the
 119  * completed CWQ entries and adjust the HEAD marker to clear
 120  * the IRQ.
 121  */
 122 static irqreturn_t cwq_intr(int irq, void *dev_id)
 123 {
 124         unsigned long off, new_head, hv_ret;
 125         struct spu_queue *q = dev_id;
 126
 127         pr_err("CPU[%d]: Got CWQ interrupt for qhdl[%lx]\n",
 128                smp_processor_id(), q->qhandle);
 129
 130         spin_lock(&q->lock);
 131
 132         hv_ret = sun4v_ncs_gethead(q->qhandle, &new_head);
 133
 134         pr_err("CPU[%d]: CWQ gethead[%lx] hv_ret[%lu]\n",
 135                smp_processor_id(), new_head, hv_ret);
 136
 137         for (off = q->head; off != new_head; off = spu_next_offset(q, off)) {
 138                 /* XXX ... XXX */
 139         }
 140
 141         hv_ret = sun4v_ncs_sethead_marker(q->qhandle, new_head);
 142         if (hv_ret == HV_EOK)
 143                 q->head = new_head;
 144
 145         spin_unlock(&q->lock);
 146
 147         return IRQ_HANDLED;
 148 }
 149
 150 static irqreturn_t mau_intr(int irq, void *dev_id)
 151 {
 152         struct spu_queue *q = dev_id;
 153         unsigned long head, hv_ret;
 154
 155         spin_lock(&q->lock);
 156
 157         pr_err("CPU[%d]: Got MAU interrupt for qhdl[%lx]\n",
 158                smp_processor_id(), q->qhandle);
 159
 160         hv_ret = sun4v_ncs_gethead(q->qhandle, &head);
 161
 162         pr_err("CPU[%d]: MAU gethead[%lx] hv_ret[%lu]\n",
 163                smp_processor_id(), head, hv_ret);
 164
 165         sun4v_ncs_sethead_marker(q->qhandle, head);
 166
 167         spin_unlock(&q->lock);
 168
 169         return IRQ_HANDLED;
 170 }
 171
 172 static void *spu_queue_next(struct spu_queue *q, void *cur)
 173 {
 174         return q->q + spu_next_offset(q, cur - q->q);
 175 }
 176
 177 static int spu_queue_num_free(struct spu_queue *q)
 178 {
 179         unsigned long head = q->head;
 180         unsigned long tail = q->tail;
 181         unsigned long end = (CWQ_ENTRY_SIZE * CWQ_NUM_ENTRIES);
 182         unsigned long diff;
 183
 184         if (head > tail)
 185                 diff = head - tail;
 186         else
 187                 diff = (end - tail) + head;
 188
 189         return (diff / CWQ_ENTRY_SIZE) - 1;
 190 }
 191
 192 static void *spu_queue_alloc(struct spu_queue *q, int num_entries)
 193 {
 194         int avail = spu_queue_num_free(q);
 195
 196         if (avail >= num_entries)
 197                 return q->q + q->tail;
 198
 199         return NULL;
 200 }
 201
 202 static unsigned long spu_queue_submit(struct spu_queue *q, void *last)
 203 {
 204         unsigned long hv_ret, new_tail;
 205
 206         new_tail = spu_next_offset(q, last - q->q);
 207
 208         hv_ret = sun4v_ncs_settail(q->qhandle, new_tail);
 209         if (hv_ret == HV_EOK)
 210                 q->tail = new_tail;
 211         return hv_ret;
 212 }
 213
 214 static u64 control_word_base(unsigned int len, unsigned int hmac_key_len,
 215                              int enc_type, int auth_type,
 216                              unsigned int hash_len,
 217                              bool sfas, bool sob, bool eob, bool encrypt,
 218                              int opcode)
 219 {
 220         u64 word = (len - 1) & CONTROL_LEN;
 221
 222         word |= ((u64) opcode << CONTROL_OPCODE_SHIFT);
 223         word |= ((u64) enc_type << CONTROL_ENC_TYPE_SHIFT);
 224         word |= ((u64) auth_type << CONTROL_AUTH_TYPE_SHIFT);
 225         if (sfas)
 226                 word |= CONTROL_STORE_FINAL_AUTH_STATE;
 227         if (sob)
 228                 word |= CONTROL_START_OF_BLOCK;
 229         if (eob)
 230                 word |= CONTROL_END_OF_BLOCK;
 231         if (encrypt)
 232                 word |= CONTROL_ENCRYPT;
 233         if (hmac_key_len)
 234                 word |= ((u64) (hmac_key_len - 1)) << CONTROL_HMAC_KEY_LEN_SHIFT;
 235         if (hash_len)
 236                 word |= ((u64) (hash_len - 1)) << CONTROL_HASH_LEN_SHIFT;
 237
 238         return word;
 239 }
 240
 241 #if 0
 242 static inline bool n2_should_run_async(struct spu_queue *qp, int this_len)
 243 {
 244         if (this_len >= 64 ||
 245             qp->head != qp->tail)
 246                 return true;
 247         return false;
 248 }
 249 #endif
 250
 251 struct n2_ahash_alg {
 252         struct list_head        entry;
 253         const u8                *hash_zero;
 254         const u8                *hash_init;
 255         u8                      hw_op_hashsz;
 256         u8                      digest_size;
 257         u8                      auth_type;
 258         u8                      hmac_type;
 259         struct ahash_alg        alg;
 260 };
 261
 262 static inline struct n2_ahash_alg *n2_ahash_alg(struct crypto_tfm *tfm)
 263 {
 264         struct crypto_alg *alg = tfm->__crt_alg;
 265         struct ahash_alg *ahash_alg;
 266
 267         ahash_alg = container_of(alg, struct ahash_alg, halg.base);
 268
 269         return container_of(ahash_alg, struct n2_ahash_alg, alg);
 270 }
 271
 272 struct n2_hmac_alg {
 273         const char              *child_alg;
 274         struct n2_ahash_alg     derived;
 275 };
 276
 277 static inline struct n2_hmac_alg *n2_hmac_alg(struct crypto_tfm *tfm)
 278 {
 279         struct crypto_alg *alg = tfm->__crt_alg;
 280         struct ahash_alg *ahash_alg;
 281
 282         ahash_alg = container_of(alg, struct ahash_alg, halg.base);
 283
 284         return container_of(ahash_alg, struct n2_hmac_alg, derived.alg);
 285 }
 286
 287 struct n2_hash_ctx {
 288         struct crypto_ahash             *fallback_tfm;
 289 };
 290
 291 #define N2_HASH_KEY_MAX                 32 /* HW limit for all HMAC requests */
 292
 293 struct n2_hmac_ctx {
 294         struct n2_hash_ctx              base;
 295
 296         struct crypto_shash             *child_shash;
 297
 298         int                             hash_key_len;
 299         unsigned char                   hash_key[N2_HASH_KEY_MAX];
 300 };
 301
 302 struct n2_hash_req_ctx {
 303         union {
 304                 struct md5_state        md5;
 305                 struct sha1_state       sha1;
 306                 struct sha256_state     sha256;
 307         } u;
 308
 309         struct ahash_request            fallback_req;
 310 };
 311
 312 static int n2_hash_async_init(struct ahash_request *req)
 313 {
 314         struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
 315         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 316         struct n2_hash_ctx *ctx = crypto_ahash_ctx(tfm);
 317
 318         ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
 319         rctx->fallback_req.base.flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP;
 320
 321         return crypto_ahash_init(&rctx->fallback_req);
 322 }
 323
 324 static int n2_hash_async_update(struct ahash_request *req)
 325 {
 326         struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
 327         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 328         struct n2_hash_ctx *ctx = crypto_ahash_ctx(tfm);
 329
 330         ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
 331         rctx->fallback_req.base.flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP;
 332         rctx->fallback_req.nbytes = req->nbytes;
 333         rctx->fallback_req.src = req->src;
 334
 335         return crypto_ahash_update(&rctx->fallback_req);
 336 }
 337
 338 static int n2_hash_async_final(struct ahash_request *req)
 339 {
 340         struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
 341         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 342         struct n2_hash_ctx *ctx = crypto_ahash_ctx(tfm);
 343
 344         ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
 345         rctx->fallback_req.base.flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP;
 346         rctx->fallback_req.result = req->result;
 347
 348         return crypto_ahash_final(&rctx->fallback_req);
 349 }
 350
 351 static int n2_hash_async_finup(struct ahash_request *req)
 352 {
 353         struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
 354         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 355         struct n2_hash_ctx *ctx = crypto_ahash_ctx(tfm);
 356
 357         ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
 358         rctx->fallback_req.base.flags = req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP;
 359         rctx->fallback_req.nbytes = req->nbytes;
 360         rctx->fallback_req.src = req->src;
 361         rctx->fallback_req.result = req->result;
 362
 363         return crypto_ahash_finup(&rctx->fallback_req);
 364 }
 365
 366 static int n2_hash_async_noimport(struct ahash_request *req, const void *in)
 367 {
 368         return -ENOSYS;
 369 }
 370
 371 static int n2_hash_async_noexport(struct ahash_request *req, void *out)
 372 {
 373         return -ENOSYS;
 374 }
 375
 376 static int n2_hash_cra_init(struct crypto_tfm *tfm)
 377 {
 378         const char *fallback_driver_name = crypto_tfm_alg_name(tfm);
 379         struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
 380         struct n2_hash_ctx *ctx = crypto_ahash_ctx(ahash);
 381         struct crypto_ahash *fallback_tfm;
 382         int err;
 383
 384         fallback_tfm = crypto_alloc_ahash(fallback_driver_name, 0,
 385                                           CRYPTO_ALG_NEED_FALLBACK);
 386         if (IS_ERR(fallback_tfm)) {
 387                 pr_warn("Fallback driver '%s' could not be loaded!\n",
 388                         fallback_driver_name);
 389                 err = PTR_ERR(fallback_tfm);
 390                 goto out;
 391         }
 392
 393         crypto_ahash_set_reqsize(ahash, (sizeof(struct n2_hash_req_ctx) +
 394                                          crypto_ahash_reqsize(fallback_tfm)));
 395
 396         ctx->fallback_tfm = fallback_tfm;
 397         return 0;
 398
 399 out:
 400         return err;
 401 }
 402
 403 static void n2_hash_cra_exit(struct crypto_tfm *tfm)
 404 {
 405         struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
 406         struct n2_hash_ctx *ctx = crypto_ahash_ctx(ahash);
 407
 408         crypto_free_ahash(ctx->fallback_tfm);
 409 }
 410
 411 static int n2_hmac_cra_init(struct crypto_tfm *tfm)
 412 {
 413         const char *fallback_driver_name = crypto_tfm_alg_name(tfm);
 414         struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
 415         struct n2_hmac_ctx *ctx = crypto_ahash_ctx(ahash);
 416         struct n2_hmac_alg *n2alg = n2_hmac_alg(tfm);
 417         struct crypto_ahash *fallback_tfm;
 418         struct crypto_shash *child_shash;
 419         int err;
 420
 421         fallback_tfm = crypto_alloc_ahash(fallback_driver_name, 0,
 422                                           CRYPTO_ALG_NEED_FALLBACK);
 423         if (IS_ERR(fallback_tfm)) {
 424                 pr_warn("Fallback driver '%s' could not be loaded!\n",
 425                         fallback_driver_name);
 426                 err = PTR_ERR(fallback_tfm);
 427                 goto out;
 428         }
 429
 430         child_shash = crypto_alloc_shash(n2alg->child_alg, 0, 0);
 431         if (IS_ERR(child_shash)) {
 432                 pr_warn("Child shash '%s' could not be loaded!\n",
 433                         n2alg->child_alg);
 434                 err = PTR_ERR(child_shash);
 435                 goto out_free_fallback;
 436         }
 437
 438         crypto_ahash_set_reqsize(ahash, (sizeof(struct n2_hash_req_ctx) +
 439                                          crypto_ahash_reqsize(fallback_tfm)));
 440
 441         ctx->child_shash = child_shash;
 442         ctx->base.fallback_tfm = fallback_tfm;
 443         return 0;
 444
 445 out_free_fallback:
 446         crypto_free_ahash(fallback_tfm);
 447
 448 out:
 449         return err;
 450 }
 451
 452 static void n2_hmac_cra_exit(struct crypto_tfm *tfm)
 453 {
 454         struct crypto_ahash *ahash = __crypto_ahash_cast(tfm);
 455         struct n2_hmac_ctx *ctx = crypto_ahash_ctx(ahash);
 456
 457         crypto_free_ahash(ctx->base.fallback_tfm);
 458         crypto_free_shash(ctx->child_shash);
 459 }
 460
 461 static int n2_hmac_async_setkey(struct crypto_ahash *tfm, const u8 *key,
 462                                 unsigned int keylen)
 463 {
 464         struct n2_hmac_ctx *ctx = crypto_ahash_ctx(tfm);
 465         struct crypto_shash *child_shash = ctx->child_shash;
 466         struct crypto_ahash *fallback_tfm;
 467         int err, bs, ds;
 468
 469         fallback_tfm = ctx->base.fallback_tfm;
 470         err = crypto_ahash_setkey(fallback_tfm, key, keylen);
 471         if (err)
 472                 return err;
 473
 474         bs = crypto_shash_blocksize(child_shash);
 475         ds = crypto_shash_digestsize(child_shash);
 476         BUG_ON(ds > N2_HASH_KEY_MAX);
 477         if (keylen > bs) {
 478                 err = crypto_shash_tfm_digest(child_shash, key, keylen,
 479                                               ctx->hash_key);
 480                 if (err)
 481                         return err;
 482                 keylen = ds;
 483         } else if (keylen <= N2_HASH_KEY_MAX)
 484                 memcpy(ctx->hash_key, key, keylen);
 485
 486         ctx->hash_key_len = keylen;
 487
 488         return err;
 489 }
 490
 491 static unsigned long wait_for_tail(struct spu_queue *qp)
 492 {
 493         unsigned long head, hv_ret;
 494
 495         do {
 496                 hv_ret = sun4v_ncs_gethead(qp->qhandle, &head);
 497                 if (hv_ret != HV_EOK) {
 498                         pr_err("Hypervisor error on gethead\n");
 499                         break;
 500                 }
 501                 if (head == qp->tail) {
 502                         qp->head = head;
 503                         break;
 504                 }
 505         } while (1);
 506         return hv_ret;
 507 }
 508
 509 static unsigned long submit_and_wait_for_tail(struct spu_queue *qp,
 510                                               struct cwq_initial_entry *ent)
 511 {
 512         unsigned long hv_ret = spu_queue_submit(qp, ent);
 513
 514         if (hv_ret == HV_EOK)
 515                 hv_ret = wait_for_tail(qp);
 516
 517         return hv_ret;
 518 }
 519
 520 static int n2_do_async_digest(struct ahash_request *req,
 521                               unsigned int auth_type, unsigned int digest_size,
 522                               unsigned int result_size, void *hash_loc,
 523                               unsigned long auth_key, unsigned int auth_key_len)
 524 {
 525         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 526         struct cwq_initial_entry *ent;
 527         struct crypto_hash_walk walk;
 528         struct spu_queue *qp;
 529         unsigned long flags;
 530         int err = -ENODEV;
 531         int nbytes, cpu;
 532
 533         /* The total effective length of the operation may not
 534          * exceed 2^16.
 535          */
 536         if (unlikely(req->nbytes > (1 << 16))) {
 537                 struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
 538                 struct n2_hash_ctx *ctx = crypto_ahash_ctx(tfm);
 539
 540                 ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
 541                 rctx->fallback_req.base.flags =
 542                         req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP;
 543                 rctx->fallback_req.nbytes = req->nbytes;
 544                 rctx->fallback_req.src = req->src;
 545                 rctx->fallback_req.result = req->result;
 546
 547                 return crypto_ahash_digest(&rctx->fallback_req);
 548         }
 549
 550         nbytes = crypto_hash_walk_first(req, &walk);
 551
 552         cpu = get_cpu();
 553         qp = cpu_to_cwq[cpu];
 554         if (!qp)
 555                 goto out;
 556
 557         spin_lock_irqsave(&qp->lock, flags);
 558
 559         /* XXX can do better, improve this later by doing a by-hand scatterlist
 560          * XXX walk, etc.
 561          */
 562         ent = qp->q + qp->tail;
 563
 564         ent->control = control_word_base(nbytes, auth_key_len, 0,
 565                                          auth_type, digest_size,
 566                                          false, true, false, false,
 567                                          OPCODE_INPLACE_BIT |
 568                                          OPCODE_AUTH_MAC);
 569         ent->src_addr = __pa(walk.data);
 570         ent->auth_key_addr = auth_key;
 571         ent->auth_iv_addr = __pa(hash_loc);
 572         ent->final_auth_state_addr = 0UL;
 573         ent->enc_key_addr = 0UL;
 574         ent->enc_iv_addr = 0UL;
 575         ent->dest_addr = __pa(hash_loc);
 576
 577         nbytes = crypto_hash_walk_done(&walk, 0);
 578         while (nbytes > 0) {
 579                 ent = spu_queue_next(qp, ent);
 580
 581                 ent->control = (nbytes - 1);
 582                 ent->src_addr = __pa(walk.data);
 583                 ent->auth_key_addr = 0UL;
 584                 ent->auth_iv_addr = 0UL;
 585                 ent->final_auth_state_addr = 0UL;
 586                 ent->enc_key_addr = 0UL;
 587                 ent->enc_iv_addr = 0UL;
 588                 ent->dest_addr = 0UL;
 589
 590                 nbytes = crypto_hash_walk_done(&walk, 0);
 591         }
 592         ent->control |= CONTROL_END_OF_BLOCK;
 593
 594         if (submit_and_wait_for_tail(qp, ent) != HV_EOK)
 595                 err = -EINVAL;
 596         else
 597                 err = 0;
 598
 599         spin_unlock_irqrestore(&qp->lock, flags);
 600
 601         if (!err)
 602                 memcpy(req->result, hash_loc, result_size);
 603 out:
 604         put_cpu();
 605
 606         return err;
 607 }
 608
 609 static int n2_hash_async_digest(struct ahash_request *req)
 610 {
 611         struct n2_ahash_alg *n2alg = n2_ahash_alg(req->base.tfm);
 612         struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
 613         int ds;
 614
 615         ds = n2alg->digest_size;
 616         if (unlikely(req->nbytes == 0)) {
 617                 memcpy(req->result, n2alg->hash_zero, ds);
 618                 return 0;
 619         }
 620         memcpy(&rctx->u, n2alg->hash_init, n2alg->hw_op_hashsz);
 621
 622         return n2_do_async_digest(req, n2alg->auth_type,
 623                                   n2alg->hw_op_hashsz, ds,
 624                                   &rctx->u, 0UL, 0);
 625 }
 626
 627 static int n2_hmac_async_digest(struct ahash_request *req)
 628 {
 629         struct n2_hmac_alg *n2alg = n2_hmac_alg(req->base.tfm);
 630         struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
 631         struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
 632         struct n2_hmac_ctx *ctx = crypto_ahash_ctx(tfm);
 633         int ds;
 634
 635         ds = n2alg->derived.digest_size;
 636         if (unlikely(req->nbytes == 0) ||
 637             unlikely(ctx->hash_key_len > N2_HASH_KEY_MAX)) {
 638                 struct n2_hash_req_ctx *rctx = ahash_request_ctx(req);
 639                 struct n2_hash_ctx *ctx = crypto_ahash_ctx(tfm);
 640
 641                 ahash_request_set_tfm(&rctx->fallback_req, ctx->fallback_tfm);
 642                 rctx->fallback_req.base.flags =
 643                         req->base.flags & CRYPTO_TFM_REQ_MAY_SLEEP;
 644                 rctx->fallback_req.nbytes = req->nbytes;
 645                 rctx->fallback_req.src = req->src;
 646                 rctx->fallback_req.result = req->result;
 647
 648                 return crypto_ahash_digest(&rctx->fallback_req);
 649         }
 650         memcpy(&rctx->u, n2alg->derived.hash_init,
 651                n2alg->derived.hw_op_hashsz);
 652
 653         return n2_do_async_digest(req, n2alg->derived.hmac_type,
 654                                   n2alg->derived.hw_op_hashsz, ds,
 655                                   &rctx->u,
 656                                   __pa(&ctx->hash_key),
 657                                   ctx->hash_key_len);
 658 }
 659
 660 struct n2_skcipher_context {
 661         int                     key_len;
 662         int                     enc_type;
 663         union {
 664                 u8              aes[AES_MAX_KEY_SIZE];
 665                 u8              des[DES_KEY_SIZE];
 666                 u8              des3[3 * DES_KEY_SIZE];
 667         } key;
 668 };
 669
 670 #define N2_CHUNK_ARR_LEN        16
 671
 672 struct n2_crypto_chunk {
 673         struct list_head        entry;
 674         unsigned long           iv_paddr : 44;
 675         unsigned long           arr_len : 20;
 676         unsigned long           dest_paddr;
 677         unsigned long           dest_final;
 678         struct {
 679                 unsigned long   src_paddr : 44;
 680                 unsigned long   src_len : 20;
 681         } arr[N2_CHUNK_ARR_LEN];
 682 };
 683
 684 struct n2_request_context {
 685         struct skcipher_walk    walk;
 686         struct list_head        chunk_list;
 687         struct n2_crypto_chunk  chunk;
 688         u8                      temp_iv[16];
 689 };
 690
 691 /* The SPU allows some level of flexibility for partial cipher blocks
 692  * being specified in a descriptor.
 693  *
 694  * It merely requires that every descriptor's length field is at least
 695  * as large as the cipher block size.  This means that a cipher block
 696  * can span at most 2 descriptors.  However, this does not allow a
 697  * partial block to span into the final descriptor as that would
 698  * violate the rule (since every descriptor's length must be at lest
 699  * the block size).  So, for example, assuming an 8 byte block size:
 700  *
 701  *      0xe --> 0xa --> 0x8
 702  *
 703  * is a valid length sequence, whereas:
 704  *
 705  *      0xe --> 0xb --> 0x7
 706  *
 707  * is not a valid sequence.
 708  */
 709
 710 struct n2_skcipher_alg {
 711         struct list_head        entry;
 712         u8                      enc_type;
 713         struct skcipher_alg     skcipher;
 714 };
 715
 716 static inline struct n2_skcipher_alg *n2_skcipher_alg(struct crypto_skcipher *tfm)
 717 {
 718         struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
 719
 720         return container_of(alg, struct n2_skcipher_alg, skcipher);
 721 }
 722
 723 struct n2_skcipher_request_context {
 724         struct skcipher_walk    walk;
 725 };
 726
 727 static int n2_aes_setkey(struct crypto_skcipher *skcipher, const u8 *key,
 728                          unsigned int keylen)
 729 {
 730         struct crypto_tfm *tfm = crypto_skcipher_tfm(skcipher);
 731         struct n2_skcipher_context *ctx = crypto_tfm_ctx(tfm);
 732         struct n2_skcipher_alg *n2alg = n2_skcipher_alg(skcipher);
 733
 734         ctx->enc_type = (n2alg->enc_type & ENC_TYPE_CHAINING_MASK);
 735
 736         switch (keylen) {
 737         case AES_KEYSIZE_128:
 738                 ctx->enc_type |= ENC_TYPE_ALG_AES128;
 739                 break;
 740         case AES_KEYSIZE_192:
 741                 ctx->enc_type |= ENC_TYPE_ALG_AES192;
 742                 break;
 743         case AES_KEYSIZE_256:
 744                 ctx->enc_type |= ENC_TYPE_ALG_AES256;
 745                 break;
 746         default:
 747                 return -EINVAL;
 748         }
 749
 750         ctx->key_len = keylen;
 751         memcpy(ctx->key.aes, key, keylen);
 752         return 0;
 753 }
 754
 755 static int n2_des_setkey(struct crypto_skcipher *skcipher, const u8 *key,
 756                          unsigned int keylen)
 757 {
 758         struct crypto_tfm *tfm = crypto_skcipher_tfm(skcipher);
 759         struct n2_skcipher_context *ctx = crypto_tfm_ctx(tfm);
 760         struct n2_skcipher_alg *n2alg = n2_skcipher_alg(skcipher);
 761         int err;
 762
 763         err = verify_skcipher_des_key(skcipher, key);
 764         if (err)
 765                 return err;
 766
 767         ctx->enc_type = n2alg->enc_type;
 768
 769         ctx->key_len = keylen;
 770         memcpy(ctx->key.des, key, keylen);
 771         return 0;
 772 }
 773
 774 static int n2_3des_setkey(struct crypto_skcipher *skcipher, const u8 *key,
 775                           unsigned int keylen)
 776 {
 777         struct crypto_tfm *tfm = crypto_skcipher_tfm(skcipher);
 778         struct n2_skcipher_context *ctx = crypto_tfm_ctx(tfm);
 779         struct n2_skcipher_alg *n2alg = n2_skcipher_alg(skcipher);
 780         int err;
 781
 782         err = verify_skcipher_des3_key(skcipher, key);
 783         if (err)
 784                 return err;
 785
 786         ctx->enc_type = n2alg->enc_type;
 787
 788         ctx->key_len = keylen;
 789         memcpy(ctx->key.des3, key, keylen);
 790         return 0;
 791 }
 792
 793 static inline int skcipher_descriptor_len(int nbytes, unsigned int block_size)
 794 {
 795         int this_len = nbytes;
 796
 797         this_len -= (nbytes & (block_size - 1));
 798         return this_len > (1 << 16) ? (1 << 16) : this_len;
 799 }
 800
 801 static int __n2_crypt_chunk(struct crypto_skcipher *skcipher,
 802                             struct n2_crypto_chunk *cp,
 803                             struct spu_queue *qp, bool encrypt)
 804 {
 805         struct n2_skcipher_context *ctx = crypto_skcipher_ctx(skcipher);
 806         struct cwq_initial_entry *ent;
 807         bool in_place;
 808         int i;
 809
 810         ent = spu_queue_alloc(qp, cp->arr_len);
 811         if (!ent) {
 812                 pr_info("queue_alloc() of %d fails\n",
 813                         cp->arr_len);
 814                 return -EBUSY;
 815         }
 816
 817         in_place = (cp->dest_paddr == cp->arr[0].src_paddr);
 818
 819         ent->control = control_word_base(cp->arr[0].src_len,
 820                                          0, ctx->enc_type, 0, 0,
 821                                          false, true, false, encrypt,
 822                                          OPCODE_ENCRYPT |
 823                                          (in_place ? OPCODE_INPLACE_BIT : 0));
 824         ent->src_addr = cp->arr[0].src_paddr;
 825         ent->auth_key_addr = 0UL;
 826         ent->auth_iv_addr = 0UL;
 827         ent->final_auth_state_addr = 0UL;
 828         ent->enc_key_addr = __pa(&ctx->key);
 829         ent->enc_iv_addr = cp->iv_paddr;
 830         ent->dest_addr = (in_place ? 0UL : cp->dest_paddr);
 831
 832         for (i = 1; i < cp->arr_len; i++) {
 833                 ent = spu_queue_next(qp, ent);
 834
 835                 ent->control = cp->arr[i].src_len - 1;
 836                 ent->src_addr = cp->arr[i].src_paddr;
 837                 ent->auth_key_addr = 0UL;
 838                 ent->auth_iv_addr = 0UL;
 839                 ent->final_auth_state_addr = 0UL;
 840                 ent->enc_key_addr = 0UL;
 841                 ent->enc_iv_addr = 0UL;
 842                 ent->dest_addr = 0UL;
 843         }
 844         ent->control |= CONTROL_END_OF_BLOCK;
 845
 846         return (spu_queue_submit(qp, ent) != HV_EOK) ? -EINVAL : 0;
 847 }
 848
 849 static int n2_compute_chunks(struct skcipher_request *req)
 850 {
 851         struct n2_request_context *rctx = skcipher_request_ctx(req);
 852         struct skcipher_walk *walk = &rctx->walk;
 853         struct n2_crypto_chunk *chunk;
 854         unsigned long dest_prev;
 855         unsigned int tot_len;
 856         bool prev_in_place;
 857         int err, nbytes;
 858
 859         err = skcipher_walk_async(walk, req);
 860         if (err)
 861                 return err;
 862
 863         INIT_LIST_HEAD(&rctx->chunk_list);
 864
 865         chunk = &rctx->chunk;
 866         INIT_LIST_HEAD(&chunk->entry);
 867
 868         chunk->iv_paddr = 0UL;
 869         chunk->arr_len = 0;
 870         chunk->dest_paddr = 0UL;
 871
 872         prev_in_place = false;
 873         dest_prev = ~0UL;
 874         tot_len = 0;
 875
 876         while ((nbytes = walk->nbytes) != 0) {
 877                 unsigned long dest_paddr, src_paddr;
 878                 bool in_place;
 879                 int this_len;
 880
 881                 src_paddr = (page_to_phys(walk->src.phys.page) +
 882                              walk->src.phys.offset);
 883                 dest_paddr = (page_to_phys(walk->dst.phys.page) +
 884                               walk->dst.phys.offset);
 885                 in_place = (src_paddr == dest_paddr);
 886                 this_len = skcipher_descriptor_len(nbytes, walk->blocksize);
 887
 888                 if (chunk->arr_len != 0) {
 889                         if (in_place != prev_in_place ||
 890                             (!prev_in_place &&
 891                              dest_paddr != dest_prev) ||
 892                             chunk->arr_len == N2_CHUNK_ARR_LEN ||
 893                             tot_len + this_len > (1 << 16)) {
 894                                 chunk->dest_final = dest_prev;
 895                                 list_add_tail(&chunk->entry,
 896                                               &rctx->chunk_list);
 897                                 chunk = kzalloc(sizeof(*chunk), GFP_ATOMIC);
 898                                 if (!chunk) {
 899                                         err = -ENOMEM;
 900                                         break;
 901                                 }
 902                                 INIT_LIST_HEAD(&chunk->entry);
 903                         }
 904                 }
 905                 if (chunk->arr_len == 0) {
 906                         chunk->dest_paddr = dest_paddr;
 907                         tot_len = 0;
 908                 }
 909                 chunk->arr[chunk->arr_len].src_paddr = src_paddr;
 910                 chunk->arr[chunk->arr_len].src_len = this_len;
 911                 chunk->arr_len++;
 912
 913                 dest_prev = dest_paddr + this_len;
 914                 prev_in_place = in_place;
 915                 tot_len += this_len;
 916
 917                 err = skcipher_walk_done(walk, nbytes - this_len);
 918                 if (err)
 919                         break;
 920         }
 921         if (!err && chunk->arr_len != 0) {
 922                 chunk->dest_final = dest_prev;
 923                 list_add_tail(&chunk->entry, &rctx->chunk_list);
 924         }
 925
 926         return err;
 927 }
 928
 929 static void n2_chunk_complete(struct skcipher_request *req, void *final_iv)
 930 {
 931         struct n2_request_context *rctx = skcipher_request_ctx(req);
 932         struct n2_crypto_chunk *c, *tmp;
 933
 934         if (final_iv)
 935                 memcpy(rctx->walk.iv, final_iv, rctx->walk.blocksize);
 936
 937         list_for_each_entry_safe(c, tmp, &rctx->chunk_list, entry) {
 938                 list_del(&c->entry);
 939                 if (unlikely(c != &rctx->chunk))
 940                         kfree(c);
 941         }
 942
 943 }
 944
 945 static int n2_do_ecb(struct skcipher_request *req, bool encrypt)
 946 {
 947         struct n2_request_context *rctx = skcipher_request_ctx(req);
 948         struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
 949         int err = n2_compute_chunks(req);
 950         struct n2_crypto_chunk *c, *tmp;
 951         unsigned long flags, hv_ret;
 952         struct spu_queue *qp;
 953
 954         if (err)
 955                 return err;
 956
 957         qp = cpu_to_cwq[get_cpu()];
 958         err = -ENODEV;
 959         if (!qp)
 960                 goto out;
 961
 962         spin_lock_irqsave(&qp->lock, flags);
 963
 964         list_for_each_entry_safe(c, tmp, &rctx->chunk_list, entry) {
 965                 err = __n2_crypt_chunk(tfm, c, qp, encrypt);
 966                 if (err)
 967                         break;
 968                 list_del(&c->entry);
 969                 if (unlikely(c != &rctx->chunk))
 970                         kfree(c);
 971         }
 972         if (!err) {
 973                 hv_ret = wait_for_tail(qp);
 974                 if (hv_ret != HV_EOK)
 975                         err = -EINVAL;
 976         }
 977
 978         spin_unlock_irqrestore(&qp->lock, flags);
 979
 980 out:
 981         put_cpu();
 982
 983         n2_chunk_complete(req, NULL);
 984         return err;
 985 }
 986
 987 static int n2_encrypt_ecb(struct skcipher_request *req)
 988 {
 989         return n2_do_ecb(req, true);
 990 }
 991
 992 static int n2_decrypt_ecb(struct skcipher_request *req)
 993 {
 994         return n2_do_ecb(req, false);
 995 }
 996
 997 static int n2_do_chaining(struct skcipher_request *req, bool encrypt)
 998 {
 999         struct n2_request_context *rctx = skcipher_request_ctx(req);
1000         struct crypto_skcipher *tfm = crypto_skcipher_reqtfm(req);
1001         unsigned long flags, hv_ret, iv_paddr;
1002         int err = n2_compute_chunks(req);
1003         struct n2_crypto_chunk *c, *tmp;
1004         struct spu_queue *qp;
1005         void *final_iv_addr;
1006
1007         final_iv_addr = NULL;
1008
1009         if (err)
1010                 return err;
1011
1012         qp = cpu_to_cwq[get_cpu()];
1013         err = -ENODEV;
1014         if (!qp)
1015                 goto out;
1016
1017         spin_lock_irqsave(&qp->lock, flags);
1018
1019         if (encrypt) {
1020                 iv_paddr = __pa(rctx->walk.iv);
1021                 list_for_each_entry_safe(c, tmp, &rctx->chunk_list,
1022                                          entry) {
1023                         c->iv_paddr = iv_paddr;
1024                         err = __n2_crypt_chunk(tfm, c, qp, true);
1025                         if (err)
1026                                 break;
1027                         iv_paddr = c->dest_final - rctx->walk.blocksize;
1028                         list_del(&c->entry);
1029                         if (unlikely(c != &rctx->chunk))
1030                                 kfree(c);
1031                 }
1032                 final_iv_addr = __va(iv_paddr);
1033         } else {
1034                 list_for_each_entry_safe_reverse(c, tmp, &rctx->chunk_list,
1035                                                  entry) {
1036                         if (c == &rctx->chunk) {
1037                                 iv_paddr = __pa(rctx->walk.iv);
1038                         } else {
1039                                 iv_paddr = (tmp->arr[tmp->arr_len-1].src_paddr +
1040                                             tmp->arr[tmp->arr_len-1].src_len -
1041                                             rctx->walk.blocksize);
1042                         }
1043                         if (!final_iv_addr) {
1044                                 unsigned long pa;
1045
1046                                 pa = (c->arr[c->arr_len-1].src_paddr +
1047                                       c->arr[c->arr_len-1].src_len -
1048                                       rctx->walk.blocksize);
1049                                 final_iv_addr = rctx->temp_iv;
1050                                 memcpy(rctx->temp_iv, __va(pa),
1051                                        rctx->walk.blocksize);
1052                         }
1053                         c->iv_paddr = iv_paddr;
1054                         err = __n2_crypt_chunk(tfm, c, qp, false);
1055                         if (err)
1056                                 break;
1057                         list_del(&c->entry);
1058                         if (unlikely(c != &rctx->chunk))
1059                                 kfree(c);
1060                 }
1061         }
1062         if (!err) {
1063                 hv_ret = wait_for_tail(qp);
1064                 if (hv_ret != HV_EOK)
1065                         err = -EINVAL;
1066         }
1067
1068         spin_unlock_irqrestore(&qp->lock, flags);
1069
1070 out:
1071         put_cpu();
1072
1073         n2_chunk_complete(req, err ? NULL : final_iv_addr);
1074         return err;
1075 }
1076
1077 static int n2_encrypt_chaining(struct skcipher_request *req)
1078 {
1079         return n2_do_chaining(req, true);
1080 }
1081
1082 static int n2_decrypt_chaining(struct skcipher_request *req)
1083 {
1084         return n2_do_chaining(req, false);
1085 }
1086
1087 struct n2_skcipher_tmpl {
1088         const char              *name;
1089         const char              *drv_name;
1090         u8                      block_size;
1091         u8                      enc_type;
1092         struct skcipher_alg     skcipher;
1093 };
1094
1095 static const struct n2_skcipher_tmpl skcipher_tmpls[] = {
1096         /* DES: ECB CBC and CFB are supported */
1097         {       .name           = "ecb(des)",
1098                 .drv_name       = "ecb-des",
1099                 .block_size     = DES_BLOCK_SIZE,
1100                 .enc_type       = (ENC_TYPE_ALG_DES |
1101                                    ENC_TYPE_CHAINING_ECB),
1102                 .skcipher       = {
1103                         .min_keysize    = DES_KEY_SIZE,
1104                         .max_keysize    = DES_KEY_SIZE,
1105                         .setkey         = n2_des_setkey,
1106                         .encrypt        = n2_encrypt_ecb,
1107                         .decrypt        = n2_decrypt_ecb,
1108                 },
1109         },
1110         {       .name           = "cbc(des)",
1111                 .drv_name       = "cbc-des",
1112                 .block_size     = DES_BLOCK_SIZE,
1113                 .enc_type       = (ENC_TYPE_ALG_DES |
1114                                    ENC_TYPE_CHAINING_CBC),
1115                 .skcipher       = {
1116                         .ivsize         = DES_BLOCK_SIZE,
1117                         .min_keysize    = DES_KEY_SIZE,
1118                         .max_keysize    = DES_KEY_SIZE,
1119                         .setkey         = n2_des_setkey,
1120                         .encrypt        = n2_encrypt_chaining,
1121                         .decrypt        = n2_decrypt_chaining,
1122                 },
1123         },
1124
1125         /* 3DES: ECB CBC and CFB are supported */
1126         {       .name           = "ecb(des3_ede)",
1127                 .drv_name       = "ecb-3des",
1128                 .block_size     = DES_BLOCK_SIZE,
1129                 .enc_type       = (ENC_TYPE_ALG_3DES |
1130                                    ENC_TYPE_CHAINING_ECB),
1131                 .skcipher       = {
1132                         .min_keysize    = 3 * DES_KEY_SIZE,
1133                         .max_keysize    = 3 * DES_KEY_SIZE,
1134                         .setkey         = n2_3des_setkey,
1135                         .encrypt        = n2_encrypt_ecb,
1136                         .decrypt        = n2_decrypt_ecb,
1137                 },
1138         },
1139         {       .name           = "cbc(des3_ede)",
1140                 .drv_name       = "cbc-3des",
1141                 .block_size     = DES_BLOCK_SIZE,
1142                 .enc_type       = (ENC_TYPE_ALG_3DES |
1143                                    ENC_TYPE_CHAINING_CBC),
1144                 .skcipher       = {
1145                         .ivsize         = DES_BLOCK_SIZE,
1146                         .min_keysize    = 3 * DES_KEY_SIZE,
1147                         .max_keysize    = 3 * DES_KEY_SIZE,
1148                         .setkey         = n2_3des_setkey,
1149                         .encrypt        = n2_encrypt_chaining,
1150                         .decrypt        = n2_decrypt_chaining,
1151                 },
1152         },
1153
1154         /* AES: ECB CBC and CTR are supported */
1155         {       .name           = "ecb(aes)",
1156                 .drv_name       = "ecb-aes",
1157                 .block_size     = AES_BLOCK_SIZE,
1158                 .enc_type       = (ENC_TYPE_ALG_AES128 |
1159                                    ENC_TYPE_CHAINING_ECB),
1160                 .skcipher       = {
1161                         .min_keysize    = AES_MIN_KEY_SIZE,
1162                         .max_keysize    = AES_MAX_KEY_SIZE,
1163                         .setkey         = n2_aes_setkey,
1164                         .encrypt        = n2_encrypt_ecb,
1165                         .decrypt        = n2_decrypt_ecb,
1166                 },
1167         },
1168         {       .name           = "cbc(aes)",
1169                 .drv_name       = "cbc-aes",
1170                 .block_size     = AES_BLOCK_SIZE,
1171                 .enc_type       = (ENC_TYPE_ALG_AES128 |
1172                                    ENC_TYPE_CHAINING_CBC),
1173                 .skcipher       = {
1174                         .ivsize         = AES_BLOCK_SIZE,
1175                         .min_keysize    = AES_MIN_KEY_SIZE,
1176                         .max_keysize    = AES_MAX_KEY_SIZE,
1177                         .setkey         = n2_aes_setkey,
1178                         .encrypt        = n2_encrypt_chaining,
1179                         .decrypt        = n2_decrypt_chaining,
1180                 },
1181         },
1182         {       .name           = "ctr(aes)",
1183                 .drv_name       = "ctr-aes",
1184                 .block_size     = AES_BLOCK_SIZE,
1185                 .enc_type       = (ENC_TYPE_ALG_AES128 |
1186                                    ENC_TYPE_CHAINING_COUNTER),
1187                 .skcipher       = {
1188                         .ivsize         = AES_BLOCK_SIZE,
1189                         .min_keysize    = AES_MIN_KEY_SIZE,
1190                         .max_keysize    = AES_MAX_KEY_SIZE,
1191                         .setkey         = n2_aes_setkey,
1192                         .encrypt        = n2_encrypt_chaining,
1193                         .decrypt        = n2_encrypt_chaining,
1194                 },
1195         },
1196
1197 };
1198 #define NUM_CIPHER_TMPLS ARRAY_SIZE(skcipher_tmpls)
1199
1200 static LIST_HEAD(skcipher_algs);
1201
1202 struct n2_hash_tmpl {
1203         const char      *name;
1204         const u8        *hash_zero;
1205         const u8        *hash_init;
1206         u8              hw_op_hashsz;
1207         u8              digest_size;
1208         u8              statesize;
1209         u8              block_size;
1210         u8              auth_type;
1211         u8              hmac_type;
1212 };
1213
1214 static const __le32 n2_md5_init[MD5_HASH_WORDS] = {
1215         cpu_to_le32(MD5_H0),
1216         cpu_to_le32(MD5_H1),
1217         cpu_to_le32(MD5_H2),
1218         cpu_to_le32(MD5_H3),
1219 };
1220 static const u32 n2_sha1_init[SHA1_DIGEST_SIZE / 4] = {
1221         SHA1_H0, SHA1_H1, SHA1_H2, SHA1_H3, SHA1_H4,
1222 };
1223 static const u32 n2_sha256_init[SHA256_DIGEST_SIZE / 4] = {
1224         SHA256_H0, SHA256_H1, SHA256_H2, SHA256_H3,
1225         SHA256_H4, SHA256_H5, SHA256_H6, SHA256_H7,
1226 };
1227 static const u32 n2_sha224_init[SHA256_DIGEST_SIZE / 4] = {
1228         SHA224_H0, SHA224_H1, SHA224_H2, SHA224_H3,
1229         SHA224_H4, SHA224_H5, SHA224_H6, SHA224_H7,
1230 };
1231
1232 static const struct n2_hash_tmpl hash_tmpls[] = {
1233         { .name         = "md5",
1234           .hash_zero    = md5_zero_message_hash,
1235           .hash_init    = (u8 *)n2_md5_init,
1236           .auth_type    = AUTH_TYPE_MD5,
1237           .hmac_type    = AUTH_TYPE_HMAC_MD5,
1238           .hw_op_hashsz = MD5_DIGEST_SIZE,
1239           .digest_size  = MD5_DIGEST_SIZE,
1240           .statesize    = sizeof(struct md5_state),
1241           .block_size   = MD5_HMAC_BLOCK_SIZE },
1242         { .name         = "sha1",
1243           .hash_zero    = sha1_zero_message_hash,
1244           .hash_init    = (u8 *)n2_sha1_init,
1245           .auth_type    = AUTH_TYPE_SHA1,
1246           .hmac_type    = AUTH_TYPE_HMAC_SHA1,
1247           .hw_op_hashsz = SHA1_DIGEST_SIZE,
1248           .digest_size  = SHA1_DIGEST_SIZE,
1249           .statesize    = sizeof(struct sha1_state),
1250           .block_size   = SHA1_BLOCK_SIZE },
1251         { .name         = "sha256",
1252           .hash_zero    = sha256_zero_message_hash,
1253           .hash_init    = (u8 *)n2_sha256_init,
1254           .auth_type    = AUTH_TYPE_SHA256,
1255           .hmac_type    = AUTH_TYPE_HMAC_SHA256,
1256           .hw_op_hashsz = SHA256_DIGEST_SIZE,
1257           .digest_size  = SHA256_DIGEST_SIZE,
1258           .statesize    = sizeof(struct sha256_state),
1259           .block_size   = SHA256_BLOCK_SIZE },
1260         { .name         = "sha224",
1261           .hash_zero    = sha224_zero_message_hash,
1262           .hash_init    = (u8 *)n2_sha224_init,
1263           .auth_type    = AUTH_TYPE_SHA256,
1264           .hmac_type    = AUTH_TYPE_RESERVED,
1265           .hw_op_hashsz = SHA256_DIGEST_SIZE,
1266           .digest_size  = SHA224_DIGEST_SIZE,
1267           .statesize    = sizeof(struct sha256_state),
1268           .block_size   = SHA224_BLOCK_SIZE },
1269 };
1270 #define NUM_HASH_TMPLS ARRAY_SIZE(hash_tmpls)
1271
1272 static LIST_HEAD(ahash_algs);
1273 static LIST_HEAD(hmac_algs);
1274
1275 static int algs_registered;
1276
1277 static void __n2_unregister_algs(void)
1278 {
1279         struct n2_skcipher_alg *skcipher, *skcipher_tmp;
1280         struct n2_ahash_alg *alg, *alg_tmp;
1281         struct n2_hmac_alg *hmac, *hmac_tmp;
1282
1283         list_for_each_entry_safe(skcipher, skcipher_tmp, &skcipher_algs, entry) {
1284                 crypto_unregister_skcipher(&skcipher->skcipher);
1285                 list_del(&skcipher->entry);
1286                 kfree(skcipher);
1287         }
1288         list_for_each_entry_safe(hmac, hmac_tmp, &hmac_algs, derived.entry) {
1289                 crypto_unregister_ahash(&hmac->derived.alg);
1290                 list_del(&hmac->derived.entry);
1291                 kfree(hmac);
1292         }
1293         list_for_each_entry_safe(alg, alg_tmp, &ahash_algs, entry) {
1294                 crypto_unregister_ahash(&alg->alg);
1295                 list_del(&alg->entry);
1296                 kfree(alg);
1297         }
1298 }
1299
1300 static int n2_skcipher_init_tfm(struct crypto_skcipher *tfm)
1301 {
1302         crypto_skcipher_set_reqsize(tfm, sizeof(struct n2_request_context));
1303         return 0;
1304 }
1305
1306 static int __n2_register_one_skcipher(const struct n2_skcipher_tmpl *tmpl)
1307 {
1308         struct n2_skcipher_alg *p = kzalloc(sizeof(*p), GFP_KERNEL);
1309         struct skcipher_alg *alg;
1310         int err;
1311
1312         if (!p)
1313                 return -ENOMEM;
1314
1315         alg = &p->skcipher;
1316         *alg = tmpl->skcipher;
1317
1318         snprintf(alg->base.cra_name, CRYPTO_MAX_ALG_NAME, "%s", tmpl->name);
1319         snprintf(alg->base.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s-n2", tmpl->drv_name);
1320         alg->base.cra_priority = N2_CRA_PRIORITY;
1321         alg->base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC |
1322                               CRYPTO_ALG_ALLOCATES_MEMORY;
1323         alg->base.cra_blocksize = tmpl->block_size;
1324         p->enc_type = tmpl->enc_type;
1325         alg->base.cra_ctxsize = sizeof(struct n2_skcipher_context);
1326         alg->base.cra_module = THIS_MODULE;
1327         alg->init = n2_skcipher_init_tfm;
1328
1329         list_add(&p->entry, &skcipher_algs);
1330         err = crypto_register_skcipher(alg);
1331         if (err) {
1332                 pr_err("%s alg registration failed\n", alg->base.cra_name);
1333                 list_del(&p->entry);
1334                 kfree(p);
1335         } else {
1336                 pr_info("%s alg registered\n", alg->base.cra_name);
1337         }
1338         return err;
1339 }
1340
1341 static int __n2_register_one_hmac(struct n2_ahash_alg *n2ahash)
1342 {
1343         struct n2_hmac_alg *p = kzalloc(sizeof(*p), GFP_KERNEL);
1344         struct ahash_alg *ahash;
1345         struct crypto_alg *base;
1346         int err;
1347
1348         if (!p)
1349                 return -ENOMEM;
1350
1351         p->child_alg = n2ahash->alg.halg.base.cra_name;
1352         memcpy(&p->derived, n2ahash, sizeof(struct n2_ahash_alg));
1353         INIT_LIST_HEAD(&p->derived.entry);
1354
1355         ahash = &p->derived.alg;
1356         ahash->digest = n2_hmac_async_digest;
1357         ahash->setkey = n2_hmac_async_setkey;
1358
1359         base = &ahash->halg.base;
1360         if (snprintf(base->cra_name, CRYPTO_MAX_ALG_NAME, "hmac(%s)",
1361                      p->child_alg) >= CRYPTO_MAX_ALG_NAME)
1362                 goto out_free_p;
1363         if (snprintf(base->cra_driver_name, CRYPTO_MAX_ALG_NAME, "hmac-%s-n2",
1364                      p->child_alg) >= CRYPTO_MAX_ALG_NAME)
1365                 goto out_free_p;
1366
1367         base->cra_ctxsize = sizeof(struct n2_hmac_ctx);
1368         base->cra_init = n2_hmac_cra_init;
1369         base->cra_exit = n2_hmac_cra_exit;
1370
1371         list_add(&p->derived.entry, &hmac_algs);
1372         err = crypto_register_ahash(ahash);
1373         if (err) {
1374                 pr_err("%s alg registration failed\n", base->cra_name);
1375                 list_del(&p->derived.entry);
1376 out_free_p:
1377                 kfree(p);
1378         } else {
1379                 pr_info("%s alg registered\n", base->cra_name);
1380         }
1381         return err;
1382 }
1383
1384 static int __n2_register_one_ahash(const struct n2_hash_tmpl *tmpl)
1385 {
1386         struct n2_ahash_alg *p = kzalloc(sizeof(*p), GFP_KERNEL);
1387         struct hash_alg_common *halg;
1388         struct crypto_alg *base;
1389         struct ahash_alg *ahash;
1390         int err;
1391
1392         if (!p)
1393                 return -ENOMEM;
1394
1395         p->hash_zero = tmpl->hash_zero;
1396         p->hash_init = tmpl->hash_init;
1397         p->auth_type = tmpl->auth_type;
1398         p->hmac_type = tmpl->hmac_type;
1399         p->hw_op_hashsz = tmpl->hw_op_hashsz;
1400         p->digest_size = tmpl->digest_size;
1401
1402         ahash = &p->alg;
1403         ahash->init = n2_hash_async_init;
1404         ahash->update = n2_hash_async_update;
1405         ahash->final = n2_hash_async_final;
1406         ahash->finup = n2_hash_async_finup;
1407         ahash->digest = n2_hash_async_digest;
1408         ahash->export = n2_hash_async_noexport;
1409         ahash->import = n2_hash_async_noimport;
1410
1411         halg = &ahash->halg;
1412         halg->digestsize = tmpl->digest_size;
1413         halg->statesize = tmpl->statesize;
1414
1415         base = &halg->base;
1416         snprintf(base->cra_name, CRYPTO_MAX_ALG_NAME, "%s", tmpl->name);
1417         snprintf(base->cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s-n2", tmpl->name);
1418         base->cra_priority = N2_CRA_PRIORITY;
1419         base->cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
1420                           CRYPTO_ALG_NEED_FALLBACK;
1421         base->cra_blocksize = tmpl->block_size;
1422         base->cra_ctxsize = sizeof(struct n2_hash_ctx);
1423         base->cra_module = THIS_MODULE;
1424         base->cra_init = n2_hash_cra_init;
1425         base->cra_exit = n2_hash_cra_exit;
1426
1427         list_add(&p->entry, &ahash_algs);
1428         err = crypto_register_ahash(ahash);
1429         if (err) {
1430                 pr_err("%s alg registration failed\n", base->cra_name);
1431                 list_del(&p->entry);
1432                 kfree(p);
1433         } else {
1434                 pr_info("%s alg registered\n", base->cra_name);
1435         }
1436         if (!err && p->hmac_type != AUTH_TYPE_RESERVED)
1437                 err = __n2_register_one_hmac(p);
1438         return err;
1439 }
1440
1441 static int n2_register_algs(void)
1442 {
1443         int i, err = 0;
1444
1445         mutex_lock(&spu_lock);
1446         if (algs_registered++)
1447                 goto out;
1448
1449         for (i = 0; i < NUM_HASH_TMPLS; i++) {
1450                 err = __n2_register_one_ahash(&hash_tmpls[i]);
1451                 if (err) {
1452                         __n2_unregister_algs();
1453                         goto out;
1454                 }
1455         }
1456         for (i = 0; i < NUM_CIPHER_TMPLS; i++) {
1457                 err = __n2_register_one_skcipher(&skcipher_tmpls[i]);
1458                 if (err) {
1459                         __n2_unregister_algs();
1460                         goto out;
1461                 }
1462         }
1463
1464 out:
1465         mutex_unlock(&spu_lock);
1466         return err;
1467 }
1468
1469 static void n2_unregister_algs(void)
1470 {
1471         mutex_lock(&spu_lock);
1472         if (!--algs_registered)
1473                 __n2_unregister_algs();
1474         mutex_unlock(&spu_lock);
1475 }
1476
1477 /* To map CWQ queues to interrupt sources, the hypervisor API provides
1478  * a devino.  This isn't very useful to us because all of the
1479  * interrupts listed in the device_node have been translated to
1480  * Linux virtual IRQ cookie numbers.
1481  *
1482  * So we have to back-translate, going through the 'intr' and 'ino'
1483  * property tables of the n2cp MDESC node, matching it with the OF
1484  * 'interrupts' property entries, in order to figure out which
1485  * devino goes to which already-translated IRQ.
1486  */
1487 static int find_devino_index(struct platform_device *dev, struct spu_mdesc_info *ip,
1488                              unsigned long dev_ino)
1489 {
1490         const unsigned int *dev_intrs;
1491         unsigned int intr;
1492         int i;
1493
1494         for (i = 0; i < ip->num_intrs; i++) {
1495                 if (ip->ino_table[i].ino == dev_ino)
1496                         break;
1497         }
1498         if (i == ip->num_intrs)
1499                 return -ENODEV;
1500
1501         intr = ip->ino_table[i].intr;
1502
1503         dev_intrs = of_get_property(dev->dev.of_node, "interrupts", NULL);
1504         if (!dev_intrs)
1505                 return -ENODEV;
1506
1507         for (i = 0; i < dev->archdata.num_irqs; i++) {
1508                 if (dev_intrs[i] == intr)
1509                         return i;
1510         }
1511
1512         return -ENODEV;
1513 }
1514
1515 static int spu_map_ino(struct platform_device *dev, struct spu_mdesc_info *ip,
1516                        const char *irq_name, struct spu_queue *p,
1517                        irq_handler_t handler)
1518 {
1519         unsigned long herr;
1520         int index;
1521
1522         herr = sun4v_ncs_qhandle_to_devino(p->qhandle, &p->devino);
1523         if (herr)
1524                 return -EINVAL;
1525
1526         index = find_devino_index(dev, ip, p->devino);
1527         if (index < 0)
1528                 return index;
1529
1530         p->irq = dev->archdata.irqs[index];
1531
1532         sprintf(p->irq_name, "%s-%d", irq_name, index);
1533
1534         return request_irq(p->irq, handler, 0, p->irq_name, p);
1535 }
1536
1537 static struct kmem_cache *queue_cache[2];
1538
1539 static void *new_queue(unsigned long q_type)
1540 {
1541         return kmem_cache_zalloc(queue_cache[q_type - 1], GFP_KERNEL);
1542 }
1543
1544 static void free_queue(void *p, unsigned long q_type)
1545 {
1546         kmem_cache_free(queue_cache[q_type - 1], p);
1547 }
1548
1549 static int queue_cache_init(void)
1550 {
1551         if (!queue_cache[HV_NCS_QTYPE_MAU - 1])
1552                 queue_cache[HV_NCS_QTYPE_MAU - 1] =
1553                         kmem_cache_create("mau_queue",
1554                                           (MAU_NUM_ENTRIES *
1555                                            MAU_ENTRY_SIZE),
1556                                           MAU_ENTRY_SIZE, 0, NULL);
1557         if (!queue_cache[HV_NCS_QTYPE_MAU - 1])
1558                 return -ENOMEM;
1559
1560         if (!queue_cache[HV_NCS_QTYPE_CWQ - 1])
1561                 queue_cache[HV_NCS_QTYPE_CWQ - 1] =
1562                         kmem_cache_create("cwq_queue",
1563                                           (CWQ_NUM_ENTRIES *
1564                                            CWQ_ENTRY_SIZE),
1565                                           CWQ_ENTRY_SIZE, 0, NULL);
1566         if (!queue_cache[HV_NCS_QTYPE_CWQ - 1]) {
1567                 kmem_cache_destroy(queue_cache[HV_NCS_QTYPE_MAU - 1]);
1568                 queue_cache[HV_NCS_QTYPE_MAU - 1] = NULL;
1569                 return -ENOMEM;
1570         }
1571         return 0;
1572 }
1573
1574 static void queue_cache_destroy(void)
1575 {
1576         kmem_cache_destroy(queue_cache[HV_NCS_QTYPE_MAU - 1]);
1577         kmem_cache_destroy(queue_cache[HV_NCS_QTYPE_CWQ - 1]);
1578         queue_cache[HV_NCS_QTYPE_MAU - 1] = NULL;
1579         queue_cache[HV_NCS_QTYPE_CWQ - 1] = NULL;
1580 }
1581
1582 static long spu_queue_register_workfn(void *arg)
1583 {
1584         struct spu_qreg *qr = arg;
1585         struct spu_queue *p = qr->queue;
1586         unsigned long q_type = qr->type;
1587         unsigned long hv_ret;
1588
1589         hv_ret = sun4v_ncs_qconf(q_type, __pa(p->q),
1590                                  CWQ_NUM_ENTRIES, &p->qhandle);
1591         if (!hv_ret)
1592                 sun4v_ncs_sethead_marker(p->qhandle, 0);
1593
1594         return hv_ret ? -EINVAL : 0;
1595 }
1596
1597 static int spu_queue_register(struct spu_queue *p, unsigned long q_type)
1598 {
1599         int cpu = cpumask_any_and(&p->sharing, cpu_online_mask);
1600         struct spu_qreg qr = { .queue = p, .type = q_type };
1601
1602         return work_on_cpu_safe(cpu, spu_queue_register_workfn, &qr);
1603 }
1604
1605 static int spu_queue_setup(struct spu_queue *p)
1606 {
1607         int err;
1608
1609         p->q = new_queue(p->q_type);
1610         if (!p->q)
1611                 return -ENOMEM;
1612
1613         err = spu_queue_register(p, p->q_type);
1614         if (err) {
1615                 free_queue(p->q, p->q_type);
1616                 p->q = NULL;
1617         }
1618
1619         return err;
1620 }
1621
1622 static void spu_queue_destroy(struct spu_queue *p)
1623 {
1624         unsigned long hv_ret;
1625
1626         if (!p->q)
1627                 return;
1628
1629         hv_ret = sun4v_ncs_qconf(p->q_type, p->qhandle, 0, &p->qhandle);
1630
1631         if (!hv_ret)
1632                 free_queue(p->q, p->q_type);
1633 }
1634
1635 static void spu_list_destroy(struct list_head *list)
1636 {
1637         struct spu_queue *p, *n;
1638
1639         list_for_each_entry_safe(p, n, list, list) {
1640                 int i;
1641
1642                 for (i = 0; i < NR_CPUS; i++) {
1643                         if (cpu_to_cwq[i] == p)
1644                                 cpu_to_cwq[i] = NULL;
1645                 }
1646
1647                 if (p->irq) {
1648                         free_irq(p->irq, p);
1649                         p->irq = 0;
1650                 }
1651                 spu_queue_destroy(p);
1652                 list_del(&p->list);
1653                 kfree(p);
1654         }
1655 }
1656
1657 /* Walk the backward arcs of a CWQ 'exec-unit' node,
1658  * gathering cpu membership information.
1659  */
1660 static int spu_mdesc_walk_arcs(struct mdesc_handle *mdesc,
1661                                struct platform_device *dev,
1662                                u64 node, struct spu_queue *p,
1663                                struct spu_queue **table)
1664 {
1665         u64 arc;
1666
1667         mdesc_for_each_arc(arc, mdesc, node, MDESC_ARC_TYPE_BACK) {
1668                 u64 tgt = mdesc_arc_target(mdesc, arc);
1669                 const char *name = mdesc_node_name(mdesc, tgt);
1670                 const u64 *id;
1671
1672                 if (strcmp(name, "cpu"))
1673                         continue;
1674                 id = mdesc_get_property(mdesc, tgt, "id", NULL);
1675                 if (table[*id] != NULL) {
1676                         dev_err(&dev->dev, "%pOF: SPU cpu slot already set.\n",
1677                                 dev->dev.of_node);
1678                         return -EINVAL;
1679                 }
1680                 cpumask_set_cpu(*id, &p->sharing);
1681                 table[*id] = p;
1682         }
1683         return 0;
1684 }
1685
1686 /* Process an 'exec-unit' MDESC node of type 'cwq'.  */
1687 static int handle_exec_unit(struct spu_mdesc_info *ip, struct list_head *list,
1688                             struct platform_device *dev, struct mdesc_handle *mdesc,
1689                             u64 node, const char *iname, unsigned long q_type,
1690                             irq_handler_t handler, struct spu_queue **table)
1691 {
1692         struct spu_queue *p;
1693         int err;
1694
1695         p = kzalloc(sizeof(struct spu_queue), GFP_KERNEL);
1696         if (!p) {
1697                 dev_err(&dev->dev, "%pOF: Could not allocate SPU queue.\n",
1698                         dev->dev.of_node);
1699                 return -ENOMEM;
1700         }
1701
1702         cpumask_clear(&p->sharing);
1703         spin_lock_init(&p->lock);
1704         p->q_type = q_type;
1705         INIT_LIST_HEAD(&p->jobs);
1706         list_add(&p->list, list);
1707
1708         err = spu_mdesc_walk_arcs(mdesc, dev, node, p, table);
1709         if (err)
1710                 return err;
1711
1712         err = spu_queue_setup(p);
1713         if (err)
1714                 return err;
1715
1716         return spu_map_ino(dev, ip, iname, p, handler);
1717 }
1718
1719 static int spu_mdesc_scan(struct mdesc_handle *mdesc, struct platform_device *dev,
1720                           struct spu_mdesc_info *ip, struct list_head *list,
1721                           const char *exec_name, unsigned long q_type,
1722                           irq_handler_t handler, struct spu_queue **table)
1723 {
1724         int err = 0;
1725         u64 node;
1726
1727         mdesc_for_each_node_by_name(mdesc, node, "exec-unit") {
1728                 const char *type;
1729
1730                 type = mdesc_get_property(mdesc, node, "type", NULL);
1731                 if (!type || strcmp(type, exec_name))
1732                         continue;
1733
1734                 err = handle_exec_unit(ip, list, dev, mdesc, node,
1735                                        exec_name, q_type, handler, table);
1736                 if (err) {
1737                         spu_list_destroy(list);
1738                         break;
1739                 }
1740         }
1741
1742         return err;
1743 }
1744
1745 static int get_irq_props(struct mdesc_handle *mdesc, u64 node,
1746                          struct spu_mdesc_info *ip)
1747 {
1748         const u64 *ino;
1749         int ino_len;
1750         int i;
1751
1752         ino = mdesc_get_property(mdesc, node, "ino", &ino_len);
1753         if (!ino) {
1754                 printk("NO 'ino'\n");
1755                 return -ENODEV;
1756         }
1757
1758         ip->num_intrs = ino_len / sizeof(u64);
1759         ip->ino_table = kzalloc((sizeof(struct ino_blob) *
1760                                  ip->num_intrs),
1761                                 GFP_KERNEL);
1762         if (!ip->ino_table)
1763                 return -ENOMEM;
1764
1765         for (i = 0; i < ip->num_intrs; i++) {
1766                 struct ino_blob *b = &ip->ino_table[i];
1767                 b->intr = i + 1;
1768                 b->ino = ino[i];
1769         }
1770
1771         return 0;
1772 }
1773
1774 static int grab_mdesc_irq_props(struct mdesc_handle *mdesc,
1775                                 struct platform_device *dev,
1776                                 struct spu_mdesc_info *ip,
1777                                 const char *node_name)
1778 {
1779         u64 node, reg;
1780
1781         if (of_property_read_reg(dev->dev.of_node, 0, &reg, NULL) < 0)
1782                 return -ENODEV;
1783
1784         mdesc_for_each_node_by_name(mdesc, node, "virtual-device") {
1785                 const char *name;
1786                 const u64 *chdl;
1787
1788                 name = mdesc_get_property(mdesc, node, "name", NULL);
1789                 if (!name || strcmp(name, node_name))
1790                         continue;
1791                 chdl = mdesc_get_property(mdesc, node, "cfg-handle", NULL);
1792                 if (!chdl || (*chdl != reg))
1793                         continue;
1794                 ip->cfg_handle = *chdl;
1795                 return get_irq_props(mdesc, node, ip);
1796         }
1797
1798         return -ENODEV;
1799 }
1800
1801 static unsigned long n2_spu_hvapi_major;
1802 static unsigned long n2_spu_hvapi_minor;
1803
1804 static int n2_spu_hvapi_register(void)
1805 {
1806         int err;
1807
1808         n2_spu_hvapi_major = 2;
1809         n2_spu_hvapi_minor = 0;
1810
1811         err = sun4v_hvapi_register(HV_GRP_NCS,
1812                                    n2_spu_hvapi_major,
1813                                    &n2_spu_hvapi_minor);
1814
1815         if (!err)
1816                 pr_info("Registered NCS HVAPI version %lu.%lu\n",
1817                         n2_spu_hvapi_major,
1818                         n2_spu_hvapi_minor);
1819
1820         return err;
1821 }
1822
1823 static void n2_spu_hvapi_unregister(void)
1824 {
1825         sun4v_hvapi_unregister(HV_GRP_NCS);
1826 }
1827
1828 static int global_ref;
1829
1830 static int grab_global_resources(void)
1831 {
1832         int err = 0;
1833
1834         mutex_lock(&spu_lock);
1835
1836         if (global_ref++)
1837                 goto out;
1838
1839         err = n2_spu_hvapi_register();
1840         if (err)
1841                 goto out;
1842
1843         err = queue_cache_init();
1844         if (err)
1845                 goto out_hvapi_release;
1846
1847         err = -ENOMEM;
1848         cpu_to_cwq = kcalloc(NR_CPUS, sizeof(struct spu_queue *),
1849                              GFP_KERNEL);
1850         if (!cpu_to_cwq)
1851                 goto out_queue_cache_destroy;
1852
1853         cpu_to_mau = kcalloc(NR_CPUS, sizeof(struct spu_queue *),
1854                              GFP_KERNEL);
1855         if (!cpu_to_mau)
1856                 goto out_free_cwq_table;
1857
1858         err = 0;
1859
1860 out:
1861         if (err)
1862                 global_ref--;
1863         mutex_unlock(&spu_lock);
1864         return err;
1865
1866 out_free_cwq_table:
1867         kfree(cpu_to_cwq);
1868         cpu_to_cwq = NULL;
1869
1870 out_queue_cache_destroy:
1871         queue_cache_destroy();
1872
1873 out_hvapi_release:
1874         n2_spu_hvapi_unregister();
1875         goto out;
1876 }
1877
1878 static void release_global_resources(void)
1879 {
1880         mutex_lock(&spu_lock);
1881         if (!--global_ref) {
1882                 kfree(cpu_to_cwq);
1883                 cpu_to_cwq = NULL;
1884
1885                 kfree(cpu_to_mau);
1886                 cpu_to_mau = NULL;
1887
1888                 queue_cache_destroy();
1889                 n2_spu_hvapi_unregister();
1890         }
1891         mutex_unlock(&spu_lock);
1892 }
1893
1894 static struct n2_crypto *alloc_n2cp(void)
1895 {
1896         struct n2_crypto *np = kzalloc(sizeof(struct n2_crypto), GFP_KERNEL);
1897
1898         if (np)
1899                 INIT_LIST_HEAD(&np->cwq_list);
1900
1901         return np;
1902 }
1903
1904 static void free_n2cp(struct n2_crypto *np)
1905 {
1906         kfree(np->cwq_info.ino_table);
1907         np->cwq_info.ino_table = NULL;
1908
1909         kfree(np);
1910 }
1911
1912 static void n2_spu_driver_version(void)
1913 {
1914         static int n2_spu_version_printed;
1915
1916         if (n2_spu_version_printed++ == 0)
1917                 pr_info("%s", version);
1918 }
1919
1920 static int n2_crypto_probe(struct platform_device *dev)
1921 {
1922         struct mdesc_handle *mdesc;
1923         struct n2_crypto *np;
1924         int err;
1925
1926         n2_spu_driver_version();
1927
1928         pr_info("Found N2CP at %pOF\n", dev->dev.of_node);
1929
1930         np = alloc_n2cp();
1931         if (!np) {
1932                 dev_err(&dev->dev, "%pOF: Unable to allocate n2cp.\n",
1933                         dev->dev.of_node);
1934                 return -ENOMEM;
1935         }
1936
1937         err = grab_global_resources();
1938         if (err) {
1939                 dev_err(&dev->dev, "%pOF: Unable to grab global resources.\n",
1940                         dev->dev.of_node);
1941                 goto out_free_n2cp;
1942         }
1943
1944         mdesc = mdesc_grab();
1945
1946         if (!mdesc) {
1947                 dev_err(&dev->dev, "%pOF: Unable to grab MDESC.\n",
1948                         dev->dev.of_node);
1949                 err = -ENODEV;
1950                 goto out_free_global;
1951         }
1952         err = grab_mdesc_irq_props(mdesc, dev, &np->cwq_info, "n2cp");
1953         if (err) {
1954                 dev_err(&dev->dev, "%pOF: Unable to grab IRQ props.\n",
1955                         dev->dev.of_node);
1956                 mdesc_release(mdesc);
1957                 goto out_free_global;
1958         }
1959
1960         err = spu_mdesc_scan(mdesc, dev, &np->cwq_info, &np->cwq_list,
1961                              "cwq", HV_NCS_QTYPE_CWQ, cwq_intr,
1962                              cpu_to_cwq);
1963         mdesc_release(mdesc);
1964
1965         if (err) {
1966                 dev_err(&dev->dev, "%pOF: CWQ MDESC scan failed.\n",
1967                         dev->dev.of_node);
1968                 goto out_free_global;
1969         }
1970
1971         err = n2_register_algs();
1972         if (err) {
1973                 dev_err(&dev->dev, "%pOF: Unable to register algorithms.\n",
1974                         dev->dev.of_node);
1975                 goto out_free_spu_list;
1976         }
1977
1978         dev_set_drvdata(&dev->dev, np);
1979
1980         return 0;
1981
1982 out_free_spu_list:
1983         spu_list_destroy(&np->cwq_list);
1984
1985 out_free_global:
1986         release_global_resources();
1987
1988 out_free_n2cp:
1989         free_n2cp(np);
1990
1991         return err;
1992 }
1993
1994 static void n2_crypto_remove(struct platform_device *dev)
1995 {
1996         struct n2_crypto *np = dev_get_drvdata(&dev->dev);
1997
1998         n2_unregister_algs();
1999
2000         spu_list_destroy(&np->cwq_list);
2001
2002         release_global_resources();
2003
2004         free_n2cp(np);
2005 }
2006
2007 static struct n2_mau *alloc_ncp(void)
2008 {
2009         struct n2_mau *mp = kzalloc(sizeof(struct n2_mau), GFP_KERNEL);
2010
2011         if (mp)
2012                 INIT_LIST_HEAD(&mp->mau_list);
2013
2014         return mp;
2015 }
2016
2017 static void free_ncp(struct n2_mau *mp)
2018 {
2019         kfree(mp->mau_info.ino_table);
2020         mp->mau_info.ino_table = NULL;
2021
2022         kfree(mp);
2023 }
2024
2025 static int n2_mau_probe(struct platform_device *dev)
2026 {
2027         struct mdesc_handle *mdesc;
2028         struct n2_mau *mp;
2029         int err;
2030
2031         n2_spu_driver_version();
2032
2033         pr_info("Found NCP at %pOF\n", dev->dev.of_node);
2034
2035         mp = alloc_ncp();
2036         if (!mp) {
2037                 dev_err(&dev->dev, "%pOF: Unable to allocate ncp.\n",
2038                         dev->dev.of_node);
2039                 return -ENOMEM;
2040         }
2041
2042         err = grab_global_resources();
2043         if (err) {
2044                 dev_err(&dev->dev, "%pOF: Unable to grab global resources.\n",
2045                         dev->dev.of_node);
2046                 goto out_free_ncp;
2047         }
2048
2049         mdesc = mdesc_grab();
2050
2051         if (!mdesc) {
2052                 dev_err(&dev->dev, "%pOF: Unable to grab MDESC.\n",
2053                         dev->dev.of_node);
2054                 err = -ENODEV;
2055                 goto out_free_global;
2056         }
2057
2058         err = grab_mdesc_irq_props(mdesc, dev, &mp->mau_info, "ncp");
2059         if (err) {
2060                 dev_err(&dev->dev, "%pOF: Unable to grab IRQ props.\n",
2061                         dev->dev.of_node);
2062                 mdesc_release(mdesc);
2063                 goto out_free_global;
2064         }
2065
2066         err = spu_mdesc_scan(mdesc, dev, &mp->mau_info, &mp->mau_list,
2067                              "mau", HV_NCS_QTYPE_MAU, mau_intr,
2068                              cpu_to_mau);
2069         mdesc_release(mdesc);
2070
2071         if (err) {
2072                 dev_err(&dev->dev, "%pOF: MAU MDESC scan failed.\n",
2073                         dev->dev.of_node);
2074                 goto out_free_global;
2075         }
2076
2077         dev_set_drvdata(&dev->dev, mp);
2078
2079         return 0;
2080
2081 out_free_global:
2082         release_global_resources();
2083
2084 out_free_ncp:
2085         free_ncp(mp);
2086
2087         return err;
2088 }
2089
2090 static void n2_mau_remove(struct platform_device *dev)
2091 {
2092         struct n2_mau *mp = dev_get_drvdata(&dev->dev);
2093
2094         spu_list_destroy(&mp->mau_list);
2095
2096         release_global_resources();
2097
2098         free_ncp(mp);
2099 }
2100
2101 static const struct of_device_id n2_crypto_match[] = {
2102         {
2103                 .name = "n2cp",
2104                 .compatible = "SUNW,n2-cwq",
2105         },
2106         {
2107                 .name = "n2cp",
2108                 .compatible = "SUNW,vf-cwq",
2109         },
2110         {
2111                 .name = "n2cp",
2112                 .compatible = "SUNW,kt-cwq",
2113         },
2114         {},
2115 };
2116
2117 MODULE_DEVICE_TABLE(of, n2_crypto_match);
2118
2119 static struct platform_driver n2_crypto_driver = {
2120         .driver = {
2121                 .name           =       "n2cp",
2122                 .of_match_table =       n2_crypto_match,
2123         },
2124         .probe          =       n2_crypto_probe,
2125         .remove_new     =       n2_crypto_remove,
2126 };
2127
2128 static const struct of_device_id n2_mau_match[] = {
2129         {
2130                 .name = "ncp",
2131                 .compatible = "SUNW,n2-mau",
2132         },
2133         {
2134                 .name = "ncp",
2135                 .compatible = "SUNW,vf-mau",
2136         },
2137         {
2138                 .name = "ncp",
2139                 .compatible = "SUNW,kt-mau",
2140         },
2141         {},
2142 };
2143
2144 MODULE_DEVICE_TABLE(of, n2_mau_match);
2145
2146 static struct platform_driver n2_mau_driver = {
2147         .driver = {
2148                 .name           =       "ncp",
2149                 .of_match_table =       n2_mau_match,
2150         },
2151         .probe          =       n2_mau_probe,
2152         .remove_new     =       n2_mau_remove,
2153 };
2154
2155 static struct platform_driver * const drivers[] = {
2156         &n2_crypto_driver,
2157         &n2_mau_driver,
2158 };
2159
2160 static int __init n2_init(void)
2161 {
2162         return platform_register_drivers(drivers, ARRAY_SIZE(drivers));
2163 }
2164
2165 static void __exit n2_exit(void)
2166 {
2167         platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
2168 }
2169
2170 module_init(n2_init);
2171 module_exit(n2_exit);