]> Git Repo - linux.git/blob - arch/riscv/include/asm/semihost.h
Merge patch series "riscv: Extension parsing fixes"
[linux.git] / arch / riscv / include / asm / semihost.h
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (C) 2022 tinylab.org
4  * Author: Bin Meng <[email protected]>
5  */
6
7 #ifndef _RISCV_SEMIHOST_H_
8 #define _RISCV_SEMIHOST_H_
9
10 struct uart_port;
11
12 static inline void smh_putc(struct uart_port *port, unsigned char c)
13 {
14         asm volatile("addi    a1, %0, 0\n"
15                      "addi    a0, zero, 3\n"
16                      ".balign 16\n"
17                      ".option push\n"
18                      ".option norvc\n"
19                      "slli    zero, zero, 0x1f\n"
20                      "ebreak\n"
21                      "srai    zero, zero, 0x7\n"
22                      ".option pop\n"
23                      : : "r" (&c) : "a0", "a1", "memory");
24 }
25
26 #endif /* _RISCV_SEMIHOST_H_ */
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