drivers/gpu/drm/i915/intel_runtime_pm.c

   1 /*
   2  * Copyright © 2012-2014 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eugeni Dodonov <[email protected]>
  25  *    Daniel Vetter <[email protected]>
  26  *
  27  */
  28
  29 #include <linux/pm_runtime.h>
  30 #include <linux/vgaarb.h>
  31
  32 #include "i915_drv.h"
  33 #include "intel_drv.h"
  34
  35 /**
  36  * DOC: runtime pm
  37  *
  38  * The i915 driver supports dynamic enabling and disabling of entire hardware
  39  * blocks at runtime. This is especially important on the display side where
  40  * software is supposed to control many power gates manually on recent hardware,
  41  * since on the GT side a lot of the power management is done by the hardware.
  42  * But even there some manual control at the device level is required.
  43  *
  44  * Since i915 supports a diverse set of platforms with a unified codebase and
  45  * hardware engineers just love to shuffle functionality around between power
  46  * domains there's a sizeable amount of indirection required. This file provides
  47  * generic functions to the driver for grabbing and releasing references for
  48  * abstract power domains. It then maps those to the actual power wells
  49  * present for a given platform.
  50  */
  51
  52 #define for_each_power_well(i, power_well, domain_mask, power_domains)  \
  53         for (i = 0;                                                     \
  54              i < (power_domains)->power_well_count &&                   \
  55                  ((power_well) = &(power_domains)->power_wells[i]);     \
  56              i++)                                                       \
  57                 for_each_if ((power_well)->domains & (domain_mask))
  58
  59 #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \
  60         for (i = (power_domains)->power_well_count - 1;                  \
  61              i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\
  62              i--)                                                        \
  63                 for_each_if ((power_well)->domains & (domain_mask))
  64
  65 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
  66                                     int power_well_id);
  67
  68 const char *
  69 intel_display_power_domain_str(enum intel_display_power_domain domain)
  70 {
  71         switch (domain) {
  72         case POWER_DOMAIN_PIPE_A:
  73                 return "PIPE_A";
  74         case POWER_DOMAIN_PIPE_B:
  75                 return "PIPE_B";
  76         case POWER_DOMAIN_PIPE_C:
  77                 return "PIPE_C";
  78         case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
  79                 return "PIPE_A_PANEL_FITTER";
  80         case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
  81                 return "PIPE_B_PANEL_FITTER";
  82         case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
  83                 return "PIPE_C_PANEL_FITTER";
  84         case POWER_DOMAIN_TRANSCODER_A:
  85                 return "TRANSCODER_A";
  86         case POWER_DOMAIN_TRANSCODER_B:
  87                 return "TRANSCODER_B";
  88         case POWER_DOMAIN_TRANSCODER_C:
  89                 return "TRANSCODER_C";
  90         case POWER_DOMAIN_TRANSCODER_EDP:
  91                 return "TRANSCODER_EDP";
  92         case POWER_DOMAIN_TRANSCODER_DSI_A:
  93                 return "TRANSCODER_DSI_A";
  94         case POWER_DOMAIN_TRANSCODER_DSI_C:
  95                 return "TRANSCODER_DSI_C";
  96         case POWER_DOMAIN_PORT_DDI_A_LANES:
  97                 return "PORT_DDI_A_LANES";
  98         case POWER_DOMAIN_PORT_DDI_B_LANES:
  99                 return "PORT_DDI_B_LANES";
 100         case POWER_DOMAIN_PORT_DDI_C_LANES:
 101                 return "PORT_DDI_C_LANES";
 102         case POWER_DOMAIN_PORT_DDI_D_LANES:
 103                 return "PORT_DDI_D_LANES";
 104         case POWER_DOMAIN_PORT_DDI_E_LANES:
 105                 return "PORT_DDI_E_LANES";
 106         case POWER_DOMAIN_PORT_DSI:
 107                 return "PORT_DSI";
 108         case POWER_DOMAIN_PORT_CRT:
 109                 return "PORT_CRT";
 110         case POWER_DOMAIN_PORT_OTHER:
 111                 return "PORT_OTHER";
 112         case POWER_DOMAIN_VGA:
 113                 return "VGA";
 114         case POWER_DOMAIN_AUDIO:
 115                 return "AUDIO";
 116         case POWER_DOMAIN_PLLS:
 117                 return "PLLS";
 118         case POWER_DOMAIN_AUX_A:
 119                 return "AUX_A";
 120         case POWER_DOMAIN_AUX_B:
 121                 return "AUX_B";
 122         case POWER_DOMAIN_AUX_C:
 123                 return "AUX_C";
 124         case POWER_DOMAIN_AUX_D:
 125                 return "AUX_D";
 126         case POWER_DOMAIN_GMBUS:
 127                 return "GMBUS";
 128         case POWER_DOMAIN_INIT:
 129                 return "INIT";
 130         case POWER_DOMAIN_MODESET:
 131                 return "MODESET";
 132         default:
 133                 MISSING_CASE(domain);
 134                 return "?";
 135         }
 136 }
 137
 138 static void intel_power_well_enable(struct drm_i915_private *dev_priv,
 139                                     struct i915_power_well *power_well)
 140 {
 141         DRM_DEBUG_KMS("enabling %s\n", power_well->name);
 142         power_well->ops->enable(dev_priv, power_well);
 143         power_well->hw_enabled = true;
 144 }
 145
 146 static void intel_power_well_disable(struct drm_i915_private *dev_priv,
 147                                      struct i915_power_well *power_well)
 148 {
 149         DRM_DEBUG_KMS("disabling %s\n", power_well->name);
 150         power_well->hw_enabled = false;
 151         power_well->ops->disable(dev_priv, power_well);
 152 }
 153
 154 /*
 155  * We should only use the power well if we explicitly asked the hardware to
 156  * enable it, so check if it's enabled and also check if we've requested it to
 157  * be enabled.
 158  */
 159 static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
 160                                    struct i915_power_well *power_well)
 161 {
 162         return I915_READ(HSW_PWR_WELL_DRIVER) ==
 163                      (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
 164 }
 165
 166 /**
 167  * __intel_display_power_is_enabled - unlocked check for a power domain
 168  * @dev_priv: i915 device instance
 169  * @domain: power domain to check
 170  *
 171  * This is the unlocked version of intel_display_power_is_enabled() and should
 172  * only be used from error capture and recovery code where deadlocks are
 173  * possible.
 174  *
 175  * Returns:
 176  * True when the power domain is enabled, false otherwise.
 177  */
 178 bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 179                                       enum intel_display_power_domain domain)
 180 {
 181         struct i915_power_domains *power_domains;
 182         struct i915_power_well *power_well;
 183         bool is_enabled;
 184         int i;
 185
 186         if (dev_priv->pm.suspended)
 187                 return false;
 188
 189         power_domains = &dev_priv->power_domains;
 190
 191         is_enabled = true;
 192
 193         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
 194                 if (power_well->always_on)
 195                         continue;
 196
 197                 if (!power_well->hw_enabled) {
 198                         is_enabled = false;
 199                         break;
 200                 }
 201         }
 202
 203         return is_enabled;
 204 }
 205
 206 /**
 207  * intel_display_power_is_enabled - check for a power domain
 208  * @dev_priv: i915 device instance
 209  * @domain: power domain to check
 210  *
 211  * This function can be used to check the hw power domain state. It is mostly
 212  * used in hardware state readout functions. Everywhere else code should rely
 213  * upon explicit power domain reference counting to ensure that the hardware
 214  * block is powered up before accessing it.
 215  *
 216  * Callers must hold the relevant modesetting locks to ensure that concurrent
 217  * threads can't disable the power well while the caller tries to read a few
 218  * registers.
 219  *
 220  * Returns:
 221  * True when the power domain is enabled, false otherwise.
 222  */
 223 bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
 224                                     enum intel_display_power_domain domain)
 225 {
 226         struct i915_power_domains *power_domains;
 227         bool ret;
 228
 229         power_domains = &dev_priv->power_domains;
 230
 231         mutex_lock(&power_domains->lock);
 232         ret = __intel_display_power_is_enabled(dev_priv, domain);
 233         mutex_unlock(&power_domains->lock);
 234
 235         return ret;
 236 }
 237
 238 /**
 239  * intel_display_set_init_power - set the initial power domain state
 240  * @dev_priv: i915 device instance
 241  * @enable: whether to enable or disable the initial power domain state
 242  *
 243  * For simplicity our driver load/unload and system suspend/resume code assumes
 244  * that all power domains are always enabled. This functions controls the state
 245  * of this little hack. While the initial power domain state is enabled runtime
 246  * pm is effectively disabled.
 247  */
 248 void intel_display_set_init_power(struct drm_i915_private *dev_priv,
 249                                   bool enable)
 250 {
 251         if (dev_priv->power_domains.init_power_on == enable)
 252                 return;
 253
 254         if (enable)
 255                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
 256         else
 257                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
 258
 259         dev_priv->power_domains.init_power_on = enable;
 260 }
 261
 262 /*
 263  * Starting with Haswell, we have a "Power Down Well" that can be turned off
 264  * when not needed anymore. We have 4 registers that can request the power well
 265  * to be enabled, and it will only be disabled if none of the registers is
 266  * requesting it to be enabled.
 267  */
 268 static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv)
 269 {
 270         struct drm_device *dev = dev_priv->dev;
 271
 272         /*
 273          * After we re-enable the power well, if we touch VGA register 0x3d5
 274          * we'll get unclaimed register interrupts. This stops after we write
 275          * anything to the VGA MSR register. The vgacon module uses this
 276          * register all the time, so if we unbind our driver and, as a
 277          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 278          * console_unlock(). So make here we touch the VGA MSR register, making
 279          * sure vgacon can keep working normally without triggering interrupts
 280          * and error messages.
 281          */
 282         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 283         outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 284         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 285
 286         if (IS_BROADWELL(dev))
 287                 gen8_irq_power_well_post_enable(dev_priv,
 288                                                 1 << PIPE_C | 1 << PIPE_B);
 289 }
 290
 291 static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv)
 292 {
 293         if (IS_BROADWELL(dev_priv))
 294                 gen8_irq_power_well_pre_disable(dev_priv,
 295                                                 1 << PIPE_C | 1 << PIPE_B);
 296 }
 297
 298 static void skl_power_well_post_enable(struct drm_i915_private *dev_priv,
 299                                        struct i915_power_well *power_well)
 300 {
 301         struct drm_device *dev = dev_priv->dev;
 302
 303         /*
 304          * After we re-enable the power well, if we touch VGA register 0x3d5
 305          * we'll get unclaimed register interrupts. This stops after we write
 306          * anything to the VGA MSR register. The vgacon module uses this
 307          * register all the time, so if we unbind our driver and, as a
 308          * consequence, bind vgacon, we'll get stuck in an infinite loop at
 309          * console_unlock(). So make here we touch the VGA MSR register, making
 310          * sure vgacon can keep working normally without triggering interrupts
 311          * and error messages.
 312          */
 313         if (power_well->data == SKL_DISP_PW_2) {
 314                 vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
 315                 outb(inb(VGA_MSR_READ), VGA_MSR_WRITE);
 316                 vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
 317
 318                 gen8_irq_power_well_post_enable(dev_priv,
 319                                                 1 << PIPE_C | 1 << PIPE_B);
 320         }
 321 }
 322
 323 static void skl_power_well_pre_disable(struct drm_i915_private *dev_priv,
 324                                        struct i915_power_well *power_well)
 325 {
 326         if (power_well->data == SKL_DISP_PW_2)
 327                 gen8_irq_power_well_pre_disable(dev_priv,
 328                                                 1 << PIPE_C | 1 << PIPE_B);
 329 }
 330
 331 static void hsw_set_power_well(struct drm_i915_private *dev_priv,
 332                                struct i915_power_well *power_well, bool enable)
 333 {
 334         bool is_enabled, enable_requested;
 335         uint32_t tmp;
 336
 337         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 338         is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
 339         enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
 340
 341         if (enable) {
 342                 if (!enable_requested)
 343                         I915_WRITE(HSW_PWR_WELL_DRIVER,
 344                                    HSW_PWR_WELL_ENABLE_REQUEST);
 345
 346                 if (!is_enabled) {
 347                         DRM_DEBUG_KMS("Enabling power well\n");
 348                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
 349                                       HSW_PWR_WELL_STATE_ENABLED), 20))
 350                                 DRM_ERROR("Timeout enabling power well\n");
 351                         hsw_power_well_post_enable(dev_priv);
 352                 }
 353
 354         } else {
 355                 if (enable_requested) {
 356                         hsw_power_well_pre_disable(dev_priv);
 357                         I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
 358                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 359                         DRM_DEBUG_KMS("Requesting to disable the power well\n");
 360                 }
 361         }
 362 }
 363
 364 #define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 365         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 366         BIT(POWER_DOMAIN_PIPE_B) |                      \
 367         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 368         BIT(POWER_DOMAIN_PIPE_C) |                      \
 369         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 370         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 371         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 372         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 373         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 374         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
 375         BIT(POWER_DOMAIN_PORT_DDI_E_LANES) |            \
 376         BIT(POWER_DOMAIN_AUX_B) |                       \
 377         BIT(POWER_DOMAIN_AUX_C) |                       \
 378         BIT(POWER_DOMAIN_AUX_D) |                       \
 379         BIT(POWER_DOMAIN_AUDIO) |                       \
 380         BIT(POWER_DOMAIN_VGA) |                         \
 381         BIT(POWER_DOMAIN_INIT))
 382 #define SKL_DISPLAY_DDI_A_E_POWER_DOMAINS (             \
 383         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
 384         BIT(POWER_DOMAIN_PORT_DDI_E_LANES) |            \
 385         BIT(POWER_DOMAIN_INIT))
 386 #define SKL_DISPLAY_DDI_B_POWER_DOMAINS (               \
 387         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 388         BIT(POWER_DOMAIN_INIT))
 389 #define SKL_DISPLAY_DDI_C_POWER_DOMAINS (               \
 390         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 391         BIT(POWER_DOMAIN_INIT))
 392 #define SKL_DISPLAY_DDI_D_POWER_DOMAINS (               \
 393         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
 394         BIT(POWER_DOMAIN_INIT))
 395 #define SKL_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 396         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 397         BIT(POWER_DOMAIN_MODESET) |                     \
 398         BIT(POWER_DOMAIN_AUX_A) |                       \
 399         BIT(POWER_DOMAIN_INIT))
 400 #define SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS (           \
 401         (POWER_DOMAIN_MASK & ~(                         \
 402         SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 403         SKL_DISPLAY_DC_OFF_POWER_DOMAINS)) |            \
 404         BIT(POWER_DOMAIN_INIT))
 405
 406 #define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS (         \
 407         BIT(POWER_DOMAIN_TRANSCODER_A) |                \
 408         BIT(POWER_DOMAIN_PIPE_B) |                      \
 409         BIT(POWER_DOMAIN_TRANSCODER_B) |                \
 410         BIT(POWER_DOMAIN_PIPE_C) |                      \
 411         BIT(POWER_DOMAIN_TRANSCODER_C) |                \
 412         BIT(POWER_DOMAIN_PIPE_B_PANEL_FITTER) |         \
 413         BIT(POWER_DOMAIN_PIPE_C_PANEL_FITTER) |         \
 414         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
 415         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
 416         BIT(POWER_DOMAIN_AUX_B) |                       \
 417         BIT(POWER_DOMAIN_AUX_C) |                       \
 418         BIT(POWER_DOMAIN_AUDIO) |                       \
 419         BIT(POWER_DOMAIN_VGA) |                         \
 420         BIT(POWER_DOMAIN_GMBUS) |                       \
 421         BIT(POWER_DOMAIN_INIT))
 422 #define BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS (         \
 423         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 424         BIT(POWER_DOMAIN_PIPE_A) |                      \
 425         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
 426         BIT(POWER_DOMAIN_TRANSCODER_DSI_A) |            \
 427         BIT(POWER_DOMAIN_TRANSCODER_DSI_C) |            \
 428         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER) |         \
 429         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
 430         BIT(POWER_DOMAIN_PORT_DSI) |                    \
 431         BIT(POWER_DOMAIN_AUX_A) |                       \
 432         BIT(POWER_DOMAIN_PLLS) |                        \
 433         BIT(POWER_DOMAIN_INIT))
 434 #define BXT_DISPLAY_DC_OFF_POWER_DOMAINS (              \
 435         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS |         \
 436         BIT(POWER_DOMAIN_MODESET) |                     \
 437         BIT(POWER_DOMAIN_AUX_A) |                       \
 438         BIT(POWER_DOMAIN_INIT))
 439 #define BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS (           \
 440         (POWER_DOMAIN_MASK & ~(BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS |  \
 441         BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS)) |       \
 442         BIT(POWER_DOMAIN_INIT))
 443
 444 static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
 445 {
 446         struct drm_device *dev = dev_priv->dev;
 447
 448         WARN(!IS_BROXTON(dev), "Platform doesn't support DC9.\n");
 449         WARN((I915_READ(DC_STATE_EN) & DC_STATE_EN_DC9),
 450                 "DC9 already programmed to be enabled.\n");
 451         WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 452                 "DC5 still not disabled to enable DC9.\n");
 453         WARN(I915_READ(HSW_PWR_WELL_DRIVER), "Power well on.\n");
 454         WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
 455
 456          /*
 457           * TODO: check for the following to verify the conditions to enter DC9
 458           * state are satisfied:
 459           * 1] Check relevant display engine registers to verify if mode set
 460           * disable sequence was followed.
 461           * 2] Check if display uninitialize sequence is initialized.
 462           */
 463 }
 464
 465 static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
 466 {
 467         WARN(intel_irqs_enabled(dev_priv), "Interrupts not disabled yet.\n");
 468         WARN(I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5,
 469                 "DC5 still not disabled.\n");
 470
 471          /*
 472           * TODO: check for the following to verify DC9 state was indeed
 473           * entered before programming to disable it:
 474           * 1] Check relevant display engine registers to verify if mode
 475           *  set disable sequence was followed.
 476           * 2] Check if display uninitialize sequence is initialized.
 477           */
 478 }
 479
 480 static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
 481                                 u32 state)
 482 {
 483         int rewrites = 0;
 484         int rereads = 0;
 485         u32 v;
 486
 487         I915_WRITE(DC_STATE_EN, state);
 488
 489         /* It has been observed that disabling the dc6 state sometimes
 490          * doesn't stick and dmc keeps returning old value. Make sure
 491          * the write really sticks enough times and also force rewrite until
 492          * we are confident that state is exactly what we want.
 493          */
 494         do  {
 495                 v = I915_READ(DC_STATE_EN);
 496
 497                 if (v != state) {
 498                         I915_WRITE(DC_STATE_EN, state);
 499                         rewrites++;
 500                         rereads = 0;
 501                 } else if (rereads++ > 5) {
 502                         break;
 503                 }
 504
 505         } while (rewrites < 100);
 506
 507         if (v != state)
 508                 DRM_ERROR("Writing dc state to 0x%x failed, now 0x%x\n",
 509                           state, v);
 510
 511         /* Most of the times we need one retry, avoid spam */
 512         if (rewrites > 1)
 513                 DRM_DEBUG_KMS("Rewrote dc state to 0x%x %d times\n",
 514                               state, rewrites);
 515 }
 516
 517 static void gen9_set_dc_state(struct drm_i915_private *dev_priv, uint32_t state)
 518 {
 519         uint32_t val;
 520         uint32_t mask;
 521
 522         mask = DC_STATE_EN_UPTO_DC5;
 523         if (IS_BROXTON(dev_priv))
 524                 mask |= DC_STATE_EN_DC9;
 525         else
 526                 mask |= DC_STATE_EN_UPTO_DC6;
 527
 528         if (WARN_ON_ONCE(state & ~dev_priv->csr.allowed_dc_mask))
 529                 state &= dev_priv->csr.allowed_dc_mask;
 530
 531         val = I915_READ(DC_STATE_EN);
 532         DRM_DEBUG_KMS("Setting DC state from %02x to %02x\n",
 533                       val & mask, state);
 534
 535         /* Check if DMC is ignoring our DC state requests */
 536         if ((val & mask) != dev_priv->csr.dc_state)
 537                 DRM_ERROR("DC state mismatch (0x%x -> 0x%x)\n",
 538                           dev_priv->csr.dc_state, val & mask);
 539
 540         val &= ~mask;
 541         val |= state;
 542
 543         gen9_write_dc_state(dev_priv, val);
 544
 545         dev_priv->csr.dc_state = val & mask;
 546 }
 547
 548 void bxt_enable_dc9(struct drm_i915_private *dev_priv)
 549 {
 550         assert_can_enable_dc9(dev_priv);
 551
 552         DRM_DEBUG_KMS("Enabling DC9\n");
 553
 554         gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
 555 }
 556
 557 void bxt_disable_dc9(struct drm_i915_private *dev_priv)
 558 {
 559         assert_can_disable_dc9(dev_priv);
 560
 561         DRM_DEBUG_KMS("Disabling DC9\n");
 562
 563         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 564 }
 565
 566 static void assert_csr_loaded(struct drm_i915_private *dev_priv)
 567 {
 568         WARN_ONCE(!I915_READ(CSR_PROGRAM(0)),
 569                   "CSR program storage start is NULL\n");
 570         WARN_ONCE(!I915_READ(CSR_SSP_BASE), "CSR SSP Base Not fine\n");
 571         WARN_ONCE(!I915_READ(CSR_HTP_SKL), "CSR HTP Not fine\n");
 572 }
 573
 574 static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
 575 {
 576         struct drm_device *dev = dev_priv->dev;
 577         bool pg2_enabled = intel_display_power_well_is_enabled(dev_priv,
 578                                         SKL_DISP_PW_2);
 579
 580         WARN_ONCE(!IS_SKYLAKE(dev) && !IS_KABYLAKE(dev),
 581                   "Platform doesn't support DC5.\n");
 582         WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
 583         WARN_ONCE(pg2_enabled, "PG2 not disabled to enable DC5.\n");
 584
 585         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5),
 586                   "DC5 already programmed to be enabled.\n");
 587         assert_rpm_wakelock_held(dev_priv);
 588
 589         assert_csr_loaded(dev_priv);
 590 }
 591
 592 static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
 593 {
 594         assert_can_enable_dc5(dev_priv);
 595
 596         DRM_DEBUG_KMS("Enabling DC5\n");
 597
 598         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
 599 }
 600
 601 static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
 602 {
 603         struct drm_device *dev = dev_priv->dev;
 604
 605         WARN_ONCE(!IS_SKYLAKE(dev) && !IS_KABYLAKE(dev),
 606                   "Platform doesn't support DC6.\n");
 607         WARN_ONCE(!HAS_RUNTIME_PM(dev), "Runtime PM not enabled.\n");
 608         WARN_ONCE(I915_READ(UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
 609                   "Backlight is not disabled.\n");
 610         WARN_ONCE((I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC6),
 611                   "DC6 already programmed to be enabled.\n");
 612
 613         assert_csr_loaded(dev_priv);
 614 }
 615
 616 void skl_enable_dc6(struct drm_i915_private *dev_priv)
 617 {
 618         assert_can_enable_dc6(dev_priv);
 619
 620         DRM_DEBUG_KMS("Enabling DC6\n");
 621
 622         gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
 623
 624 }
 625
 626 void skl_disable_dc6(struct drm_i915_private *dev_priv)
 627 {
 628         DRM_DEBUG_KMS("Disabling DC6\n");
 629
 630         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 631 }
 632
 633 static void
 634 gen9_sanitize_power_well_requests(struct drm_i915_private *dev_priv,
 635                                   struct i915_power_well *power_well)
 636 {
 637         enum skl_disp_power_wells power_well_id = power_well->data;
 638         u32 val;
 639         u32 mask;
 640
 641         mask = SKL_POWER_WELL_REQ(power_well_id);
 642
 643         val = I915_READ(HSW_PWR_WELL_KVMR);
 644         if (WARN_ONCE(val & mask, "Clearing unexpected KVMR request for %s\n",
 645                       power_well->name))
 646                 I915_WRITE(HSW_PWR_WELL_KVMR, val & ~mask);
 647
 648         val = I915_READ(HSW_PWR_WELL_BIOS);
 649         val |= I915_READ(HSW_PWR_WELL_DEBUG);
 650
 651         if (!(val & mask))
 652                 return;
 653
 654         /*
 655          * DMC is known to force on the request bits for power well 1 on SKL
 656          * and BXT and the misc IO power well on SKL but we don't expect any
 657          * other request bits to be set, so WARN for those.
 658          */
 659         if (power_well_id == SKL_DISP_PW_1 ||
 660             (IS_SKYLAKE(dev_priv) && power_well_id == SKL_DISP_PW_MISC_IO))
 661                 DRM_DEBUG_DRIVER("Clearing auxiliary requests for %s forced on "
 662                                  "by DMC\n", power_well->name);
 663         else
 664                 WARN_ONCE(1, "Clearing unexpected auxiliary requests for %s\n",
 665                           power_well->name);
 666
 667         I915_WRITE(HSW_PWR_WELL_BIOS, val & ~mask);
 668         I915_WRITE(HSW_PWR_WELL_DEBUG, val & ~mask);
 669 }
 670
 671 static void skl_set_power_well(struct drm_i915_private *dev_priv,
 672                         struct i915_power_well *power_well, bool enable)
 673 {
 674         uint32_t tmp, fuse_status;
 675         uint32_t req_mask, state_mask;
 676         bool is_enabled, enable_requested, check_fuse_status = false;
 677
 678         tmp = I915_READ(HSW_PWR_WELL_DRIVER);
 679         fuse_status = I915_READ(SKL_FUSE_STATUS);
 680
 681         switch (power_well->data) {
 682         case SKL_DISP_PW_1:
 683                 if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 684                         SKL_FUSE_PG0_DIST_STATUS), 1)) {
 685                         DRM_ERROR("PG0 not enabled\n");
 686                         return;
 687                 }
 688                 break;
 689         case SKL_DISP_PW_2:
 690                 if (!(fuse_status & SKL_FUSE_PG1_DIST_STATUS)) {
 691                         DRM_ERROR("PG1 in disabled state\n");
 692                         return;
 693                 }
 694                 break;
 695         case SKL_DISP_PW_DDI_A_E:
 696         case SKL_DISP_PW_DDI_B:
 697         case SKL_DISP_PW_DDI_C:
 698         case SKL_DISP_PW_DDI_D:
 699         case SKL_DISP_PW_MISC_IO:
 700                 break;
 701         default:
 702                 WARN(1, "Unknown power well %lu\n", power_well->data);
 703                 return;
 704         }
 705
 706         req_mask = SKL_POWER_WELL_REQ(power_well->data);
 707         enable_requested = tmp & req_mask;
 708         state_mask = SKL_POWER_WELL_STATE(power_well->data);
 709         is_enabled = tmp & state_mask;
 710
 711         if (!enable && enable_requested)
 712                 skl_power_well_pre_disable(dev_priv, power_well);
 713
 714         if (enable) {
 715                 if (!enable_requested) {
 716                         WARN((tmp & state_mask) &&
 717                                 !I915_READ(HSW_PWR_WELL_BIOS),
 718                                 "Invalid for power well status to be enabled, unless done by the BIOS, \
 719                                 when request is to disable!\n");
 720                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp | req_mask);
 721                 }
 722
 723                 if (!is_enabled) {
 724                         DRM_DEBUG_KMS("Enabling %s\n", power_well->name);
 725                         if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
 726                                 state_mask), 1))
 727                                 DRM_ERROR("%s enable timeout\n",
 728                                         power_well->name);
 729                         check_fuse_status = true;
 730                 }
 731         } else {
 732                 if (enable_requested) {
 733                         I915_WRITE(HSW_PWR_WELL_DRIVER, tmp & ~req_mask);
 734                         POSTING_READ(HSW_PWR_WELL_DRIVER);
 735                         DRM_DEBUG_KMS("Disabling %s\n", power_well->name);
 736                 }
 737
 738                 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv))
 739                         gen9_sanitize_power_well_requests(dev_priv, power_well);
 740         }
 741
 742         if (check_fuse_status) {
 743                 if (power_well->data == SKL_DISP_PW_1) {
 744                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 745                                 SKL_FUSE_PG1_DIST_STATUS), 1))
 746                                 DRM_ERROR("PG1 distributing status timeout\n");
 747                 } else if (power_well->data == SKL_DISP_PW_2) {
 748                         if (wait_for((I915_READ(SKL_FUSE_STATUS) &
 749                                 SKL_FUSE_PG2_DIST_STATUS), 1))
 750                                 DRM_ERROR("PG2 distributing status timeout\n");
 751                 }
 752         }
 753
 754         if (enable && !is_enabled)
 755                 skl_power_well_post_enable(dev_priv, power_well);
 756 }
 757
 758 static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
 759                                    struct i915_power_well *power_well)
 760 {
 761         hsw_set_power_well(dev_priv, power_well, power_well->count > 0);
 762
 763         /*
 764          * We're taking over the BIOS, so clear any requests made by it since
 765          * the driver is in charge now.
 766          */
 767         if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
 768                 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 769 }
 770
 771 static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
 772                                   struct i915_power_well *power_well)
 773 {
 774         hsw_set_power_well(dev_priv, power_well, true);
 775 }
 776
 777 static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
 778                                    struct i915_power_well *power_well)
 779 {
 780         hsw_set_power_well(dev_priv, power_well, false);
 781 }
 782
 783 static bool skl_power_well_enabled(struct drm_i915_private *dev_priv,
 784                                         struct i915_power_well *power_well)
 785 {
 786         uint32_t mask = SKL_POWER_WELL_REQ(power_well->data) |
 787                 SKL_POWER_WELL_STATE(power_well->data);
 788
 789         return (I915_READ(HSW_PWR_WELL_DRIVER) & mask) == mask;
 790 }
 791
 792 static void skl_power_well_sync_hw(struct drm_i915_private *dev_priv,
 793                                 struct i915_power_well *power_well)
 794 {
 795         skl_set_power_well(dev_priv, power_well, power_well->count > 0);
 796
 797         /* Clear any request made by BIOS as driver is taking over */
 798         I915_WRITE(HSW_PWR_WELL_BIOS, 0);
 799 }
 800
 801 static void skl_power_well_enable(struct drm_i915_private *dev_priv,
 802                                 struct i915_power_well *power_well)
 803 {
 804         skl_set_power_well(dev_priv, power_well, true);
 805 }
 806
 807 static void skl_power_well_disable(struct drm_i915_private *dev_priv,
 808                                 struct i915_power_well *power_well)
 809 {
 810         skl_set_power_well(dev_priv, power_well, false);
 811 }
 812
 813 static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
 814                                            struct i915_power_well *power_well)
 815 {
 816         return (I915_READ(DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0;
 817 }
 818
 819 static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
 820                                           struct i915_power_well *power_well)
 821 {
 822         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
 823 }
 824
 825 static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
 826                                            struct i915_power_well *power_well)
 827 {
 828         if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC6)
 829                 skl_enable_dc6(dev_priv);
 830         else if (dev_priv->csr.allowed_dc_mask & DC_STATE_EN_UPTO_DC5)
 831                 gen9_enable_dc5(dev_priv);
 832 }
 833
 834 static void gen9_dc_off_power_well_sync_hw(struct drm_i915_private *dev_priv,
 835                                            struct i915_power_well *power_well)
 836 {
 837         if (power_well->count > 0)
 838                 gen9_dc_off_power_well_enable(dev_priv, power_well);
 839         else
 840                 gen9_dc_off_power_well_disable(dev_priv, power_well);
 841 }
 842
 843 static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
 844                                            struct i915_power_well *power_well)
 845 {
 846 }
 847
 848 static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
 849                                              struct i915_power_well *power_well)
 850 {
 851         return true;
 852 }
 853
 854 static void vlv_set_power_well(struct drm_i915_private *dev_priv,
 855                                struct i915_power_well *power_well, bool enable)
 856 {
 857         enum punit_power_well power_well_id = power_well->data;
 858         u32 mask;
 859         u32 state;
 860         u32 ctrl;
 861
 862         mask = PUNIT_PWRGT_MASK(power_well_id);
 863         state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) :
 864                          PUNIT_PWRGT_PWR_GATE(power_well_id);
 865
 866         mutex_lock(&dev_priv->rps.hw_lock);
 867
 868 #define COND \
 869         ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
 870
 871         if (COND)
 872                 goto out;
 873
 874         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
 875         ctrl &= ~mask;
 876         ctrl |= state;
 877         vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
 878
 879         if (wait_for(COND, 100))
 880                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
 881                           state,
 882                           vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
 883
 884 #undef COND
 885
 886 out:
 887         mutex_unlock(&dev_priv->rps.hw_lock);
 888 }
 889
 890 static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv,
 891                                    struct i915_power_well *power_well)
 892 {
 893         vlv_set_power_well(dev_priv, power_well, power_well->count > 0);
 894 }
 895
 896 static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
 897                                   struct i915_power_well *power_well)
 898 {
 899         vlv_set_power_well(dev_priv, power_well, true);
 900 }
 901
 902 static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
 903                                    struct i915_power_well *power_well)
 904 {
 905         vlv_set_power_well(dev_priv, power_well, false);
 906 }
 907
 908 static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
 909                                    struct i915_power_well *power_well)
 910 {
 911         int power_well_id = power_well->data;
 912         bool enabled = false;
 913         u32 mask;
 914         u32 state;
 915         u32 ctrl;
 916
 917         mask = PUNIT_PWRGT_MASK(power_well_id);
 918         ctrl = PUNIT_PWRGT_PWR_ON(power_well_id);
 919
 920         mutex_lock(&dev_priv->rps.hw_lock);
 921
 922         state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
 923         /*
 924          * We only ever set the power-on and power-gate states, anything
 925          * else is unexpected.
 926          */
 927         WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) &&
 928                 state != PUNIT_PWRGT_PWR_GATE(power_well_id));
 929         if (state == ctrl)
 930                 enabled = true;
 931
 932         /*
 933          * A transient state at this point would mean some unexpected party
 934          * is poking at the power controls too.
 935          */
 936         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
 937         WARN_ON(ctrl != state);
 938
 939         mutex_unlock(&dev_priv->rps.hw_lock);
 940
 941         return enabled;
 942 }
 943
 944 static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
 945 {
 946         I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
 947
 948         /*
 949          * Disable trickle feed and enable pnd deadline calculation
 950          */
 951         I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
 952         I915_WRITE(CBR1_VLV, 0);
 953 }
 954
 955 static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
 956 {
 957         enum pipe pipe;
 958
 959         /*
 960          * Enable the CRI clock source so we can get at the
 961          * display and the reference clock for VGA
 962          * hotplug / manual detection. Supposedly DSI also
 963          * needs the ref clock up and running.
 964          *
 965          * CHV DPLL B/C have some issues if VGA mode is enabled.
 966          */
 967         for_each_pipe(dev_priv->dev, pipe) {
 968                 u32 val = I915_READ(DPLL(pipe));
 969
 970                 val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
 971                 if (pipe != PIPE_A)
 972                         val |= DPLL_INTEGRATED_CRI_CLK_VLV;
 973
 974                 I915_WRITE(DPLL(pipe), val);
 975         }
 976
 977         vlv_init_display_clock_gating(dev_priv);
 978
 979         spin_lock_irq(&dev_priv->irq_lock);
 980         valleyview_enable_display_irqs(dev_priv);
 981         spin_unlock_irq(&dev_priv->irq_lock);
 982
 983         /*
 984          * During driver initialization/resume we can avoid restoring the
 985          * part of the HW/SW state that will be inited anyway explicitly.
 986          */
 987         if (dev_priv->power_domains.initializing)
 988                 return;
 989
 990         intel_hpd_init(dev_priv);
 991
 992         i915_redisable_vga_power_on(dev_priv->dev);
 993 }
 994
 995 static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
 996 {
 997         spin_lock_irq(&dev_priv->irq_lock);
 998         valleyview_disable_display_irqs(dev_priv);
 999         spin_unlock_irq(&dev_priv->irq_lock);
1000
1001         /* make sure we're done processing display irqs */
1002         synchronize_irq(dev_priv->dev->irq);
1003
1004         vlv_power_sequencer_reset(dev_priv);
1005 }
1006
1007 static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
1008                                           struct i915_power_well *power_well)
1009 {
1010         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
1011
1012         vlv_set_power_well(dev_priv, power_well, true);
1013
1014         vlv_display_power_well_init(dev_priv);
1015 }
1016
1017 static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
1018                                            struct i915_power_well *power_well)
1019 {
1020         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D);
1021
1022         vlv_display_power_well_deinit(dev_priv);
1023
1024         vlv_set_power_well(dev_priv, power_well, false);
1025 }
1026
1027 static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1028                                            struct i915_power_well *power_well)
1029 {
1030         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1031
1032         /* since ref/cri clock was enabled */
1033         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1034
1035         vlv_set_power_well(dev_priv, power_well, true);
1036
1037         /*
1038          * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
1039          *  6.  De-assert cmn_reset/side_reset. Same as VLV X0.
1040          *   a. GUnit 0x2110 bit[0] set to 1 (def 0)
1041          *   b. The other bits such as sfr settings / modesel may all
1042          *      be set to 0.
1043          *
1044          * This should only be done on init and resume from S3 with
1045          * both PLLs disabled, or we risk losing DPIO and PLL
1046          * synchronization.
1047          */
1048         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST);
1049 }
1050
1051 static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1052                                             struct i915_power_well *power_well)
1053 {
1054         enum pipe pipe;
1055
1056         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC);
1057
1058         for_each_pipe(dev_priv, pipe)
1059                 assert_pll_disabled(dev_priv, pipe);
1060
1061         /* Assert common reset */
1062         I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST);
1063
1064         vlv_set_power_well(dev_priv, power_well, false);
1065 }
1066
1067 #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1)
1068
1069 static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv,
1070                                                  int power_well_id)
1071 {
1072         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1073         int i;
1074
1075         for (i = 0; i < power_domains->power_well_count; i++) {
1076                 struct i915_power_well *power_well;
1077
1078                 power_well = &power_domains->power_wells[i];
1079                 if (power_well->data == power_well_id)
1080                         return power_well;
1081         }
1082
1083         return NULL;
1084 }
1085
1086 #define BITS_SET(val, bits) (((val) & (bits)) == (bits))
1087
1088 static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
1089 {
1090         struct i915_power_well *cmn_bc =
1091                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
1092         struct i915_power_well *cmn_d =
1093                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
1094         u32 phy_control = dev_priv->chv_phy_control;
1095         u32 phy_status = 0;
1096         u32 phy_status_mask = 0xffffffff;
1097         u32 tmp;
1098
1099         /*
1100          * The BIOS can leave the PHY is some weird state
1101          * where it doesn't fully power down some parts.
1102          * Disable the asserts until the PHY has been fully
1103          * reset (ie. the power well has been disabled at
1104          * least once).
1105          */
1106         if (!dev_priv->chv_phy_assert[DPIO_PHY0])
1107                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
1108                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
1109                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
1110                                      PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
1111                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
1112                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
1113
1114         if (!dev_priv->chv_phy_assert[DPIO_PHY1])
1115                 phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
1116                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
1117                                      PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
1118
1119         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
1120                 phy_status |= PHY_POWERGOOD(DPIO_PHY0);
1121
1122                 /* this assumes override is only used to enable lanes */
1123                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
1124                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
1125
1126                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
1127                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
1128
1129                 /* CL1 is on whenever anything is on in either channel */
1130                 if (BITS_SET(phy_control,
1131                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
1132                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
1133                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
1134
1135                 /*
1136                  * The DPLLB check accounts for the pipe B + port A usage
1137                  * with CL2 powered up but all the lanes in the second channel
1138                  * powered down.
1139                  */
1140                 if (BITS_SET(phy_control,
1141                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
1142                     (I915_READ(DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
1143                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
1144
1145                 if (BITS_SET(phy_control,
1146                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
1147                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
1148                 if (BITS_SET(phy_control,
1149                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
1150                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
1151
1152                 if (BITS_SET(phy_control,
1153                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
1154                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
1155                 if (BITS_SET(phy_control,
1156                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
1157                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
1158         }
1159
1160         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
1161                 phy_status |= PHY_POWERGOOD(DPIO_PHY1);
1162
1163                 /* this assumes override is only used to enable lanes */
1164                 if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
1165                         phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
1166
1167                 if (BITS_SET(phy_control,
1168                              PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
1169                         phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
1170
1171                 if (BITS_SET(phy_control,
1172                              PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
1173                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
1174                 if (BITS_SET(phy_control,
1175                              PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
1176                         phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
1177         }
1178
1179         phy_status &= phy_status_mask;
1180
1181         /*
1182          * The PHY may be busy with some initial calibration and whatnot,
1183          * so the power state can take a while to actually change.
1184          */
1185         if (wait_for((tmp = I915_READ(DISPLAY_PHY_STATUS) & phy_status_mask) == phy_status, 10))
1186                 WARN(phy_status != tmp,
1187                      "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
1188                      tmp, phy_status, dev_priv->chv_phy_control);
1189 }
1190
1191 #undef BITS_SET
1192
1193 static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1194                                            struct i915_power_well *power_well)
1195 {
1196         enum dpio_phy phy;
1197         enum pipe pipe;
1198         uint32_t tmp;
1199
1200         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1201                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1202
1203         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1204                 pipe = PIPE_A;
1205                 phy = DPIO_PHY0;
1206         } else {
1207                 pipe = PIPE_C;
1208                 phy = DPIO_PHY1;
1209         }
1210
1211         /* since ref/cri clock was enabled */
1212         udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
1213         vlv_set_power_well(dev_priv, power_well, true);
1214
1215         /* Poll for phypwrgood signal */
1216         if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1))
1217                 DRM_ERROR("Display PHY %d is not power up\n", phy);
1218
1219         mutex_lock(&dev_priv->sb_lock);
1220
1221         /* Enable dynamic power down */
1222         tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
1223         tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
1224                 DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
1225         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
1226
1227         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1228                 tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
1229                 tmp |= DPIO_DYNPWRDOWNEN_CH1;
1230                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
1231         } else {
1232                 /*
1233                  * Force the non-existing CL2 off. BXT does this
1234                  * too, so maybe it saves some power even though
1235                  * CL2 doesn't exist?
1236                  */
1237                 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
1238                 tmp |= DPIO_CL2_LDOFUSE_PWRENB;
1239                 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
1240         }
1241
1242         mutex_unlock(&dev_priv->sb_lock);
1243
1244         dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
1245         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1246
1247         DRM_DEBUG_KMS("Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1248                       phy, dev_priv->chv_phy_control);
1249
1250         assert_chv_phy_status(dev_priv);
1251 }
1252
1253 static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
1254                                             struct i915_power_well *power_well)
1255 {
1256         enum dpio_phy phy;
1257
1258         WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC &&
1259                      power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D);
1260
1261         if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) {
1262                 phy = DPIO_PHY0;
1263                 assert_pll_disabled(dev_priv, PIPE_A);
1264                 assert_pll_disabled(dev_priv, PIPE_B);
1265         } else {
1266                 phy = DPIO_PHY1;
1267                 assert_pll_disabled(dev_priv, PIPE_C);
1268         }
1269
1270         dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
1271         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1272
1273         vlv_set_power_well(dev_priv, power_well, false);
1274
1275         DRM_DEBUG_KMS("Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
1276                       phy, dev_priv->chv_phy_control);
1277
1278         /* PHY is fully reset now, so we can enable the PHY state asserts */
1279         dev_priv->chv_phy_assert[phy] = true;
1280
1281         assert_chv_phy_status(dev_priv);
1282 }
1283
1284 static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1285                                      enum dpio_channel ch, bool override, unsigned int mask)
1286 {
1287         enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
1288         u32 reg, val, expected, actual;
1289
1290         /*
1291          * The BIOS can leave the PHY is some weird state
1292          * where it doesn't fully power down some parts.
1293          * Disable the asserts until the PHY has been fully
1294          * reset (ie. the power well has been disabled at
1295          * least once).
1296          */
1297         if (!dev_priv->chv_phy_assert[phy])
1298                 return;
1299
1300         if (ch == DPIO_CH0)
1301                 reg = _CHV_CMN_DW0_CH0;
1302         else
1303                 reg = _CHV_CMN_DW6_CH1;
1304
1305         mutex_lock(&dev_priv->sb_lock);
1306         val = vlv_dpio_read(dev_priv, pipe, reg);
1307         mutex_unlock(&dev_priv->sb_lock);
1308
1309         /*
1310          * This assumes !override is only used when the port is disabled.
1311          * All lanes should power down even without the override when
1312          * the port is disabled.
1313          */
1314         if (!override || mask == 0xf) {
1315                 expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1316                 /*
1317                  * If CH1 common lane is not active anymore
1318                  * (eg. for pipe B DPLL) the entire channel will
1319                  * shut down, which causes the common lane registers
1320                  * to read as 0. That means we can't actually check
1321                  * the lane power down status bits, but as the entire
1322                  * register reads as 0 it's a good indication that the
1323                  * channel is indeed entirely powered down.
1324                  */
1325                 if (ch == DPIO_CH1 && val == 0)
1326                         expected = 0;
1327         } else if (mask != 0x0) {
1328                 expected = DPIO_ANYDL_POWERDOWN;
1329         } else {
1330                 expected = 0;
1331         }
1332
1333         if (ch == DPIO_CH0)
1334                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
1335         else
1336                 actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
1337         actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
1338
1339         WARN(actual != expected,
1340              "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
1341              !!(actual & DPIO_ALLDL_POWERDOWN), !!(actual & DPIO_ANYDL_POWERDOWN),
1342              !!(expected & DPIO_ALLDL_POWERDOWN), !!(expected & DPIO_ANYDL_POWERDOWN),
1343              reg, val);
1344 }
1345
1346 bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
1347                           enum dpio_channel ch, bool override)
1348 {
1349         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1350         bool was_override;
1351
1352         mutex_lock(&power_domains->lock);
1353
1354         was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1355
1356         if (override == was_override)
1357                 goto out;
1358
1359         if (override)
1360                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1361         else
1362                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1363
1364         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1365
1366         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
1367                       phy, ch, dev_priv->chv_phy_control);
1368
1369         assert_chv_phy_status(dev_priv);
1370
1371 out:
1372         mutex_unlock(&power_domains->lock);
1373
1374         return was_override;
1375 }
1376
1377 void chv_phy_powergate_lanes(struct intel_encoder *encoder,
1378                              bool override, unsigned int mask)
1379 {
1380         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1381         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1382         enum dpio_phy phy = vlv_dport_to_phy(enc_to_dig_port(&encoder->base));
1383         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
1384
1385         mutex_lock(&power_domains->lock);
1386
1387         dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
1388         dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
1389
1390         if (override)
1391                 dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1392         else
1393                 dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
1394
1395         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
1396
1397         DRM_DEBUG_KMS("Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
1398                       phy, ch, mask, dev_priv->chv_phy_control);
1399
1400         assert_chv_phy_status(dev_priv);
1401
1402         assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
1403
1404         mutex_unlock(&power_domains->lock);
1405 }
1406
1407 static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
1408                                         struct i915_power_well *power_well)
1409 {
1410         enum pipe pipe = power_well->data;
1411         bool enabled;
1412         u32 state, ctrl;
1413
1414         mutex_lock(&dev_priv->rps.hw_lock);
1415
1416         state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe);
1417         /*
1418          * We only ever set the power-on and power-gate states, anything
1419          * else is unexpected.
1420          */
1421         WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe));
1422         enabled = state == DP_SSS_PWR_ON(pipe);
1423
1424         /*
1425          * A transient state at this point would mean some unexpected party
1426          * is poking at the power controls too.
1427          */
1428         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe);
1429         WARN_ON(ctrl << 16 != state);
1430
1431         mutex_unlock(&dev_priv->rps.hw_lock);
1432
1433         return enabled;
1434 }
1435
1436 static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
1437                                     struct i915_power_well *power_well,
1438                                     bool enable)
1439 {
1440         enum pipe pipe = power_well->data;
1441         u32 state;
1442         u32 ctrl;
1443
1444         state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
1445
1446         mutex_lock(&dev_priv->rps.hw_lock);
1447
1448 #define COND \
1449         ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state)
1450
1451         if (COND)
1452                 goto out;
1453
1454         ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
1455         ctrl &= ~DP_SSC_MASK(pipe);
1456         ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
1457         vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl);
1458
1459         if (wait_for(COND, 100))
1460                 DRM_ERROR("timeout setting power well state %08x (%08x)\n",
1461                           state,
1462                           vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ));
1463
1464 #undef COND
1465
1466 out:
1467         mutex_unlock(&dev_priv->rps.hw_lock);
1468 }
1469
1470 static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
1471                                         struct i915_power_well *power_well)
1472 {
1473         WARN_ON_ONCE(power_well->data != PIPE_A);
1474
1475         chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0);
1476 }
1477
1478 static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
1479                                        struct i915_power_well *power_well)
1480 {
1481         WARN_ON_ONCE(power_well->data != PIPE_A);
1482
1483         chv_set_pipe_power_well(dev_priv, power_well, true);
1484
1485         vlv_display_power_well_init(dev_priv);
1486 }
1487
1488 static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
1489                                         struct i915_power_well *power_well)
1490 {
1491         WARN_ON_ONCE(power_well->data != PIPE_A);
1492
1493         vlv_display_power_well_deinit(dev_priv);
1494
1495         chv_set_pipe_power_well(dev_priv, power_well, false);
1496 }
1497
1498 static void
1499 __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
1500                                  enum intel_display_power_domain domain)
1501 {
1502         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1503         struct i915_power_well *power_well;
1504         int i;
1505
1506         for_each_power_well(i, power_well, BIT(domain), power_domains) {
1507                 if (!power_well->count++)
1508                         intel_power_well_enable(dev_priv, power_well);
1509         }
1510
1511         power_domains->domain_use_count[domain]++;
1512 }
1513
1514 /**
1515  * intel_display_power_get - grab a power domain reference
1516  * @dev_priv: i915 device instance
1517  * @domain: power domain to reference
1518  *
1519  * This function grabs a power domain reference for @domain and ensures that the
1520  * power domain and all its parents are powered up. Therefore users should only
1521  * grab a reference to the innermost power domain they need.
1522  *
1523  * Any power domain reference obtained by this function must have a symmetric
1524  * call to intel_display_power_put() to release the reference again.
1525  */
1526 void intel_display_power_get(struct drm_i915_private *dev_priv,
1527                              enum intel_display_power_domain domain)
1528 {
1529         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1530
1531         intel_runtime_pm_get(dev_priv);
1532
1533         mutex_lock(&power_domains->lock);
1534
1535         __intel_display_power_get_domain(dev_priv, domain);
1536
1537         mutex_unlock(&power_domains->lock);
1538 }
1539
1540 /**
1541  * intel_display_power_get_if_enabled - grab a reference for an enabled display power domain
1542  * @dev_priv: i915 device instance
1543  * @domain: power domain to reference
1544  *
1545  * This function grabs a power domain reference for @domain and ensures that the
1546  * power domain and all its parents are powered up. Therefore users should only
1547  * grab a reference to the innermost power domain they need.
1548  *
1549  * Any power domain reference obtained by this function must have a symmetric
1550  * call to intel_display_power_put() to release the reference again.
1551  */
1552 bool intel_display_power_get_if_enabled(struct drm_i915_private *dev_priv,
1553                                         enum intel_display_power_domain domain)
1554 {
1555         struct i915_power_domains *power_domains = &dev_priv->power_domains;
1556         bool is_enabled;
1557
1558         if (!intel_runtime_pm_get_if_in_use(dev_priv))
1559                 return false;
1560
1561         mutex_lock(&power_domains->lock);
1562
1563         if (__intel_display_power_is_enabled(dev_priv, domain)) {
1564                 __intel_display_power_get_domain(dev_priv, domain);
1565                 is_enabled = true;
1566         } else {
1567                 is_enabled = false;
1568         }
1569
1570         mutex_unlock(&power_domains->lock);
1571
1572         if (!is_enabled)
1573                 intel_runtime_pm_put(dev_priv);
1574
1575         return is_enabled;
1576 }
1577
1578 /**
1579  * intel_display_power_put - release a power domain reference
1580  * @dev_priv: i915 device instance
1581  * @domain: power domain to reference
1582  *
1583  * This function drops the power domain reference obtained by
1584  * intel_display_power_get() and might power down the corresponding hardware
1585  * block right away if this is the last reference.
1586  */
1587 void intel_display_power_put(struct drm_i915_private *dev_priv,
1588                              enum intel_display_power_domain domain)
1589 {
1590         struct i915_power_domains *power_domains;
1591         struct i915_power_well *power_well;
1592         int i;
1593
1594         power_domains = &dev_priv->power_domains;
1595
1596         mutex_lock(&power_domains->lock);
1597
1598         WARN(!power_domains->domain_use_count[domain],
1599              "Use count on domain %s is already zero\n",
1600              intel_display_power_domain_str(domain));
1601         power_domains->domain_use_count[domain]--;
1602
1603         for_each_power_well_rev(i, power_well, BIT(domain), power_domains) {
1604                 WARN(!power_well->count,
1605                      "Use count on power well %s is already zero",
1606                      power_well->name);
1607
1608                 if (!--power_well->count)
1609                         intel_power_well_disable(dev_priv, power_well);
1610         }
1611
1612         mutex_unlock(&power_domains->lock);
1613
1614         intel_runtime_pm_put(dev_priv);
1615 }
1616
1617 #define HSW_ALWAYS_ON_POWER_DOMAINS (                   \
1618         BIT(POWER_DOMAIN_PIPE_A) |                      \
1619         BIT(POWER_DOMAIN_TRANSCODER_EDP) |              \
1620         BIT(POWER_DOMAIN_PORT_DDI_A_LANES) |            \
1621         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |            \
1622         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |            \
1623         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |            \
1624         BIT(POWER_DOMAIN_PORT_CRT) |                    \
1625         BIT(POWER_DOMAIN_PLLS) |                        \
1626         BIT(POWER_DOMAIN_AUX_A) |                       \
1627         BIT(POWER_DOMAIN_AUX_B) |                       \
1628         BIT(POWER_DOMAIN_AUX_C) |                       \
1629         BIT(POWER_DOMAIN_AUX_D) |                       \
1630         BIT(POWER_DOMAIN_GMBUS) |                       \
1631         BIT(POWER_DOMAIN_INIT))
1632 #define HSW_DISPLAY_POWER_DOMAINS (                             \
1633         (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) |    \
1634         BIT(POWER_DOMAIN_INIT))
1635
1636 #define BDW_ALWAYS_ON_POWER_DOMAINS (                   \
1637         HSW_ALWAYS_ON_POWER_DOMAINS |                   \
1638         BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER))
1639 #define BDW_DISPLAY_POWER_DOMAINS (                             \
1640         (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) |    \
1641         BIT(POWER_DOMAIN_INIT))
1642
1643 #define VLV_ALWAYS_ON_POWER_DOMAINS     BIT(POWER_DOMAIN_INIT)
1644 #define VLV_DISPLAY_POWER_DOMAINS       POWER_DOMAIN_MASK
1645
1646 #define VLV_DPIO_CMN_BC_POWER_DOMAINS (         \
1647         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1648         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1649         BIT(POWER_DOMAIN_PORT_CRT) |            \
1650         BIT(POWER_DOMAIN_AUX_B) |               \
1651         BIT(POWER_DOMAIN_AUX_C) |               \
1652         BIT(POWER_DOMAIN_INIT))
1653
1654 #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS (  \
1655         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1656         BIT(POWER_DOMAIN_AUX_B) |               \
1657         BIT(POWER_DOMAIN_INIT))
1658
1659 #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS (  \
1660         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1661         BIT(POWER_DOMAIN_AUX_B) |               \
1662         BIT(POWER_DOMAIN_INIT))
1663
1664 #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS (  \
1665         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1666         BIT(POWER_DOMAIN_AUX_C) |               \
1667         BIT(POWER_DOMAIN_INIT))
1668
1669 #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS (  \
1670         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1671         BIT(POWER_DOMAIN_AUX_C) |               \
1672         BIT(POWER_DOMAIN_INIT))
1673
1674 #define CHV_DPIO_CMN_BC_POWER_DOMAINS (         \
1675         BIT(POWER_DOMAIN_PORT_DDI_B_LANES) |    \
1676         BIT(POWER_DOMAIN_PORT_DDI_C_LANES) |    \
1677         BIT(POWER_DOMAIN_AUX_B) |               \
1678         BIT(POWER_DOMAIN_AUX_C) |               \
1679         BIT(POWER_DOMAIN_INIT))
1680
1681 #define CHV_DPIO_CMN_D_POWER_DOMAINS (          \
1682         BIT(POWER_DOMAIN_PORT_DDI_D_LANES) |    \
1683         BIT(POWER_DOMAIN_AUX_D) |               \
1684         BIT(POWER_DOMAIN_INIT))
1685
1686 static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
1687         .sync_hw = i9xx_always_on_power_well_noop,
1688         .enable = i9xx_always_on_power_well_noop,
1689         .disable = i9xx_always_on_power_well_noop,
1690         .is_enabled = i9xx_always_on_power_well_enabled,
1691 };
1692
1693 static const struct i915_power_well_ops chv_pipe_power_well_ops = {
1694         .sync_hw = chv_pipe_power_well_sync_hw,
1695         .enable = chv_pipe_power_well_enable,
1696         .disable = chv_pipe_power_well_disable,
1697         .is_enabled = chv_pipe_power_well_enabled,
1698 };
1699
1700 static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
1701         .sync_hw = vlv_power_well_sync_hw,
1702         .enable = chv_dpio_cmn_power_well_enable,
1703         .disable = chv_dpio_cmn_power_well_disable,
1704         .is_enabled = vlv_power_well_enabled,
1705 };
1706
1707 static struct i915_power_well i9xx_always_on_power_well[] = {
1708         {
1709                 .name = "always-on",
1710                 .always_on = 1,
1711                 .domains = POWER_DOMAIN_MASK,
1712                 .ops = &i9xx_always_on_power_well_ops,
1713         },
1714 };
1715
1716 static const struct i915_power_well_ops hsw_power_well_ops = {
1717         .sync_hw = hsw_power_well_sync_hw,
1718         .enable = hsw_power_well_enable,
1719         .disable = hsw_power_well_disable,
1720         .is_enabled = hsw_power_well_enabled,
1721 };
1722
1723 static const struct i915_power_well_ops skl_power_well_ops = {
1724         .sync_hw = skl_power_well_sync_hw,
1725         .enable = skl_power_well_enable,
1726         .disable = skl_power_well_disable,
1727         .is_enabled = skl_power_well_enabled,
1728 };
1729
1730 static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
1731         .sync_hw = gen9_dc_off_power_well_sync_hw,
1732         .enable = gen9_dc_off_power_well_enable,
1733         .disable = gen9_dc_off_power_well_disable,
1734         .is_enabled = gen9_dc_off_power_well_enabled,
1735 };
1736
1737 static struct i915_power_well hsw_power_wells[] = {
1738         {
1739                 .name = "always-on",
1740                 .always_on = 1,
1741                 .domains = HSW_ALWAYS_ON_POWER_DOMAINS,
1742                 .ops = &i9xx_always_on_power_well_ops,
1743         },
1744         {
1745                 .name = "display",
1746                 .domains = HSW_DISPLAY_POWER_DOMAINS,
1747                 .ops = &hsw_power_well_ops,
1748         },
1749 };
1750
1751 static struct i915_power_well bdw_power_wells[] = {
1752         {
1753                 .name = "always-on",
1754                 .always_on = 1,
1755                 .domains = BDW_ALWAYS_ON_POWER_DOMAINS,
1756                 .ops = &i9xx_always_on_power_well_ops,
1757         },
1758         {
1759                 .name = "display",
1760                 .domains = BDW_DISPLAY_POWER_DOMAINS,
1761                 .ops = &hsw_power_well_ops,
1762         },
1763 };
1764
1765 static const struct i915_power_well_ops vlv_display_power_well_ops = {
1766         .sync_hw = vlv_power_well_sync_hw,
1767         .enable = vlv_display_power_well_enable,
1768         .disable = vlv_display_power_well_disable,
1769         .is_enabled = vlv_power_well_enabled,
1770 };
1771
1772 static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
1773         .sync_hw = vlv_power_well_sync_hw,
1774         .enable = vlv_dpio_cmn_power_well_enable,
1775         .disable = vlv_dpio_cmn_power_well_disable,
1776         .is_enabled = vlv_power_well_enabled,
1777 };
1778
1779 static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
1780         .sync_hw = vlv_power_well_sync_hw,
1781         .enable = vlv_power_well_enable,
1782         .disable = vlv_power_well_disable,
1783         .is_enabled = vlv_power_well_enabled,
1784 };
1785
1786 static struct i915_power_well vlv_power_wells[] = {
1787         {
1788                 .name = "always-on",
1789                 .always_on = 1,
1790                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1791                 .ops = &i9xx_always_on_power_well_ops,
1792                 .data = PUNIT_POWER_WELL_ALWAYS_ON,
1793         },
1794         {
1795                 .name = "display",
1796                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1797                 .data = PUNIT_POWER_WELL_DISP2D,
1798                 .ops = &vlv_display_power_well_ops,
1799         },
1800         {
1801                 .name = "dpio-tx-b-01",
1802                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1803                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1804                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1805                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1806                 .ops = &vlv_dpio_power_well_ops,
1807                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01,
1808         },
1809         {
1810                 .name = "dpio-tx-b-23",
1811                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1812                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1813                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1814                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1815                 .ops = &vlv_dpio_power_well_ops,
1816                 .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23,
1817         },
1818         {
1819                 .name = "dpio-tx-c-01",
1820                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1821                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1822                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1823                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1824                 .ops = &vlv_dpio_power_well_ops,
1825                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01,
1826         },
1827         {
1828                 .name = "dpio-tx-c-23",
1829                 .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
1830                            VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
1831                            VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
1832                            VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
1833                 .ops = &vlv_dpio_power_well_ops,
1834                 .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23,
1835         },
1836         {
1837                 .name = "dpio-common",
1838                 .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
1839                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1840                 .ops = &vlv_dpio_cmn_power_well_ops,
1841         },
1842 };
1843
1844 static struct i915_power_well chv_power_wells[] = {
1845         {
1846                 .name = "always-on",
1847                 .always_on = 1,
1848                 .domains = VLV_ALWAYS_ON_POWER_DOMAINS,
1849                 .ops = &i9xx_always_on_power_well_ops,
1850         },
1851         {
1852                 .name = "display",
1853                 /*
1854                  * Pipe A power well is the new disp2d well. Pipe B and C
1855                  * power wells don't actually exist. Pipe A power well is
1856                  * required for any pipe to work.
1857                  */
1858                 .domains = VLV_DISPLAY_POWER_DOMAINS,
1859                 .data = PIPE_A,
1860                 .ops = &chv_pipe_power_well_ops,
1861         },
1862         {
1863                 .name = "dpio-common-bc",
1864                 .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
1865                 .data = PUNIT_POWER_WELL_DPIO_CMN_BC,
1866                 .ops = &chv_dpio_cmn_power_well_ops,
1867         },
1868         {
1869                 .name = "dpio-common-d",
1870                 .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
1871                 .data = PUNIT_POWER_WELL_DPIO_CMN_D,
1872                 .ops = &chv_dpio_cmn_power_well_ops,
1873         },
1874 };
1875
1876 bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
1877                                     int power_well_id)
1878 {
1879         struct i915_power_well *power_well;
1880         bool ret;
1881
1882         power_well = lookup_power_well(dev_priv, power_well_id);
1883         ret = power_well->ops->is_enabled(dev_priv, power_well);
1884
1885         return ret;
1886 }
1887
1888 static struct i915_power_well skl_power_wells[] = {
1889         {
1890                 .name = "always-on",
1891                 .always_on = 1,
1892                 .domains = SKL_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1893                 .ops = &i9xx_always_on_power_well_ops,
1894                 .data = SKL_DISP_PW_ALWAYS_ON,
1895         },
1896         {
1897                 .name = "power well 1",
1898                 /* Handled by the DMC firmware */
1899                 .domains = 0,
1900                 .ops = &skl_power_well_ops,
1901                 .data = SKL_DISP_PW_1,
1902         },
1903         {
1904                 .name = "MISC IO power well",
1905                 /* Handled by the DMC firmware */
1906                 .domains = 0,
1907                 .ops = &skl_power_well_ops,
1908                 .data = SKL_DISP_PW_MISC_IO,
1909         },
1910         {
1911                 .name = "DC off",
1912                 .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
1913                 .ops = &gen9_dc_off_power_well_ops,
1914                 .data = SKL_DISP_PW_DC_OFF,
1915         },
1916         {
1917                 .name = "power well 2",
1918                 .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1919                 .ops = &skl_power_well_ops,
1920                 .data = SKL_DISP_PW_2,
1921         },
1922         {
1923                 .name = "DDI A/E power well",
1924                 .domains = SKL_DISPLAY_DDI_A_E_POWER_DOMAINS,
1925                 .ops = &skl_power_well_ops,
1926                 .data = SKL_DISP_PW_DDI_A_E,
1927         },
1928         {
1929                 .name = "DDI B power well",
1930                 .domains = SKL_DISPLAY_DDI_B_POWER_DOMAINS,
1931                 .ops = &skl_power_well_ops,
1932                 .data = SKL_DISP_PW_DDI_B,
1933         },
1934         {
1935                 .name = "DDI C power well",
1936                 .domains = SKL_DISPLAY_DDI_C_POWER_DOMAINS,
1937                 .ops = &skl_power_well_ops,
1938                 .data = SKL_DISP_PW_DDI_C,
1939         },
1940         {
1941                 .name = "DDI D power well",
1942                 .domains = SKL_DISPLAY_DDI_D_POWER_DOMAINS,
1943                 .ops = &skl_power_well_ops,
1944                 .data = SKL_DISP_PW_DDI_D,
1945         },
1946 };
1947
1948 void skl_pw1_misc_io_init(struct drm_i915_private *dev_priv)
1949 {
1950         struct i915_power_well *well;
1951
1952         if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
1953                 return;
1954
1955         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1956         intel_power_well_enable(dev_priv, well);
1957
1958         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
1959         intel_power_well_enable(dev_priv, well);
1960 }
1961
1962 void skl_pw1_misc_io_fini(struct drm_i915_private *dev_priv)
1963 {
1964         struct i915_power_well *well;
1965
1966         if (!(IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)))
1967                 return;
1968
1969         well = lookup_power_well(dev_priv, SKL_DISP_PW_1);
1970         intel_power_well_disable(dev_priv, well);
1971
1972         well = lookup_power_well(dev_priv, SKL_DISP_PW_MISC_IO);
1973         intel_power_well_disable(dev_priv, well);
1974 }
1975
1976 static struct i915_power_well bxt_power_wells[] = {
1977         {
1978                 .name = "always-on",
1979                 .always_on = 1,
1980                 .domains = BXT_DISPLAY_ALWAYS_ON_POWER_DOMAINS,
1981                 .ops = &i9xx_always_on_power_well_ops,
1982         },
1983         {
1984                 .name = "power well 1",
1985                 .domains = BXT_DISPLAY_POWERWELL_1_POWER_DOMAINS,
1986                 .ops = &skl_power_well_ops,
1987                 .data = SKL_DISP_PW_1,
1988         },
1989         {
1990                 .name = "DC off",
1991                 .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
1992                 .ops = &gen9_dc_off_power_well_ops,
1993                 .data = SKL_DISP_PW_DC_OFF,
1994         },
1995         {
1996                 .name = "power well 2",
1997                 .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
1998                 .ops = &skl_power_well_ops,
1999                 .data = SKL_DISP_PW_2,
2000         },
2001 };
2002
2003 static int
2004 sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
2005                                    int disable_power_well)
2006 {
2007         if (disable_power_well >= 0)
2008                 return !!disable_power_well;
2009
2010         if (IS_BROXTON(dev_priv)) {
2011                 DRM_DEBUG_KMS("Disabling display power well support\n");
2012                 return 0;
2013         }
2014
2015         return 1;
2016 }
2017
2018 static uint32_t get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
2019                                     int enable_dc)
2020 {
2021         uint32_t mask;
2022         int requested_dc;
2023         int max_dc;
2024
2025         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2026                 max_dc = 2;
2027                 mask = 0;
2028         } else if (IS_BROXTON(dev_priv)) {
2029                 max_dc = 1;
2030                 /*
2031                  * DC9 has a separate HW flow from the rest of the DC states,
2032                  * not depending on the DMC firmware. It's needed by system
2033                  * suspend/resume, so allow it unconditionally.
2034                  */
2035                 mask = DC_STATE_EN_DC9;
2036         } else {
2037                 max_dc = 0;
2038                 mask = 0;
2039         }
2040
2041         if (!i915.disable_power_well)
2042                 max_dc = 0;
2043
2044         if (enable_dc >= 0 && enable_dc <= max_dc) {
2045                 requested_dc = enable_dc;
2046         } else if (enable_dc == -1) {
2047                 requested_dc = max_dc;
2048         } else if (enable_dc > max_dc && enable_dc <= 2) {
2049                 DRM_DEBUG_KMS("Adjusting requested max DC state (%d->%d)\n",
2050                               enable_dc, max_dc);
2051                 requested_dc = max_dc;
2052         } else {
2053                 DRM_ERROR("Unexpected value for enable_dc (%d)\n", enable_dc);
2054                 requested_dc = max_dc;
2055         }
2056
2057         if (requested_dc > 1)
2058                 mask |= DC_STATE_EN_UPTO_DC6;
2059         if (requested_dc > 0)
2060                 mask |= DC_STATE_EN_UPTO_DC5;
2061
2062         DRM_DEBUG_KMS("Allowed DC state mask %02x\n", mask);
2063
2064         return mask;
2065 }
2066
2067 #define set_power_wells(power_domains, __power_wells) ({                \
2068         (power_domains)->power_wells = (__power_wells);                 \
2069         (power_domains)->power_well_count = ARRAY_SIZE(__power_wells);  \
2070 })
2071
2072 /**
2073  * intel_power_domains_init - initializes the power domain structures
2074  * @dev_priv: i915 device instance
2075  *
2076  * Initializes the power domain structures for @dev_priv depending upon the
2077  * supported platform.
2078  */
2079 int intel_power_domains_init(struct drm_i915_private *dev_priv)
2080 {
2081         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2082
2083         i915.disable_power_well = sanitize_disable_power_well_option(dev_priv,
2084                                                      i915.disable_power_well);
2085         dev_priv->csr.allowed_dc_mask = get_allowed_dc_mask(dev_priv,
2086                                                             i915.enable_dc);
2087
2088         BUILD_BUG_ON(POWER_DOMAIN_NUM > 31);
2089
2090         mutex_init(&power_domains->lock);
2091
2092         /*
2093          * The enabling order will be from lower to higher indexed wells,
2094          * the disabling order is reversed.
2095          */
2096         if (IS_HASWELL(dev_priv)) {
2097                 set_power_wells(power_domains, hsw_power_wells);
2098         } else if (IS_BROADWELL(dev_priv)) {
2099                 set_power_wells(power_domains, bdw_power_wells);
2100         } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
2101                 set_power_wells(power_domains, skl_power_wells);
2102         } else if (IS_BROXTON(dev_priv)) {
2103                 set_power_wells(power_domains, bxt_power_wells);
2104         } else if (IS_CHERRYVIEW(dev_priv)) {
2105                 set_power_wells(power_domains, chv_power_wells);
2106         } else if (IS_VALLEYVIEW(dev_priv)) {
2107                 set_power_wells(power_domains, vlv_power_wells);
2108         } else {
2109                 set_power_wells(power_domains, i9xx_always_on_power_well);
2110         }
2111
2112         return 0;
2113 }
2114
2115 /**
2116  * intel_power_domains_fini - finalizes the power domain structures
2117  * @dev_priv: i915 device instance
2118  *
2119  * Finalizes the power domain structures for @dev_priv depending upon the
2120  * supported platform. This function also disables runtime pm and ensures that
2121  * the device stays powered up so that the driver can be reloaded.
2122  */
2123 void intel_power_domains_fini(struct drm_i915_private *dev_priv)
2124 {
2125         struct device *device = &dev_priv->dev->pdev->dev;
2126
2127         /*
2128          * The i915.ko module is still not prepared to be loaded when
2129          * the power well is not enabled, so just enable it in case
2130          * we're going to unload/reload.
2131          * The following also reacquires the RPM reference the core passed
2132          * to the driver during loading, which is dropped in
2133          * intel_runtime_pm_enable(). We have to hand back the control of the
2134          * device to the core with this reference held.
2135          */
2136         intel_display_set_init_power(dev_priv, true);
2137
2138         /* Remove the refcount we took to keep power well support disabled. */
2139         if (!i915.disable_power_well)
2140                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2141
2142         /*
2143          * Remove the refcount we took in intel_runtime_pm_enable() in case
2144          * the platform doesn't support runtime PM.
2145          */
2146         if (!HAS_RUNTIME_PM(dev_priv))
2147                 pm_runtime_put(device);
2148 }
2149
2150 static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
2151 {
2152         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2153         struct i915_power_well *power_well;
2154         int i;
2155
2156         mutex_lock(&power_domains->lock);
2157         for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) {
2158                 power_well->ops->sync_hw(dev_priv, power_well);
2159                 power_well->hw_enabled = power_well->ops->is_enabled(dev_priv,
2160                                                                      power_well);
2161         }
2162         mutex_unlock(&power_domains->lock);
2163 }
2164
2165 static void skl_display_core_init(struct drm_i915_private *dev_priv,
2166                                   bool resume)
2167 {
2168         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2169         uint32_t val;
2170
2171         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2172
2173         /* enable PCH reset handshake */
2174         val = I915_READ(HSW_NDE_RSTWRN_OPT);
2175         I915_WRITE(HSW_NDE_RSTWRN_OPT, val | RESET_PCH_HANDSHAKE_ENABLE);
2176
2177         /* enable PG1 and Misc I/O */
2178         mutex_lock(&power_domains->lock);
2179         skl_pw1_misc_io_init(dev_priv);
2180         mutex_unlock(&power_domains->lock);
2181
2182         if (!resume)
2183                 return;
2184
2185         skl_init_cdclk(dev_priv);
2186
2187         if (dev_priv->csr.dmc_payload)
2188                 intel_csr_load_program(dev_priv);
2189 }
2190
2191 static void skl_display_core_uninit(struct drm_i915_private *dev_priv)
2192 {
2193         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2194
2195         gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
2196
2197         skl_uninit_cdclk(dev_priv);
2198
2199         /* The spec doesn't call for removing the reset handshake flag */
2200         /* disable PG1 and Misc I/O */
2201         mutex_lock(&power_domains->lock);
2202         skl_pw1_misc_io_fini(dev_priv);
2203         mutex_unlock(&power_domains->lock);
2204 }
2205
2206 static void chv_phy_control_init(struct drm_i915_private *dev_priv)
2207 {
2208         struct i915_power_well *cmn_bc =
2209                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2210         struct i915_power_well *cmn_d =
2211                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_D);
2212
2213         /*
2214          * DISPLAY_PHY_CONTROL can get corrupted if read. As a
2215          * workaround never ever read DISPLAY_PHY_CONTROL, and
2216          * instead maintain a shadow copy ourselves. Use the actual
2217          * power well state and lane status to reconstruct the
2218          * expected initial value.
2219          */
2220         dev_priv->chv_phy_control =
2221                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY0) |
2222                 PHY_LDO_SEQ_DELAY(PHY_LDO_DELAY_600NS, DPIO_PHY1) |
2223                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH0) |
2224                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY0, DPIO_CH1) |
2225                 PHY_CH_POWER_MODE(PHY_CH_DEEP_PSR, DPIO_PHY1, DPIO_CH0);
2226
2227         /*
2228          * If all lanes are disabled we leave the override disabled
2229          * with all power down bits cleared to match the state we
2230          * would use after disabling the port. Otherwise enable the
2231          * override and set the lane powerdown bits accding to the
2232          * current lane status.
2233          */
2234         if (cmn_bc->ops->is_enabled(dev_priv, cmn_bc)) {
2235                 uint32_t status = I915_READ(DPLL(PIPE_A));
2236                 unsigned int mask;
2237
2238                 mask = status & DPLL_PORTB_READY_MASK;
2239                 if (mask == 0xf)
2240                         mask = 0x0;
2241                 else
2242                         dev_priv->chv_phy_control |=
2243                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0);
2244
2245                 dev_priv->chv_phy_control |=
2246                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH0);
2247
2248                 mask = (status & DPLL_PORTC_READY_MASK) >> 4;
2249                 if (mask == 0xf)
2250                         mask = 0x0;
2251                 else
2252                         dev_priv->chv_phy_control |=
2253                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1);
2254
2255                 dev_priv->chv_phy_control |=
2256                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY0, DPIO_CH1);
2257
2258                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY0);
2259
2260                 dev_priv->chv_phy_assert[DPIO_PHY0] = false;
2261         } else {
2262                 dev_priv->chv_phy_assert[DPIO_PHY0] = true;
2263         }
2264
2265         if (cmn_d->ops->is_enabled(dev_priv, cmn_d)) {
2266                 uint32_t status = I915_READ(DPIO_PHY_STATUS);
2267                 unsigned int mask;
2268
2269                 mask = status & DPLL_PORTD_READY_MASK;
2270
2271                 if (mask == 0xf)
2272                         mask = 0x0;
2273                 else
2274                         dev_priv->chv_phy_control |=
2275                                 PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0);
2276
2277                 dev_priv->chv_phy_control |=
2278                         PHY_CH_POWER_DOWN_OVRD(mask, DPIO_PHY1, DPIO_CH0);
2279
2280                 dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(DPIO_PHY1);
2281
2282                 dev_priv->chv_phy_assert[DPIO_PHY1] = false;
2283         } else {
2284                 dev_priv->chv_phy_assert[DPIO_PHY1] = true;
2285         }
2286
2287         I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
2288
2289         DRM_DEBUG_KMS("Initial PHY_CONTROL=0x%08x\n",
2290                       dev_priv->chv_phy_control);
2291 }
2292
2293 static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv)
2294 {
2295         struct i915_power_well *cmn =
2296                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC);
2297         struct i915_power_well *disp2d =
2298                 lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D);
2299
2300         /* If the display might be already active skip this */
2301         if (cmn->ops->is_enabled(dev_priv, cmn) &&
2302             disp2d->ops->is_enabled(dev_priv, disp2d) &&
2303             I915_READ(DPIO_CTL) & DPIO_CMNRST)
2304                 return;
2305
2306         DRM_DEBUG_KMS("toggling display PHY side reset\n");
2307
2308         /* cmnlane needs DPLL registers */
2309         disp2d->ops->enable(dev_priv, disp2d);
2310
2311         /*
2312          * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx:
2313          * Need to assert and de-assert PHY SB reset by gating the
2314          * common lane power, then un-gating it.
2315          * Simply ungating isn't enough to reset the PHY enough to get
2316          * ports and lanes running.
2317          */
2318         cmn->ops->disable(dev_priv, cmn);
2319 }
2320
2321 /**
2322  * intel_power_domains_init_hw - initialize hardware power domain state
2323  * @dev_priv: i915 device instance
2324  *
2325  * This function initializes the hardware power domain state and enables all
2326  * power domains using intel_display_set_init_power().
2327  */
2328 void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume)
2329 {
2330         struct drm_device *dev = dev_priv->dev;
2331         struct i915_power_domains *power_domains = &dev_priv->power_domains;
2332
2333         power_domains->initializing = true;
2334
2335         if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
2336                 skl_display_core_init(dev_priv, resume);
2337         } else if (IS_CHERRYVIEW(dev)) {
2338                 mutex_lock(&power_domains->lock);
2339                 chv_phy_control_init(dev_priv);
2340                 mutex_unlock(&power_domains->lock);
2341         } else if (IS_VALLEYVIEW(dev)) {
2342                 mutex_lock(&power_domains->lock);
2343                 vlv_cmnlane_wa(dev_priv);
2344                 mutex_unlock(&power_domains->lock);
2345         }
2346
2347         /* For now, we need the power well to be always enabled. */
2348         intel_display_set_init_power(dev_priv, true);
2349         /* Disable power support if the user asked so. */
2350         if (!i915.disable_power_well)
2351                 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT);
2352         intel_power_domains_sync_hw(dev_priv);
2353         power_domains->initializing = false;
2354 }
2355
2356 /**
2357  * intel_power_domains_suspend - suspend power domain state
2358  * @dev_priv: i915 device instance
2359  *
2360  * This function prepares the hardware power domain state before entering
2361  * system suspend. It must be paired with intel_power_domains_init_hw().
2362  */
2363 void intel_power_domains_suspend(struct drm_i915_private *dev_priv)
2364 {
2365         /*
2366          * Even if power well support was disabled we still want to disable
2367          * power wells while we are system suspended.
2368          */
2369         if (!i915.disable_power_well)
2370                 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT);
2371
2372         if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
2373                 skl_display_core_uninit(dev_priv);
2374 }
2375
2376 /**
2377  * intel_runtime_pm_get - grab a runtime pm reference
2378  * @dev_priv: i915 device instance
2379  *
2380  * This function grabs a device-level runtime pm reference (mostly used for GEM
2381  * code to ensure the GTT or GT is on) and ensures that it is powered up.
2382  *
2383  * Any runtime pm reference obtained by this function must have a symmetric
2384  * call to intel_runtime_pm_put() to release the reference again.
2385  */
2386 void intel_runtime_pm_get(struct drm_i915_private *dev_priv)
2387 {
2388         struct drm_device *dev = dev_priv->dev;
2389         struct device *device = &dev->pdev->dev;
2390
2391         pm_runtime_get_sync(device);
2392
2393         atomic_inc(&dev_priv->pm.wakeref_count);
2394         assert_rpm_wakelock_held(dev_priv);
2395 }
2396
2397 /**
2398  * intel_runtime_pm_get_if_in_use - grab a runtime pm reference if device in use
2399  * @dev_priv: i915 device instance
2400  *
2401  * This function grabs a device-level runtime pm reference if the device is
2402  * already in use and ensures that it is powered up.
2403  *
2404  * Any runtime pm reference obtained by this function must have a symmetric
2405  * call to intel_runtime_pm_put() to release the reference again.
2406  */
2407 bool intel_runtime_pm_get_if_in_use(struct drm_i915_private *dev_priv)
2408 {
2409         struct drm_device *dev = dev_priv->dev;
2410         struct device *device = &dev->pdev->dev;
2411
2412         if (IS_ENABLED(CONFIG_PM)) {
2413                 int ret = pm_runtime_get_if_in_use(device);
2414
2415                 /*
2416                  * In cases runtime PM is disabled by the RPM core and we get
2417                  * an -EINVAL return value we are not supposed to call this
2418                  * function, since the power state is undefined. This applies
2419                  * atm to the late/early system suspend/resume handlers.
2420                  */
2421                 WARN_ON_ONCE(ret < 0);
2422                 if (ret <= 0)
2423                         return false;
2424         }
2425
2426         atomic_inc(&dev_priv->pm.wakeref_count);
2427         assert_rpm_wakelock_held(dev_priv);
2428
2429         return true;
2430 }
2431
2432 /**
2433  * intel_runtime_pm_get_noresume - grab a runtime pm reference
2434  * @dev_priv: i915 device instance
2435  *
2436  * This function grabs a device-level runtime pm reference (mostly used for GEM
2437  * code to ensure the GTT or GT is on).
2438  *
2439  * It will _not_ power up the device but instead only check that it's powered
2440  * on.  Therefore it is only valid to call this functions from contexts where
2441  * the device is known to be powered up and where trying to power it up would
2442  * result in hilarity and deadlocks. That pretty much means only the system
2443  * suspend/resume code where this is used to grab runtime pm references for
2444  * delayed setup down in work items.
2445  *
2446  * Any runtime pm reference obtained by this function must have a symmetric
2447  * call to intel_runtime_pm_put() to release the reference again.
2448  */
2449 void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv)
2450 {
2451         struct drm_device *dev = dev_priv->dev;
2452         struct device *device = &dev->pdev->dev;
2453
2454         assert_rpm_wakelock_held(dev_priv);
2455         pm_runtime_get_noresume(device);
2456
2457         atomic_inc(&dev_priv->pm.wakeref_count);
2458 }
2459
2460 /**
2461  * intel_runtime_pm_put - release a runtime pm reference
2462  * @dev_priv: i915 device instance
2463  *
2464  * This function drops the device-level runtime pm reference obtained by
2465  * intel_runtime_pm_get() and might power down the corresponding
2466  * hardware block right away if this is the last reference.
2467  */
2468 void intel_runtime_pm_put(struct drm_i915_private *dev_priv)
2469 {
2470         struct drm_device *dev = dev_priv->dev;
2471         struct device *device = &dev->pdev->dev;
2472
2473         assert_rpm_wakelock_held(dev_priv);
2474         if (atomic_dec_and_test(&dev_priv->pm.wakeref_count))
2475                 atomic_inc(&dev_priv->pm.atomic_seq);
2476
2477         pm_runtime_mark_last_busy(device);
2478         pm_runtime_put_autosuspend(device);
2479 }
2480
2481 /**
2482  * intel_runtime_pm_enable - enable runtime pm
2483  * @dev_priv: i915 device instance
2484  *
2485  * This function enables runtime pm at the end of the driver load sequence.
2486  *
2487  * Note that this function does currently not enable runtime pm for the
2488  * subordinate display power domains. That is only done on the first modeset
2489  * using intel_display_set_init_power().
2490  */
2491 void intel_runtime_pm_enable(struct drm_i915_private *dev_priv)
2492 {
2493         struct drm_device *dev = dev_priv->dev;
2494         struct device *device = &dev->pdev->dev;
2495
2496         pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */
2497         pm_runtime_mark_last_busy(device);
2498
2499         /*
2500          * Take a permanent reference to disable the RPM functionality and drop
2501          * it only when unloading the driver. Use the low level get/put helpers,
2502          * so the driver's own RPM reference tracking asserts also work on
2503          * platforms without RPM support.
2504          */
2505         if (!HAS_RUNTIME_PM(dev)) {
2506                 pm_runtime_dont_use_autosuspend(device);
2507                 pm_runtime_get_sync(device);
2508         } else {
2509                 pm_runtime_use_autosuspend(device);
2510         }
2511
2512         /*
2513          * The core calls the driver load handler with an RPM reference held.
2514          * We drop that here and will reacquire it during unloading in
2515          * intel_power_domains_fini().
2516          */
2517         pm_runtime_put_autosuspend(device);
2518 }
2519