drivers/gpu/drm/ast/ast_dram_tables.h

   1 #ifndef AST_DRAM_TABLES_H
   2 #define AST_DRAM_TABLES_H
   3
   4 /* DRAM timing tables */
   5 struct ast_dramstruct {
   6         u16 index;
   7         u32 data;
   8 };
   9
  10 static const struct ast_dramstruct ast2000_dram_table_data[] = {
  11         { 0x0108, 0x00000000 },
  12         { 0x0120, 0x00004a21 },
  13         { 0xFF00, 0x00000043 },
  14         { 0x0000, 0xFFFFFFFF },
  15         { 0x0004, 0x00000089 },
  16         { 0x0008, 0x22331353 },
  17         { 0x000C, 0x0d07000b },
  18         { 0x0010, 0x11113333 },
  19         { 0x0020, 0x00110350 },
  20         { 0x0028, 0x1e0828f0 },
  21         { 0x0024, 0x00000001 },
  22         { 0x001C, 0x00000000 },
  23         { 0x0014, 0x00000003 },
  24         { 0xFF00, 0x00000043 },
  25         { 0x0018, 0x00000131 },
  26         { 0x0014, 0x00000001 },
  27         { 0xFF00, 0x00000043 },
  28         { 0x0018, 0x00000031 },
  29         { 0x0014, 0x00000001 },
  30         { 0xFF00, 0x00000043 },
  31         { 0x0028, 0x1e0828f1 },
  32         { 0x0024, 0x00000003 },
  33         { 0x002C, 0x1f0f28fb },
  34         { 0x0030, 0xFFFFFE01 },
  35         { 0xFFFF, 0xFFFFFFFF }
  36 };
  37
  38 static const struct ast_dramstruct ast1100_dram_table_data[] = {
  39         { 0x2000, 0x1688a8a8 },
  40         { 0x2020, 0x000041f0 },
  41         { 0xFF00, 0x00000043 },
  42         { 0x0000, 0xfc600309 },
  43         { 0x006C, 0x00909090 },
  44         { 0x0064, 0x00050000 },
  45         { 0x0004, 0x00000585 },
  46         { 0x0008, 0x0011030f },
  47         { 0x0010, 0x22201724 },
  48         { 0x0018, 0x1e29011a },
  49         { 0x0020, 0x00c82222 },
  50         { 0x0014, 0x01001523 },
  51         { 0x001C, 0x1024010d },
  52         { 0x0024, 0x00cb2522 },
  53         { 0x0038, 0xffffff82 },
  54         { 0x003C, 0x00000000 },
  55         { 0x0040, 0x00000000 },
  56         { 0x0044, 0x00000000 },
  57         { 0x0048, 0x00000000 },
  58         { 0x004C, 0x00000000 },
  59         { 0x0050, 0x00000000 },
  60         { 0x0054, 0x00000000 },
  61         { 0x0058, 0x00000000 },
  62         { 0x005C, 0x00000000 },
  63         { 0x0060, 0x032aa02a },
  64         { 0x0064, 0x002d3000 },
  65         { 0x0068, 0x00000000 },
  66         { 0x0070, 0x00000000 },
  67         { 0x0074, 0x00000000 },
  68         { 0x0078, 0x00000000 },
  69         { 0x007C, 0x00000000 },
  70         { 0x0034, 0x00000001 },
  71         { 0xFF00, 0x00000043 },
  72         { 0x002C, 0x00000732 },
  73         { 0x0030, 0x00000040 },
  74         { 0x0028, 0x00000005 },
  75         { 0x0028, 0x00000007 },
  76         { 0x0028, 0x00000003 },
  77         { 0x0028, 0x00000001 },
  78         { 0x000C, 0x00005a08 },
  79         { 0x002C, 0x00000632 },
  80         { 0x0028, 0x00000001 },
  81         { 0x0030, 0x000003c0 },
  82         { 0x0028, 0x00000003 },
  83         { 0x0030, 0x00000040 },
  84         { 0x0028, 0x00000003 },
  85         { 0x000C, 0x00005a21 },
  86         { 0x0034, 0x00007c03 },
  87         { 0x0120, 0x00004c41 },
  88         { 0xffff, 0xffffffff },
  89 };
  90
  91 static const struct ast_dramstruct ast2100_dram_table_data[] = {
  92         { 0x2000, 0x1688a8a8 },
  93         { 0x2020, 0x00004120 },
  94         { 0xFF00, 0x00000043 },
  95         { 0x0000, 0xfc600309 },
  96         { 0x006C, 0x00909090 },
  97         { 0x0064, 0x00070000 },
  98         { 0x0004, 0x00000489 },
  99         { 0x0008, 0x0011030f },
 100         { 0x0010, 0x32302926 },
 101         { 0x0018, 0x274c0122 },
 102         { 0x0020, 0x00ce2222 },
 103         { 0x0014, 0x01001523 },
 104         { 0x001C, 0x1024010d },
 105         { 0x0024, 0x00cb2522 },
 106         { 0x0038, 0xffffff82 },
 107         { 0x003C, 0x00000000 },
 108         { 0x0040, 0x00000000 },
 109         { 0x0044, 0x00000000 },
 110         { 0x0048, 0x00000000 },
 111         { 0x004C, 0x00000000 },
 112         { 0x0050, 0x00000000 },
 113         { 0x0054, 0x00000000 },
 114         { 0x0058, 0x00000000 },
 115         { 0x005C, 0x00000000 },
 116         { 0x0060, 0x0f2aa02a },
 117         { 0x0064, 0x003f3005 },
 118         { 0x0068, 0x02020202 },
 119         { 0x0070, 0x00000000 },
 120         { 0x0074, 0x00000000 },
 121         { 0x0078, 0x00000000 },
 122         { 0x007C, 0x00000000 },
 123         { 0x0034, 0x00000001 },
 124         { 0xFF00, 0x00000043 },
 125         { 0x002C, 0x00000942 },
 126         { 0x0030, 0x00000040 },
 127         { 0x0028, 0x00000005 },
 128         { 0x0028, 0x00000007 },
 129         { 0x0028, 0x00000003 },
 130         { 0x0028, 0x00000001 },
 131         { 0x000C, 0x00005a08 },
 132         { 0x002C, 0x00000842 },
 133         { 0x0028, 0x00000001 },
 134         { 0x0030, 0x000003c0 },
 135         { 0x0028, 0x00000003 },
 136         { 0x0030, 0x00000040 },
 137         { 0x0028, 0x00000003 },
 138         { 0x000C, 0x00005a21 },
 139         { 0x0034, 0x00007c03 },
 140         { 0x0120, 0x00005061 },
 141         { 0xffff, 0xffffffff },
 142 };
 143
 144 /*
 145  * AST2500 DRAM settings modules
 146  */
 147 #define REGTBL_NUM           17
 148 #define REGIDX_010           0
 149 #define REGIDX_014           1
 150 #define REGIDX_018           2
 151 #define REGIDX_020           3
 152 #define REGIDX_024           4
 153 #define REGIDX_02C           5
 154 #define REGIDX_030           6
 155 #define REGIDX_214           7
 156 #define REGIDX_2E0           8
 157 #define REGIDX_2E4           9
 158 #define REGIDX_2E8           10
 159 #define REGIDX_2EC           11
 160 #define REGIDX_2F0           12
 161 #define REGIDX_2F4           13
 162 #define REGIDX_2F8           14
 163 #define REGIDX_RFC           15
 164 #define REGIDX_PLL           16
 165
 166 static const u32 ast2500_ddr3_1600_timing_table[REGTBL_NUM] = {
 167         0x64604D38,                  /* 0x010 */
 168         0x29690599,                  /* 0x014 */
 169         0x00000300,                  /* 0x018 */
 170         0x00000000,                  /* 0x020 */
 171         0x00000000,                  /* 0x024 */
 172         0x02181E70,                  /* 0x02C */
 173         0x00000040,                  /* 0x030 */
 174         0x00000024,                  /* 0x214 */
 175         0x02001300,                  /* 0x2E0 */
 176         0x0E0000A0,                  /* 0x2E4 */
 177         0x000E001B,                  /* 0x2E8 */
 178         0x35B8C105,                  /* 0x2EC */
 179         0x08090408,                  /* 0x2F0 */
 180         0x9B000800,                  /* 0x2F4 */
 181         0x0E400A00,                  /* 0x2F8 */
 182         0x9971452F,                  /* tRFC  */
 183         0x000071C1                   /* PLL   */
 184 };
 185
 186 static const u32 ast2500_ddr4_1600_timing_table[REGTBL_NUM] = {
 187         0x63604E37,                  /* 0x010 */
 188         0xE97AFA99,                  /* 0x014 */
 189         0x00019000,                  /* 0x018 */
 190         0x08000000,                  /* 0x020 */
 191         0x00000400,                  /* 0x024 */
 192         0x00000410,                  /* 0x02C */
 193         0x00000101,                  /* 0x030 */
 194         0x00000024,                  /* 0x214 */
 195         0x03002900,                  /* 0x2E0 */
 196         0x0E0000A0,                  /* 0x2E4 */
 197         0x000E001C,                  /* 0x2E8 */
 198         0x35B8C106,                  /* 0x2EC */
 199         0x08080607,                  /* 0x2F0 */
 200         0x9B000900,                  /* 0x2F4 */
 201         0x0E400A00,                  /* 0x2F8 */
 202         0x99714545,                  /* tRFC  */
 203         0x000071C1                   /* PLL   */
 204 };
 205
 206 #endif