drivers/gpu/drm/arm/malidp_crtc.c

   1 /*
   2  * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
   3  * Author: Liviu Dudau <[email protected]>
   4  *
   5  * This program is free software and is provided to you under the terms of the
   6  * GNU General Public License version 2 as published by the Free Software
   7  * Foundation, and any use by you of this program is subject to the terms
   8  * of such GNU licence.
   9  *
  10  * ARM Mali DP500/DP550/DP650 driver (crtc operations)
  11  */
  12
  13 #include <drm/drmP.h>
  14 #include <drm/drm_atomic.h>
  15 #include <drm/drm_atomic_helper.h>
  16 #include <drm/drm_crtc.h>
  17 #include <drm/drm_crtc_helper.h>
  18 #include <linux/clk.h>
  19 #include <linux/pm_runtime.h>
  20 #include <video/videomode.h>
  21
  22 #include "malidp_drv.h"
  23 #include "malidp_hw.h"
  24
  25 static bool malidp_crtc_mode_fixup(struct drm_crtc *crtc,
  26                                    const struct drm_display_mode *mode,
  27                                    struct drm_display_mode *adjusted_mode)
  28 {
  29         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
  30         struct malidp_hw_device *hwdev = malidp->dev;
  31
  32         /*
  33          * check that the hardware can drive the required clock rate,
  34          * but skip the check if the clock is meant to be disabled (req_rate = 0)
  35          */
  36         long rate, req_rate = mode->crtc_clock * 1000;
  37
  38         if (req_rate) {
  39                 rate = clk_round_rate(hwdev->pxlclk, req_rate);
  40                 if (rate != req_rate) {
  41                         DRM_DEBUG_DRIVER("pxlclk doesn't support %ld Hz\n",
  42                                          req_rate);
  43                         return false;
  44                 }
  45         }
  46
  47         return true;
  48 }
  49
  50 static void malidp_crtc_enable(struct drm_crtc *crtc)
  51 {
  52         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
  53         struct malidp_hw_device *hwdev = malidp->dev;
  54         struct videomode vm;
  55         int err = pm_runtime_get_sync(crtc->dev->dev);
  56
  57         if (err < 0) {
  58                 DRM_DEBUG_DRIVER("Failed to enable runtime power management: %d\n", err);
  59                 return;
  60         }
  61
  62         drm_display_mode_to_videomode(&crtc->state->adjusted_mode, &vm);
  63         clk_prepare_enable(hwdev->pxlclk);
  64
  65         /* We rely on firmware to set mclk to a sensible level. */
  66         clk_set_rate(hwdev->pxlclk, crtc->state->adjusted_mode.crtc_clock * 1000);
  67
  68         hwdev->modeset(hwdev, &vm);
  69         hwdev->leave_config_mode(hwdev);
  70         drm_crtc_vblank_on(crtc);
  71 }
  72
  73 static void malidp_crtc_disable(struct drm_crtc *crtc)
  74 {
  75         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
  76         struct malidp_hw_device *hwdev = malidp->dev;
  77         int err;
  78
  79         drm_crtc_vblank_off(crtc);
  80         hwdev->enter_config_mode(hwdev);
  81         clk_disable_unprepare(hwdev->pxlclk);
  82
  83         err = pm_runtime_put(crtc->dev->dev);
  84         if (err < 0) {
  85                 DRM_DEBUG_DRIVER("Failed to disable runtime power management: %d\n", err);
  86         }
  87 }
  88
  89 static const struct gamma_curve_segment {
  90         u16 start;
  91         u16 end;
  92 } segments[MALIDP_COEFFTAB_NUM_COEFFS] = {
  93         /* sector 0 */
  94         {    0,    0 }, {    1,    1 }, {    2,    2 }, {    3,    3 },
  95         {    4,    4 }, {    5,    5 }, {    6,    6 }, {    7,    7 },
  96         {    8,    8 }, {    9,    9 }, {   10,   10 }, {   11,   11 },
  97         {   12,   12 }, {   13,   13 }, {   14,   14 }, {   15,   15 },
  98         /* sector 1 */
  99         {   16,   19 }, {   20,   23 }, {   24,   27 }, {   28,   31 },
 100         /* sector 2 */
 101         {   32,   39 }, {   40,   47 }, {   48,   55 }, {   56,   63 },
 102         /* sector 3 */
 103         {   64,   79 }, {   80,   95 }, {   96,  111 }, {  112,  127 },
 104         /* sector 4 */
 105         {  128,  159 }, {  160,  191 }, {  192,  223 }, {  224,  255 },
 106         /* sector 5 */
 107         {  256,  319 }, {  320,  383 }, {  384,  447 }, {  448,  511 },
 108         /* sector 6 */
 109         {  512,  639 }, {  640,  767 }, {  768,  895 }, {  896, 1023 },
 110         { 1024, 1151 }, { 1152, 1279 }, { 1280, 1407 }, { 1408, 1535 },
 111         { 1536, 1663 }, { 1664, 1791 }, { 1792, 1919 }, { 1920, 2047 },
 112         { 2048, 2175 }, { 2176, 2303 }, { 2304, 2431 }, { 2432, 2559 },
 113         { 2560, 2687 }, { 2688, 2815 }, { 2816, 2943 }, { 2944, 3071 },
 114         { 3072, 3199 }, { 3200, 3327 }, { 3328, 3455 }, { 3456, 3583 },
 115         { 3584, 3711 }, { 3712, 3839 }, { 3840, 3967 }, { 3968, 4095 },
 116 };
 117
 118 #define DE_COEFTAB_DATA(a, b) ((((a) & 0xfff) << 16) | (((b) & 0xfff)))
 119
 120 static void malidp_generate_gamma_table(struct drm_property_blob *lut_blob,
 121                                         u32 coeffs[MALIDP_COEFFTAB_NUM_COEFFS])
 122 {
 123         struct drm_color_lut *lut = (struct drm_color_lut *)lut_blob->data;
 124         int i;
 125
 126         for (i = 0; i < MALIDP_COEFFTAB_NUM_COEFFS; ++i) {
 127                 u32 a, b, delta_in, out_start, out_end;
 128
 129                 delta_in = segments[i].end - segments[i].start;
 130                 /* DP has 12-bit internal precision for its LUTs. */
 131                 out_start = drm_color_lut_extract(lut[segments[i].start].green,
 132                                                   12);
 133                 out_end = drm_color_lut_extract(lut[segments[i].end].green, 12);
 134                 a = (delta_in == 0) ? 0 : ((out_end - out_start) * 256) / delta_in;
 135                 b = out_start;
 136                 coeffs[i] = DE_COEFTAB_DATA(a, b);
 137         }
 138 }
 139
 140 /*
 141  * Check if there is a new gamma LUT and if it is of an acceptable size. Also,
 142  * reject any LUTs that use distinct red, green, and blue curves.
 143  */
 144 static int malidp_crtc_atomic_check_gamma(struct drm_crtc *crtc,
 145                                           struct drm_crtc_state *state)
 146 {
 147         struct malidp_crtc_state *mc = to_malidp_crtc_state(state);
 148         struct drm_color_lut *lut;
 149         size_t lut_size;
 150         int i;
 151
 152         if (!state->color_mgmt_changed || !state->gamma_lut)
 153                 return 0;
 154
 155         if (crtc->state->gamma_lut &&
 156             (crtc->state->gamma_lut->base.id == state->gamma_lut->base.id))
 157                 return 0;
 158
 159         if (state->gamma_lut->length % sizeof(struct drm_color_lut))
 160                 return -EINVAL;
 161
 162         lut_size = state->gamma_lut->length / sizeof(struct drm_color_lut);
 163         if (lut_size != MALIDP_GAMMA_LUT_SIZE)
 164                 return -EINVAL;
 165
 166         lut = (struct drm_color_lut *)state->gamma_lut->data;
 167         for (i = 0; i < lut_size; ++i)
 168                 if (!((lut[i].red == lut[i].green) &&
 169                       (lut[i].red == lut[i].blue)))
 170                         return -EINVAL;
 171
 172         if (!state->mode_changed) {
 173                 int ret;
 174
 175                 state->mode_changed = true;
 176                 /*
 177                  * Kerneldoc for drm_atomic_helper_check_modeset mandates that
 178                  * it be invoked when the driver sets ->mode_changed. Since
 179                  * changing the gamma LUT doesn't depend on any external
 180                  * resources, it is safe to call it only once.
 181                  */
 182                 ret = drm_atomic_helper_check_modeset(crtc->dev, state->state);
 183                 if (ret)
 184                         return ret;
 185         }
 186
 187         malidp_generate_gamma_table(state->gamma_lut, mc->gamma_coeffs);
 188         return 0;
 189 }
 190
 191 /*
 192  * Check if there is a new CTM and if it contains valid input. Valid here means
 193  * that the number is inside the representable range for a Q3.12 number,
 194  * excluding truncating the fractional part of the input data.
 195  *
 196  * The COLORADJ registers can be changed atomically.
 197  */
 198 static int malidp_crtc_atomic_check_ctm(struct drm_crtc *crtc,
 199                                         struct drm_crtc_state *state)
 200 {
 201         struct malidp_crtc_state *mc = to_malidp_crtc_state(state);
 202         struct drm_color_ctm *ctm;
 203         int i;
 204
 205         if (!state->color_mgmt_changed)
 206                 return 0;
 207
 208         if (!state->ctm)
 209                 return 0;
 210
 211         if (crtc->state->ctm && (crtc->state->ctm->base.id ==
 212                                  state->ctm->base.id))
 213                 return 0;
 214
 215         /*
 216          * The size of the ctm is checked in
 217          * drm_atomic_replace_property_blob_from_id.
 218          */
 219         ctm = (struct drm_color_ctm *)state->ctm->data;
 220         for (i = 0; i < ARRAY_SIZE(ctm->matrix); ++i) {
 221                 /* Convert from S31.32 to Q3.12. */
 222                 s64 val = ctm->matrix[i];
 223                 u32 mag = ((((u64)val) & ~BIT_ULL(63)) >> 20) &
 224                           GENMASK_ULL(14, 0);
 225
 226                 /*
 227                  * Convert to 2s complement and check the destination's top bit
 228                  * for overflow. NB: Can't check before converting or it'd
 229                  * incorrectly reject the case:
 230                  * sign == 1
 231                  * mag == 0x2000
 232                  */
 233                 if (val & BIT_ULL(63))
 234                         mag = ~mag + 1;
 235                 if (!!(val & BIT_ULL(63)) != !!(mag & BIT(14)))
 236                         return -EINVAL;
 237                 mc->coloradj_coeffs[i] = mag;
 238         }
 239
 240         return 0;
 241 }
 242
 243 static int malidp_crtc_atomic_check_scaling(struct drm_crtc *crtc,
 244                                             struct drm_crtc_state *state)
 245 {
 246         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
 247         struct malidp_hw_device *hwdev = malidp->dev;
 248         struct malidp_crtc_state *cs = to_malidp_crtc_state(state);
 249         struct malidp_se_config *s = &cs->scaler_config;
 250         struct drm_plane *plane;
 251         struct videomode vm;
 252         const struct drm_plane_state *pstate;
 253         u32 h_upscale_factor = 0; /* U16.16 */
 254         u32 v_upscale_factor = 0; /* U16.16 */
 255         u8 scaling = cs->scaled_planes_mask;
 256         int ret;
 257
 258         if (!scaling) {
 259                 s->scale_enable = false;
 260                 goto mclk_calc;
 261         }
 262
 263         /* The scaling engine can only handle one plane at a time. */
 264         if (scaling & (scaling - 1))
 265                 return -EINVAL;
 266
 267         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
 268                 struct malidp_plane *mp = to_malidp_plane(plane);
 269                 u32 phase;
 270
 271                 if (!(mp->layer->id & scaling))
 272                         continue;
 273
 274                 /*
 275                  * Convert crtc_[w|h] to U32.32, then divide by U16.16 src_[w|h]
 276                  * to get the U16.16 result.
 277                  */
 278                 h_upscale_factor = div_u64((u64)pstate->crtc_w << 32,
 279                                            pstate->src_w);
 280                 v_upscale_factor = div_u64((u64)pstate->crtc_h << 32,
 281                                            pstate->src_h);
 282
 283                 s->enhancer_enable = ((h_upscale_factor >> 16) >= 2 ||
 284                                       (v_upscale_factor >> 16) >= 2);
 285
 286                 s->input_w = pstate->src_w >> 16;
 287                 s->input_h = pstate->src_h >> 16;
 288                 s->output_w = pstate->crtc_w;
 289                 s->output_h = pstate->crtc_h;
 290
 291 #define SE_N_PHASE 4
 292 #define SE_SHIFT_N_PHASE 12
 293                 /* Calculate initial_phase and delta_phase for horizontal. */
 294                 phase = s->input_w;
 295                 s->h_init_phase =
 296                                 ((phase << SE_N_PHASE) / s->output_w + 1) / 2;
 297
 298                 phase = s->input_w;
 299                 phase <<= (SE_SHIFT_N_PHASE + SE_N_PHASE);
 300                 s->h_delta_phase = phase / s->output_w;
 301
 302                 /* Same for vertical. */
 303                 phase = s->input_h;
 304                 s->v_init_phase =
 305                                 ((phase << SE_N_PHASE) / s->output_h + 1) / 2;
 306
 307                 phase = s->input_h;
 308                 phase <<= (SE_SHIFT_N_PHASE + SE_N_PHASE);
 309                 s->v_delta_phase = phase / s->output_h;
 310 #undef SE_N_PHASE
 311 #undef SE_SHIFT_N_PHASE
 312                 s->plane_src_id = mp->layer->id;
 313         }
 314
 315         s->scale_enable = true;
 316         s->hcoeff = malidp_se_select_coeffs(h_upscale_factor);
 317         s->vcoeff = malidp_se_select_coeffs(v_upscale_factor);
 318
 319 mclk_calc:
 320         drm_display_mode_to_videomode(&state->adjusted_mode, &vm);
 321         ret = hwdev->se_calc_mclk(hwdev, s, &vm);
 322         if (ret < 0)
 323                 return -EINVAL;
 324         return 0;
 325 }
 326
 327 static int malidp_crtc_atomic_check(struct drm_crtc *crtc,
 328                                     struct drm_crtc_state *state)
 329 {
 330         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
 331         struct malidp_hw_device *hwdev = malidp->dev;
 332         struct drm_plane *plane;
 333         const struct drm_plane_state *pstate;
 334         u32 rot_mem_free, rot_mem_usable;
 335         int rotated_planes = 0;
 336         int ret;
 337
 338         /*
 339          * check if there is enough rotation memory available for planes
 340          * that need 90° and 270° rotation. Each plane has set its required
 341          * memory size in the ->plane_check() callback, here we only make
 342          * sure that the sums are less that the total usable memory.
 343          *
 344          * The rotation memory allocation algorithm (for each plane):
 345          *  a. If no more rotated planes exist, all remaining rotate
 346          *     memory in the bank is available for use by the plane.
 347          *  b. If other rotated planes exist, and plane's layer ID is
 348          *     DE_VIDEO1, it can use all the memory from first bank if
 349          *     secondary rotation memory bank is available, otherwise it can
 350          *     use up to half the bank's memory.
 351          *  c. If other rotated planes exist, and plane's layer ID is not
 352          *     DE_VIDEO1, it can use half of the available memory
 353          *
 354          * Note: this algorithm assumes that the order in which the planes are
 355          * checked always has DE_VIDEO1 plane first in the list if it is
 356          * rotated. Because that is how we create the planes in the first
 357          * place, under current DRM version things work, but if ever the order
 358          * in which drm_atomic_crtc_state_for_each_plane() iterates over planes
 359          * changes, we need to pre-sort the planes before validation.
 360          */
 361
 362         /* first count the number of rotated planes */
 363         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
 364                 if (pstate->rotation & MALIDP_ROTATED_MASK)
 365                         rotated_planes++;
 366         }
 367
 368         rot_mem_free = hwdev->rotation_memory[0];
 369         /*
 370          * if we have more than 1 plane using rotation memory, use the second
 371          * block of rotation memory as well
 372          */
 373         if (rotated_planes > 1)
 374                 rot_mem_free += hwdev->rotation_memory[1];
 375
 376         /* now validate the rotation memory requirements */
 377         drm_atomic_crtc_state_for_each_plane_state(plane, pstate, state) {
 378                 struct malidp_plane *mp = to_malidp_plane(plane);
 379                 struct malidp_plane_state *ms = to_malidp_plane_state(pstate);
 380
 381                 if (pstate->rotation & MALIDP_ROTATED_MASK) {
 382                         /* process current plane */
 383                         rotated_planes--;
 384
 385                         if (!rotated_planes) {
 386                                 /* no more rotated planes, we can use what's left */
 387                                 rot_mem_usable = rot_mem_free;
 388                         } else {
 389                                 if ((mp->layer->id != DE_VIDEO1) ||
 390                                     (hwdev->rotation_memory[1] == 0))
 391                                         rot_mem_usable = rot_mem_free / 2;
 392                                 else
 393                                         rot_mem_usable = hwdev->rotation_memory[0];
 394                         }
 395
 396                         rot_mem_free -= rot_mem_usable;
 397
 398                         if (ms->rotmem_size > rot_mem_usable)
 399                                 return -EINVAL;
 400                 }
 401         }
 402
 403         ret = malidp_crtc_atomic_check_gamma(crtc, state);
 404         ret = ret ? ret : malidp_crtc_atomic_check_ctm(crtc, state);
 405         ret = ret ? ret : malidp_crtc_atomic_check_scaling(crtc, state);
 406
 407         return ret;
 408 }
 409
 410 static const struct drm_crtc_helper_funcs malidp_crtc_helper_funcs = {
 411         .mode_fixup = malidp_crtc_mode_fixup,
 412         .enable = malidp_crtc_enable,
 413         .disable = malidp_crtc_disable,
 414         .atomic_check = malidp_crtc_atomic_check,
 415 };
 416
 417 static struct drm_crtc_state *malidp_crtc_duplicate_state(struct drm_crtc *crtc)
 418 {
 419         struct malidp_crtc_state *state, *old_state;
 420
 421         if (WARN_ON(!crtc->state))
 422                 return NULL;
 423
 424         old_state = to_malidp_crtc_state(crtc->state);
 425         state = kmalloc(sizeof(*state), GFP_KERNEL);
 426         if (!state)
 427                 return NULL;
 428
 429         __drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
 430         memcpy(state->gamma_coeffs, old_state->gamma_coeffs,
 431                sizeof(state->gamma_coeffs));
 432         memcpy(state->coloradj_coeffs, old_state->coloradj_coeffs,
 433                sizeof(state->coloradj_coeffs));
 434         memcpy(&state->scaler_config, &old_state->scaler_config,
 435                sizeof(state->scaler_config));
 436         state->scaled_planes_mask = 0;
 437
 438         return &state->base;
 439 }
 440
 441 static void malidp_crtc_reset(struct drm_crtc *crtc)
 442 {
 443         struct malidp_crtc_state *state = NULL;
 444
 445         if (crtc->state) {
 446                 state = to_malidp_crtc_state(crtc->state);
 447                 __drm_atomic_helper_crtc_destroy_state(crtc->state);
 448         }
 449
 450         kfree(state);
 451         state = kzalloc(sizeof(*state), GFP_KERNEL);
 452         if (state) {
 453                 crtc->state = &state->base;
 454                 crtc->state->crtc = crtc;
 455         }
 456 }
 457
 458 static void malidp_crtc_destroy_state(struct drm_crtc *crtc,
 459                                       struct drm_crtc_state *state)
 460 {
 461         struct malidp_crtc_state *mali_state = NULL;
 462
 463         if (state) {
 464                 mali_state = to_malidp_crtc_state(state);
 465                 __drm_atomic_helper_crtc_destroy_state(state);
 466         }
 467
 468         kfree(mali_state);
 469 }
 470
 471 static int malidp_crtc_enable_vblank(struct drm_crtc *crtc)
 472 {
 473         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
 474         struct malidp_hw_device *hwdev = malidp->dev;
 475
 476         malidp_hw_enable_irq(hwdev, MALIDP_DE_BLOCK,
 477                              hwdev->map.de_irq_map.vsync_irq);
 478         return 0;
 479 }
 480
 481 static void malidp_crtc_disable_vblank(struct drm_crtc *crtc)
 482 {
 483         struct malidp_drm *malidp = crtc_to_malidp_device(crtc);
 484         struct malidp_hw_device *hwdev = malidp->dev;
 485
 486         malidp_hw_disable_irq(hwdev, MALIDP_DE_BLOCK,
 487                               hwdev->map.de_irq_map.vsync_irq);
 488 }
 489
 490 static const struct drm_crtc_funcs malidp_crtc_funcs = {
 491         .gamma_set = drm_atomic_helper_legacy_gamma_set,
 492         .destroy = drm_crtc_cleanup,
 493         .set_config = drm_atomic_helper_set_config,
 494         .page_flip = drm_atomic_helper_page_flip,
 495         .reset = malidp_crtc_reset,
 496         .atomic_duplicate_state = malidp_crtc_duplicate_state,
 497         .atomic_destroy_state = malidp_crtc_destroy_state,
 498         .enable_vblank = malidp_crtc_enable_vblank,
 499         .disable_vblank = malidp_crtc_disable_vblank,
 500 };
 501
 502 int malidp_crtc_init(struct drm_device *drm)
 503 {
 504         struct malidp_drm *malidp = drm->dev_private;
 505         struct drm_plane *primary = NULL, *plane;
 506         int ret;
 507
 508         ret = malidp_de_planes_init(drm);
 509         if (ret < 0) {
 510                 DRM_ERROR("Failed to initialise planes\n");
 511                 return ret;
 512         }
 513
 514         drm_for_each_plane(plane, drm) {
 515                 if (plane->type == DRM_PLANE_TYPE_PRIMARY) {
 516                         primary = plane;
 517                         break;
 518                 }
 519         }
 520
 521         if (!primary) {
 522                 DRM_ERROR("no primary plane found\n");
 523                 ret = -EINVAL;
 524                 goto crtc_cleanup_planes;
 525         }
 526
 527         ret = drm_crtc_init_with_planes(drm, &malidp->crtc, primary, NULL,
 528                                         &malidp_crtc_funcs, NULL);
 529         if (ret)
 530                 goto crtc_cleanup_planes;
 531
 532         drm_crtc_helper_add(&malidp->crtc, &malidp_crtc_helper_funcs);
 533         drm_mode_crtc_set_gamma_size(&malidp->crtc, MALIDP_GAMMA_LUT_SIZE);
 534         /* No inverse-gamma: it is per-plane. */
 535         drm_crtc_enable_color_mgmt(&malidp->crtc, 0, true, MALIDP_GAMMA_LUT_SIZE);
 536
 537         malidp_se_set_enh_coeffs(malidp->dev);
 538
 539         return 0;
 540
 541 crtc_cleanup_planes:
 542         malidp_de_planes_destroy(drm);
 543
 544         return ret;
 545 }