drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_uvd.h"
  28 #include "soc15.h"
  29 #include "soc15d.h"
  30 #include "soc15_common.h"
  31 #include "mmsch_v1_0.h"
  32
  33 #include "uvd/uvd_7_0_offset.h"
  34 #include "uvd/uvd_7_0_sh_mask.h"
  35 #include "vce/vce_4_0_offset.h"
  36 #include "vce/vce_4_0_default.h"
  37 #include "vce/vce_4_0_sh_mask.h"
  38 #include "nbif/nbif_6_1_offset.h"
  39 #include "hdp/hdp_4_0_offset.h"
  40 #include "mmhub/mmhub_1_0_offset.h"
  41 #include "mmhub/mmhub_1_0_sh_mask.h"
  42 #include "ivsrcid/uvd/irqsrcs_uvd_7_0.h"
  43
  44 #define mmUVD_PG0_CC_UVD_HARVESTING                                                                    0x00c7
  45 #define mmUVD_PG0_CC_UVD_HARVESTING_BASE_IDX                                                           1
  46 //UVD_PG0_CC_UVD_HARVESTING
  47 #define UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE__SHIFT                                                         0x1
  48 #define UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE_MASK                                                           0x00000002L
  49
  50 #define UVD7_MAX_HW_INSTANCES_VEGA20                    2
  51
  52 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev);
  53 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev);
  54 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev);
  55 static int uvd_v7_0_start(struct amdgpu_device *adev);
  56 static void uvd_v7_0_stop(struct amdgpu_device *adev);
  57 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev);
  58
  59 static int amdgpu_ih_clientid_uvds[] = {
  60         SOC15_IH_CLIENTID_UVD,
  61         SOC15_IH_CLIENTID_UVD1
  62 };
  63
  64 /**
  65  * uvd_v7_0_ring_get_rptr - get read pointer
  66  *
  67  * @ring: amdgpu_ring pointer
  68  *
  69  * Returns the current hardware read pointer
  70  */
  71 static uint64_t uvd_v7_0_ring_get_rptr(struct amdgpu_ring *ring)
  72 {
  73         struct amdgpu_device *adev = ring->adev;
  74
  75         return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_RPTR);
  76 }
  77
  78 /**
  79  * uvd_v7_0_enc_ring_get_rptr - get enc read pointer
  80  *
  81  * @ring: amdgpu_ring pointer
  82  *
  83  * Returns the current hardware enc read pointer
  84  */
  85 static uint64_t uvd_v7_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
  86 {
  87         struct amdgpu_device *adev = ring->adev;
  88
  89         if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
  90                 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR);
  91         else
  92                 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_RPTR2);
  93 }
  94
  95 /**
  96  * uvd_v7_0_ring_get_wptr - get write pointer
  97  *
  98  * @ring: amdgpu_ring pointer
  99  *
 100  * Returns the current hardware write pointer
 101  */
 102 static uint64_t uvd_v7_0_ring_get_wptr(struct amdgpu_ring *ring)
 103 {
 104         struct amdgpu_device *adev = ring->adev;
 105
 106         return RREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR);
 107 }
 108
 109 /**
 110  * uvd_v7_0_enc_ring_get_wptr - get enc write pointer
 111  *
 112  * @ring: amdgpu_ring pointer
 113  *
 114  * Returns the current hardware enc write pointer
 115  */
 116 static uint64_t uvd_v7_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
 117 {
 118         struct amdgpu_device *adev = ring->adev;
 119
 120         if (ring->use_doorbell)
 121                 return adev->wb.wb[ring->wptr_offs];
 122
 123         if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
 124                 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR);
 125         else
 126                 return RREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2);
 127 }
 128
 129 /**
 130  * uvd_v7_0_ring_set_wptr - set write pointer
 131  *
 132  * @ring: amdgpu_ring pointer
 133  *
 134  * Commits the write pointer to the hardware
 135  */
 136 static void uvd_v7_0_ring_set_wptr(struct amdgpu_ring *ring)
 137 {
 138         struct amdgpu_device *adev = ring->adev;
 139
 140         WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
 141 }
 142
 143 /**
 144  * uvd_v7_0_enc_ring_set_wptr - set enc write pointer
 145  *
 146  * @ring: amdgpu_ring pointer
 147  *
 148  * Commits the enc write pointer to the hardware
 149  */
 150 static void uvd_v7_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
 151 {
 152         struct amdgpu_device *adev = ring->adev;
 153
 154         if (ring->use_doorbell) {
 155                 /* XXX check if swapping is necessary on BE */
 156                 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr);
 157                 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr));
 158                 return;
 159         }
 160
 161         if (ring == &adev->uvd.inst[ring->me].ring_enc[0])
 162                 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR,
 163                         lower_32_bits(ring->wptr));
 164         else
 165                 WREG32_SOC15(UVD, ring->me, mmUVD_RB_WPTR2,
 166                         lower_32_bits(ring->wptr));
 167 }
 168
 169 /**
 170  * uvd_v7_0_enc_ring_test_ring - test if UVD ENC ring is working
 171  *
 172  * @ring: the engine to test on
 173  *
 174  */
 175 static int uvd_v7_0_enc_ring_test_ring(struct amdgpu_ring *ring)
 176 {
 177         struct amdgpu_device *adev = ring->adev;
 178         uint32_t rptr = amdgpu_ring_get_rptr(ring);
 179         unsigned i;
 180         int r;
 181
 182         if (amdgpu_sriov_vf(adev))
 183                 return 0;
 184
 185         r = amdgpu_ring_alloc(ring, 16);
 186         if (r) {
 187                 DRM_ERROR("amdgpu: uvd enc failed to lock (%d)ring %d (%d).\n",
 188                           ring->me, ring->idx, r);
 189                 return r;
 190         }
 191         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
 192         amdgpu_ring_commit(ring);
 193
 194         for (i = 0; i < adev->usec_timeout; i++) {
 195                 if (amdgpu_ring_get_rptr(ring) != rptr)
 196                         break;
 197                 DRM_UDELAY(1);
 198         }
 199
 200         if (i < adev->usec_timeout) {
 201                 DRM_DEBUG("(%d)ring test on %d succeeded in %d usecs\n",
 202                          ring->me, ring->idx, i);
 203         } else {
 204                 DRM_ERROR("amdgpu: (%d)ring %d test failed\n",
 205                           ring->me, ring->idx);
 206                 r = -ETIMEDOUT;
 207         }
 208
 209         return r;
 210 }
 211
 212 /**
 213  * uvd_v7_0_enc_get_create_msg - generate a UVD ENC create msg
 214  *
 215  * @adev: amdgpu_device pointer
 216  * @ring: ring we should submit the msg to
 217  * @handle: session handle to use
 218  * @fence: optional fence to return
 219  *
 220  * Open up a stream for HW test
 221  */
 222 static int uvd_v7_0_enc_get_create_msg(struct amdgpu_ring *ring, uint32_t handle,
 223                                        struct dma_fence **fence)
 224 {
 225         const unsigned ib_size_dw = 16;
 226         struct amdgpu_job *job;
 227         struct amdgpu_ib *ib;
 228         struct dma_fence *f = NULL;
 229         uint64_t dummy;
 230         int i, r;
 231
 232         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 233         if (r)
 234                 return r;
 235
 236         ib = &job->ibs[0];
 237         dummy = ib->gpu_addr + 1024;
 238
 239         ib->length_dw = 0;
 240         ib->ptr[ib->length_dw++] = 0x00000018;
 241         ib->ptr[ib->length_dw++] = 0x00000001; /* session info */
 242         ib->ptr[ib->length_dw++] = handle;
 243         ib->ptr[ib->length_dw++] = 0x00000000;
 244         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 245         ib->ptr[ib->length_dw++] = dummy;
 246
 247         ib->ptr[ib->length_dw++] = 0x00000014;
 248         ib->ptr[ib->length_dw++] = 0x00000002; /* task info */
 249         ib->ptr[ib->length_dw++] = 0x0000001c;
 250         ib->ptr[ib->length_dw++] = 0x00000000;
 251         ib->ptr[ib->length_dw++] = 0x00000000;
 252
 253         ib->ptr[ib->length_dw++] = 0x00000008;
 254         ib->ptr[ib->length_dw++] = 0x08000001; /* op initialize */
 255
 256         for (i = ib->length_dw; i < ib_size_dw; ++i)
 257                 ib->ptr[i] = 0x0;
 258
 259         r = amdgpu_job_submit_direct(job, ring, &f);
 260         if (r)
 261                 goto err;
 262
 263         if (fence)
 264                 *fence = dma_fence_get(f);
 265         dma_fence_put(f);
 266         return 0;
 267
 268 err:
 269         amdgpu_job_free(job);
 270         return r;
 271 }
 272
 273 /**
 274  * uvd_v7_0_enc_get_destroy_msg - generate a UVD ENC destroy msg
 275  *
 276  * @adev: amdgpu_device pointer
 277  * @ring: ring we should submit the msg to
 278  * @handle: session handle to use
 279  * @fence: optional fence to return
 280  *
 281  * Close up a stream for HW test or if userspace failed to do so
 282  */
 283 static int uvd_v7_0_enc_get_destroy_msg(struct amdgpu_ring *ring, uint32_t handle,
 284                                 struct dma_fence **fence)
 285 {
 286         const unsigned ib_size_dw = 16;
 287         struct amdgpu_job *job;
 288         struct amdgpu_ib *ib;
 289         struct dma_fence *f = NULL;
 290         uint64_t dummy;
 291         int i, r;
 292
 293         r = amdgpu_job_alloc_with_ib(ring->adev, ib_size_dw * 4, &job);
 294         if (r)
 295                 return r;
 296
 297         ib = &job->ibs[0];
 298         dummy = ib->gpu_addr + 1024;
 299
 300         ib->length_dw = 0;
 301         ib->ptr[ib->length_dw++] = 0x00000018;
 302         ib->ptr[ib->length_dw++] = 0x00000001;
 303         ib->ptr[ib->length_dw++] = handle;
 304         ib->ptr[ib->length_dw++] = 0x00000000;
 305         ib->ptr[ib->length_dw++] = upper_32_bits(dummy);
 306         ib->ptr[ib->length_dw++] = dummy;
 307
 308         ib->ptr[ib->length_dw++] = 0x00000014;
 309         ib->ptr[ib->length_dw++] = 0x00000002;
 310         ib->ptr[ib->length_dw++] = 0x0000001c;
 311         ib->ptr[ib->length_dw++] = 0x00000000;
 312         ib->ptr[ib->length_dw++] = 0x00000000;
 313
 314         ib->ptr[ib->length_dw++] = 0x00000008;
 315         ib->ptr[ib->length_dw++] = 0x08000002; /* op close session */
 316
 317         for (i = ib->length_dw; i < ib_size_dw; ++i)
 318                 ib->ptr[i] = 0x0;
 319
 320         r = amdgpu_job_submit_direct(job, ring, &f);
 321         if (r)
 322                 goto err;
 323
 324         if (fence)
 325                 *fence = dma_fence_get(f);
 326         dma_fence_put(f);
 327         return 0;
 328
 329 err:
 330         amdgpu_job_free(job);
 331         return r;
 332 }
 333
 334 /**
 335  * uvd_v7_0_enc_ring_test_ib - test if UVD ENC IBs are working
 336  *
 337  * @ring: the engine to test on
 338  *
 339  */
 340 static int uvd_v7_0_enc_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 341 {
 342         struct dma_fence *fence = NULL;
 343         long r;
 344
 345         r = uvd_v7_0_enc_get_create_msg(ring, 1, NULL);
 346         if (r) {
 347                 DRM_ERROR("amdgpu: (%d)failed to get create msg (%ld).\n", ring->me, r);
 348                 goto error;
 349         }
 350
 351         r = uvd_v7_0_enc_get_destroy_msg(ring, 1, &fence);
 352         if (r) {
 353                 DRM_ERROR("amdgpu: (%d)failed to get destroy ib (%ld).\n", ring->me, r);
 354                 goto error;
 355         }
 356
 357         r = dma_fence_wait_timeout(fence, false, timeout);
 358         if (r == 0) {
 359                 DRM_ERROR("amdgpu: (%d)IB test timed out.\n", ring->me);
 360                 r = -ETIMEDOUT;
 361         } else if (r < 0) {
 362                 DRM_ERROR("amdgpu: (%d)fence wait failed (%ld).\n", ring->me, r);
 363         } else {
 364                 DRM_DEBUG("ib test on (%d)ring %d succeeded\n", ring->me, ring->idx);
 365                 r = 0;
 366         }
 367 error:
 368         dma_fence_put(fence);
 369         return r;
 370 }
 371
 372 static int uvd_v7_0_early_init(void *handle)
 373 {
 374         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 375
 376         if (adev->asic_type == CHIP_VEGA20) {
 377                 u32 harvest;
 378                 int i;
 379
 380                 adev->uvd.num_uvd_inst = UVD7_MAX_HW_INSTANCES_VEGA20;
 381                 for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
 382                         harvest = RREG32_SOC15(UVD, i, mmUVD_PG0_CC_UVD_HARVESTING);
 383                         if (harvest & UVD_PG0_CC_UVD_HARVESTING__UVD_DISABLE_MASK) {
 384                                 adev->uvd.harvest_config |= 1 << i;
 385                         }
 386                 }
 387                 if (adev->uvd.harvest_config == (AMDGPU_UVD_HARVEST_UVD0 |
 388                                                  AMDGPU_UVD_HARVEST_UVD1))
 389                         /* both instances are harvested, disable the block */
 390                         return -ENOENT;
 391         } else {
 392                 adev->uvd.num_uvd_inst = 1;
 393         }
 394
 395         if (amdgpu_sriov_vf(adev))
 396                 adev->uvd.num_enc_rings = 1;
 397         else
 398                 adev->uvd.num_enc_rings = 2;
 399         uvd_v7_0_set_ring_funcs(adev);
 400         uvd_v7_0_set_enc_ring_funcs(adev);
 401         uvd_v7_0_set_irq_funcs(adev);
 402
 403         return 0;
 404 }
 405
 406 static int uvd_v7_0_sw_init(void *handle)
 407 {
 408         struct amdgpu_ring *ring;
 409
 410         int i, j, r;
 411         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 412
 413         for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
 414                 if (adev->uvd.harvest_config & (1 << j))
 415                         continue;
 416                 /* UVD TRAP */
 417                 r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], UVD_7_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->uvd.inst[j].irq);
 418                 if (r)
 419                         return r;
 420
 421                 /* UVD ENC TRAP */
 422                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 423                         r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], i + UVD_7_0__SRCID__UVD_ENC_GEN_PURP, &adev->uvd.inst[j].irq);
 424                         if (r)
 425                                 return r;
 426                 }
 427         }
 428
 429         r = amdgpu_uvd_sw_init(adev);
 430         if (r)
 431                 return r;
 432
 433         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 434                 const struct common_firmware_header *hdr;
 435                 hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
 436                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].ucode_id = AMDGPU_UCODE_ID_UVD;
 437                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].fw = adev->uvd.fw;
 438                 adev->firmware.fw_size +=
 439                         ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
 440
 441                 if (adev->uvd.num_uvd_inst == UVD7_MAX_HW_INSTANCES_VEGA20) {
 442                         adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].ucode_id = AMDGPU_UCODE_ID_UVD1;
 443                         adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].fw = adev->uvd.fw;
 444                         adev->firmware.fw_size +=
 445                                 ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
 446                 }
 447                 DRM_INFO("PSP loading UVD firmware\n");
 448         }
 449
 450         r = amdgpu_uvd_resume(adev);
 451         if (r)
 452                 return r;
 453
 454         for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
 455                 if (adev->uvd.harvest_config & (1 << j))
 456                         continue;
 457                 if (!amdgpu_sriov_vf(adev)) {
 458                         ring = &adev->uvd.inst[j].ring;
 459                         sprintf(ring->name, "uvd<%d>", j);
 460                         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0);
 461                         if (r)
 462                                 return r;
 463                 }
 464
 465                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 466                         ring = &adev->uvd.inst[j].ring_enc[i];
 467                         sprintf(ring->name, "uvd_enc%d<%d>", i, j);
 468                         if (amdgpu_sriov_vf(adev)) {
 469                                 ring->use_doorbell = true;
 470
 471                                 /* currently only use the first enconding ring for
 472                                  * sriov, so set unused location for other unused rings.
 473                                  */
 474                                 if (i == 0)
 475                                         ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING0_1 * 2;
 476                                 else
 477                                         ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING2_3 * 2 + 1;
 478                         }
 479                         r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0);
 480                         if (r)
 481                                 return r;
 482                 }
 483         }
 484
 485         r = amdgpu_uvd_entity_init(adev);
 486         if (r)
 487                 return r;
 488
 489         r = amdgpu_virt_alloc_mm_table(adev);
 490         if (r)
 491                 return r;
 492
 493         return r;
 494 }
 495
 496 static int uvd_v7_0_sw_fini(void *handle)
 497 {
 498         int i, j, r;
 499         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 500
 501         amdgpu_virt_free_mm_table(adev);
 502
 503         r = amdgpu_uvd_suspend(adev);
 504         if (r)
 505                 return r;
 506
 507         for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
 508                 if (adev->uvd.harvest_config & (1 << j))
 509                         continue;
 510                 for (i = 0; i < adev->uvd.num_enc_rings; ++i)
 511                         amdgpu_ring_fini(&adev->uvd.inst[j].ring_enc[i]);
 512         }
 513         return amdgpu_uvd_sw_fini(adev);
 514 }
 515
 516 /**
 517  * uvd_v7_0_hw_init - start and test UVD block
 518  *
 519  * @adev: amdgpu_device pointer
 520  *
 521  * Initialize the hardware, boot up the VCPU and do some testing
 522  */
 523 static int uvd_v7_0_hw_init(void *handle)
 524 {
 525         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 526         struct amdgpu_ring *ring;
 527         uint32_t tmp;
 528         int i, j, r;
 529
 530         if (amdgpu_sriov_vf(adev))
 531                 r = uvd_v7_0_sriov_start(adev);
 532         else
 533                 r = uvd_v7_0_start(adev);
 534         if (r)
 535                 goto done;
 536
 537         for (j = 0; j < adev->uvd.num_uvd_inst; ++j) {
 538                 if (adev->uvd.harvest_config & (1 << j))
 539                         continue;
 540                 ring = &adev->uvd.inst[j].ring;
 541
 542                 if (!amdgpu_sriov_vf(adev)) {
 543                         r = amdgpu_ring_test_helper(ring);
 544                         if (r)
 545                                 goto done;
 546
 547                         r = amdgpu_ring_alloc(ring, 10);
 548                         if (r) {
 549                                 DRM_ERROR("amdgpu: (%d)ring failed to lock UVD ring (%d).\n", j, r);
 550                                 goto done;
 551                         }
 552
 553                         tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
 554                                 mmUVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL), 0);
 555                         amdgpu_ring_write(ring, tmp);
 556                         amdgpu_ring_write(ring, 0xFFFFF);
 557
 558                         tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
 559                                 mmUVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL), 0);
 560                         amdgpu_ring_write(ring, tmp);
 561                         amdgpu_ring_write(ring, 0xFFFFF);
 562
 563                         tmp = PACKET0(SOC15_REG_OFFSET(UVD, j,
 564                                 mmUVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL), 0);
 565                         amdgpu_ring_write(ring, tmp);
 566                         amdgpu_ring_write(ring, 0xFFFFF);
 567
 568                         /* Clear timeout status bits */
 569                         amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,
 570                                 mmUVD_SEMA_TIMEOUT_STATUS), 0));
 571                         amdgpu_ring_write(ring, 0x8);
 572
 573                         amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, j,
 574                                 mmUVD_SEMA_CNTL), 0));
 575                         amdgpu_ring_write(ring, 3);
 576
 577                         amdgpu_ring_commit(ring);
 578                 }
 579
 580                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
 581                         ring = &adev->uvd.inst[j].ring_enc[i];
 582                         r = amdgpu_ring_test_helper(ring);
 583                         if (r)
 584                                 goto done;
 585                 }
 586         }
 587 done:
 588         if (!r)
 589                 DRM_INFO("UVD and UVD ENC initialized successfully.\n");
 590
 591         return r;
 592 }
 593
 594 /**
 595  * uvd_v7_0_hw_fini - stop the hardware block
 596  *
 597  * @adev: amdgpu_device pointer
 598  *
 599  * Stop the UVD block, mark ring as not ready any more
 600  */
 601 static int uvd_v7_0_hw_fini(void *handle)
 602 {
 603         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 604         int i;
 605
 606         if (!amdgpu_sriov_vf(adev))
 607                 uvd_v7_0_stop(adev);
 608         else {
 609                 /* full access mode, so don't touch any UVD register */
 610                 DRM_DEBUG("For SRIOV client, shouldn't do anything.\n");
 611         }
 612
 613         for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
 614                 if (adev->uvd.harvest_config & (1 << i))
 615                         continue;
 616                 adev->uvd.inst[i].ring.sched.ready = false;
 617         }
 618
 619         return 0;
 620 }
 621
 622 static int uvd_v7_0_suspend(void *handle)
 623 {
 624         int r;
 625         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 626
 627         r = uvd_v7_0_hw_fini(adev);
 628         if (r)
 629                 return r;
 630
 631         return amdgpu_uvd_suspend(adev);
 632 }
 633
 634 static int uvd_v7_0_resume(void *handle)
 635 {
 636         int r;
 637         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 638
 639         r = amdgpu_uvd_resume(adev);
 640         if (r)
 641                 return r;
 642
 643         return uvd_v7_0_hw_init(adev);
 644 }
 645
 646 /**
 647  * uvd_v7_0_mc_resume - memory controller programming
 648  *
 649  * @adev: amdgpu_device pointer
 650  *
 651  * Let the UVD memory controller know it's offsets
 652  */
 653 static void uvd_v7_0_mc_resume(struct amdgpu_device *adev)
 654 {
 655         uint32_t size = AMDGPU_UVD_FIRMWARE_SIZE(adev);
 656         uint32_t offset;
 657         int i;
 658
 659         for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
 660                 if (adev->uvd.harvest_config & (1 << i))
 661                         continue;
 662                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 663                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 664                                 i == 0 ?
 665                                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_lo:
 666                                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].tmr_mc_addr_lo);
 667                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 668                                 i == 0 ?
 669                                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].tmr_mc_addr_hi:
 670                                 adev->firmware.ucode[AMDGPU_UCODE_ID_UVD1].tmr_mc_addr_hi);
 671                         WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0, 0);
 672                         offset = 0;
 673                 } else {
 674                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 675                                 lower_32_bits(adev->uvd.inst[i].gpu_addr));
 676                         WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 677                                 upper_32_bits(adev->uvd.inst[i].gpu_addr));
 678                         offset = size;
 679                         WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET0,
 680                                         AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 681                 }
 682
 683                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE0, size);
 684
 685                 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 686                                 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset));
 687                 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 688                                 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset));
 689                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET1, (1 << 21));
 690                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_UVD_HEAP_SIZE);
 691
 692                 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 693                                 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 694                 WREG32_SOC15(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 695                                 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 696                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_OFFSET2, (2 << 21));
 697                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CACHE_SIZE2,
 698                                 AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40));
 699
 700                 WREG32_SOC15(UVD, i, mmUVD_UDEC_ADDR_CONFIG,
 701                                 adev->gfx.config.gb_addr_config);
 702                 WREG32_SOC15(UVD, i, mmUVD_UDEC_DB_ADDR_CONFIG,
 703                                 adev->gfx.config.gb_addr_config);
 704                 WREG32_SOC15(UVD, i, mmUVD_UDEC_DBW_ADDR_CONFIG,
 705                                 adev->gfx.config.gb_addr_config);
 706
 707                 WREG32_SOC15(UVD, i, mmUVD_GP_SCRATCH4, adev->uvd.max_handles);
 708         }
 709 }
 710
 711 static int uvd_v7_0_mmsch_start(struct amdgpu_device *adev,
 712                                 struct amdgpu_mm_table *table)
 713 {
 714         uint32_t data = 0, loop;
 715         uint64_t addr = table->gpu_addr;
 716         struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)table->cpu_addr;
 717         uint32_t size;
 718         int i;
 719
 720         size = header->header_size + header->vce_table_size + header->uvd_table_size;
 721
 722         /* 1, write to vce_mmsch_vf_ctx_addr_lo/hi register with GPU mc addr of memory descriptor location */
 723         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr));
 724         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr));
 725
 726         /* 2, update vmid of descriptor */
 727         data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID);
 728         data &= ~VCE_MMSCH_VF_VMID__VF_CTX_VMID_MASK;
 729         data |= (0 << VCE_MMSCH_VF_VMID__VF_CTX_VMID__SHIFT); /* use domain0 for MM scheduler */
 730         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_VMID, data);
 731
 732         /* 3, notify mmsch about the size of this descriptor */
 733         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_SIZE, size);
 734
 735         /* 4, set resp to zero */
 736         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP, 0);
 737
 738         for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
 739                 if (adev->uvd.harvest_config & (1 << i))
 740                         continue;
 741                 WDOORBELL32(adev->uvd.inst[i].ring_enc[0].doorbell_index, 0);
 742                 adev->wb.wb[adev->uvd.inst[i].ring_enc[0].wptr_offs] = 0;
 743                 adev->uvd.inst[i].ring_enc[0].wptr = 0;
 744                 adev->uvd.inst[i].ring_enc[0].wptr_old = 0;
 745         }
 746         /* 5, kick off the initialization and wait until VCE_MMSCH_VF_MAILBOX_RESP becomes non-zero */
 747         WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_HOST, 0x10000001);
 748
 749         data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP);
 750         loop = 1000;
 751         while ((data & 0x10000002) != 0x10000002) {
 752                 udelay(10);
 753                 data = RREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_MAILBOX_RESP);
 754                 loop--;
 755                 if (!loop)
 756                         break;
 757         }
 758
 759         if (!loop) {
 760                 dev_err(adev->dev, "failed to init MMSCH, mmVCE_MMSCH_VF_MAILBOX_RESP = %x\n", data);
 761                 return -EBUSY;
 762         }
 763
 764         return 0;
 765 }
 766
 767 static int uvd_v7_0_sriov_start(struct amdgpu_device *adev)
 768 {
 769         struct amdgpu_ring *ring;
 770         uint32_t offset, size, tmp;
 771         uint32_t table_size = 0;
 772         struct mmsch_v1_0_cmd_direct_write direct_wt = { {0} };
 773         struct mmsch_v1_0_cmd_direct_read_modify_write direct_rd_mod_wt = { {0} };
 774         struct mmsch_v1_0_cmd_direct_polling direct_poll = { {0} };
 775         struct mmsch_v1_0_cmd_end end = { {0} };
 776         uint32_t *init_table = adev->virt.mm_table.cpu_addr;
 777         struct mmsch_v1_0_init_header *header = (struct mmsch_v1_0_init_header *)init_table;
 778         uint8_t i = 0;
 779
 780         direct_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_WRITE;
 781         direct_rd_mod_wt.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_READ_MODIFY_WRITE;
 782         direct_poll.cmd_header.command_type = MMSCH_COMMAND__DIRECT_REG_POLLING;
 783         end.cmd_header.command_type = MMSCH_COMMAND__END;
 784
 785         if (header->uvd_table_offset == 0 && header->uvd_table_size == 0) {
 786                 header->version = MMSCH_VERSION;
 787                 header->header_size = sizeof(struct mmsch_v1_0_init_header) >> 2;
 788
 789                 if (header->vce_table_offset == 0 && header->vce_table_size == 0)
 790                         header->uvd_table_offset = header->header_size;
 791                 else
 792                         header->uvd_table_offset = header->vce_table_size + header->vce_table_offset;
 793
 794                 init_table += header->uvd_table_offset;
 795
 796                 for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
 797                         if (adev->uvd.harvest_config & (1 << i))
 798                                 continue;
 799                         ring = &adev->uvd.inst[i].ring;
 800                         ring->wptr = 0;
 801                         size = AMDGPU_GPU_PAGE_ALIGN(adev->uvd.fw->size + 4);
 802
 803                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
 804                                                            0xFFFFFFFF, 0x00000004);
 805                         /* mc resume*/
 806                         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 807                                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 808                                                             lower_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
 809                                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 810                                                             upper_32_bits(adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].mc_addr));
 811                                 offset = 0;
 812                         } else {
 813                                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW),
 814                                                             lower_32_bits(adev->uvd.inst[i].gpu_addr));
 815                                 MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH),
 816                                                             upper_32_bits(adev->uvd.inst[i].gpu_addr));
 817                                 offset = size;
 818                         }
 819
 820                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET0),
 821                                                     AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 822                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE0), size);
 823
 824                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW),
 825                                                     lower_32_bits(adev->uvd.inst[i].gpu_addr + offset));
 826                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH),
 827                                                     upper_32_bits(adev->uvd.inst[i].gpu_addr + offset));
 828                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET1), (1 << 21));
 829                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE1), AMDGPU_UVD_HEAP_SIZE);
 830
 831                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW),
 832                                                     lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 833                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH),
 834                                                     upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE));
 835                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_OFFSET2), (2 << 21));
 836                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CACHE_SIZE2),
 837                                                     AMDGPU_UVD_STACK_SIZE + (AMDGPU_UVD_SESSION_SIZE * 40));
 838
 839                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_GP_SCRATCH4), adev->uvd.max_handles);
 840                         /* mc resume end*/
 841
 842                         /* disable clock gating */
 843                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_CGC_CTRL),
 844                                                            ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK, 0);
 845
 846                         /* disable interupt */
 847                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
 848                                                            ~UVD_MASTINT_EN__VCPU_EN_MASK, 0);
 849
 850                         /* stall UMC and register bus before resetting VCPU */
 851                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
 852                                                            ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
 853                                                            UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 854
 855                         /* put LMI, VCPU, RBC etc... into reset */
 856                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET),
 857                                                     (uint32_t)(UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 858                                                                UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 859                                                                UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 860                                                                UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 861                                                                UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 862                                                                UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 863                                                                UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 864                                                                UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK));
 865
 866                         /* initialize UVD memory controller */
 867                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL),
 868                                                     (uint32_t)((0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 869                                                                UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 870                                                                UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 871                                                                UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 872                                                                UVD_LMI_CTRL__REQ_MODE_MASK |
 873                                                                0x00100000L));
 874
 875                         /* take all subblocks out of reset, except VCPU */
 876                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET),
 877                                                     UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 878
 879                         /* enable VCPU clock */
 880                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_VCPU_CNTL),
 881                                                     UVD_VCPU_CNTL__CLK_EN_MASK);
 882
 883                         /* enable master interrupt */
 884                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_MASTINT_EN),
 885                                                            ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
 886                                                            (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
 887
 888                         /* clear the bit 4 of UVD_STATUS */
 889                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS),
 890                                                            ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT), 0);
 891
 892                         /* force RBC into idle state */
 893                         size = order_base_2(ring->ring_size);
 894                         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, size);
 895                         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 896                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RBC_RB_CNTL), tmp);
 897
 898                         ring = &adev->uvd.inst[i].ring_enc[0];
 899                         ring->wptr = 0;
 900                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_LO), ring->gpu_addr);
 901                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_addr));
 902                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_SIZE), ring->ring_size / 4);
 903
 904                         /* boot up the VCPU */
 905                         MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_SOFT_RESET), 0);
 906
 907                         /* enable UMC */
 908                         MMSCH_V1_0_INSERT_DIRECT_RD_MOD_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
 909                                                                                            ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK, 0);
 910
 911                         MMSCH_V1_0_INSERT_DIRECT_POLL(SOC15_REG_OFFSET(UVD, i, mmUVD_STATUS), 0x02, 0x02);
 912                 }
 913                 /* add end packet */
 914                 memcpy((void *)init_table, &end, sizeof(struct mmsch_v1_0_cmd_end));
 915                 table_size += sizeof(struct mmsch_v1_0_cmd_end) / 4;
 916                 header->uvd_table_size = table_size;
 917
 918         }
 919         return uvd_v7_0_mmsch_start(adev, &adev->virt.mm_table);
 920 }
 921
 922 /**
 923  * uvd_v7_0_start - start UVD block
 924  *
 925  * @adev: amdgpu_device pointer
 926  *
 927  * Setup and start the UVD block
 928  */
 929 static int uvd_v7_0_start(struct amdgpu_device *adev)
 930 {
 931         struct amdgpu_ring *ring;
 932         uint32_t rb_bufsz, tmp;
 933         uint32_t lmi_swap_cntl;
 934         uint32_t mp_swap_cntl;
 935         int i, j, k, r;
 936
 937         for (k = 0; k < adev->uvd.num_uvd_inst; ++k) {
 938                 if (adev->uvd.harvest_config & (1 << k))
 939                         continue;
 940                 /* disable DPG */
 941                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_POWER_STATUS), 0,
 942                                 ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
 943         }
 944
 945         /* disable byte swapping */
 946         lmi_swap_cntl = 0;
 947         mp_swap_cntl = 0;
 948
 949         uvd_v7_0_mc_resume(adev);
 950
 951         for (k = 0; k < adev->uvd.num_uvd_inst; ++k) {
 952                 if (adev->uvd.harvest_config & (1 << k))
 953                         continue;
 954                 ring = &adev->uvd.inst[k].ring;
 955                 /* disable clock gating */
 956                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_CGC_CTRL), 0,
 957                                 ~UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK);
 958
 959                 /* disable interupt */
 960                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN), 0,
 961                                 ~UVD_MASTINT_EN__VCPU_EN_MASK);
 962
 963                 /* stall UMC and register bus before resetting VCPU */
 964                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2),
 965                                 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
 966                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 967                 mdelay(1);
 968
 969                 /* put LMI, VCPU, RBC etc... into reset */
 970                 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET,
 971                         UVD_SOFT_RESET__LMI_SOFT_RESET_MASK |
 972                         UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK |
 973                         UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK |
 974                         UVD_SOFT_RESET__RBC_SOFT_RESET_MASK |
 975                         UVD_SOFT_RESET__CSM_SOFT_RESET_MASK |
 976                         UVD_SOFT_RESET__CXW_SOFT_RESET_MASK |
 977                         UVD_SOFT_RESET__TAP_SOFT_RESET_MASK |
 978                         UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
 979                 mdelay(5);
 980
 981                 /* initialize UVD memory controller */
 982                 WREG32_SOC15(UVD, k, mmUVD_LMI_CTRL,
 983                         (0x40 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 984                         UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 985                         UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 986                         UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 987                         UVD_LMI_CTRL__REQ_MODE_MASK |
 988                         0x00100000L);
 989
 990 #ifdef __BIG_ENDIAN
 991                 /* swap (8 in 32) RB and IB */
 992                 lmi_swap_cntl = 0xa;
 993                 mp_swap_cntl = 0;
 994 #endif
 995                 WREG32_SOC15(UVD, k, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 996                 WREG32_SOC15(UVD, k, mmUVD_MP_SWAP_CNTL, mp_swap_cntl);
 997
 998                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA0, 0x40c2040);
 999                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXA1, 0x0);
1000                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB0, 0x40c2040);
1001                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUXB1, 0x0);
1002                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_ALU, 0);
1003                 WREG32_SOC15(UVD, k, mmUVD_MPC_SET_MUX, 0x88);
1004
1005                 /* take all subblocks out of reset, except VCPU */
1006                 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET,
1007                                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1008                 mdelay(5);
1009
1010                 /* enable VCPU clock */
1011                 WREG32_SOC15(UVD, k, mmUVD_VCPU_CNTL,
1012                                 UVD_VCPU_CNTL__CLK_EN_MASK);
1013
1014                 /* enable UMC */
1015                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_LMI_CTRL2), 0,
1016                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1017
1018                 /* boot up the VCPU */
1019                 WREG32_SOC15(UVD, k, mmUVD_SOFT_RESET, 0);
1020                 mdelay(10);
1021
1022                 for (i = 0; i < 10; ++i) {
1023                         uint32_t status;
1024
1025                         for (j = 0; j < 100; ++j) {
1026                                 status = RREG32_SOC15(UVD, k, mmUVD_STATUS);
1027                                 if (status & 2)
1028                                         break;
1029                                 mdelay(10);
1030                         }
1031                         r = 0;
1032                         if (status & 2)
1033                                 break;
1034
1035                         DRM_ERROR("UVD(%d) not responding, trying to reset the VCPU!!!\n", k);
1036                         WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET),
1037                                         UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1038                                         ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1039                         mdelay(10);
1040                         WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_SOFT_RESET), 0,
1041                                         ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1042                         mdelay(10);
1043                         r = -1;
1044                 }
1045
1046                 if (r) {
1047                         DRM_ERROR("UVD(%d) not responding, giving up!!!\n", k);
1048                         return r;
1049                 }
1050                 /* enable master interrupt */
1051                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_MASTINT_EN),
1052                         (UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK),
1053                         ~(UVD_MASTINT_EN__VCPU_EN_MASK|UVD_MASTINT_EN__SYS_EN_MASK));
1054
1055                 /* clear the bit 4 of UVD_STATUS */
1056                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_STATUS), 0,
1057                                 ~(2 << UVD_STATUS__VCPU_REPORT__SHIFT));
1058
1059                 /* force RBC into idle state */
1060                 rb_bufsz = order_base_2(ring->ring_size);
1061                 tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1062                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1063                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1064                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_WPTR_POLL_EN, 0);
1065                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1066                 tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1067                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_CNTL, tmp);
1068
1069                 /* set the write pointer delay */
1070                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR_CNTL, 0);
1071
1072                 /* set the wb address */
1073                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR_ADDR,
1074                                 (upper_32_bits(ring->gpu_addr) >> 2));
1075
1076                 /* programm the RB_BASE for ring buffer */
1077                 WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1078                                 lower_32_bits(ring->gpu_addr));
1079                 WREG32_SOC15(UVD, k, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1080                                 upper_32_bits(ring->gpu_addr));
1081
1082                 /* Initialize the ring buffer's read and write pointers */
1083                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR, 0);
1084
1085                 ring->wptr = RREG32_SOC15(UVD, k, mmUVD_RBC_RB_RPTR);
1086                 WREG32_SOC15(UVD, k, mmUVD_RBC_RB_WPTR,
1087                                 lower_32_bits(ring->wptr));
1088
1089                 WREG32_P(SOC15_REG_OFFSET(UVD, k, mmUVD_RBC_RB_CNTL), 0,
1090                                 ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
1091
1092                 ring = &adev->uvd.inst[k].ring_enc[0];
1093                 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1094                 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1095                 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO, ring->gpu_addr);
1096                 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1097                 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE, ring->ring_size / 4);
1098
1099                 ring = &adev->uvd.inst[k].ring_enc[1];
1100                 WREG32_SOC15(UVD, k, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1101                 WREG32_SOC15(UVD, k, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1102                 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1103                 WREG32_SOC15(UVD, k, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1104                 WREG32_SOC15(UVD, k, mmUVD_RB_SIZE2, ring->ring_size / 4);
1105         }
1106         return 0;
1107 }
1108
1109 /**
1110  * uvd_v7_0_stop - stop UVD block
1111  *
1112  * @adev: amdgpu_device pointer
1113  *
1114  * stop the UVD block
1115  */
1116 static void uvd_v7_0_stop(struct amdgpu_device *adev)
1117 {
1118         uint8_t i = 0;
1119
1120         for (i = 0; i < adev->uvd.num_uvd_inst; ++i) {
1121                 if (adev->uvd.harvest_config & (1 << i))
1122                         continue;
1123                 /* force RBC into idle state */
1124                 WREG32_SOC15(UVD, i, mmUVD_RBC_RB_CNTL, 0x11010101);
1125
1126                 /* Stall UMC and register bus before resetting VCPU */
1127                 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2),
1128                                 UVD_LMI_CTRL2__STALL_ARB_UMC_MASK,
1129                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1130                 mdelay(1);
1131
1132                 /* put VCPU into reset */
1133                 WREG32_SOC15(UVD, i, mmUVD_SOFT_RESET,
1134                                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1135                 mdelay(5);
1136
1137                 /* disable VCPU clock */
1138                 WREG32_SOC15(UVD, i, mmUVD_VCPU_CNTL, 0x0);
1139
1140                 /* Unstall UMC and register bus */
1141                 WREG32_P(SOC15_REG_OFFSET(UVD, i, mmUVD_LMI_CTRL2), 0,
1142                                 ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
1143         }
1144 }
1145
1146 /**
1147  * uvd_v7_0_ring_emit_fence - emit an fence & trap command
1148  *
1149  * @ring: amdgpu_ring pointer
1150  * @fence: fence to emit
1151  *
1152  * Write a fence and a trap command to the ring.
1153  */
1154 static void uvd_v7_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1155                                      unsigned flags)
1156 {
1157         struct amdgpu_device *adev = ring->adev;
1158
1159         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1160
1161         amdgpu_ring_write(ring,
1162                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));
1163         amdgpu_ring_write(ring, seq);
1164         amdgpu_ring_write(ring,
1165                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1166         amdgpu_ring_write(ring, addr & 0xffffffff);
1167         amdgpu_ring_write(ring,
1168                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1169         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1170         amdgpu_ring_write(ring,
1171                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1172         amdgpu_ring_write(ring, 0);
1173
1174         amdgpu_ring_write(ring,
1175                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1176         amdgpu_ring_write(ring, 0);
1177         amdgpu_ring_write(ring,
1178                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1179         amdgpu_ring_write(ring, 0);
1180         amdgpu_ring_write(ring,
1181                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1182         amdgpu_ring_write(ring, 2);
1183 }
1184
1185 /**
1186  * uvd_v7_0_enc_ring_emit_fence - emit an enc fence & trap command
1187  *
1188  * @ring: amdgpu_ring pointer
1189  * @fence: fence to emit
1190  *
1191  * Write enc a fence and a trap command to the ring.
1192  */
1193 static void uvd_v7_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1194                         u64 seq, unsigned flags)
1195 {
1196
1197         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1198
1199         amdgpu_ring_write(ring, HEVC_ENC_CMD_FENCE);
1200         amdgpu_ring_write(ring, addr);
1201         amdgpu_ring_write(ring, upper_32_bits(addr));
1202         amdgpu_ring_write(ring, seq);
1203         amdgpu_ring_write(ring, HEVC_ENC_CMD_TRAP);
1204 }
1205
1206 /**
1207  * uvd_v7_0_ring_emit_hdp_flush - skip HDP flushing
1208  *
1209  * @ring: amdgpu_ring pointer
1210  */
1211 static void uvd_v7_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
1212 {
1213         /* The firmware doesn't seem to like touching registers at this point. */
1214 }
1215
1216 /**
1217  * uvd_v7_0_ring_test_ring - register write test
1218  *
1219  * @ring: amdgpu_ring pointer
1220  *
1221  * Test if we can successfully write to the context register
1222  */
1223 static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring)
1224 {
1225         struct amdgpu_device *adev = ring->adev;
1226         uint32_t tmp = 0;
1227         unsigned i;
1228         int r;
1229
1230         WREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID, 0xCAFEDEAD);
1231         r = amdgpu_ring_alloc(ring, 3);
1232         if (r) {
1233                 DRM_ERROR("amdgpu: (%d)cp failed to lock ring %d (%d).\n",
1234                           ring->me, ring->idx, r);
1235                 return r;
1236         }
1237         amdgpu_ring_write(ring,
1238                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_CONTEXT_ID), 0));
1239         amdgpu_ring_write(ring, 0xDEADBEEF);
1240         amdgpu_ring_commit(ring);
1241         for (i = 0; i < adev->usec_timeout; i++) {
1242                 tmp = RREG32_SOC15(UVD, ring->me, mmUVD_CONTEXT_ID);
1243                 if (tmp == 0xDEADBEEF)
1244                         break;
1245                 DRM_UDELAY(1);
1246         }
1247
1248         if (i < adev->usec_timeout) {
1249                 DRM_DEBUG("(%d)ring test on %d succeeded in %d usecs\n",
1250                          ring->me, ring->idx, i);
1251         } else {
1252                 DRM_ERROR("(%d)amdgpu: ring %d test failed (0x%08X)\n",
1253                           ring->me, ring->idx, tmp);
1254                 r = -EINVAL;
1255         }
1256         return r;
1257 }
1258
1259 /**
1260  * uvd_v7_0_ring_patch_cs_in_place - Patch the IB for command submission.
1261  *
1262  * @p: the CS parser with the IBs
1263  * @ib_idx: which IB to patch
1264  *
1265  */
1266 static int uvd_v7_0_ring_patch_cs_in_place(struct amdgpu_cs_parser *p,
1267                                            uint32_t ib_idx)
1268 {
1269         struct amdgpu_ring *ring = to_amdgpu_ring(p->entity->rq->sched);
1270         struct amdgpu_ib *ib = &p->job->ibs[ib_idx];
1271         unsigned i;
1272
1273         /* No patching necessary for the first instance */
1274         if (!ring->me)
1275                 return 0;
1276
1277         for (i = 0; i < ib->length_dw; i += 2) {
1278                 uint32_t reg = amdgpu_get_ib_value(p, ib_idx, i);
1279
1280                 reg -= p->adev->reg_offset[UVD_HWIP][0][1];
1281                 reg += p->adev->reg_offset[UVD_HWIP][1][1];
1282
1283                 amdgpu_set_ib_value(p, ib_idx, i, reg);
1284         }
1285         return 0;
1286 }
1287
1288 /**
1289  * uvd_v7_0_ring_emit_ib - execute indirect buffer
1290  *
1291  * @ring: amdgpu_ring pointer
1292  * @ib: indirect buffer to execute
1293  *
1294  * Write ring commands to execute the indirect buffer
1295  */
1296 static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
1297                                   struct amdgpu_ib *ib,
1298                                   unsigned vmid, bool ctx_switch)
1299 {
1300         struct amdgpu_device *adev = ring->adev;
1301
1302         amdgpu_ring_write(ring,
1303                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_VMID), 0));
1304         amdgpu_ring_write(ring, vmid);
1305
1306         amdgpu_ring_write(ring,
1307                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
1308         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1309         amdgpu_ring_write(ring,
1310                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
1311         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1312         amdgpu_ring_write(ring,
1313                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_RBC_IB_SIZE), 0));
1314         amdgpu_ring_write(ring, ib->length_dw);
1315 }
1316
1317 /**
1318  * uvd_v7_0_enc_ring_emit_ib - enc execute indirect buffer
1319  *
1320  * @ring: amdgpu_ring pointer
1321  * @ib: indirect buffer to execute
1322  *
1323  * Write enc ring commands to execute the indirect buffer
1324  */
1325 static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1326                 struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
1327 {
1328         amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
1329         amdgpu_ring_write(ring, vmid);
1330         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1331         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1332         amdgpu_ring_write(ring, ib->length_dw);
1333 }
1334
1335 static void uvd_v7_0_ring_emit_wreg(struct amdgpu_ring *ring,
1336                                     uint32_t reg, uint32_t val)
1337 {
1338         struct amdgpu_device *adev = ring->adev;
1339
1340         amdgpu_ring_write(ring,
1341                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1342         amdgpu_ring_write(ring, reg << 2);
1343         amdgpu_ring_write(ring,
1344                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1345         amdgpu_ring_write(ring, val);
1346         amdgpu_ring_write(ring,
1347                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1348         amdgpu_ring_write(ring, 8);
1349 }
1350
1351 static void uvd_v7_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
1352                                         uint32_t val, uint32_t mask)
1353 {
1354         struct amdgpu_device *adev = ring->adev;
1355
1356         amdgpu_ring_write(ring,
1357                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA0), 0));
1358         amdgpu_ring_write(ring, reg << 2);
1359         amdgpu_ring_write(ring,
1360                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_DATA1), 0));
1361         amdgpu_ring_write(ring, val);
1362         amdgpu_ring_write(ring,
1363                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GP_SCRATCH8), 0));
1364         amdgpu_ring_write(ring, mask);
1365         amdgpu_ring_write(ring,
1366                 PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_GPCOM_VCPU_CMD), 0));
1367         amdgpu_ring_write(ring, 12);
1368 }
1369
1370 static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1371                                         unsigned vmid, uint64_t pd_addr)
1372 {
1373         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1374         uint32_t data0, data1, mask;
1375
1376         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1377
1378         /* wait for reg writes */
1379         data0 = hub->ctx0_ptb_addr_lo32 + vmid * 2;
1380         data1 = lower_32_bits(pd_addr);
1381         mask = 0xffffffff;
1382         uvd_v7_0_ring_emit_reg_wait(ring, data0, data1, mask);
1383 }
1384
1385 static void uvd_v7_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1386 {
1387         struct amdgpu_device *adev = ring->adev;
1388         int i;
1389
1390         WARN_ON(ring->wptr % 2 || count % 2);
1391
1392         for (i = 0; i < count / 2; i++) {
1393                 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, ring->me, mmUVD_NO_OP), 0));
1394                 amdgpu_ring_write(ring, 0);
1395         }
1396 }
1397
1398 static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1399 {
1400         amdgpu_ring_write(ring, HEVC_ENC_CMD_END);
1401 }
1402
1403 static void uvd_v7_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring,
1404                                             uint32_t reg, uint32_t val,
1405                                             uint32_t mask)
1406 {
1407         amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
1408         amdgpu_ring_write(ring, reg << 2);
1409         amdgpu_ring_write(ring, mask);
1410         amdgpu_ring_write(ring, val);
1411 }
1412
1413 static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1414                                             unsigned int vmid, uint64_t pd_addr)
1415 {
1416         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1417
1418         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1419
1420         /* wait for reg writes */
1421         uvd_v7_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2,
1422                                         lower_32_bits(pd_addr), 0xffffffff);
1423 }
1424
1425 static void uvd_v7_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
1426                                         uint32_t reg, uint32_t val)
1427 {
1428         amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
1429         amdgpu_ring_write(ring, reg << 2);
1430         amdgpu_ring_write(ring, val);
1431 }
1432
1433 #if 0
1434 static bool uvd_v7_0_is_idle(void *handle)
1435 {
1436         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1437
1438         return !(RREG32(mmSRBM_STATUS) & SRBM_STATUS__UVD_BUSY_MASK);
1439 }
1440
1441 static int uvd_v7_0_wait_for_idle(void *handle)
1442 {
1443         unsigned i;
1444         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1445
1446         for (i = 0; i < adev->usec_timeout; i++) {
1447                 if (uvd_v7_0_is_idle(handle))
1448                         return 0;
1449         }
1450         return -ETIMEDOUT;
1451 }
1452
1453 #define AMDGPU_UVD_STATUS_BUSY_MASK    0xfd
1454 static bool uvd_v7_0_check_soft_reset(void *handle)
1455 {
1456         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1457         u32 srbm_soft_reset = 0;
1458         u32 tmp = RREG32(mmSRBM_STATUS);
1459
1460         if (REG_GET_FIELD(tmp, SRBM_STATUS, UVD_RQ_PENDING) ||
1461             REG_GET_FIELD(tmp, SRBM_STATUS, UVD_BUSY) ||
1462             (RREG32_SOC15(UVD, ring->me, mmUVD_STATUS) &
1463                     AMDGPU_UVD_STATUS_BUSY_MASK))
1464                 srbm_soft_reset = REG_SET_FIELD(srbm_soft_reset,
1465                                 SRBM_SOFT_RESET, SOFT_RESET_UVD, 1);
1466
1467         if (srbm_soft_reset) {
1468                 adev->uvd.inst[ring->me].srbm_soft_reset = srbm_soft_reset;
1469                 return true;
1470         } else {
1471                 adev->uvd.inst[ring->me].srbm_soft_reset = 0;
1472                 return false;
1473         }
1474 }
1475
1476 static int uvd_v7_0_pre_soft_reset(void *handle)
1477 {
1478         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1479
1480         if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1481                 return 0;
1482
1483         uvd_v7_0_stop(adev);
1484         return 0;
1485 }
1486
1487 static int uvd_v7_0_soft_reset(void *handle)
1488 {
1489         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1490         u32 srbm_soft_reset;
1491
1492         if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1493                 return 0;
1494         srbm_soft_reset = adev->uvd.inst[ring->me].srbm_soft_reset;
1495
1496         if (srbm_soft_reset) {
1497                 u32 tmp;
1498
1499                 tmp = RREG32(mmSRBM_SOFT_RESET);
1500                 tmp |= srbm_soft_reset;
1501                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1502                 WREG32(mmSRBM_SOFT_RESET, tmp);
1503                 tmp = RREG32(mmSRBM_SOFT_RESET);
1504
1505                 udelay(50);
1506
1507                 tmp &= ~srbm_soft_reset;
1508                 WREG32(mmSRBM_SOFT_RESET, tmp);
1509                 tmp = RREG32(mmSRBM_SOFT_RESET);
1510
1511                 /* Wait a little for things to settle down */
1512                 udelay(50);
1513         }
1514
1515         return 0;
1516 }
1517
1518 static int uvd_v7_0_post_soft_reset(void *handle)
1519 {
1520         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1521
1522         if (!adev->uvd.inst[ring->me].srbm_soft_reset)
1523                 return 0;
1524
1525         mdelay(5);
1526
1527         return uvd_v7_0_start(adev);
1528 }
1529 #endif
1530
1531 static int uvd_v7_0_set_interrupt_state(struct amdgpu_device *adev,
1532                                         struct amdgpu_irq_src *source,
1533                                         unsigned type,
1534                                         enum amdgpu_interrupt_state state)
1535 {
1536         // TODO
1537         return 0;
1538 }
1539
1540 static int uvd_v7_0_process_interrupt(struct amdgpu_device *adev,
1541                                       struct amdgpu_irq_src *source,
1542                                       struct amdgpu_iv_entry *entry)
1543 {
1544         uint32_t ip_instance;
1545
1546         switch (entry->client_id) {
1547         case SOC15_IH_CLIENTID_UVD:
1548                 ip_instance = 0;
1549                 break;
1550         case SOC15_IH_CLIENTID_UVD1:
1551                 ip_instance = 1;
1552                 break;
1553         default:
1554                 DRM_ERROR("Unhandled client id: %d\n", entry->client_id);
1555                 return 0;
1556         }
1557
1558         DRM_DEBUG("IH: UVD TRAP\n");
1559
1560         switch (entry->src_id) {
1561         case 124:
1562                 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring);
1563                 break;
1564         case 119:
1565                 amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[0]);
1566                 break;
1567         case 120:
1568                 if (!amdgpu_sriov_vf(adev))
1569                         amdgpu_fence_process(&adev->uvd.inst[ip_instance].ring_enc[1]);
1570                 break;
1571         default:
1572                 DRM_ERROR("Unhandled interrupt: %d %d\n",
1573                           entry->src_id, entry->src_data[0]);
1574                 break;
1575         }
1576
1577         return 0;
1578 }
1579
1580 #if 0
1581 static void uvd_v7_0_set_sw_clock_gating(struct amdgpu_device *adev)
1582 {
1583         uint32_t data, data1, data2, suvd_flags;
1584
1585         data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL);
1586         data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1587         data2 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL);
1588
1589         data &= ~(UVD_CGC_CTRL__CLK_OFF_DELAY_MASK |
1590                   UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK);
1591
1592         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1593                      UVD_SUVD_CGC_GATE__SIT_MASK |
1594                      UVD_SUVD_CGC_GATE__SMP_MASK |
1595                      UVD_SUVD_CGC_GATE__SCM_MASK |
1596                      UVD_SUVD_CGC_GATE__SDB_MASK;
1597
1598         data |= UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK |
1599                 (1 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_GATE_DLY_TIMER)) |
1600                 (4 << REG_FIELD_SHIFT(UVD_CGC_CTRL, CLK_OFF_DELAY));
1601
1602         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
1603                         UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
1604                         UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
1605                         UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
1606                         UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
1607                         UVD_CGC_CTRL__SYS_MODE_MASK |
1608                         UVD_CGC_CTRL__UDEC_MODE_MASK |
1609                         UVD_CGC_CTRL__MPEG2_MODE_MASK |
1610                         UVD_CGC_CTRL__REGS_MODE_MASK |
1611                         UVD_CGC_CTRL__RBC_MODE_MASK |
1612                         UVD_CGC_CTRL__LMI_MC_MODE_MASK |
1613                         UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
1614                         UVD_CGC_CTRL__IDCT_MODE_MASK |
1615                         UVD_CGC_CTRL__MPRD_MODE_MASK |
1616                         UVD_CGC_CTRL__MPC_MODE_MASK |
1617                         UVD_CGC_CTRL__LBSI_MODE_MASK |
1618                         UVD_CGC_CTRL__LRBBM_MODE_MASK |
1619                         UVD_CGC_CTRL__WCB_MODE_MASK |
1620                         UVD_CGC_CTRL__VCPU_MODE_MASK |
1621                         UVD_CGC_CTRL__JPEG_MODE_MASK |
1622                         UVD_CGC_CTRL__JPEG2_MODE_MASK |
1623                         UVD_CGC_CTRL__SCPU_MODE_MASK);
1624         data2 &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK |
1625                         UVD_SUVD_CGC_CTRL__SIT_MODE_MASK |
1626                         UVD_SUVD_CGC_CTRL__SMP_MODE_MASK |
1627                         UVD_SUVD_CGC_CTRL__SCM_MODE_MASK |
1628                         UVD_SUVD_CGC_CTRL__SDB_MODE_MASK);
1629         data1 |= suvd_flags;
1630
1631         WREG32_SOC15(UVD, ring->me, mmUVD_CGC_CTRL, data);
1632         WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, 0);
1633         WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1634         WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_CTRL, data2);
1635 }
1636
1637 static void uvd_v7_0_set_hw_clock_gating(struct amdgpu_device *adev)
1638 {
1639         uint32_t data, data1, cgc_flags, suvd_flags;
1640
1641         data = RREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE);
1642         data1 = RREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE);
1643
1644         cgc_flags = UVD_CGC_GATE__SYS_MASK |
1645                 UVD_CGC_GATE__UDEC_MASK |
1646                 UVD_CGC_GATE__MPEG2_MASK |
1647                 UVD_CGC_GATE__RBC_MASK |
1648                 UVD_CGC_GATE__LMI_MC_MASK |
1649                 UVD_CGC_GATE__IDCT_MASK |
1650                 UVD_CGC_GATE__MPRD_MASK |
1651                 UVD_CGC_GATE__MPC_MASK |
1652                 UVD_CGC_GATE__LBSI_MASK |
1653                 UVD_CGC_GATE__LRBBM_MASK |
1654                 UVD_CGC_GATE__UDEC_RE_MASK |
1655                 UVD_CGC_GATE__UDEC_CM_MASK |
1656                 UVD_CGC_GATE__UDEC_IT_MASK |
1657                 UVD_CGC_GATE__UDEC_DB_MASK |
1658                 UVD_CGC_GATE__UDEC_MP_MASK |
1659                 UVD_CGC_GATE__WCB_MASK |
1660                 UVD_CGC_GATE__VCPU_MASK |
1661                 UVD_CGC_GATE__SCPU_MASK |
1662                 UVD_CGC_GATE__JPEG_MASK |
1663                 UVD_CGC_GATE__JPEG2_MASK;
1664
1665         suvd_flags = UVD_SUVD_CGC_GATE__SRE_MASK |
1666                                 UVD_SUVD_CGC_GATE__SIT_MASK |
1667                                 UVD_SUVD_CGC_GATE__SMP_MASK |
1668                                 UVD_SUVD_CGC_GATE__SCM_MASK |
1669                                 UVD_SUVD_CGC_GATE__SDB_MASK;
1670
1671         data |= cgc_flags;
1672         data1 |= suvd_flags;
1673
1674         WREG32_SOC15(UVD, ring->me, mmUVD_CGC_GATE, data);
1675         WREG32_SOC15(UVD, ring->me, mmUVD_SUVD_CGC_GATE, data1);
1676 }
1677
1678 static void uvd_v7_0_set_bypass_mode(struct amdgpu_device *adev, bool enable)
1679 {
1680         u32 tmp = RREG32_SMC(ixGCK_DFS_BYPASS_CNTL);
1681
1682         if (enable)
1683                 tmp |= (GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
1684                         GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
1685         else
1686                 tmp &= ~(GCK_DFS_BYPASS_CNTL__BYPASSDCLK_MASK |
1687                          GCK_DFS_BYPASS_CNTL__BYPASSVCLK_MASK);
1688
1689         WREG32_SMC(ixGCK_DFS_BYPASS_CNTL, tmp);
1690 }
1691
1692
1693 static int uvd_v7_0_set_clockgating_state(void *handle,
1694                                           enum amd_clockgating_state state)
1695 {
1696         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1697         bool enable = (state == AMD_CG_STATE_GATE) ? true : false;
1698
1699         uvd_v7_0_set_bypass_mode(adev, enable);
1700
1701         if (!(adev->cg_flags & AMD_CG_SUPPORT_UVD_MGCG))
1702                 return 0;
1703
1704         if (enable) {
1705                 /* disable HW gating and enable Sw gating */
1706                 uvd_v7_0_set_sw_clock_gating(adev);
1707         } else {
1708                 /* wait for STATUS to clear */
1709                 if (uvd_v7_0_wait_for_idle(handle))
1710                         return -EBUSY;
1711
1712                 /* enable HW gates because UVD is idle */
1713                 /* uvd_v7_0_set_hw_clock_gating(adev); */
1714         }
1715
1716         return 0;
1717 }
1718
1719 static int uvd_v7_0_set_powergating_state(void *handle,
1720                                           enum amd_powergating_state state)
1721 {
1722         /* This doesn't actually powergate the UVD block.
1723          * That's done in the dpm code via the SMC.  This
1724          * just re-inits the block as necessary.  The actual
1725          * gating still happens in the dpm code.  We should
1726          * revisit this when there is a cleaner line between
1727          * the smc and the hw blocks
1728          */
1729         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1730
1731         if (!(adev->pg_flags & AMD_PG_SUPPORT_UVD))
1732                 return 0;
1733
1734         WREG32_SOC15(UVD, ring->me, mmUVD_POWER_STATUS, UVD_POWER_STATUS__UVD_PG_EN_MASK);
1735
1736         if (state == AMD_PG_STATE_GATE) {
1737                 uvd_v7_0_stop(adev);
1738                 return 0;
1739         } else {
1740                 return uvd_v7_0_start(adev);
1741         }
1742 }
1743 #endif
1744
1745 static int uvd_v7_0_set_clockgating_state(void *handle,
1746                                           enum amd_clockgating_state state)
1747 {
1748         /* needed for driver unload*/
1749         return 0;
1750 }
1751
1752 const struct amd_ip_funcs uvd_v7_0_ip_funcs = {
1753         .name = "uvd_v7_0",
1754         .early_init = uvd_v7_0_early_init,
1755         .late_init = NULL,
1756         .sw_init = uvd_v7_0_sw_init,
1757         .sw_fini = uvd_v7_0_sw_fini,
1758         .hw_init = uvd_v7_0_hw_init,
1759         .hw_fini = uvd_v7_0_hw_fini,
1760         .suspend = uvd_v7_0_suspend,
1761         .resume = uvd_v7_0_resume,
1762         .is_idle = NULL /* uvd_v7_0_is_idle */,
1763         .wait_for_idle = NULL /* uvd_v7_0_wait_for_idle */,
1764         .check_soft_reset = NULL /* uvd_v7_0_check_soft_reset */,
1765         .pre_soft_reset = NULL /* uvd_v7_0_pre_soft_reset */,
1766         .soft_reset = NULL /* uvd_v7_0_soft_reset */,
1767         .post_soft_reset = NULL /* uvd_v7_0_post_soft_reset */,
1768         .set_clockgating_state = uvd_v7_0_set_clockgating_state,
1769         .set_powergating_state = NULL /* uvd_v7_0_set_powergating_state */,
1770 };
1771
1772 static const struct amdgpu_ring_funcs uvd_v7_0_ring_vm_funcs = {
1773         .type = AMDGPU_RING_TYPE_UVD,
1774         .align_mask = 0xf,
1775         .support_64bit_ptrs = false,
1776         .vmhub = AMDGPU_MMHUB,
1777         .get_rptr = uvd_v7_0_ring_get_rptr,
1778         .get_wptr = uvd_v7_0_ring_get_wptr,
1779         .set_wptr = uvd_v7_0_ring_set_wptr,
1780         .patch_cs_in_place = uvd_v7_0_ring_patch_cs_in_place,
1781         .emit_frame_size =
1782                 6 + /* hdp invalidate */
1783                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1784                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1785                 8 + /* uvd_v7_0_ring_emit_vm_flush */
1786                 14 + 14, /* uvd_v7_0_ring_emit_fence x2 vm fence */
1787         .emit_ib_size = 8, /* uvd_v7_0_ring_emit_ib */
1788         .emit_ib = uvd_v7_0_ring_emit_ib,
1789         .emit_fence = uvd_v7_0_ring_emit_fence,
1790         .emit_vm_flush = uvd_v7_0_ring_emit_vm_flush,
1791         .emit_hdp_flush = uvd_v7_0_ring_emit_hdp_flush,
1792         .test_ring = uvd_v7_0_ring_test_ring,
1793         .test_ib = amdgpu_uvd_ring_test_ib,
1794         .insert_nop = uvd_v7_0_ring_insert_nop,
1795         .pad_ib = amdgpu_ring_generic_pad_ib,
1796         .begin_use = amdgpu_uvd_ring_begin_use,
1797         .end_use = amdgpu_uvd_ring_end_use,
1798         .emit_wreg = uvd_v7_0_ring_emit_wreg,
1799         .emit_reg_wait = uvd_v7_0_ring_emit_reg_wait,
1800         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1801 };
1802
1803 static const struct amdgpu_ring_funcs uvd_v7_0_enc_ring_vm_funcs = {
1804         .type = AMDGPU_RING_TYPE_UVD_ENC,
1805         .align_mask = 0x3f,
1806         .nop = HEVC_ENC_CMD_NO_OP,
1807         .support_64bit_ptrs = false,
1808         .vmhub = AMDGPU_MMHUB,
1809         .get_rptr = uvd_v7_0_enc_ring_get_rptr,
1810         .get_wptr = uvd_v7_0_enc_ring_get_wptr,
1811         .set_wptr = uvd_v7_0_enc_ring_set_wptr,
1812         .emit_frame_size =
1813                 3 + 3 + /* hdp flush / invalidate */
1814                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1815                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1816                 4 + /* uvd_v7_0_enc_ring_emit_vm_flush */
1817                 5 + 5 + /* uvd_v7_0_enc_ring_emit_fence x2 vm fence */
1818                 1, /* uvd_v7_0_enc_ring_insert_end */
1819         .emit_ib_size = 5, /* uvd_v7_0_enc_ring_emit_ib */
1820         .emit_ib = uvd_v7_0_enc_ring_emit_ib,
1821         .emit_fence = uvd_v7_0_enc_ring_emit_fence,
1822         .emit_vm_flush = uvd_v7_0_enc_ring_emit_vm_flush,
1823         .test_ring = uvd_v7_0_enc_ring_test_ring,
1824         .test_ib = uvd_v7_0_enc_ring_test_ib,
1825         .insert_nop = amdgpu_ring_insert_nop,
1826         .insert_end = uvd_v7_0_enc_ring_insert_end,
1827         .pad_ib = amdgpu_ring_generic_pad_ib,
1828         .begin_use = amdgpu_uvd_ring_begin_use,
1829         .end_use = amdgpu_uvd_ring_end_use,
1830         .emit_wreg = uvd_v7_0_enc_ring_emit_wreg,
1831         .emit_reg_wait = uvd_v7_0_enc_ring_emit_reg_wait,
1832         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1833 };
1834
1835 static void uvd_v7_0_set_ring_funcs(struct amdgpu_device *adev)
1836 {
1837         int i;
1838
1839         for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
1840                 if (adev->uvd.harvest_config & (1 << i))
1841                         continue;
1842                 adev->uvd.inst[i].ring.funcs = &uvd_v7_0_ring_vm_funcs;
1843                 adev->uvd.inst[i].ring.me = i;
1844                 DRM_INFO("UVD(%d) is enabled in VM mode\n", i);
1845         }
1846 }
1847
1848 static void uvd_v7_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1849 {
1850         int i, j;
1851
1852         for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
1853                 if (adev->uvd.harvest_config & (1 << j))
1854                         continue;
1855                 for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
1856                         adev->uvd.inst[j].ring_enc[i].funcs = &uvd_v7_0_enc_ring_vm_funcs;
1857                         adev->uvd.inst[j].ring_enc[i].me = j;
1858                 }
1859
1860                 DRM_INFO("UVD(%d) ENC is enabled in VM mode\n", j);
1861         }
1862 }
1863
1864 static const struct amdgpu_irq_src_funcs uvd_v7_0_irq_funcs = {
1865         .set = uvd_v7_0_set_interrupt_state,
1866         .process = uvd_v7_0_process_interrupt,
1867 };
1868
1869 static void uvd_v7_0_set_irq_funcs(struct amdgpu_device *adev)
1870 {
1871         int i;
1872
1873         for (i = 0; i < adev->uvd.num_uvd_inst; i++) {
1874                 if (adev->uvd.harvest_config & (1 << i))
1875                         continue;
1876                 adev->uvd.inst[i].irq.num_types = adev->uvd.num_enc_rings + 1;
1877                 adev->uvd.inst[i].irq.funcs = &uvd_v7_0_irq_funcs;
1878         }
1879 }
1880
1881 const struct amdgpu_ip_block_version uvd_v7_0_ip_block =
1882 {
1883                 .type = AMD_IP_BLOCK_TYPE_UVD,
1884                 .major = 7,
1885                 .minor = 0,
1886                 .rev = 0,
1887                 .funcs = &uvd_v7_0_ip_funcs,
1888 };