drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_ucode.h"
  28 #include "amdgpu_trace.h"
  29 #include "vi.h"
  30 #include "vid.h"
  31
  32 #include "oss/oss_2_4_d.h"
  33 #include "oss/oss_2_4_sh_mask.h"
  34
  35 #include "gmc/gmc_7_1_d.h"
  36 #include "gmc/gmc_7_1_sh_mask.h"
  37
  38 #include "gca/gfx_8_0_d.h"
  39 #include "gca/gfx_8_0_enum.h"
  40 #include "gca/gfx_8_0_sh_mask.h"
  41
  42 #include "bif/bif_5_0_d.h"
  43 #include "bif/bif_5_0_sh_mask.h"
  44
  45 #include "iceland_sdma_pkt_open.h"
  46
  47 #include "ivsrcid/ivsrcid_vislands30.h"
  48
  49 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev);
  50 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev);
  51 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev);
  52 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev);
  53
  54 MODULE_FIRMWARE("amdgpu/topaz_sdma.bin");
  55 MODULE_FIRMWARE("amdgpu/topaz_sdma1.bin");
  56
  57 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  58 {
  59         SDMA0_REGISTER_OFFSET,
  60         SDMA1_REGISTER_OFFSET
  61 };
  62
  63 static const u32 golden_settings_iceland_a11[] =
  64 {
  65         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  66         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  67         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  68         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  69 };
  70
  71 static const u32 iceland_mgcg_cgcg_init[] =
  72 {
  73         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  74         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  75 };
  76
  77 /*
  78  * sDMA - System DMA
  79  * Starting with CIK, the GPU has new asynchronous
  80  * DMA engines.  These engines are used for compute
  81  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
  82  * and each one supports 1 ring buffer used for gfx
  83  * and 2 queues used for compute.
  84  *
  85  * The programming model is very similar to the CP
  86  * (ring buffer, IBs, etc.), but sDMA has it's own
  87  * packet format that is different from the PM4 format
  88  * used by the CP. sDMA supports copying data, writing
  89  * embedded data, solid fills, and a number of other
  90  * things.  It also has support for tiling/detiling of
  91  * buffers.
  92  */
  93
  94 static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev)
  95 {
  96         switch (adev->asic_type) {
  97         case CHIP_TOPAZ:
  98                 amdgpu_device_program_register_sequence(adev,
  99                                                         iceland_mgcg_cgcg_init,
 100                                                         ARRAY_SIZE(iceland_mgcg_cgcg_init));
 101                 amdgpu_device_program_register_sequence(adev,
 102                                                         golden_settings_iceland_a11,
 103                                                         ARRAY_SIZE(golden_settings_iceland_a11));
 104                 break;
 105         default:
 106                 break;
 107         }
 108 }
 109
 110 static void sdma_v2_4_free_microcode(struct amdgpu_device *adev)
 111 {
 112         int i;
 113         for (i = 0; i < adev->sdma.num_instances; i++) {
 114                 release_firmware(adev->sdma.instance[i].fw);
 115                 adev->sdma.instance[i].fw = NULL;
 116         }
 117 }
 118
 119 /**
 120  * sdma_v2_4_init_microcode - load ucode images from disk
 121  *
 122  * @adev: amdgpu_device pointer
 123  *
 124  * Use the firmware interface to load the ucode images into
 125  * the driver (not loaded into hw).
 126  * Returns 0 on success, error on failure.
 127  */
 128 static int sdma_v2_4_init_microcode(struct amdgpu_device *adev)
 129 {
 130         const char *chip_name;
 131         char fw_name[30];
 132         int err = 0, i;
 133         struct amdgpu_firmware_info *info = NULL;
 134         const struct common_firmware_header *header = NULL;
 135         const struct sdma_firmware_header_v1_0 *hdr;
 136
 137         DRM_DEBUG("\n");
 138
 139         switch (adev->asic_type) {
 140         case CHIP_TOPAZ:
 141                 chip_name = "topaz";
 142                 break;
 143         default: BUG();
 144         }
 145
 146         for (i = 0; i < adev->sdma.num_instances; i++) {
 147                 if (i == 0)
 148                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 149                 else
 150                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 151                 err = request_firmware(&adev->sdma.instance[i].fw, fw_name, adev->dev);
 152                 if (err)
 153                         goto out;
 154                 err = amdgpu_ucode_validate(adev->sdma.instance[i].fw);
 155                 if (err)
 156                         goto out;
 157                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 158                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 159                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 160                 if (adev->sdma.instance[i].feature_version >= 20)
 161                         adev->sdma.instance[i].burst_nop = true;
 162
 163                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_SMU) {
 164                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 165                         info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 166                         info->fw = adev->sdma.instance[i].fw;
 167                         header = (const struct common_firmware_header *)info->fw->data;
 168                         adev->firmware.fw_size +=
 169                                 ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 170                 }
 171         }
 172
 173 out:
 174         if (err) {
 175                 pr_err("sdma_v2_4: Failed to load firmware \"%s\"\n", fw_name);
 176                 for (i = 0; i < adev->sdma.num_instances; i++) {
 177                         release_firmware(adev->sdma.instance[i].fw);
 178                         adev->sdma.instance[i].fw = NULL;
 179                 }
 180         }
 181         return err;
 182 }
 183
 184 /**
 185  * sdma_v2_4_ring_get_rptr - get the current read pointer
 186  *
 187  * @ring: amdgpu ring pointer
 188  *
 189  * Get the current rptr from the hardware (VI+).
 190  */
 191 static uint64_t sdma_v2_4_ring_get_rptr(struct amdgpu_ring *ring)
 192 {
 193         /* XXX check if swapping is necessary on BE */
 194         return ring->adev->wb.wb[ring->rptr_offs] >> 2;
 195 }
 196
 197 /**
 198  * sdma_v2_4_ring_get_wptr - get the current write pointer
 199  *
 200  * @ring: amdgpu ring pointer
 201  *
 202  * Get the current wptr from the hardware (VI+).
 203  */
 204 static uint64_t sdma_v2_4_ring_get_wptr(struct amdgpu_ring *ring)
 205 {
 206         struct amdgpu_device *adev = ring->adev;
 207         u32 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
 208
 209         return wptr;
 210 }
 211
 212 /**
 213  * sdma_v2_4_ring_set_wptr - commit the write pointer
 214  *
 215  * @ring: amdgpu ring pointer
 216  *
 217  * Write the wptr back to the hardware (VI+).
 218  */
 219 static void sdma_v2_4_ring_set_wptr(struct amdgpu_ring *ring)
 220 {
 221         struct amdgpu_device *adev = ring->adev;
 222
 223         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2);
 224 }
 225
 226 static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 227 {
 228         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 229         int i;
 230
 231         for (i = 0; i < count; i++)
 232                 if (sdma && sdma->burst_nop && (i == 0))
 233                         amdgpu_ring_write(ring, ring->funcs->nop |
 234                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 235                 else
 236                         amdgpu_ring_write(ring, ring->funcs->nop);
 237 }
 238
 239 /**
 240  * sdma_v2_4_ring_emit_ib - Schedule an IB on the DMA engine
 241  *
 242  * @ring: amdgpu ring pointer
 243  * @ib: IB object to schedule
 244  *
 245  * Schedule an IB in the DMA ring (VI).
 246  */
 247 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
 248                                    struct amdgpu_ib *ib,
 249                                    unsigned vmid, bool ctx_switch)
 250 {
 251         /* IB packet must end on a 8 DW boundary */
 252         sdma_v2_4_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
 253
 254         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 255                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 256         /* base must be 32 byte aligned */
 257         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 258         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 259         amdgpu_ring_write(ring, ib->length_dw);
 260         amdgpu_ring_write(ring, 0);
 261         amdgpu_ring_write(ring, 0);
 262
 263 }
 264
 265 /**
 266  * sdma_v2_4_hdp_flush_ring_emit - emit an hdp flush on the DMA ring
 267  *
 268  * @ring: amdgpu ring pointer
 269  *
 270  * Emit an hdp flush packet on the requested DMA ring.
 271  */
 272 static void sdma_v2_4_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 273 {
 274         u32 ref_and_mask = 0;
 275
 276         if (ring->me == 0)
 277                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
 278         else
 279                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
 280
 281         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 282                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 283                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 284         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 285         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 286         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 287         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 288         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 289                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 290 }
 291
 292 /**
 293  * sdma_v2_4_ring_emit_fence - emit a fence on the DMA ring
 294  *
 295  * @ring: amdgpu ring pointer
 296  * @fence: amdgpu fence object
 297  *
 298  * Add a DMA fence packet to the ring to write
 299  * the fence seq number and DMA trap packet to generate
 300  * an interrupt if needed (VI).
 301  */
 302 static void sdma_v2_4_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 303                                       unsigned flags)
 304 {
 305         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 306         /* write the fence */
 307         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 308         amdgpu_ring_write(ring, lower_32_bits(addr));
 309         amdgpu_ring_write(ring, upper_32_bits(addr));
 310         amdgpu_ring_write(ring, lower_32_bits(seq));
 311
 312         /* optionally write high bits as well */
 313         if (write64bit) {
 314                 addr += 4;
 315                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 316                 amdgpu_ring_write(ring, lower_32_bits(addr));
 317                 amdgpu_ring_write(ring, upper_32_bits(addr));
 318                 amdgpu_ring_write(ring, upper_32_bits(seq));
 319         }
 320
 321         /* generate an interrupt */
 322         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 323         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 324 }
 325
 326 /**
 327  * sdma_v2_4_gfx_stop - stop the gfx async dma engines
 328  *
 329  * @adev: amdgpu_device pointer
 330  *
 331  * Stop the gfx async dma ring buffers (VI).
 332  */
 333 static void sdma_v2_4_gfx_stop(struct amdgpu_device *adev)
 334 {
 335         struct amdgpu_ring *sdma0 = &adev->sdma.instance[0].ring;
 336         struct amdgpu_ring *sdma1 = &adev->sdma.instance[1].ring;
 337         u32 rb_cntl, ib_cntl;
 338         int i;
 339
 340         if ((adev->mman.buffer_funcs_ring == sdma0) ||
 341             (adev->mman.buffer_funcs_ring == sdma1))
 342                 amdgpu_ttm_set_buffer_funcs_status(adev, false);
 343
 344         for (i = 0; i < adev->sdma.num_instances; i++) {
 345                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 346                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 347                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 348                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 349                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 350                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 351         }
 352         sdma0->sched.ready = false;
 353         sdma1->sched.ready = false;
 354 }
 355
 356 /**
 357  * sdma_v2_4_rlc_stop - stop the compute async dma engines
 358  *
 359  * @adev: amdgpu_device pointer
 360  *
 361  * Stop the compute async dma queues (VI).
 362  */
 363 static void sdma_v2_4_rlc_stop(struct amdgpu_device *adev)
 364 {
 365         /* XXX todo */
 366 }
 367
 368 /**
 369  * sdma_v2_4_enable - stop the async dma engines
 370  *
 371  * @adev: amdgpu_device pointer
 372  * @enable: enable/disable the DMA MEs.
 373  *
 374  * Halt or unhalt the async dma engines (VI).
 375  */
 376 static void sdma_v2_4_enable(struct amdgpu_device *adev, bool enable)
 377 {
 378         u32 f32_cntl;
 379         int i;
 380
 381         if (!enable) {
 382                 sdma_v2_4_gfx_stop(adev);
 383                 sdma_v2_4_rlc_stop(adev);
 384         }
 385
 386         for (i = 0; i < adev->sdma.num_instances; i++) {
 387                 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 388                 if (enable)
 389                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
 390                 else
 391                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
 392                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
 393         }
 394 }
 395
 396 /**
 397  * sdma_v2_4_gfx_resume - setup and start the async dma engines
 398  *
 399  * @adev: amdgpu_device pointer
 400  *
 401  * Set up the gfx DMA ring buffers and enable them (VI).
 402  * Returns 0 for success, error for failure.
 403  */
 404 static int sdma_v2_4_gfx_resume(struct amdgpu_device *adev)
 405 {
 406         struct amdgpu_ring *ring;
 407         u32 rb_cntl, ib_cntl;
 408         u32 rb_bufsz;
 409         u32 wb_offset;
 410         int i, j, r;
 411
 412         for (i = 0; i < adev->sdma.num_instances; i++) {
 413                 ring = &adev->sdma.instance[i].ring;
 414                 wb_offset = (ring->rptr_offs * 4);
 415
 416                 mutex_lock(&adev->srbm_mutex);
 417                 for (j = 0; j < 16; j++) {
 418                         vi_srbm_select(adev, 0, 0, 0, j);
 419                         /* SDMA GFX */
 420                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 421                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 422                 }
 423                 vi_srbm_select(adev, 0, 0, 0, 0);
 424                 mutex_unlock(&adev->srbm_mutex);
 425
 426                 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
 427                        adev->gfx.config.gb_addr_config & 0x70);
 428
 429                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 430
 431                 /* Set ring buffer size in dwords */
 432                 rb_bufsz = order_base_2(ring->ring_size / 4);
 433                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 434                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 435 #ifdef __BIG_ENDIAN
 436                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 437                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 438                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 439 #endif
 440                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 441
 442                 /* Initialize the ring buffer's read and write pointers */
 443                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 444                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 445                 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
 446                 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 447
 448                 /* set the wb address whether it's enabled or not */
 449                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 450                        upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF);
 451                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 452                        lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC);
 453
 454                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 455
 456                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 457                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 458
 459                 ring->wptr = 0;
 460                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2);
 461
 462                 /* enable DMA RB */
 463                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 464                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 465
 466                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 467                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 468 #ifdef __BIG_ENDIAN
 469                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 470 #endif
 471                 /* enable DMA IBs */
 472                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 473
 474                 ring->sched.ready = true;
 475         }
 476
 477         sdma_v2_4_enable(adev, true);
 478         for (i = 0; i < adev->sdma.num_instances; i++) {
 479                 ring = &adev->sdma.instance[i].ring;
 480                 r = amdgpu_ring_test_helper(ring);
 481                 if (r)
 482                         return r;
 483
 484                 if (adev->mman.buffer_funcs_ring == ring)
 485                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 486         }
 487
 488         return 0;
 489 }
 490
 491 /**
 492  * sdma_v2_4_rlc_resume - setup and start the async dma engines
 493  *
 494  * @adev: amdgpu_device pointer
 495  *
 496  * Set up the compute DMA queues and enable them (VI).
 497  * Returns 0 for success, error for failure.
 498  */
 499 static int sdma_v2_4_rlc_resume(struct amdgpu_device *adev)
 500 {
 501         /* XXX todo */
 502         return 0;
 503 }
 504
 505
 506 /**
 507  * sdma_v2_4_start - setup and start the async dma engines
 508  *
 509  * @adev: amdgpu_device pointer
 510  *
 511  * Set up the DMA engines and enable them (VI).
 512  * Returns 0 for success, error for failure.
 513  */
 514 static int sdma_v2_4_start(struct amdgpu_device *adev)
 515 {
 516         int r;
 517
 518         /* halt the engine before programing */
 519         sdma_v2_4_enable(adev, false);
 520
 521         /* start the gfx rings and rlc compute queues */
 522         r = sdma_v2_4_gfx_resume(adev);
 523         if (r)
 524                 return r;
 525         r = sdma_v2_4_rlc_resume(adev);
 526         if (r)
 527                 return r;
 528
 529         return 0;
 530 }
 531
 532 /**
 533  * sdma_v2_4_ring_test_ring - simple async dma engine test
 534  *
 535  * @ring: amdgpu_ring structure holding ring information
 536  *
 537  * Test the DMA engine by writing using it to write an
 538  * value to memory. (VI).
 539  * Returns 0 for success, error for failure.
 540  */
 541 static int sdma_v2_4_ring_test_ring(struct amdgpu_ring *ring)
 542 {
 543         struct amdgpu_device *adev = ring->adev;
 544         unsigned i;
 545         unsigned index;
 546         int r;
 547         u32 tmp;
 548         u64 gpu_addr;
 549
 550         r = amdgpu_device_wb_get(adev, &index);
 551         if (r) {
 552                 dev_err(adev->dev, "(%d) failed to allocate wb slot\n", r);
 553                 return r;
 554         }
 555
 556         gpu_addr = adev->wb.gpu_addr + (index * 4);
 557         tmp = 0xCAFEDEAD;
 558         adev->wb.wb[index] = cpu_to_le32(tmp);
 559
 560         r = amdgpu_ring_alloc(ring, 5);
 561         if (r) {
 562                 DRM_ERROR("amdgpu: dma failed to lock ring %d (%d).\n", ring->idx, r);
 563                 amdgpu_device_wb_free(adev, index);
 564                 return r;
 565         }
 566
 567         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 568                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 569         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 570         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 571         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 572         amdgpu_ring_write(ring, 0xDEADBEEF);
 573         amdgpu_ring_commit(ring);
 574
 575         for (i = 0; i < adev->usec_timeout; i++) {
 576                 tmp = le32_to_cpu(adev->wb.wb[index]);
 577                 if (tmp == 0xDEADBEEF)
 578                         break;
 579                 DRM_UDELAY(1);
 580         }
 581
 582         if (i < adev->usec_timeout) {
 583                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n", ring->idx, i);
 584         } else {
 585                 DRM_ERROR("amdgpu: ring %d test failed (0x%08X)\n",
 586                           ring->idx, tmp);
 587                 r = -EINVAL;
 588         }
 589         amdgpu_device_wb_free(adev, index);
 590
 591         return r;
 592 }
 593
 594 /**
 595  * sdma_v2_4_ring_test_ib - test an IB on the DMA engine
 596  *
 597  * @ring: amdgpu_ring structure holding ring information
 598  *
 599  * Test a simple IB in the DMA ring (VI).
 600  * Returns 0 on success, error on failure.
 601  */
 602 static int sdma_v2_4_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 603 {
 604         struct amdgpu_device *adev = ring->adev;
 605         struct amdgpu_ib ib;
 606         struct dma_fence *f = NULL;
 607         unsigned index;
 608         u32 tmp = 0;
 609         u64 gpu_addr;
 610         long r;
 611
 612         r = amdgpu_device_wb_get(adev, &index);
 613         if (r) {
 614                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 615                 return r;
 616         }
 617
 618         gpu_addr = adev->wb.gpu_addr + (index * 4);
 619         tmp = 0xCAFEDEAD;
 620         adev->wb.wb[index] = cpu_to_le32(tmp);
 621         memset(&ib, 0, sizeof(ib));
 622         r = amdgpu_ib_get(adev, NULL, 256, &ib);
 623         if (r) {
 624                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 625                 goto err0;
 626         }
 627
 628         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 629                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 630         ib.ptr[1] = lower_32_bits(gpu_addr);
 631         ib.ptr[2] = upper_32_bits(gpu_addr);
 632         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
 633         ib.ptr[4] = 0xDEADBEEF;
 634         ib.ptr[5] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 635         ib.ptr[6] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 636         ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 637         ib.length_dw = 8;
 638
 639         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 640         if (r)
 641                 goto err1;
 642
 643         r = dma_fence_wait_timeout(f, false, timeout);
 644         if (r == 0) {
 645                 DRM_ERROR("amdgpu: IB test timed out\n");
 646                 r = -ETIMEDOUT;
 647                 goto err1;
 648         } else if (r < 0) {
 649                 DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 650                 goto err1;
 651         }
 652         tmp = le32_to_cpu(adev->wb.wb[index]);
 653         if (tmp == 0xDEADBEEF) {
 654                 DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
 655                 r = 0;
 656         } else {
 657                 DRM_ERROR("amdgpu: ib test failed (0x%08X)\n", tmp);
 658                 r = -EINVAL;
 659         }
 660
 661 err1:
 662         amdgpu_ib_free(adev, &ib, NULL);
 663         dma_fence_put(f);
 664 err0:
 665         amdgpu_device_wb_free(adev, index);
 666         return r;
 667 }
 668
 669 /**
 670  * sdma_v2_4_vm_copy_pte - update PTEs by copying them from the GART
 671  *
 672  * @ib: indirect buffer to fill with commands
 673  * @pe: addr of the page entry
 674  * @src: src addr to copy from
 675  * @count: number of page entries to update
 676  *
 677  * Update PTEs by copying them from the GART using sDMA (CIK).
 678  */
 679 static void sdma_v2_4_vm_copy_pte(struct amdgpu_ib *ib,
 680                                   uint64_t pe, uint64_t src,
 681                                   unsigned count)
 682 {
 683         unsigned bytes = count * 8;
 684
 685         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
 686                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 687         ib->ptr[ib->length_dw++] = bytes;
 688         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 689         ib->ptr[ib->length_dw++] = lower_32_bits(src);
 690         ib->ptr[ib->length_dw++] = upper_32_bits(src);
 691         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 692         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 693 }
 694
 695 /**
 696  * sdma_v2_4_vm_write_pte - update PTEs by writing them manually
 697  *
 698  * @ib: indirect buffer to fill with commands
 699  * @pe: addr of the page entry
 700  * @value: dst addr to write into pe
 701  * @count: number of page entries to update
 702  * @incr: increase next addr by incr bytes
 703  *
 704  * Update PTEs by writing them manually using sDMA (CIK).
 705  */
 706 static void sdma_v2_4_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
 707                                    uint64_t value, unsigned count,
 708                                    uint32_t incr)
 709 {
 710         unsigned ndw = count * 2;
 711
 712         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 713                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 714         ib->ptr[ib->length_dw++] = pe;
 715         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 716         ib->ptr[ib->length_dw++] = ndw;
 717         for (; ndw > 0; ndw -= 2) {
 718                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
 719                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 720                 value += incr;
 721         }
 722 }
 723
 724 /**
 725  * sdma_v2_4_vm_set_pte_pde - update the page tables using sDMA
 726  *
 727  * @ib: indirect buffer to fill with commands
 728  * @pe: addr of the page entry
 729  * @addr: dst addr to write into pe
 730  * @count: number of page entries to update
 731  * @incr: increase next addr by incr bytes
 732  * @flags: access flags
 733  *
 734  * Update the page tables using sDMA (CIK).
 735  */
 736 static void sdma_v2_4_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
 737                                      uint64_t addr, unsigned count,
 738                                      uint32_t incr, uint64_t flags)
 739 {
 740         /* for physically contiguous pages (vram) */
 741         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
 742         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
 743         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 744         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
 745         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
 746         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
 747         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 748         ib->ptr[ib->length_dw++] = incr; /* increment size */
 749         ib->ptr[ib->length_dw++] = 0;
 750         ib->ptr[ib->length_dw++] = count; /* number of entries */
 751 }
 752
 753 /**
 754  * sdma_v2_4_ring_pad_ib - pad the IB to the required number of dw
 755  *
 756  * @ib: indirect buffer to fill with padding
 757  *
 758  */
 759 static void sdma_v2_4_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
 760 {
 761         struct amdgpu_sdma_instance *sdma = amdgpu_get_sdma_instance(ring);
 762         u32 pad_count;
 763         int i;
 764
 765         pad_count = (8 - (ib->length_dw & 0x7)) % 8;
 766         for (i = 0; i < pad_count; i++)
 767                 if (sdma && sdma->burst_nop && (i == 0))
 768                         ib->ptr[ib->length_dw++] =
 769                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
 770                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
 771                 else
 772                         ib->ptr[ib->length_dw++] =
 773                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
 774 }
 775
 776 /**
 777  * sdma_v2_4_ring_emit_pipeline_sync - sync the pipeline
 778  *
 779  * @ring: amdgpu_ring pointer
 780  *
 781  * Make sure all previous operations are completed (CIK).
 782  */
 783 static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 784 {
 785         uint32_t seq = ring->fence_drv.sync_seq;
 786         uint64_t addr = ring->fence_drv.gpu_addr;
 787
 788         /* wait for idle */
 789         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 790                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
 791                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
 792                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
 793         amdgpu_ring_write(ring, addr & 0xfffffffc);
 794         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
 795         amdgpu_ring_write(ring, seq); /* reference */
 796         amdgpu_ring_write(ring, 0xffffffff); /* mask */
 797         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 798                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
 799 }
 800
 801 /**
 802  * sdma_v2_4_ring_emit_vm_flush - cik vm flush using sDMA
 803  *
 804  * @ring: amdgpu_ring pointer
 805  * @vm: amdgpu_vm pointer
 806  *
 807  * Update the page table base and flush the VM TLB
 808  * using sDMA (VI).
 809  */
 810 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
 811                                          unsigned vmid, uint64_t pd_addr)
 812 {
 813         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
 814
 815         /* wait for flush */
 816         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 817                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
 818                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
 819         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
 820         amdgpu_ring_write(ring, 0);
 821         amdgpu_ring_write(ring, 0); /* reference */
 822         amdgpu_ring_write(ring, 0); /* mask */
 823         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 824                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 825 }
 826
 827 static void sdma_v2_4_ring_emit_wreg(struct amdgpu_ring *ring,
 828                                      uint32_t reg, uint32_t val)
 829 {
 830         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
 831                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
 832         amdgpu_ring_write(ring, reg);
 833         amdgpu_ring_write(ring, val);
 834 }
 835
 836 static int sdma_v2_4_early_init(void *handle)
 837 {
 838         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 839
 840         adev->sdma.num_instances = SDMA_MAX_INSTANCE;
 841
 842         sdma_v2_4_set_ring_funcs(adev);
 843         sdma_v2_4_set_buffer_funcs(adev);
 844         sdma_v2_4_set_vm_pte_funcs(adev);
 845         sdma_v2_4_set_irq_funcs(adev);
 846
 847         return 0;
 848 }
 849
 850 static int sdma_v2_4_sw_init(void *handle)
 851 {
 852         struct amdgpu_ring *ring;
 853         int r, i;
 854         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 855
 856         /* SDMA trap event */
 857         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP,
 858                               &adev->sdma.trap_irq);
 859         if (r)
 860                 return r;
 861
 862         /* SDMA Privileged inst */
 863         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241,
 864                               &adev->sdma.illegal_inst_irq);
 865         if (r)
 866                 return r;
 867
 868         /* SDMA Privileged inst */
 869         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE,
 870                               &adev->sdma.illegal_inst_irq);
 871         if (r)
 872                 return r;
 873
 874         r = sdma_v2_4_init_microcode(adev);
 875         if (r) {
 876                 DRM_ERROR("Failed to load sdma firmware!\n");
 877                 return r;
 878         }
 879
 880         for (i = 0; i < adev->sdma.num_instances; i++) {
 881                 ring = &adev->sdma.instance[i].ring;
 882                 ring->ring_obj = NULL;
 883                 ring->use_doorbell = false;
 884                 sprintf(ring->name, "sdma%d", i);
 885                 r = amdgpu_ring_init(adev, ring, 1024,
 886                                      &adev->sdma.trap_irq,
 887                                      (i == 0) ?
 888                                      AMDGPU_SDMA_IRQ_TRAP0 :
 889                                      AMDGPU_SDMA_IRQ_TRAP1);
 890                 if (r)
 891                         return r;
 892         }
 893
 894         return r;
 895 }
 896
 897 static int sdma_v2_4_sw_fini(void *handle)
 898 {
 899         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 900         int i;
 901
 902         for (i = 0; i < adev->sdma.num_instances; i++)
 903                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
 904
 905         sdma_v2_4_free_microcode(adev);
 906         return 0;
 907 }
 908
 909 static int sdma_v2_4_hw_init(void *handle)
 910 {
 911         int r;
 912         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 913
 914         sdma_v2_4_init_golden_registers(adev);
 915
 916         r = sdma_v2_4_start(adev);
 917         if (r)
 918                 return r;
 919
 920         return r;
 921 }
 922
 923 static int sdma_v2_4_hw_fini(void *handle)
 924 {
 925         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 926
 927         sdma_v2_4_enable(adev, false);
 928
 929         return 0;
 930 }
 931
 932 static int sdma_v2_4_suspend(void *handle)
 933 {
 934         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 935
 936         return sdma_v2_4_hw_fini(adev);
 937 }
 938
 939 static int sdma_v2_4_resume(void *handle)
 940 {
 941         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 942
 943         return sdma_v2_4_hw_init(adev);
 944 }
 945
 946 static bool sdma_v2_4_is_idle(void *handle)
 947 {
 948         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 949         u32 tmp = RREG32(mmSRBM_STATUS2);
 950
 951         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
 952                    SRBM_STATUS2__SDMA1_BUSY_MASK))
 953             return false;
 954
 955         return true;
 956 }
 957
 958 static int sdma_v2_4_wait_for_idle(void *handle)
 959 {
 960         unsigned i;
 961         u32 tmp;
 962         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 963
 964         for (i = 0; i < adev->usec_timeout; i++) {
 965                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
 966                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
 967
 968                 if (!tmp)
 969                         return 0;
 970                 udelay(1);
 971         }
 972         return -ETIMEDOUT;
 973 }
 974
 975 static int sdma_v2_4_soft_reset(void *handle)
 976 {
 977         u32 srbm_soft_reset = 0;
 978         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 979         u32 tmp = RREG32(mmSRBM_STATUS2);
 980
 981         if (tmp & SRBM_STATUS2__SDMA_BUSY_MASK) {
 982                 /* sdma0 */
 983                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET);
 984                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
 985                 WREG32(mmSDMA0_F32_CNTL + SDMA0_REGISTER_OFFSET, tmp);
 986                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
 987         }
 988         if (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK) {
 989                 /* sdma1 */
 990                 tmp = RREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET);
 991                 tmp = REG_SET_FIELD(tmp, SDMA0_F32_CNTL, HALT, 0);
 992                 WREG32(mmSDMA0_F32_CNTL + SDMA1_REGISTER_OFFSET, tmp);
 993                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
 994         }
 995
 996         if (srbm_soft_reset) {
 997                 tmp = RREG32(mmSRBM_SOFT_RESET);
 998                 tmp |= srbm_soft_reset;
 999                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1000                 WREG32(mmSRBM_SOFT_RESET, tmp);
1001                 tmp = RREG32(mmSRBM_SOFT_RESET);
1002
1003                 udelay(50);
1004
1005                 tmp &= ~srbm_soft_reset;
1006                 WREG32(mmSRBM_SOFT_RESET, tmp);
1007                 tmp = RREG32(mmSRBM_SOFT_RESET);
1008
1009                 /* Wait a little for things to settle down */
1010                 udelay(50);
1011         }
1012
1013         return 0;
1014 }
1015
1016 static int sdma_v2_4_set_trap_irq_state(struct amdgpu_device *adev,
1017                                         struct amdgpu_irq_src *src,
1018                                         unsigned type,
1019                                         enum amdgpu_interrupt_state state)
1020 {
1021         u32 sdma_cntl;
1022
1023         switch (type) {
1024         case AMDGPU_SDMA_IRQ_TRAP0:
1025                 switch (state) {
1026                 case AMDGPU_IRQ_STATE_DISABLE:
1027                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1028                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1029                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1030                         break;
1031                 case AMDGPU_IRQ_STATE_ENABLE:
1032                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1033                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1034                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1035                         break;
1036                 default:
1037                         break;
1038                 }
1039                 break;
1040         case AMDGPU_SDMA_IRQ_TRAP1:
1041                 switch (state) {
1042                 case AMDGPU_IRQ_STATE_DISABLE:
1043                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1044                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1045                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1046                         break;
1047                 case AMDGPU_IRQ_STATE_ENABLE:
1048                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1049                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1050                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1051                         break;
1052                 default:
1053                         break;
1054                 }
1055                 break;
1056         default:
1057                 break;
1058         }
1059         return 0;
1060 }
1061
1062 static int sdma_v2_4_process_trap_irq(struct amdgpu_device *adev,
1063                                       struct amdgpu_irq_src *source,
1064                                       struct amdgpu_iv_entry *entry)
1065 {
1066         u8 instance_id, queue_id;
1067
1068         instance_id = (entry->ring_id & 0x3) >> 0;
1069         queue_id = (entry->ring_id & 0xc) >> 2;
1070         DRM_DEBUG("IH: SDMA trap\n");
1071         switch (instance_id) {
1072         case 0:
1073                 switch (queue_id) {
1074                 case 0:
1075                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1076                         break;
1077                 case 1:
1078                         /* XXX compute */
1079                         break;
1080                 case 2:
1081                         /* XXX compute */
1082                         break;
1083                 }
1084                 break;
1085         case 1:
1086                 switch (queue_id) {
1087                 case 0:
1088                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1089                         break;
1090                 case 1:
1091                         /* XXX compute */
1092                         break;
1093                 case 2:
1094                         /* XXX compute */
1095                         break;
1096                 }
1097                 break;
1098         }
1099         return 0;
1100 }
1101
1102 static int sdma_v2_4_process_illegal_inst_irq(struct amdgpu_device *adev,
1103                                               struct amdgpu_irq_src *source,
1104                                               struct amdgpu_iv_entry *entry)
1105 {
1106         u8 instance_id, queue_id;
1107
1108         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1109         instance_id = (entry->ring_id & 0x3) >> 0;
1110         queue_id = (entry->ring_id & 0xc) >> 2;
1111
1112         if (instance_id <= 1 && queue_id == 0)
1113                 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched);
1114         return 0;
1115 }
1116
1117 static int sdma_v2_4_set_clockgating_state(void *handle,
1118                                           enum amd_clockgating_state state)
1119 {
1120         /* XXX handled via the smc on VI */
1121         return 0;
1122 }
1123
1124 static int sdma_v2_4_set_powergating_state(void *handle,
1125                                           enum amd_powergating_state state)
1126 {
1127         return 0;
1128 }
1129
1130 static const struct amd_ip_funcs sdma_v2_4_ip_funcs = {
1131         .name = "sdma_v2_4",
1132         .early_init = sdma_v2_4_early_init,
1133         .late_init = NULL,
1134         .sw_init = sdma_v2_4_sw_init,
1135         .sw_fini = sdma_v2_4_sw_fini,
1136         .hw_init = sdma_v2_4_hw_init,
1137         .hw_fini = sdma_v2_4_hw_fini,
1138         .suspend = sdma_v2_4_suspend,
1139         .resume = sdma_v2_4_resume,
1140         .is_idle = sdma_v2_4_is_idle,
1141         .wait_for_idle = sdma_v2_4_wait_for_idle,
1142         .soft_reset = sdma_v2_4_soft_reset,
1143         .set_clockgating_state = sdma_v2_4_set_clockgating_state,
1144         .set_powergating_state = sdma_v2_4_set_powergating_state,
1145 };
1146
1147 static const struct amdgpu_ring_funcs sdma_v2_4_ring_funcs = {
1148         .type = AMDGPU_RING_TYPE_SDMA,
1149         .align_mask = 0xf,
1150         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1151         .support_64bit_ptrs = false,
1152         .get_rptr = sdma_v2_4_ring_get_rptr,
1153         .get_wptr = sdma_v2_4_ring_get_wptr,
1154         .set_wptr = sdma_v2_4_ring_set_wptr,
1155         .emit_frame_size =
1156                 6 + /* sdma_v2_4_ring_emit_hdp_flush */
1157                 3 + /* hdp invalidate */
1158                 6 + /* sdma_v2_4_ring_emit_pipeline_sync */
1159                 VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v2_4_ring_emit_vm_flush */
1160                 10 + 10 + 10, /* sdma_v2_4_ring_emit_fence x3 for user fence, vm fence */
1161         .emit_ib_size = 7 + 6, /* sdma_v2_4_ring_emit_ib */
1162         .emit_ib = sdma_v2_4_ring_emit_ib,
1163         .emit_fence = sdma_v2_4_ring_emit_fence,
1164         .emit_pipeline_sync = sdma_v2_4_ring_emit_pipeline_sync,
1165         .emit_vm_flush = sdma_v2_4_ring_emit_vm_flush,
1166         .emit_hdp_flush = sdma_v2_4_ring_emit_hdp_flush,
1167         .test_ring = sdma_v2_4_ring_test_ring,
1168         .test_ib = sdma_v2_4_ring_test_ib,
1169         .insert_nop = sdma_v2_4_ring_insert_nop,
1170         .pad_ib = sdma_v2_4_ring_pad_ib,
1171         .emit_wreg = sdma_v2_4_ring_emit_wreg,
1172 };
1173
1174 static void sdma_v2_4_set_ring_funcs(struct amdgpu_device *adev)
1175 {
1176         int i;
1177
1178         for (i = 0; i < adev->sdma.num_instances; i++) {
1179                 adev->sdma.instance[i].ring.funcs = &sdma_v2_4_ring_funcs;
1180                 adev->sdma.instance[i].ring.me = i;
1181         }
1182 }
1183
1184 static const struct amdgpu_irq_src_funcs sdma_v2_4_trap_irq_funcs = {
1185         .set = sdma_v2_4_set_trap_irq_state,
1186         .process = sdma_v2_4_process_trap_irq,
1187 };
1188
1189 static const struct amdgpu_irq_src_funcs sdma_v2_4_illegal_inst_irq_funcs = {
1190         .process = sdma_v2_4_process_illegal_inst_irq,
1191 };
1192
1193 static void sdma_v2_4_set_irq_funcs(struct amdgpu_device *adev)
1194 {
1195         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1196         adev->sdma.trap_irq.funcs = &sdma_v2_4_trap_irq_funcs;
1197         adev->sdma.illegal_inst_irq.funcs = &sdma_v2_4_illegal_inst_irq_funcs;
1198 }
1199
1200 /**
1201  * sdma_v2_4_emit_copy_buffer - copy buffer using the sDMA engine
1202  *
1203  * @ring: amdgpu_ring structure holding ring information
1204  * @src_offset: src GPU address
1205  * @dst_offset: dst GPU address
1206  * @byte_count: number of bytes to xfer
1207  *
1208  * Copy GPU buffers using the DMA engine (VI).
1209  * Used by the amdgpu ttm implementation to move pages if
1210  * registered as the asic copy callback.
1211  */
1212 static void sdma_v2_4_emit_copy_buffer(struct amdgpu_ib *ib,
1213                                        uint64_t src_offset,
1214                                        uint64_t dst_offset,
1215                                        uint32_t byte_count)
1216 {
1217         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1218                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1219         ib->ptr[ib->length_dw++] = byte_count;
1220         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1221         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1222         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1223         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1224         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1225 }
1226
1227 /**
1228  * sdma_v2_4_emit_fill_buffer - fill buffer using the sDMA engine
1229  *
1230  * @ring: amdgpu_ring structure holding ring information
1231  * @src_data: value to write to buffer
1232  * @dst_offset: dst GPU address
1233  * @byte_count: number of bytes to xfer
1234  *
1235  * Fill GPU buffers using the DMA engine (VI).
1236  */
1237 static void sdma_v2_4_emit_fill_buffer(struct amdgpu_ib *ib,
1238                                        uint32_t src_data,
1239                                        uint64_t dst_offset,
1240                                        uint32_t byte_count)
1241 {
1242         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1243         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1244         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1245         ib->ptr[ib->length_dw++] = src_data;
1246         ib->ptr[ib->length_dw++] = byte_count;
1247 }
1248
1249 static const struct amdgpu_buffer_funcs sdma_v2_4_buffer_funcs = {
1250         .copy_max_bytes = 0x1fffff,
1251         .copy_num_dw = 7,
1252         .emit_copy_buffer = sdma_v2_4_emit_copy_buffer,
1253
1254         .fill_max_bytes = 0x1fffff,
1255         .fill_num_dw = 7,
1256         .emit_fill_buffer = sdma_v2_4_emit_fill_buffer,
1257 };
1258
1259 static void sdma_v2_4_set_buffer_funcs(struct amdgpu_device *adev)
1260 {
1261         adev->mman.buffer_funcs = &sdma_v2_4_buffer_funcs;
1262         adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1263 }
1264
1265 static const struct amdgpu_vm_pte_funcs sdma_v2_4_vm_pte_funcs = {
1266         .copy_pte_num_dw = 7,
1267         .copy_pte = sdma_v2_4_vm_copy_pte,
1268
1269         .write_pte = sdma_v2_4_vm_write_pte,
1270         .set_pte_pde = sdma_v2_4_vm_set_pte_pde,
1271 };
1272
1273 static void sdma_v2_4_set_vm_pte_funcs(struct amdgpu_device *adev)
1274 {
1275         struct drm_gpu_scheduler *sched;
1276         unsigned i;
1277
1278         adev->vm_manager.vm_pte_funcs = &sdma_v2_4_vm_pte_funcs;
1279         for (i = 0; i < adev->sdma.num_instances; i++) {
1280                 sched = &adev->sdma.instance[i].ring.sched;
1281                 adev->vm_manager.vm_pte_rqs[i] =
1282                         &sched->sched_rq[DRM_SCHED_PRIORITY_KERNEL];
1283         }
1284         adev->vm_manager.vm_pte_num_rqs = adev->sdma.num_instances;
1285 }
1286
1287 const struct amdgpu_ip_block_version sdma_v2_4_ip_block =
1288 {
1289         .type = AMD_IP_BLOCK_TYPE_SDMA,
1290         .major = 2,
1291         .minor = 4,
1292         .rev = 0,
1293         .funcs = &sdma_v2_4_ip_funcs,
1294 };