drivers/misc/cardreader/rts5227.c

   1 // SPDX-License-Identifier: GPL-2.0-or-later
   2 /* Driver for Realtek PCI-Express card reader
   3  *
   4  * Copyright(c) 2009-2013 Realtek Semiconductor Corp. All rights reserved.
   5  *
   6  * Author:
   7  *   Wei WANG <[email protected]>
   8  *   Roger Tseng <[email protected]>
   9  */
  10
  11 #include <linux/module.h>
  12 #include <linux/delay.h>
  13 #include <linux/rtsx_pci.h>
  14
  15 #include "rtsx_pcr.h"
  16
  17 static u8 rts5227_get_ic_version(struct rtsx_pcr *pcr)
  18 {
  19         u8 val;
  20
  21         rtsx_pci_read_register(pcr, DUMMY_REG_RESET_0, &val);
  22         return val & 0x0F;
  23 }
  24
  25 static void rts5227_fill_driving(struct rtsx_pcr *pcr, u8 voltage)
  26 {
  27         u8 driving_3v3[4][3] = {
  28                 {0x13, 0x13, 0x13},
  29                 {0x96, 0x96, 0x96},
  30                 {0x7F, 0x7F, 0x7F},
  31                 {0x96, 0x96, 0x96},
  32         };
  33         u8 driving_1v8[4][3] = {
  34                 {0x99, 0x99, 0x99},
  35                 {0xAA, 0xAA, 0xAA},
  36                 {0xFE, 0xFE, 0xFE},
  37                 {0xB3, 0xB3, 0xB3},
  38         };
  39         u8 (*driving)[3], drive_sel;
  40
  41         if (voltage == OUTPUT_3V3) {
  42                 driving = driving_3v3;
  43                 drive_sel = pcr->sd30_drive_sel_3v3;
  44         } else {
  45                 driving = driving_1v8;
  46                 drive_sel = pcr->sd30_drive_sel_1v8;
  47         }
  48
  49         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CLK_DRIVE_SEL,
  50                         0xFF, driving[drive_sel][0]);
  51         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_CMD_DRIVE_SEL,
  52                         0xFF, driving[drive_sel][1]);
  53         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, SD30_DAT_DRIVE_SEL,
  54                         0xFF, driving[drive_sel][2]);
  55 }
  56
  57 static void rts5227_fetch_vendor_settings(struct rtsx_pcr *pcr)
  58 {
  59         struct pci_dev *pdev = pcr->pci;
  60         u32 reg;
  61
  62         pci_read_config_dword(pdev, PCR_SETTING_REG1, &reg);
  63         pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG1, reg);
  64
  65         if (!rtsx_vendor_setting_valid(reg))
  66                 return;
  67
  68         pcr->aspm_en = rtsx_reg_to_aspm(reg);
  69         pcr->sd30_drive_sel_1v8 = rtsx_reg_to_sd30_drive_sel_1v8(reg);
  70         pcr->card_drive_sel &= 0x3F;
  71         pcr->card_drive_sel |= rtsx_reg_to_card_drive_sel(reg);
  72
  73         pci_read_config_dword(pdev, PCR_SETTING_REG2, &reg);
  74         pcr_dbg(pcr, "Cfg 0x%x: 0x%x\n", PCR_SETTING_REG2, reg);
  75         if (CHK_PCI_PID(pcr, 0x522A))
  76                 pcr->rtd3_en = rtsx_reg_to_rtd3(reg);
  77         if (rtsx_check_mmc_support(reg))
  78                 pcr->extra_caps |= EXTRA_CAPS_NO_MMC;
  79         pcr->sd30_drive_sel_3v3 = rtsx_reg_to_sd30_drive_sel_3v3(reg);
  80         if (rtsx_reg_check_reverse_socket(reg))
  81                 pcr->flags |= PCR_REVERSE_SOCKET;
  82 }
  83
  84 static void rts5227_init_from_cfg(struct rtsx_pcr *pcr)
  85 {
  86         struct pci_dev *pdev = pcr->pci;
  87         int l1ss;
  88         u32 lval;
  89         struct rtsx_cr_option *option = &pcr->option;
  90
  91         l1ss = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_L1SS);
  92         if (!l1ss)
  93                 return;
  94
  95         pci_read_config_dword(pdev, l1ss + PCI_L1SS_CTL1, &lval);
  96
  97         if (CHK_PCI_PID(pcr, 0x522A)) {
  98                 if (0 == (lval & 0x0F))
  99                         rtsx_pci_enable_oobs_polling(pcr);
 100                 else
 101                         rtsx_pci_disable_oobs_polling(pcr);
 102         }
 103
 104         if (lval & PCI_L1SS_CTL1_ASPM_L1_1)
 105                 rtsx_set_dev_flag(pcr, ASPM_L1_1_EN);
 106         else
 107                 rtsx_clear_dev_flag(pcr, ASPM_L1_1_EN);
 108
 109         if (lval & PCI_L1SS_CTL1_ASPM_L1_2)
 110                 rtsx_set_dev_flag(pcr, ASPM_L1_2_EN);
 111         else
 112                 rtsx_clear_dev_flag(pcr, ASPM_L1_2_EN);
 113
 114         if (lval & PCI_L1SS_CTL1_PCIPM_L1_1)
 115                 rtsx_set_dev_flag(pcr, PM_L1_1_EN);
 116         else
 117                 rtsx_clear_dev_flag(pcr, PM_L1_1_EN);
 118
 119         if (lval & PCI_L1SS_CTL1_PCIPM_L1_2)
 120                 rtsx_set_dev_flag(pcr, PM_L1_2_EN);
 121         else
 122                 rtsx_clear_dev_flag(pcr, PM_L1_2_EN);
 123
 124         if (option->ltr_en) {
 125                 u16 val;
 126
 127                 pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &val);
 128                 if (val & PCI_EXP_DEVCTL2_LTR_EN) {
 129                         option->ltr_enabled = true;
 130                         option->ltr_active = true;
 131                         rtsx_set_ltr_latency(pcr, option->ltr_active_latency);
 132                 } else {
 133                         option->ltr_enabled = false;
 134                 }
 135         }
 136
 137         if (rtsx_check_dev_flag(pcr, ASPM_L1_1_EN | ASPM_L1_2_EN
 138                                 | PM_L1_1_EN | PM_L1_2_EN))
 139                 option->force_clkreq_0 = false;
 140         else
 141                 option->force_clkreq_0 = true;
 142
 143 }
 144
 145 static int rts5227_extra_init_hw(struct rtsx_pcr *pcr)
 146 {
 147         u16 cap;
 148         struct rtsx_cr_option *option = &pcr->option;
 149
 150         rts5227_init_from_cfg(pcr);
 151         rtsx_pci_init_cmd(pcr);
 152
 153         /* Configure GPIO as output */
 154         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, GPIO_CTL, 0x02, 0x02);
 155         /* Reset ASPM state to default value */
 156         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, ASPM_FORCE_CTL, 0x3F, 0);
 157         /* Switch LDO3318 source from DV33 to card_3v3 */
 158         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x00);
 159         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LDO_PWR_SEL, 0x03, 0x01);
 160         /* LED shine disabled, set initial shine cycle period */
 161         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OLT_LED_CTL, 0x0F, 0x02);
 162         /* Configure LTR */
 163         pcie_capability_read_word(pcr->pci, PCI_EXP_DEVCTL2, &cap);
 164         if (cap & PCI_EXP_DEVCTL2_LTR_EN)
 165                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, LTR_CTL, 0xFF, 0xA3);
 166         /* Configure OBFF */
 167         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, OBFF_CFG, 0x03, 0x03);
 168         /* Configure driving */
 169         rts5227_fill_driving(pcr, OUTPUT_3V3);
 170         /* Configure force_clock_req */
 171         if (pcr->flags & PCR_REVERSE_SOCKET)
 172                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x30);
 173         else
 174                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG, 0x30, 0x00);
 175
 176         if (CHK_PCI_PID(pcr, 0x522A))
 177                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS522A_AUTOLOAD_CFG1,
 178                         CD_RESUME_EN_MASK, CD_RESUME_EN_MASK);
 179
 180         if (pcr->rtd3_en) {
 181                 if (CHK_PCI_PID(pcr, 0x522A)) {
 182                         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS522A_PM_CTRL3, 0x01, 0x01);
 183                         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS522A_PME_FORCE_CTL, 0x30, 0x30);
 184                 } else {
 185                         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x01, 0x01);
 186                         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PME_FORCE_CTL, 0xFF, 0x33);
 187                 }
 188         } else {
 189                 if (CHK_PCI_PID(pcr, 0x522A)) {
 190                         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS522A_PM_CTRL3, 0x01, 0x00);
 191                         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, RTS522A_PME_FORCE_CTL, 0x30, 0x20);
 192                 } else {
 193                         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PME_FORCE_CTL, 0xFF, 0x30);
 194                         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PM_CTRL3, 0x01, 0x00);
 195                 }
 196         }
 197
 198         if (option->force_clkreq_0)
 199                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
 200                                 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_LOW);
 201         else
 202                 rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PETXCFG,
 203                                 FORCE_CLKREQ_DELINK_MASK, FORCE_CLKREQ_HIGH);
 204
 205         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, pcr->reg_pm_ctrl3, 0x10, 0x00);
 206
 207         return rtsx_pci_send_cmd(pcr, 100);
 208 }
 209
 210 static int rts5227_optimize_phy(struct rtsx_pcr *pcr)
 211 {
 212         int err;
 213
 214         err = rtsx_pci_write_register(pcr, PM_CTRL3, D3_DELINK_MODE_EN, 0x00);
 215         if (err < 0)
 216                 return err;
 217
 218         /* Optimize RX sensitivity */
 219         return rtsx_pci_write_phy_register(pcr, 0x00, 0xBA42);
 220 }
 221
 222 static int rts5227_turn_on_led(struct rtsx_pcr *pcr)
 223 {
 224         return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x02);
 225 }
 226
 227 static int rts5227_turn_off_led(struct rtsx_pcr *pcr)
 228 {
 229         return rtsx_pci_write_register(pcr, GPIO_CTL, 0x02, 0x00);
 230 }
 231
 232 static int rts5227_enable_auto_blink(struct rtsx_pcr *pcr)
 233 {
 234         return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x08);
 235 }
 236
 237 static int rts5227_disable_auto_blink(struct rtsx_pcr *pcr)
 238 {
 239         return rtsx_pci_write_register(pcr, OLT_LED_CTL, 0x08, 0x00);
 240 }
 241
 242 static int rts5227_card_power_on(struct rtsx_pcr *pcr, int card)
 243 {
 244         int err;
 245
 246         if (pcr->option.ocp_en)
 247                 rtsx_pci_enable_ocp(pcr);
 248
 249         rtsx_pci_init_cmd(pcr);
 250         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
 251                         SD_POWER_MASK, SD_PARTIAL_POWER_ON);
 252
 253         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
 254                         LDO3318_PWR_MASK, 0x02);
 255
 256         err = rtsx_pci_send_cmd(pcr, 100);
 257         if (err < 0)
 258                 return err;
 259
 260         /* To avoid too large in-rush current */
 261         msleep(20);
 262         rtsx_pci_init_cmd(pcr);
 263         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_PWR_CTL,
 264                         SD_POWER_MASK, SD_POWER_ON);
 265
 266         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, PWR_GATE_CTRL,
 267                         LDO3318_PWR_MASK, 0x06);
 268
 269         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE,
 270                         SD_OUTPUT_EN, SD_OUTPUT_EN);
 271         rtsx_pci_add_cmd(pcr, WRITE_REG_CMD, CARD_OE,
 272                         MS_OUTPUT_EN, MS_OUTPUT_EN);
 273         return rtsx_pci_send_cmd(pcr, 100);
 274 }
 275
 276 static int rts5227_card_power_off(struct rtsx_pcr *pcr, int card)
 277 {
 278         if (pcr->option.ocp_en)
 279                 rtsx_pci_disable_ocp(pcr);
 280
 281         rtsx_pci_write_register(pcr, CARD_PWR_CTL, SD_POWER_MASK |
 282                         PMOS_STRG_MASK, SD_POWER_OFF | PMOS_STRG_400mA);
 283         rtsx_pci_write_register(pcr, PWR_GATE_CTRL, LDO3318_PWR_MASK, 0X00);
 284
 285         return 0;
 286 }
 287
 288 static int rts5227_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
 289 {
 290         int err;
 291
 292         if (voltage == OUTPUT_3V3) {
 293                 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4FC0 | 0x24);
 294                 if (err < 0)
 295                         return err;
 296         } else if (voltage == OUTPUT_1V8) {
 297                 err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
 298                 if (err < 0)
 299                         return err;
 300                 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x4C80 | 0x24);
 301                 if (err < 0)
 302                         return err;
 303         } else {
 304                 return -EINVAL;
 305         }
 306
 307         /* set pad drive */
 308         rtsx_pci_init_cmd(pcr);
 309         rts5227_fill_driving(pcr, voltage);
 310         return rtsx_pci_send_cmd(pcr, 100);
 311 }
 312
 313 static const struct pcr_ops rts5227_pcr_ops = {
 314         .fetch_vendor_settings = rts5227_fetch_vendor_settings,
 315         .extra_init_hw = rts5227_extra_init_hw,
 316         .optimize_phy = rts5227_optimize_phy,
 317         .turn_on_led = rts5227_turn_on_led,
 318         .turn_off_led = rts5227_turn_off_led,
 319         .enable_auto_blink = rts5227_enable_auto_blink,
 320         .disable_auto_blink = rts5227_disable_auto_blink,
 321         .card_power_on = rts5227_card_power_on,
 322         .card_power_off = rts5227_card_power_off,
 323         .switch_output_voltage = rts5227_switch_output_voltage,
 324         .cd_deglitch = NULL,
 325         .conv_clk_and_div_n = NULL,
 326 };
 327
 328 /* SD Pull Control Enable:
 329  *     SD_DAT[3:0] ==> pull up
 330  *     SD_CD       ==> pull up
 331  *     SD_WP       ==> pull up
 332  *     SD_CMD      ==> pull up
 333  *     SD_CLK      ==> pull down
 334  */
 335 static const u32 rts5227_sd_pull_ctl_enable_tbl[] = {
 336         RTSX_REG_PAIR(CARD_PULL_CTL2, 0xAA),
 337         RTSX_REG_PAIR(CARD_PULL_CTL3, 0xE9),
 338         0,
 339 };
 340
 341 /* SD Pull Control Disable:
 342  *     SD_DAT[3:0] ==> pull down
 343  *     SD_CD       ==> pull up
 344  *     SD_WP       ==> pull down
 345  *     SD_CMD      ==> pull down
 346  *     SD_CLK      ==> pull down
 347  */
 348 static const u32 rts5227_sd_pull_ctl_disable_tbl[] = {
 349         RTSX_REG_PAIR(CARD_PULL_CTL2, 0x55),
 350         RTSX_REG_PAIR(CARD_PULL_CTL3, 0xD5),
 351         0,
 352 };
 353
 354 /* MS Pull Control Enable:
 355  *     MS CD       ==> pull up
 356  *     others      ==> pull down
 357  */
 358 static const u32 rts5227_ms_pull_ctl_enable_tbl[] = {
 359         RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
 360         RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
 361         0,
 362 };
 363
 364 /* MS Pull Control Disable:
 365  *     MS CD       ==> pull up
 366  *     others      ==> pull down
 367  */
 368 static const u32 rts5227_ms_pull_ctl_disable_tbl[] = {
 369         RTSX_REG_PAIR(CARD_PULL_CTL5, 0x55),
 370         RTSX_REG_PAIR(CARD_PULL_CTL6, 0x15),
 371         0,
 372 };
 373
 374 void rts5227_init_params(struct rtsx_pcr *pcr)
 375 {
 376         pcr->extra_caps = EXTRA_CAPS_SD_SDR50 | EXTRA_CAPS_SD_SDR104;
 377         pcr->num_slots = 2;
 378         pcr->ops = &rts5227_pcr_ops;
 379
 380         pcr->flags = 0;
 381         pcr->card_drive_sel = RTSX_CARD_DRIVE_DEFAULT;
 382         pcr->sd30_drive_sel_1v8 = CFG_DRIVER_TYPE_B;
 383         pcr->sd30_drive_sel_3v3 = CFG_DRIVER_TYPE_B;
 384         pcr->aspm_en = ASPM_L1_EN;
 385         pcr->aspm_mode = ASPM_MODE_CFG;
 386         pcr->tx_initial_phase = SET_CLOCK_PHASE(27, 27, 15);
 387         pcr->rx_initial_phase = SET_CLOCK_PHASE(30, 7, 7);
 388
 389         pcr->ic_version = rts5227_get_ic_version(pcr);
 390         pcr->sd_pull_ctl_enable_tbl = rts5227_sd_pull_ctl_enable_tbl;
 391         pcr->sd_pull_ctl_disable_tbl = rts5227_sd_pull_ctl_disable_tbl;
 392         pcr->ms_pull_ctl_enable_tbl = rts5227_ms_pull_ctl_enable_tbl;
 393         pcr->ms_pull_ctl_disable_tbl = rts5227_ms_pull_ctl_disable_tbl;
 394
 395         pcr->reg_pm_ctrl3 = PM_CTRL3;
 396 }
 397
 398 static int rts522a_optimize_phy(struct rtsx_pcr *pcr)
 399 {
 400         int err;
 401
 402         err = rtsx_pci_write_register(pcr, RTS522A_PM_CTRL3, D3_DELINK_MODE_EN,
 403                 0x00);
 404         if (err < 0)
 405                 return err;
 406
 407         if (is_version(pcr, 0x522A, IC_VER_A)) {
 408                 err = rtsx_pci_write_phy_register(pcr, PHY_RCR2,
 409                         PHY_RCR2_INIT_27S);
 410                 if (err)
 411                         return err;
 412
 413                 rtsx_pci_write_phy_register(pcr, PHY_RCR1, PHY_RCR1_INIT_27S);
 414                 rtsx_pci_write_phy_register(pcr, PHY_FLD0, PHY_FLD0_INIT_27S);
 415                 rtsx_pci_write_phy_register(pcr, PHY_FLD3, PHY_FLD3_INIT_27S);
 416                 rtsx_pci_write_phy_register(pcr, PHY_FLD4, PHY_FLD4_INIT_27S);
 417         }
 418
 419         return 0;
 420 }
 421
 422 static int rts522a_extra_init_hw(struct rtsx_pcr *pcr)
 423 {
 424         rts5227_extra_init_hw(pcr);
 425
 426         /* Power down OCP for power consumption */
 427         if (!pcr->card_exist)
 428                 rtsx_pci_write_register(pcr, FPDCTL, OC_POWER_DOWN,
 429                                 OC_POWER_DOWN);
 430
 431         rtsx_pci_write_register(pcr, FUNC_FORCE_CTL, FUNC_FORCE_UPME_XMT_DBG,
 432                 FUNC_FORCE_UPME_XMT_DBG);
 433         rtsx_pci_write_register(pcr, PCLK_CTL, 0x04, 0x04);
 434         rtsx_pci_write_register(pcr, PM_EVENT_DEBUG, PME_DEBUG_0, PME_DEBUG_0);
 435         rtsx_pci_write_register(pcr, PM_CLK_FORCE_CTL, 0xFF, 0x11);
 436
 437         return 0;
 438 }
 439
 440 static int rts522a_switch_output_voltage(struct rtsx_pcr *pcr, u8 voltage)
 441 {
 442         int err;
 443
 444         if (voltage == OUTPUT_3V3) {
 445                 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x57E4);
 446                 if (err < 0)
 447                         return err;
 448         } else if (voltage == OUTPUT_1V8) {
 449                 err = rtsx_pci_write_phy_register(pcr, 0x11, 0x3C02);
 450                 if (err < 0)
 451                         return err;
 452                 err = rtsx_pci_write_phy_register(pcr, 0x08, 0x54A4);
 453                 if (err < 0)
 454                         return err;
 455         } else {
 456                 return -EINVAL;
 457         }
 458
 459         /* set pad drive */
 460         rtsx_pci_init_cmd(pcr);
 461         rts5227_fill_driving(pcr, voltage);
 462         return rtsx_pci_send_cmd(pcr, 100);
 463 }
 464
 465 static void rts522a_force_power_down(struct rtsx_pcr *pcr, u8 pm_state, bool runtime)
 466 {
 467         /* Set relink_time to 0 */
 468         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 1, MASK_8_BIT_DEF, 0);
 469         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 2, MASK_8_BIT_DEF, 0);
 470         rtsx_pci_write_register(pcr, AUTOLOAD_CFG_BASE + 3,
 471                                 RELINK_TIME_MASK, 0);
 472
 473         rtsx_pci_write_register(pcr, RTS522A_PM_CTRL3,
 474                         D3_DELINK_MODE_EN, D3_DELINK_MODE_EN);
 475
 476         if (!runtime) {
 477                 rtsx_pci_write_register(pcr, RTS522A_AUTOLOAD_CFG1,
 478                                 CD_RESUME_EN_MASK, 0);
 479                 rtsx_pci_write_register(pcr, RTS522A_PM_CTRL3, 0x01, 0x00);
 480                 rtsx_pci_write_register(pcr, RTS522A_PME_FORCE_CTL, 0x30, 0x20);
 481         }
 482
 483         rtsx_pci_write_register(pcr, FPDCTL, ALL_POWER_DOWN, ALL_POWER_DOWN);
 484 }
 485
 486
 487 static void rts522a_set_l1off_cfg_sub_d0(struct rtsx_pcr *pcr, int active)
 488 {
 489         struct rtsx_cr_option *option = &pcr->option;
 490         int aspm_L1_1, aspm_L1_2;
 491         u8 val = 0;
 492
 493         aspm_L1_1 = rtsx_check_dev_flag(pcr, ASPM_L1_1_EN);
 494         aspm_L1_2 = rtsx_check_dev_flag(pcr, ASPM_L1_2_EN);
 495
 496         if (active) {
 497                 /* run, latency: 60us */
 498                 if (aspm_L1_1)
 499                         val = option->ltr_l1off_snooze_sspwrgate;
 500         } else {
 501                 /* l1off, latency: 300us */
 502                 if (aspm_L1_2)
 503                         val = option->ltr_l1off_sspwrgate;
 504         }
 505
 506         rtsx_set_l1off_sub(pcr, val);
 507 }
 508
 509 /* rts522a operations mainly derived from rts5227, except phy/hw init setting.
 510  */
 511 static const struct pcr_ops rts522a_pcr_ops = {
 512         .fetch_vendor_settings = rts5227_fetch_vendor_settings,
 513         .extra_init_hw = rts522a_extra_init_hw,
 514         .optimize_phy = rts522a_optimize_phy,
 515         .turn_on_led = rts5227_turn_on_led,
 516         .turn_off_led = rts5227_turn_off_led,
 517         .enable_auto_blink = rts5227_enable_auto_blink,
 518         .disable_auto_blink = rts5227_disable_auto_blink,
 519         .card_power_on = rts5227_card_power_on,
 520         .card_power_off = rts5227_card_power_off,
 521         .switch_output_voltage = rts522a_switch_output_voltage,
 522         .force_power_down = rts522a_force_power_down,
 523         .cd_deglitch = NULL,
 524         .conv_clk_and_div_n = NULL,
 525         .set_l1off_cfg_sub_d0 = rts522a_set_l1off_cfg_sub_d0,
 526 };
 527
 528 void rts522a_init_params(struct rtsx_pcr *pcr)
 529 {
 530         struct rtsx_cr_option *option = &pcr->option;
 531
 532         rts5227_init_params(pcr);
 533         pcr->ops = &rts522a_pcr_ops;
 534         pcr->aspm_mode = ASPM_MODE_REG;
 535         pcr->tx_initial_phase = SET_CLOCK_PHASE(20, 20, 11);
 536         pcr->reg_pm_ctrl3 = RTS522A_PM_CTRL3;
 537
 538         option->dev_flags = LTR_L1SS_PWR_GATE_EN;
 539         option->ltr_en = true;
 540
 541         /* init latency of active, idle, L1OFF to 60us, 300us, 3ms */
 542         option->ltr_active_latency = LTR_ACTIVE_LATENCY_DEF;
 543         option->ltr_idle_latency = LTR_IDLE_LATENCY_DEF;
 544         option->ltr_l1off_latency = LTR_L1OFF_LATENCY_DEF;
 545         option->l1_snooze_delay = L1_SNOOZE_DELAY_DEF;
 546         option->ltr_l1off_sspwrgate = 0x7F;
 547         option->ltr_l1off_snooze_sspwrgate = 0x78;
 548
 549         pcr->option.ocp_en = 1;
 550         if (pcr->option.ocp_en)
 551                 pcr->hw_param.interrupt_en |= SD_OC_INT_EN;
 552         pcr->hw_param.ocp_glitch = SD_OCP_GLITCH_10M;
 553         pcr->option.sd_800mA_ocp_thd = RTS522A_OCP_THD_800;
 554
 555 }