drivers/i2c/busses/i2c-meson.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * I2C bus driver for Amlogic Meson SoCs
   4  *
   5  * Copyright (C) 2014 Beniamino Galvani <[email protected]>
   6  */
   7
   8 #include <linux/bitfield.h>
   9 #include <linux/clk.h>
  10 #include <linux/completion.h>
  11 #include <linux/i2c.h>
  12 #include <linux/interrupt.h>
  13 #include <linux/io.h>
  14 #include <linux/iopoll.h>
  15 #include <linux/kernel.h>
  16 #include <linux/module.h>
  17 #include <linux/of.h>
  18 #include <linux/of_device.h>
  19 #include <linux/platform_device.h>
  20 #include <linux/types.h>
  21
  22 /* Meson I2C register map */
  23 #define REG_CTRL                0x00
  24 #define REG_SLAVE_ADDR          0x04
  25 #define REG_TOK_LIST0           0x08
  26 #define REG_TOK_LIST1           0x0c
  27 #define REG_TOK_WDATA0          0x10
  28 #define REG_TOK_WDATA1          0x14
  29 #define REG_TOK_RDATA0          0x18
  30 #define REG_TOK_RDATA1          0x1c
  31
  32 /* Control register fields */
  33 #define REG_CTRL_START                  BIT(0)
  34 #define REG_CTRL_ACK_IGNORE             BIT(1)
  35 #define REG_CTRL_STATUS                 BIT(2)
  36 #define REG_CTRL_ERROR                  BIT(3)
  37 #define REG_CTRL_CLKDIV_SHIFT           12
  38 #define REG_CTRL_CLKDIV_MASK            GENMASK(21, REG_CTRL_CLKDIV_SHIFT)
  39 #define REG_CTRL_CLKDIVEXT_SHIFT        28
  40 #define REG_CTRL_CLKDIVEXT_MASK         GENMASK(29, REG_CTRL_CLKDIVEXT_SHIFT)
  41
  42 #define REG_SLV_ADDR_MASK               GENMASK(7, 0)
  43 #define REG_SLV_SDA_FILTER_MASK         GENMASK(10, 8)
  44 #define REG_SLV_SCL_FILTER_MASK         GENMASK(13, 11)
  45 #define REG_SLV_SCL_LOW_SHIFT           16
  46 #define REG_SLV_SCL_LOW_MASK            GENMASK(27, REG_SLV_SCL_LOW_SHIFT)
  47 #define REG_SLV_SCL_LOW_EN              BIT(28)
  48
  49 #define I2C_TIMEOUT_MS          500
  50 #define FILTER_DELAY            15
  51
  52 enum {
  53         TOKEN_END = 0,
  54         TOKEN_START,
  55         TOKEN_SLAVE_ADDR_WRITE,
  56         TOKEN_SLAVE_ADDR_READ,
  57         TOKEN_DATA,
  58         TOKEN_DATA_LAST,
  59         TOKEN_STOP,
  60 };
  61
  62 enum {
  63         STATE_IDLE,
  64         STATE_READ,
  65         STATE_WRITE,
  66 };
  67
  68 /**
  69  * struct meson_i2c - Meson I2C device private data
  70  *
  71  * @adap:       I2C adapter instance
  72  * @dev:        Pointer to device structure
  73  * @regs:       Base address of the device memory mapped registers
  74  * @clk:        Pointer to clock structure
  75  * @msg:        Pointer to the current I2C message
  76  * @state:      Current state in the driver state machine
  77  * @last:       Flag set for the last message in the transfer
  78  * @count:      Number of bytes to be sent/received in current transfer
  79  * @pos:        Current position in the send/receive buffer
  80  * @error:      Flag set when an error is received
  81  * @lock:       To avoid race conditions between irq handler and xfer code
  82  * @done:       Completion used to wait for transfer termination
  83  * @tokens:     Sequence of tokens to be written to the device
  84  * @num_tokens: Number of tokens
  85  * @data:       Pointer to the controller's platform data
  86  */
  87 struct meson_i2c {
  88         struct i2c_adapter      adap;
  89         struct device           *dev;
  90         void __iomem            *regs;
  91         struct clk              *clk;
  92
  93         struct i2c_msg          *msg;
  94         int                     state;
  95         bool                    last;
  96         int                     count;
  97         int                     pos;
  98         int                     error;
  99
 100         spinlock_t              lock;
 101         struct completion       done;
 102         u32                     tokens[2];
 103         int                     num_tokens;
 104
 105         const struct meson_i2c_data *data;
 106 };
 107
 108 struct meson_i2c_data {
 109         void (*set_clk_div)(struct meson_i2c *i2c, unsigned int freq);
 110 };
 111
 112 static void meson_i2c_set_mask(struct meson_i2c *i2c, int reg, u32 mask,
 113                                u32 val)
 114 {
 115         u32 data;
 116
 117         data = readl(i2c->regs + reg);
 118         data &= ~mask;
 119         data |= val & mask;
 120         writel(data, i2c->regs + reg);
 121 }
 122
 123 static void meson_i2c_reset_tokens(struct meson_i2c *i2c)
 124 {
 125         i2c->tokens[0] = 0;
 126         i2c->tokens[1] = 0;
 127         i2c->num_tokens = 0;
 128 }
 129
 130 static void meson_i2c_add_token(struct meson_i2c *i2c, int token)
 131 {
 132         if (i2c->num_tokens < 8)
 133                 i2c->tokens[0] |= (token & 0xf) << (i2c->num_tokens * 4);
 134         else
 135                 i2c->tokens[1] |= (token & 0xf) << ((i2c->num_tokens % 8) * 4);
 136
 137         i2c->num_tokens++;
 138 }
 139
 140 static void meson_gxbb_axg_i2c_set_clk_div(struct meson_i2c *i2c, unsigned int freq)
 141 {
 142         unsigned long clk_rate = clk_get_rate(i2c->clk);
 143         unsigned int div_h, div_l;
 144
 145         /* According to I2C-BUS Spec 2.1, in FAST-MODE, the minimum LOW period is 1.3uS, and
 146          * minimum HIGH is least 0.6us.
 147          * For 400000 freq, the period is 2.5us. To keep within the specs, give 40% of period to
 148          * HIGH and 60% to LOW. This means HIGH at 1.0us and LOW 1.5us.
 149          * The same applies for Fast-mode plus, where LOW is 0.5us and HIGH is 0.26us.
 150          * Duty = H/(H + L) = 2/5
 151          */
 152         if (freq <= I2C_MAX_STANDARD_MODE_FREQ) {
 153                 div_h = DIV_ROUND_UP(clk_rate, freq);
 154                 div_l = DIV_ROUND_UP(div_h, 4);
 155                 div_h = DIV_ROUND_UP(div_h, 2) - FILTER_DELAY;
 156         } else {
 157                 div_h = DIV_ROUND_UP(clk_rate * 2, freq * 5) - FILTER_DELAY;
 158                 div_l = DIV_ROUND_UP(clk_rate * 3, freq * 5 * 2);
 159         }
 160
 161         /* clock divider has 12 bits */
 162         if (div_h > GENMASK(11, 0)) {
 163                 dev_err(i2c->dev, "requested bus frequency too low\n");
 164                 div_h = GENMASK(11, 0);
 165         }
 166         if (div_l > GENMASK(11, 0)) {
 167                 dev_err(i2c->dev, "requested bus frequency too low\n");
 168                 div_l = GENMASK(11, 0);
 169         }
 170
 171         meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIV_MASK,
 172                            FIELD_PREP(REG_CTRL_CLKDIV_MASK, div_h & GENMASK(9, 0)));
 173
 174         meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIVEXT_MASK,
 175                            FIELD_PREP(REG_CTRL_CLKDIVEXT_MASK, div_h >> 10));
 176
 177         /* set SCL low delay */
 178         meson_i2c_set_mask(i2c, REG_SLAVE_ADDR, REG_SLV_SCL_LOW_MASK,
 179                            FIELD_PREP(REG_SLV_SCL_LOW_MASK, div_l));
 180
 181         /* Enable HIGH/LOW mode */
 182         meson_i2c_set_mask(i2c, REG_SLAVE_ADDR, REG_SLV_SCL_LOW_EN, REG_SLV_SCL_LOW_EN);
 183
 184         dev_dbg(i2c->dev, "%s: clk %lu, freq %u, divh %u, divl %u\n", __func__,
 185                 clk_rate, freq, div_h, div_l);
 186 }
 187
 188 static void meson6_i2c_set_clk_div(struct meson_i2c *i2c, unsigned int freq)
 189 {
 190         unsigned long clk_rate = clk_get_rate(i2c->clk);
 191         unsigned int div;
 192
 193         div = DIV_ROUND_UP(clk_rate, freq);
 194         div -= FILTER_DELAY;
 195         div = DIV_ROUND_UP(div, 4);
 196
 197         /* clock divider has 12 bits */
 198         if (div > GENMASK(11, 0)) {
 199                 dev_err(i2c->dev, "requested bus frequency too low\n");
 200                 div = GENMASK(11, 0);
 201         }
 202
 203         meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIV_MASK,
 204                            FIELD_PREP(REG_CTRL_CLKDIV_MASK, div & GENMASK(9, 0)));
 205
 206         meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_CLKDIVEXT_MASK,
 207                            FIELD_PREP(REG_CTRL_CLKDIVEXT_MASK, div >> 10));
 208
 209         /* Disable HIGH/LOW mode */
 210         meson_i2c_set_mask(i2c, REG_SLAVE_ADDR, REG_SLV_SCL_LOW_EN, 0);
 211
 212         dev_dbg(i2c->dev, "%s: clk %lu, freq %u, div %u\n", __func__,
 213                 clk_rate, freq, div);
 214 }
 215
 216 static void meson_i2c_get_data(struct meson_i2c *i2c, char *buf, int len)
 217 {
 218         u32 rdata0, rdata1;
 219         int i;
 220
 221         rdata0 = readl(i2c->regs + REG_TOK_RDATA0);
 222         rdata1 = readl(i2c->regs + REG_TOK_RDATA1);
 223
 224         dev_dbg(i2c->dev, "%s: data %08x %08x len %d\n", __func__,
 225                 rdata0, rdata1, len);
 226
 227         for (i = 0; i < min(4, len); i++)
 228                 *buf++ = (rdata0 >> i * 8) & 0xff;
 229
 230         for (i = 4; i < min(8, len); i++)
 231                 *buf++ = (rdata1 >> (i - 4) * 8) & 0xff;
 232 }
 233
 234 static void meson_i2c_put_data(struct meson_i2c *i2c, char *buf, int len)
 235 {
 236         u32 wdata0 = 0, wdata1 = 0;
 237         int i;
 238
 239         for (i = 0; i < min(4, len); i++)
 240                 wdata0 |= *buf++ << (i * 8);
 241
 242         for (i = 4; i < min(8, len); i++)
 243                 wdata1 |= *buf++ << ((i - 4) * 8);
 244
 245         writel(wdata0, i2c->regs + REG_TOK_WDATA0);
 246         writel(wdata1, i2c->regs + REG_TOK_WDATA1);
 247
 248         dev_dbg(i2c->dev, "%s: data %08x %08x len %d\n", __func__,
 249                 wdata0, wdata1, len);
 250 }
 251
 252 static void meson_i2c_prepare_xfer(struct meson_i2c *i2c)
 253 {
 254         bool write = !(i2c->msg->flags & I2C_M_RD);
 255         int i;
 256
 257         i2c->count = min(i2c->msg->len - i2c->pos, 8);
 258
 259         for (i = 0; i < i2c->count - 1; i++)
 260                 meson_i2c_add_token(i2c, TOKEN_DATA);
 261
 262         if (i2c->count) {
 263                 if (write || i2c->pos + i2c->count < i2c->msg->len)
 264                         meson_i2c_add_token(i2c, TOKEN_DATA);
 265                 else
 266                         meson_i2c_add_token(i2c, TOKEN_DATA_LAST);
 267         }
 268
 269         if (write)
 270                 meson_i2c_put_data(i2c, i2c->msg->buf + i2c->pos, i2c->count);
 271
 272         if (i2c->last && i2c->pos + i2c->count >= i2c->msg->len)
 273                 meson_i2c_add_token(i2c, TOKEN_STOP);
 274
 275         writel(i2c->tokens[0], i2c->regs + REG_TOK_LIST0);
 276         writel(i2c->tokens[1], i2c->regs + REG_TOK_LIST1);
 277 }
 278
 279 static void meson_i2c_transfer_complete(struct meson_i2c *i2c, u32 ctrl)
 280 {
 281         if (ctrl & REG_CTRL_ERROR) {
 282                 /*
 283                  * The bit is set when the IGNORE_NAK bit is cleared
 284                  * and the device didn't respond. In this case, the
 285                  * I2C controller automatically generates a STOP
 286                  * condition.
 287                  */
 288                 dev_dbg(i2c->dev, "error bit set\n");
 289                 i2c->error = -ENXIO;
 290                 i2c->state = STATE_IDLE;
 291         } else {
 292                 if (i2c->state == STATE_READ && i2c->count)
 293                         meson_i2c_get_data(i2c, i2c->msg->buf + i2c->pos,
 294                                            i2c->count);
 295
 296                 i2c->pos += i2c->count;
 297
 298                 if (i2c->pos >= i2c->msg->len)
 299                         i2c->state = STATE_IDLE;
 300         }
 301 }
 302
 303 static irqreturn_t meson_i2c_irq(int irqno, void *dev_id)
 304 {
 305         struct meson_i2c *i2c = dev_id;
 306         unsigned int ctrl;
 307
 308         spin_lock(&i2c->lock);
 309
 310         meson_i2c_reset_tokens(i2c);
 311         meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
 312         ctrl = readl(i2c->regs + REG_CTRL);
 313
 314         dev_dbg(i2c->dev, "irq: state %d, pos %d, count %d, ctrl %08x\n",
 315                 i2c->state, i2c->pos, i2c->count, ctrl);
 316
 317         if (i2c->state == STATE_IDLE) {
 318                 spin_unlock(&i2c->lock);
 319                 return IRQ_NONE;
 320         }
 321
 322         meson_i2c_transfer_complete(i2c, ctrl);
 323
 324         if (i2c->state == STATE_IDLE) {
 325                 complete(&i2c->done);
 326                 goto out;
 327         }
 328
 329         /* Restart the processing */
 330         meson_i2c_prepare_xfer(i2c);
 331         meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, REG_CTRL_START);
 332 out:
 333         spin_unlock(&i2c->lock);
 334
 335         return IRQ_HANDLED;
 336 }
 337
 338 static void meson_i2c_do_start(struct meson_i2c *i2c, struct i2c_msg *msg)
 339 {
 340         int token;
 341
 342         token = (msg->flags & I2C_M_RD) ? TOKEN_SLAVE_ADDR_READ :
 343                 TOKEN_SLAVE_ADDR_WRITE;
 344
 345
 346         meson_i2c_set_mask(i2c, REG_SLAVE_ADDR, REG_SLV_ADDR_MASK,
 347                            FIELD_PREP(REG_SLV_ADDR_MASK, msg->addr << 1));
 348
 349         meson_i2c_add_token(i2c, TOKEN_START);
 350         meson_i2c_add_token(i2c, token);
 351 }
 352
 353 static int meson_i2c_xfer_msg(struct meson_i2c *i2c, struct i2c_msg *msg,
 354                               int last, bool atomic)
 355 {
 356         unsigned long time_left, flags;
 357         int ret = 0;
 358         u32 ctrl;
 359
 360         i2c->msg = msg;
 361         i2c->last = last;
 362         i2c->pos = 0;
 363         i2c->count = 0;
 364         i2c->error = 0;
 365
 366         meson_i2c_reset_tokens(i2c);
 367
 368         flags = (msg->flags & I2C_M_IGNORE_NAK) ? REG_CTRL_ACK_IGNORE : 0;
 369         meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_ACK_IGNORE, flags);
 370
 371         if (!(msg->flags & I2C_M_NOSTART))
 372                 meson_i2c_do_start(i2c, msg);
 373
 374         i2c->state = (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
 375         meson_i2c_prepare_xfer(i2c);
 376
 377         if (!atomic)
 378                 reinit_completion(&i2c->done);
 379
 380         /* Start the transfer */
 381         meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, REG_CTRL_START);
 382
 383         if (atomic) {
 384                 ret = readl_poll_timeout_atomic(i2c->regs + REG_CTRL, ctrl,
 385                                                 !(ctrl & REG_CTRL_STATUS),
 386                                                 10, I2C_TIMEOUT_MS * 1000);
 387         } else {
 388                 time_left = msecs_to_jiffies(I2C_TIMEOUT_MS);
 389                 time_left = wait_for_completion_timeout(&i2c->done, time_left);
 390
 391                 if (!time_left)
 392                         ret = -ETIMEDOUT;
 393         }
 394
 395         /*
 396          * Protect access to i2c struct and registers from interrupt
 397          * handlers triggered by a transfer terminated after the
 398          * timeout period
 399          */
 400         spin_lock_irqsave(&i2c->lock, flags);
 401
 402         if (atomic && !ret)
 403                 meson_i2c_transfer_complete(i2c, ctrl);
 404
 405         /* Abort any active operation */
 406         meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
 407
 408         if (ret)
 409                 i2c->state = STATE_IDLE;
 410
 411         if (i2c->error)
 412                 ret = i2c->error;
 413
 414         spin_unlock_irqrestore(&i2c->lock, flags);
 415
 416         return ret;
 417 }
 418
 419 static int meson_i2c_xfer_messages(struct i2c_adapter *adap,
 420                                    struct i2c_msg *msgs, int num, bool atomic)
 421 {
 422         struct meson_i2c *i2c = adap->algo_data;
 423         int i, ret = 0;
 424
 425         for (i = 0; i < num; i++) {
 426                 ret = meson_i2c_xfer_msg(i2c, msgs + i, i == num - 1, atomic);
 427                 if (ret)
 428                         break;
 429         }
 430
 431         return ret ?: i;
 432 }
 433
 434 static int meson_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs,
 435                           int num)
 436 {
 437         return meson_i2c_xfer_messages(adap, msgs, num, false);
 438 }
 439
 440 static int meson_i2c_xfer_atomic(struct i2c_adapter *adap,
 441                                  struct i2c_msg *msgs, int num)
 442 {
 443         return meson_i2c_xfer_messages(adap, msgs, num, true);
 444 }
 445
 446 static u32 meson_i2c_func(struct i2c_adapter *adap)
 447 {
 448         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 449 }
 450
 451 static const struct i2c_algorithm meson_i2c_algorithm = {
 452         .master_xfer = meson_i2c_xfer,
 453         .master_xfer_atomic = meson_i2c_xfer_atomic,
 454         .functionality = meson_i2c_func,
 455 };
 456
 457 static int meson_i2c_probe(struct platform_device *pdev)
 458 {
 459         struct device_node *np = pdev->dev.of_node;
 460         struct meson_i2c *i2c;
 461         struct i2c_timings timings;
 462         int irq, ret = 0;
 463
 464         i2c = devm_kzalloc(&pdev->dev, sizeof(struct meson_i2c), GFP_KERNEL);
 465         if (!i2c)
 466                 return -ENOMEM;
 467
 468         i2c_parse_fw_timings(&pdev->dev, &timings, true);
 469
 470         i2c->dev = &pdev->dev;
 471         platform_set_drvdata(pdev, i2c);
 472
 473         spin_lock_init(&i2c->lock);
 474         init_completion(&i2c->done);
 475
 476         i2c->data = (const struct meson_i2c_data *)
 477                 of_device_get_match_data(&pdev->dev);
 478
 479         i2c->clk = devm_clk_get(&pdev->dev, NULL);
 480         if (IS_ERR(i2c->clk)) {
 481                 dev_err(&pdev->dev, "can't get device clock\n");
 482                 return PTR_ERR(i2c->clk);
 483         }
 484
 485         i2c->regs = devm_platform_ioremap_resource(pdev, 0);
 486         if (IS_ERR(i2c->regs))
 487                 return PTR_ERR(i2c->regs);
 488
 489         irq = platform_get_irq(pdev, 0);
 490         if (irq < 0)
 491                 return irq;
 492
 493         ret = devm_request_irq(&pdev->dev, irq, meson_i2c_irq, 0, NULL, i2c);
 494         if (ret < 0) {
 495                 dev_err(&pdev->dev, "can't request IRQ\n");
 496                 return ret;
 497         }
 498
 499         ret = clk_prepare_enable(i2c->clk);
 500         if (ret < 0) {
 501                 dev_err(&pdev->dev, "can't prepare clock\n");
 502                 return ret;
 503         }
 504
 505         strscpy(i2c->adap.name, "Meson I2C adapter",
 506                 sizeof(i2c->adap.name));
 507         i2c->adap.owner = THIS_MODULE;
 508         i2c->adap.algo = &meson_i2c_algorithm;
 509         i2c->adap.dev.parent = &pdev->dev;
 510         i2c->adap.dev.of_node = np;
 511         i2c->adap.algo_data = i2c;
 512
 513         /*
 514          * A transfer is triggered when START bit changes from 0 to 1.
 515          * Ensure that the bit is set to 0 after probe
 516          */
 517         meson_i2c_set_mask(i2c, REG_CTRL, REG_CTRL_START, 0);
 518
 519         /* Disable filtering */
 520         meson_i2c_set_mask(i2c, REG_SLAVE_ADDR,
 521                            REG_SLV_SDA_FILTER_MASK | REG_SLV_SCL_FILTER_MASK, 0);
 522
 523         if (!i2c->data->set_clk_div) {
 524                 clk_disable_unprepare(i2c->clk);
 525                 return -EINVAL;
 526         }
 527         i2c->data->set_clk_div(i2c, timings.bus_freq_hz);
 528
 529         ret = i2c_add_adapter(&i2c->adap);
 530         if (ret < 0) {
 531                 clk_disable_unprepare(i2c->clk);
 532                 return ret;
 533         }
 534
 535         return 0;
 536 }
 537
 538 static int meson_i2c_remove(struct platform_device *pdev)
 539 {
 540         struct meson_i2c *i2c = platform_get_drvdata(pdev);
 541
 542         i2c_del_adapter(&i2c->adap);
 543         clk_disable_unprepare(i2c->clk);
 544
 545         return 0;
 546 }
 547
 548 static const struct meson_i2c_data i2c_meson6_data = {
 549         .set_clk_div = meson6_i2c_set_clk_div,
 550 };
 551
 552 static const struct meson_i2c_data i2c_gxbb_data = {
 553         .set_clk_div = meson_gxbb_axg_i2c_set_clk_div,
 554 };
 555
 556 static const struct meson_i2c_data i2c_axg_data = {
 557         .set_clk_div = meson_gxbb_axg_i2c_set_clk_div,
 558 };
 559
 560 static const struct of_device_id meson_i2c_match[] = {
 561         { .compatible = "amlogic,meson6-i2c", .data = &i2c_meson6_data },
 562         { .compatible = "amlogic,meson-gxbb-i2c", .data = &i2c_gxbb_data },
 563         { .compatible = "amlogic,meson-axg-i2c", .data = &i2c_axg_data },
 564         {},
 565 };
 566
 567 MODULE_DEVICE_TABLE(of, meson_i2c_match);
 568
 569 static struct platform_driver meson_i2c_driver = {
 570         .probe   = meson_i2c_probe,
 571         .remove  = meson_i2c_remove,
 572         .driver  = {
 573                 .name  = "meson-i2c",
 574                 .of_match_table = meson_i2c_match,
 575         },
 576 };
 577
 578 module_platform_driver(meson_i2c_driver);
 579
 580 MODULE_DESCRIPTION("Amlogic Meson I2C Bus driver");
 581 MODULE_AUTHOR("Beniamino Galvani <[email protected]>");
 582 MODULE_LICENSE("GPL v2");