drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "gfxhub_v1_0.h"
  25
  26 #include "gc/gc_9_0_offset.h"
  27 #include "gc/gc_9_0_sh_mask.h"
  28 #include "gc/gc_9_0_default.h"
  29 #include "vega10_enum.h"
  30
  31 #include "soc15_common.h"
  32
  33 u64 gfxhub_v1_0_get_mc_fb_offset(struct amdgpu_device *adev)
  34 {
  35         return (u64)RREG32_SOC15(GC, 0, mmMC_VM_FB_OFFSET) << 24;
  36 }
  37
  38 static void gfxhub_v1_0_init_gart_pt_regs(struct amdgpu_device *adev)
  39 {
  40         uint64_t value = amdgpu_gmc_pd_addr(adev->gart.bo);
  41
  42         WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
  43                      lower_32_bits(value));
  44
  45         WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
  46                      upper_32_bits(value));
  47 }
  48
  49 static void gfxhub_v1_0_init_gart_aperture_regs(struct amdgpu_device *adev)
  50 {
  51         gfxhub_v1_0_init_gart_pt_regs(adev);
  52
  53         WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
  54                      (u32)(adev->gmc.gart_start >> 12));
  55         WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
  56                      (u32)(adev->gmc.gart_start >> 44));
  57
  58         WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
  59                      (u32)(adev->gmc.gart_end >> 12));
  60         WREG32_SOC15(GC, 0, mmVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
  61                      (u32)(adev->gmc.gart_end >> 44));
  62 }
  63
  64 static void gfxhub_v1_0_init_system_aperture_regs(struct amdgpu_device *adev)
  65 {
  66         uint64_t value;
  67
  68         /* Program the AGP BAR */
  69         WREG32_SOC15(GC, 0, mmMC_VM_AGP_BASE, 0);
  70         WREG32_SOC15(GC, 0, mmMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
  71         WREG32_SOC15(GC, 0, mmMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
  72
  73         /* Program the system aperture low logical page number. */
  74         WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_LOW_ADDR,
  75                      min(adev->gmc.vram_start, adev->gmc.agp_start) >> 18);
  76
  77         if (adev->asic_type == CHIP_RAVEN && adev->rev_id >= 0x8)
  78                 /*
  79                  * Raven2 has a HW issue that it is unable to use the vram which
  80                  * is out of MC_VM_SYSTEM_APERTURE_HIGH_ADDR. So here is the
  81                  * workaround that increase system aperture high address (add 1)
  82                  * to get rid of the VM fault and hardware hang.
  83                  */
  84                 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
  85                              (max(adev->gmc.vram_end, adev->gmc.agp_end) >> 18) + 0x1);
  86         else
  87                 WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
  88                              max(adev->gmc.vram_end, adev->gmc.agp_end) >> 18);
  89
  90         /* Set default page address. */
  91         value = adev->vram_scratch.gpu_addr - adev->gmc.vram_start
  92                 + adev->vm_manager.vram_base_offset;
  93         WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
  94                      (u32)(value >> 12));
  95         WREG32_SOC15(GC, 0, mmMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
  96                      (u32)(value >> 44));
  97
  98         /* Program "protection fault". */
  99         WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 100                      (u32)(adev->dummy_page_addr >> 12));
 101         WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 102                      (u32)((u64)adev->dummy_page_addr >> 44));
 103
 104         WREG32_FIELD15(GC, 0, VM_L2_PROTECTION_FAULT_CNTL2,
 105                        ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 106 }
 107
 108 static void gfxhub_v1_0_init_tlb_regs(struct amdgpu_device *adev)
 109 {
 110         uint32_t tmp;
 111
 112         /* Setup TLB control */
 113         tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
 114
 115         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 116         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 117         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 118                             ENABLE_ADVANCED_DRIVER_MODEL, 1);
 119         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 120                             SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 121         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 122         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 123                             MTYPE, MTYPE_UC);/* XXX for emulation. */
 124         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
 125
 126         WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
 127 }
 128
 129 static void gfxhub_v1_0_init_cache_regs(struct amdgpu_device *adev)
 130 {
 131         uint32_t tmp;
 132
 133         /* Setup L2 cache */
 134         tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL);
 135         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 136         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 137         /* XXX for emulation, Refer to closed source code.*/
 138         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
 139                             0);
 140         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 1);
 141         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 142         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
 143         WREG32_SOC15(GC, 0, mmVM_L2_CNTL, tmp);
 144
 145         tmp = RREG32_SOC15(GC, 0, mmVM_L2_CNTL2);
 146         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 147         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 148         WREG32_SOC15(GC, 0, mmVM_L2_CNTL2, tmp);
 149
 150         tmp = mmVM_L2_CNTL3_DEFAULT;
 151         if (adev->gmc.translate_further) {
 152                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
 153                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
 154                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 155         } else {
 156                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
 157                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
 158                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 159         }
 160         WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, tmp);
 161
 162         tmp = mmVM_L2_CNTL4_DEFAULT;
 163         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 164         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4, VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 165         WREG32_SOC15(GC, 0, mmVM_L2_CNTL4, tmp);
 166 }
 167
 168 static void gfxhub_v1_0_enable_system_domain(struct amdgpu_device *adev)
 169 {
 170         uint32_t tmp;
 171
 172         tmp = RREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL);
 173         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 174         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH, 0);
 175         WREG32_SOC15(GC, 0, mmVM_CONTEXT0_CNTL, tmp);
 176 }
 177
 178 static void gfxhub_v1_0_disable_identity_aperture(struct amdgpu_device *adev)
 179 {
 180         WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 181                      0XFFFFFFFF);
 182         WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 183                      0x0000000F);
 184
 185         WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32,
 186                      0);
 187         WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32,
 188                      0);
 189
 190         WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32, 0);
 191         WREG32_SOC15(GC, 0, mmVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32, 0);
 192
 193 }
 194
 195 static void gfxhub_v1_0_setup_vmid_config(struct amdgpu_device *adev)
 196 {
 197         unsigned num_level, block_size;
 198         uint32_t tmp;
 199         int i;
 200
 201         num_level = adev->vm_manager.num_level;
 202         block_size = adev->vm_manager.block_size;
 203         if (adev->gmc.translate_further)
 204                 num_level -= 1;
 205         else
 206                 block_size -= 9;
 207
 208         for (i = 0; i <= 14; i++) {
 209                 tmp = RREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i);
 210                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 211                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
 212                                     num_level);
 213                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 214                                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 215                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 216                                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
 217                                     1);
 218                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 219                                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 220                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 221                                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 222                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 223                                     READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 224                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 225                                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 226                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 227                                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 228                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 229                                     PAGE_TABLE_BLOCK_SIZE,
 230                                     block_size);
 231                 /* Send no-retry XNACK on fault to suppress VM fault storm. */
 232                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 233                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
 234                 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_CNTL, i, tmp);
 235                 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32, i*2, 0);
 236                 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32, i*2, 0);
 237                 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,  i*2,
 238                         lower_32_bits(adev->vm_manager.max_pfn - 1));
 239                 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32, i*2,
 240                         upper_32_bits(adev->vm_manager.max_pfn - 1));
 241         }
 242 }
 243
 244 static void gfxhub_v1_0_program_invalidation(struct amdgpu_device *adev)
 245 {
 246         unsigned i;
 247
 248         for (i = 0 ; i < 18; ++i) {
 249                 WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 250                                     2 * i, 0xffffffff);
 251                 WREG32_SOC15_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 252                                     2 * i, 0x1f);
 253         }
 254 }
 255
 256 int gfxhub_v1_0_gart_enable(struct amdgpu_device *adev)
 257 {
 258         if (amdgpu_sriov_vf(adev)) {
 259                 /*
 260                  * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
 261                  * VF copy registers so vbios post doesn't program them, for
 262                  * SRIOV driver need to program them
 263                  */
 264                 WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_BASE,
 265                              adev->gmc.vram_start >> 24);
 266                 WREG32_SOC15(GC, 0, mmMC_VM_FB_LOCATION_TOP,
 267                              adev->gmc.vram_end >> 24);
 268         }
 269
 270         /* GART Enable. */
 271         gfxhub_v1_0_init_gart_aperture_regs(adev);
 272         gfxhub_v1_0_init_system_aperture_regs(adev);
 273         gfxhub_v1_0_init_tlb_regs(adev);
 274         gfxhub_v1_0_init_cache_regs(adev);
 275
 276         gfxhub_v1_0_enable_system_domain(adev);
 277         gfxhub_v1_0_disable_identity_aperture(adev);
 278         gfxhub_v1_0_setup_vmid_config(adev);
 279         gfxhub_v1_0_program_invalidation(adev);
 280
 281         return 0;
 282 }
 283
 284 void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev)
 285 {
 286         u32 tmp;
 287         u32 i;
 288
 289         /* Disable all tables */
 290         for (i = 0; i < 16; i++)
 291                 WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL, i, 0);
 292
 293         /* Setup TLB control */
 294         tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
 295         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 296         tmp = REG_SET_FIELD(tmp,
 297                                 MC_VM_MX_L1_TLB_CNTL,
 298                                 ENABLE_ADVANCED_DRIVER_MODEL,
 299                                 0);
 300         WREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL, tmp);
 301
 302         /* Setup L2 cache */
 303         WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 304         WREG32_SOC15(GC, 0, mmVM_L2_CNTL3, 0);
 305 }
 306
 307 /**
 308  * gfxhub_v1_0_set_fault_enable_default - update GART/VM fault handling
 309  *
 310  * @adev: amdgpu_device pointer
 311  * @value: true redirects VM faults to the default page
 312  */
 313 void gfxhub_v1_0_set_fault_enable_default(struct amdgpu_device *adev,
 314                                           bool value)
 315 {
 316         u32 tmp;
 317         tmp = RREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
 318         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 319                         RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 320         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 321                         PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 322         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 323                         PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 324         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 325                         PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 326         tmp = REG_SET_FIELD(tmp,
 327                         VM_L2_PROTECTION_FAULT_CNTL,
 328                         TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 329                         value);
 330         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 331                         NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 332         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 333                         DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 334         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 335                         VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 336         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 337                         READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 338         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 339                         WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 340         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 341                         EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 342         if (!value) {
 343                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 344                                 CRASH_ON_NO_RETRY_FAULT, 1);
 345                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 346                                 CRASH_ON_RETRY_FAULT, 1);
 347     }
 348         WREG32_SOC15(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL, tmp);
 349 }
 350
 351 void gfxhub_v1_0_init(struct amdgpu_device *adev)
 352 {
 353         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_GFXHUB];
 354
 355         hub->ctx0_ptb_addr_lo32 =
 356                 SOC15_REG_OFFSET(GC, 0,
 357                                  mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
 358         hub->ctx0_ptb_addr_hi32 =
 359                 SOC15_REG_OFFSET(GC, 0,
 360                                  mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
 361         hub->vm_inv_eng0_req =
 362                 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_REQ);
 363         hub->vm_inv_eng0_ack =
 364                 SOC15_REG_OFFSET(GC, 0, mmVM_INVALIDATE_ENG0_ACK);
 365         hub->vm_context0_cntl =
 366                 SOC15_REG_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL);
 367         hub->vm_l2_pro_fault_status =
 368                 SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_STATUS);
 369         hub->vm_l2_pro_fault_cntl =
 370                 SOC15_REG_OFFSET(GC, 0, mmVM_L2_PROTECTION_FAULT_CNTL);
 371 }