drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/kernel.h>
  24 #include <linux/firmware.h>
  25 #include <drm/drmP.h>
  26 #include "amdgpu.h"
  27 #include "amdgpu_gfx.h"
  28 #include "soc15.h"
  29 #include "soc15d.h"
  30 #include "amdgpu_atomfirmware.h"
  31
  32 #include "gc/gc_9_0_offset.h"
  33 #include "gc/gc_9_0_sh_mask.h"
  34 #include "vega10_enum.h"
  35 #include "hdp/hdp_4_0_offset.h"
  36
  37 #include "soc15_common.h"
  38 #include "clearstate_gfx9.h"
  39 #include "v9_structs.h"
  40
  41 #include "ivsrcid/gfx/irqsrcs_gfx_9_0.h"
  42
  43 #define GFX9_NUM_GFX_RINGS     1
  44 #define GFX9_MEC_HPD_SIZE 2048
  45 #define RLCG_UCODE_LOADING_START_ADDRESS 0x00002000L
  46 #define RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET 0x00000000L
  47
  48 #define mmPWR_MISC_CNTL_STATUS                                  0x0183
  49 #define mmPWR_MISC_CNTL_STATUS_BASE_IDX                         0
  50 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN__SHIFT        0x0
  51 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT          0x1
  52 #define PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK          0x00000001L
  53 #define PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK            0x00000006L
  54
  55 MODULE_FIRMWARE("amdgpu/vega10_ce.bin");
  56 MODULE_FIRMWARE("amdgpu/vega10_pfp.bin");
  57 MODULE_FIRMWARE("amdgpu/vega10_me.bin");
  58 MODULE_FIRMWARE("amdgpu/vega10_mec.bin");
  59 MODULE_FIRMWARE("amdgpu/vega10_mec2.bin");
  60 MODULE_FIRMWARE("amdgpu/vega10_rlc.bin");
  61
  62 MODULE_FIRMWARE("amdgpu/vega12_ce.bin");
  63 MODULE_FIRMWARE("amdgpu/vega12_pfp.bin");
  64 MODULE_FIRMWARE("amdgpu/vega12_me.bin");
  65 MODULE_FIRMWARE("amdgpu/vega12_mec.bin");
  66 MODULE_FIRMWARE("amdgpu/vega12_mec2.bin");
  67 MODULE_FIRMWARE("amdgpu/vega12_rlc.bin");
  68
  69 MODULE_FIRMWARE("amdgpu/vega20_ce.bin");
  70 MODULE_FIRMWARE("amdgpu/vega20_pfp.bin");
  71 MODULE_FIRMWARE("amdgpu/vega20_me.bin");
  72 MODULE_FIRMWARE("amdgpu/vega20_mec.bin");
  73 MODULE_FIRMWARE("amdgpu/vega20_mec2.bin");
  74 MODULE_FIRMWARE("amdgpu/vega20_rlc.bin");
  75
  76 MODULE_FIRMWARE("amdgpu/raven_ce.bin");
  77 MODULE_FIRMWARE("amdgpu/raven_pfp.bin");
  78 MODULE_FIRMWARE("amdgpu/raven_me.bin");
  79 MODULE_FIRMWARE("amdgpu/raven_mec.bin");
  80 MODULE_FIRMWARE("amdgpu/raven_mec2.bin");
  81 MODULE_FIRMWARE("amdgpu/raven_rlc.bin");
  82
  83 MODULE_FIRMWARE("amdgpu/picasso_ce.bin");
  84 MODULE_FIRMWARE("amdgpu/picasso_pfp.bin");
  85 MODULE_FIRMWARE("amdgpu/picasso_me.bin");
  86 MODULE_FIRMWARE("amdgpu/picasso_mec.bin");
  87 MODULE_FIRMWARE("amdgpu/picasso_mec2.bin");
  88 MODULE_FIRMWARE("amdgpu/picasso_rlc.bin");
  89
  90 MODULE_FIRMWARE("amdgpu/raven2_ce.bin");
  91 MODULE_FIRMWARE("amdgpu/raven2_pfp.bin");
  92 MODULE_FIRMWARE("amdgpu/raven2_me.bin");
  93 MODULE_FIRMWARE("amdgpu/raven2_mec.bin");
  94 MODULE_FIRMWARE("amdgpu/raven2_mec2.bin");
  95 MODULE_FIRMWARE("amdgpu/raven2_rlc.bin");
  96
  97 static const struct soc15_reg_golden golden_settings_gc_9_0[] =
  98 {
  99         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000400),
 100         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
 101         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
 102         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
 103         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 104         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
 105         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800),
 106         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800),
 107         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87),
 108         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f),
 109         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000),
 110         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
 111         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
 112         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
 113         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
 114         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
 115 };
 116
 117 static const struct soc15_reg_golden golden_settings_gc_9_0_vg10[] =
 118 {
 119         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0x0000f000, 0x00012107),
 120         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
 121         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080),
 122         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080),
 123         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080),
 124         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x2a114042),
 125         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x2a114042),
 126         SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080),
 127         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0x00008000, 0x00048000),
 128         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080),
 129         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
 130         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080),
 131         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080),
 132         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080),
 133         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
 134         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0x0000000f, 0x01000107),
 135         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x00001800, 0x00000800),
 136         SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080)
 137 };
 138
 139 static const struct soc15_reg_golden golden_settings_gc_9_0_vg20[] =
 140 {
 141         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x0f000080, 0x04000080),
 142         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000),
 143         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
 144         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xf3e777ff, 0x22014042),
 145         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xf3e777ff, 0x22014042),
 146         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0x00003e00, 0x00000400),
 147         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xff840000, 0x04040000),
 148         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00030000),
 149         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff010f, 0x01000107),
 150         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0x000b0000, 0x000b0000),
 151         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01000000, 0x01000000)
 152 };
 153
 154 static const struct soc15_reg_golden golden_settings_gc_9_1[] =
 155 {
 156         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
 157         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x08000000, 0x08000080),
 158         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0x08000000, 0x08000080),
 159         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x08000000, 0x08000080),
 160         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
 161         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
 162         SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x08000000, 0x08000080),
 163         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
 164         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
 165         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 166         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0x08000000, 0x08000080),
 167         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0x08000000, 0x08000080),
 168         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0x08000000, 0x08000080),
 169         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0x08000000, 0x08000080),
 170         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0x08000000, 0x08000080),
 171         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
 172         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
 173         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00003120),
 174         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
 175         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000000ff),
 176         SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x08000000, 0x08000080)
 177 };
 178
 179 static const struct soc15_reg_golden golden_settings_gc_9_1_rv1[] =
 180 {
 181         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_3, 0x30000000, 0x10000000),
 182         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24000042),
 183         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24000042),
 184         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04048000),
 185         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_MODE_CNTL_1, 0x06000000, 0x06000000),
 186         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRMI_UTCL1_CNTL2, 0x00030000, 0x00020000),
 187         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x00000800)
 188 };
 189
 190 static const struct soc15_reg_golden golden_settings_gc_9_1_rv2[] =
 191 {
 192         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0xff7fffff, 0x04000000),
 193         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
 194         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0xff7fffff, 0x0a000000),
 195         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPC_UTCL1_CNTL, 0x7f0fffff, 0x08000080),
 196         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPF_UTCL1_CNTL, 0xff8fffff, 0x08000080),
 197         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCPG_UTCL1_CNTL, 0x7f8fffff, 0x08000080),
 198         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x26013041),
 199         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x26013041),
 200         SOC15_REG_GOLDEN_VALUE(GC, 0, mmIA_UTCL1_CNTL, 0x3f8fffff, 0x08000080),
 201         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
 202         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_0, 0xff0fffff, 0x08000080),
 203         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_1, 0xff0fffff, 0x08000080),
 204         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_GPM_UTCL1_CNTL_2, 0xff0fffff, 0x08000080),
 205         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_PREWALKER_UTCL1_CNTL, 0xff0fffff, 0x08000080),
 206         SOC15_REG_GOLDEN_VALUE(GC, 0, mmRLC_SPM_UTCL1_CNTL, 0xff0fffff, 0x08000080),
 207         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
 208         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x00000010),
 209         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000),
 210         SOC15_REG_GOLDEN_VALUE(GC, 0, mmWD_UTCL1_CNTL, 0x3f8fffff, 0x08000080),
 211 };
 212
 213 static const struct soc15_reg_golden golden_settings_gc_9_x_common[] =
 214 {
 215         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_INDEX, 0xffffffff, 0x00000000),
 216         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGRBM_CAM_DATA, 0xffffffff, 0x2544c382)
 217 };
 218
 219 static const struct soc15_reg_golden golden_settings_gc_9_2_1[] =
 220 {
 221         SOC15_REG_GOLDEN_VALUE(GC, 0, mmDB_DEBUG2, 0xf00fffff, 0x00000420),
 222         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_GPU_ID, 0x0000000f, 0x00000000),
 223         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_BINNER_EVENT_CNTL_3, 0x00000003, 0x82400024),
 224         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE, 0x3fffffff, 0x00000001),
 225         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_LINE_STIPPLE_STATE, 0x0000ff0f, 0x00000000),
 226         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSH_MEM_CONFIG, 0x00001000, 0x00001000),
 227         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_0, 0x0007ffff, 0x00000800),
 228         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_CU_1, 0x0007ffff, 0x00000800),
 229         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_0, 0x01ffffff, 0x0000ff87),
 230         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_RESOURCE_RESERVE_EN_CU_1, 0x01ffffff, 0x0000ff8f),
 231         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSQC_CONFIG, 0x03000000, 0x020a2000),
 232         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTA_CNTL_AUX, 0xfffffeef, 0x010b0000),
 233         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x4a2c0e68),
 234         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0xb5d3f197),
 235         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_CACHE_INVALIDATION, 0x3fff3af3, 0x19200000),
 236         SOC15_REG_GOLDEN_VALUE(GC, 0, mmVGT_GS_MAX_WAVE_ID, 0x00000fff, 0x000003ff)
 237 };
 238
 239 static const struct soc15_reg_golden golden_settings_gc_9_2_1_vg12[] =
 240 {
 241         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_DCC_CONFIG, 0x00000080, 0x04000080),
 242         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL, 0xfffdf3cf, 0x00014104),
 243         SOC15_REG_GOLDEN_VALUE(GC, 0, mmCB_HW_CONTROL_2, 0x0f000000, 0x0a000000),
 244         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG, 0xffff77ff, 0x24104041),
 245         SOC15_REG_GOLDEN_VALUE(GC, 0, mmGB_ADDR_CONFIG_READ, 0xffff77ff, 0x24104041),
 246         SOC15_REG_GOLDEN_VALUE(GC, 0, mmPA_SC_ENHANCE_1, 0xffffffff, 0x04040000),
 247         SOC15_REG_GOLDEN_VALUE(GC, 0, mmSPI_CONFIG_CNTL_1, 0xffff03ff, 0x01000107),
 248         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_HI, 0xffffffff, 0x00000000),
 249         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTCP_CHAN_STEER_LO, 0xffffffff, 0x76325410),
 250         SOC15_REG_GOLDEN_VALUE(GC, 0, mmTD_CNTL, 0x01bd9f33, 0x01000000)
 251 };
 252
 253 static const u32 GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[] =
 254 {
 255         mmRLC_SRM_INDEX_CNTL_ADDR_0 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 256         mmRLC_SRM_INDEX_CNTL_ADDR_1 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 257         mmRLC_SRM_INDEX_CNTL_ADDR_2 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 258         mmRLC_SRM_INDEX_CNTL_ADDR_3 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 259         mmRLC_SRM_INDEX_CNTL_ADDR_4 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 260         mmRLC_SRM_INDEX_CNTL_ADDR_5 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 261         mmRLC_SRM_INDEX_CNTL_ADDR_6 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 262         mmRLC_SRM_INDEX_CNTL_ADDR_7 - mmRLC_SRM_INDEX_CNTL_ADDR_0,
 263 };
 264
 265 static const u32 GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[] =
 266 {
 267         mmRLC_SRM_INDEX_CNTL_DATA_0 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 268         mmRLC_SRM_INDEX_CNTL_DATA_1 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 269         mmRLC_SRM_INDEX_CNTL_DATA_2 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 270         mmRLC_SRM_INDEX_CNTL_DATA_3 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 271         mmRLC_SRM_INDEX_CNTL_DATA_4 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 272         mmRLC_SRM_INDEX_CNTL_DATA_5 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 273         mmRLC_SRM_INDEX_CNTL_DATA_6 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 274         mmRLC_SRM_INDEX_CNTL_DATA_7 - mmRLC_SRM_INDEX_CNTL_DATA_0,
 275 };
 276
 277 #define VEGA10_GB_ADDR_CONFIG_GOLDEN 0x2a114042
 278 #define VEGA12_GB_ADDR_CONFIG_GOLDEN 0x24104041
 279 #define RAVEN_GB_ADDR_CONFIG_GOLDEN 0x24000042
 280 #define RAVEN2_GB_ADDR_CONFIG_GOLDEN 0x26013041
 281
 282 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev);
 283 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev);
 284 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev);
 285 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev);
 286 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
 287                                  struct amdgpu_cu_info *cu_info);
 288 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev);
 289 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance);
 290 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring);
 291
 292 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev)
 293 {
 294         switch (adev->asic_type) {
 295         case CHIP_VEGA10:
 296                 soc15_program_register_sequence(adev,
 297                                                  golden_settings_gc_9_0,
 298                                                  ARRAY_SIZE(golden_settings_gc_9_0));
 299                 soc15_program_register_sequence(adev,
 300                                                  golden_settings_gc_9_0_vg10,
 301                                                  ARRAY_SIZE(golden_settings_gc_9_0_vg10));
 302                 break;
 303         case CHIP_VEGA12:
 304                 soc15_program_register_sequence(adev,
 305                                                 golden_settings_gc_9_2_1,
 306                                                 ARRAY_SIZE(golden_settings_gc_9_2_1));
 307                 soc15_program_register_sequence(adev,
 308                                                 golden_settings_gc_9_2_1_vg12,
 309                                                 ARRAY_SIZE(golden_settings_gc_9_2_1_vg12));
 310                 break;
 311         case CHIP_VEGA20:
 312                 soc15_program_register_sequence(adev,
 313                                                 golden_settings_gc_9_0,
 314                                                 ARRAY_SIZE(golden_settings_gc_9_0));
 315                 soc15_program_register_sequence(adev,
 316                                                 golden_settings_gc_9_0_vg20,
 317                                                 ARRAY_SIZE(golden_settings_gc_9_0_vg20));
 318                 break;
 319         case CHIP_RAVEN:
 320                 soc15_program_register_sequence(adev, golden_settings_gc_9_1,
 321                                                 ARRAY_SIZE(golden_settings_gc_9_1));
 322                 if (adev->rev_id >= 8)
 323                         soc15_program_register_sequence(adev,
 324                                                         golden_settings_gc_9_1_rv2,
 325                                                         ARRAY_SIZE(golden_settings_gc_9_1_rv2));
 326                 else
 327                         soc15_program_register_sequence(adev,
 328                                                         golden_settings_gc_9_1_rv1,
 329                                                         ARRAY_SIZE(golden_settings_gc_9_1_rv1));
 330                 break;
 331         default:
 332                 break;
 333         }
 334
 335         soc15_program_register_sequence(adev, golden_settings_gc_9_x_common,
 336                                         (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
 337 }
 338
 339 static void gfx_v9_0_scratch_init(struct amdgpu_device *adev)
 340 {
 341         adev->gfx.scratch.num_reg = 8;
 342         adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0);
 343         adev->gfx.scratch.free_mask = (1u << adev->gfx.scratch.num_reg) - 1;
 344 }
 345
 346 static void gfx_v9_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
 347                                        bool wc, uint32_t reg, uint32_t val)
 348 {
 349         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
 350         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
 351                                 WRITE_DATA_DST_SEL(0) |
 352                                 (wc ? WR_CONFIRM : 0));
 353         amdgpu_ring_write(ring, reg);
 354         amdgpu_ring_write(ring, 0);
 355         amdgpu_ring_write(ring, val);
 356 }
 357
 358 static void gfx_v9_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 359                                   int mem_space, int opt, uint32_t addr0,
 360                                   uint32_t addr1, uint32_t ref, uint32_t mask,
 361                                   uint32_t inv)
 362 {
 363         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
 364         amdgpu_ring_write(ring,
 365                                  /* memory (1) or register (0) */
 366                                  (WAIT_REG_MEM_MEM_SPACE(mem_space) |
 367                                  WAIT_REG_MEM_OPERATION(opt) | /* wait */
 368                                  WAIT_REG_MEM_FUNCTION(3) |  /* equal */
 369                                  WAIT_REG_MEM_ENGINE(eng_sel)));
 370
 371         if (mem_space)
 372                 BUG_ON(addr0 & 0x3); /* Dword align */
 373         amdgpu_ring_write(ring, addr0);
 374         amdgpu_ring_write(ring, addr1);
 375         amdgpu_ring_write(ring, ref);
 376         amdgpu_ring_write(ring, mask);
 377         amdgpu_ring_write(ring, inv); /* poll interval */
 378 }
 379
 380 static int gfx_v9_0_ring_test_ring(struct amdgpu_ring *ring)
 381 {
 382         struct amdgpu_device *adev = ring->adev;
 383         uint32_t scratch;
 384         uint32_t tmp = 0;
 385         unsigned i;
 386         int r;
 387
 388         r = amdgpu_gfx_scratch_get(adev, &scratch);
 389         if (r) {
 390                 DRM_ERROR("amdgpu: cp failed to get scratch reg (%d).\n", r);
 391                 return r;
 392         }
 393         WREG32(scratch, 0xCAFEDEAD);
 394         r = amdgpu_ring_alloc(ring, 3);
 395         if (r) {
 396                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 397                           ring->idx, r);
 398                 amdgpu_gfx_scratch_free(adev, scratch);
 399                 return r;
 400         }
 401         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 402         amdgpu_ring_write(ring, (scratch - PACKET3_SET_UCONFIG_REG_START));
 403         amdgpu_ring_write(ring, 0xDEADBEEF);
 404         amdgpu_ring_commit(ring);
 405
 406         for (i = 0; i < adev->usec_timeout; i++) {
 407                 tmp = RREG32(scratch);
 408                 if (tmp == 0xDEADBEEF)
 409                         break;
 410                 DRM_UDELAY(1);
 411         }
 412         if (i < adev->usec_timeout) {
 413                 DRM_DEBUG("ring test on %d succeeded in %d usecs\n",
 414                          ring->idx, i);
 415         } else {
 416                 DRM_ERROR("amdgpu: ring %d test failed (scratch(0x%04X)=0x%08X)\n",
 417                           ring->idx, scratch, tmp);
 418                 r = -EINVAL;
 419         }
 420         amdgpu_gfx_scratch_free(adev, scratch);
 421         return r;
 422 }
 423
 424 static int gfx_v9_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 425 {
 426         struct amdgpu_device *adev = ring->adev;
 427         struct amdgpu_ib ib;
 428         struct dma_fence *f = NULL;
 429
 430         unsigned index;
 431         uint64_t gpu_addr;
 432         uint32_t tmp;
 433         long r;
 434
 435         r = amdgpu_device_wb_get(adev, &index);
 436         if (r) {
 437                 dev_err(adev->dev, "(%ld) failed to allocate wb slot\n", r);
 438                 return r;
 439         }
 440
 441         gpu_addr = adev->wb.gpu_addr + (index * 4);
 442         adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
 443         memset(&ib, 0, sizeof(ib));
 444         r = amdgpu_ib_get(adev, NULL, 16, &ib);
 445         if (r) {
 446                 DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 447                 goto err1;
 448         }
 449         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
 450         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
 451         ib.ptr[2] = lower_32_bits(gpu_addr);
 452         ib.ptr[3] = upper_32_bits(gpu_addr);
 453         ib.ptr[4] = 0xDEADBEEF;
 454         ib.length_dw = 5;
 455
 456         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 457         if (r)
 458                 goto err2;
 459
 460         r = dma_fence_wait_timeout(f, false, timeout);
 461         if (r == 0) {
 462                         DRM_ERROR("amdgpu: IB test timed out.\n");
 463                         r = -ETIMEDOUT;
 464                         goto err2;
 465         } else if (r < 0) {
 466                         DRM_ERROR("amdgpu: fence wait failed (%ld).\n", r);
 467                         goto err2;
 468         }
 469
 470         tmp = adev->wb.wb[index];
 471         if (tmp == 0xDEADBEEF) {
 472                         DRM_DEBUG("ib test on ring %d succeeded\n", ring->idx);
 473                         r = 0;
 474         } else {
 475                         DRM_ERROR("ib test on ring %d failed\n", ring->idx);
 476                         r = -EINVAL;
 477         }
 478
 479 err2:
 480         amdgpu_ib_free(adev, &ib, NULL);
 481         dma_fence_put(f);
 482 err1:
 483         amdgpu_device_wb_free(adev, index);
 484         return r;
 485 }
 486
 487
 488 static void gfx_v9_0_free_microcode(struct amdgpu_device *adev)
 489 {
 490         release_firmware(adev->gfx.pfp_fw);
 491         adev->gfx.pfp_fw = NULL;
 492         release_firmware(adev->gfx.me_fw);
 493         adev->gfx.me_fw = NULL;
 494         release_firmware(adev->gfx.ce_fw);
 495         adev->gfx.ce_fw = NULL;
 496         release_firmware(adev->gfx.rlc_fw);
 497         adev->gfx.rlc_fw = NULL;
 498         release_firmware(adev->gfx.mec_fw);
 499         adev->gfx.mec_fw = NULL;
 500         release_firmware(adev->gfx.mec2_fw);
 501         adev->gfx.mec2_fw = NULL;
 502
 503         kfree(adev->gfx.rlc.register_list_format);
 504 }
 505
 506 static void gfx_v9_0_init_rlc_ext_microcode(struct amdgpu_device *adev)
 507 {
 508         const struct rlc_firmware_header_v2_1 *rlc_hdr;
 509
 510         rlc_hdr = (const struct rlc_firmware_header_v2_1 *)adev->gfx.rlc_fw->data;
 511         adev->gfx.rlc_srlc_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_ucode_ver);
 512         adev->gfx.rlc_srlc_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_cntl_feature_ver);
 513         adev->gfx.rlc.save_restore_list_cntl_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_cntl_size_bytes);
 514         adev->gfx.rlc.save_restore_list_cntl = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_cntl_offset_bytes);
 515         adev->gfx.rlc_srlg_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_ucode_ver);
 516         adev->gfx.rlc_srlg_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_gpm_feature_ver);
 517         adev->gfx.rlc.save_restore_list_gpm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_gpm_size_bytes);
 518         adev->gfx.rlc.save_restore_list_gpm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_gpm_offset_bytes);
 519         adev->gfx.rlc_srls_fw_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_ucode_ver);
 520         adev->gfx.rlc_srls_feature_version = le32_to_cpu(rlc_hdr->save_restore_list_srm_feature_ver);
 521         adev->gfx.rlc.save_restore_list_srm_size_bytes = le32_to_cpu(rlc_hdr->save_restore_list_srm_size_bytes);
 522         adev->gfx.rlc.save_restore_list_srm = (u8 *)rlc_hdr + le32_to_cpu(rlc_hdr->save_restore_list_srm_offset_bytes);
 523         adev->gfx.rlc.reg_list_format_direct_reg_list_length =
 524                         le32_to_cpu(rlc_hdr->reg_list_format_direct_reg_list_length);
 525 }
 526
 527 static void gfx_v9_0_check_fw_write_wait(struct amdgpu_device *adev)
 528 {
 529         adev->gfx.me_fw_write_wait = false;
 530         adev->gfx.mec_fw_write_wait = false;
 531
 532         switch (adev->asic_type) {
 533         case CHIP_VEGA10:
 534                 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
 535                     (adev->gfx.me_feature_version >= 42) &&
 536                     (adev->gfx.pfp_fw_version >=  0x000000b1) &&
 537                     (adev->gfx.pfp_feature_version >= 42))
 538                         adev->gfx.me_fw_write_wait = true;
 539
 540                 if ((adev->gfx.mec_fw_version >=  0x00000193) &&
 541                     (adev->gfx.mec_feature_version >= 42))
 542                         adev->gfx.mec_fw_write_wait = true;
 543                 break;
 544         case CHIP_VEGA12:
 545                 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
 546                     (adev->gfx.me_feature_version >= 44) &&
 547                     (adev->gfx.pfp_fw_version >=  0x000000b2) &&
 548                     (adev->gfx.pfp_feature_version >= 44))
 549                         adev->gfx.me_fw_write_wait = true;
 550
 551                 if ((adev->gfx.mec_fw_version >=  0x00000196) &&
 552                     (adev->gfx.mec_feature_version >= 44))
 553                         adev->gfx.mec_fw_write_wait = true;
 554                 break;
 555         case CHIP_VEGA20:
 556                 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
 557                     (adev->gfx.me_feature_version >= 44) &&
 558                     (adev->gfx.pfp_fw_version >=  0x000000b2) &&
 559                     (adev->gfx.pfp_feature_version >= 44))
 560                         adev->gfx.me_fw_write_wait = true;
 561
 562                 if ((adev->gfx.mec_fw_version >=  0x00000197) &&
 563                     (adev->gfx.mec_feature_version >= 44))
 564                         adev->gfx.mec_fw_write_wait = true;
 565                 break;
 566         case CHIP_RAVEN:
 567                 if ((adev->gfx.me_fw_version >= 0x0000009c) &&
 568                     (adev->gfx.me_feature_version >= 42) &&
 569                     (adev->gfx.pfp_fw_version >=  0x000000b1) &&
 570                     (adev->gfx.pfp_feature_version >= 42))
 571                         adev->gfx.me_fw_write_wait = true;
 572
 573                 if ((adev->gfx.mec_fw_version >=  0x00000192) &&
 574                     (adev->gfx.mec_feature_version >= 42))
 575                         adev->gfx.mec_fw_write_wait = true;
 576                 break;
 577         default:
 578                 break;
 579         }
 580 }
 581
 582 static int gfx_v9_0_init_microcode(struct amdgpu_device *adev)
 583 {
 584         const char *chip_name;
 585         char fw_name[30];
 586         int err;
 587         struct amdgpu_firmware_info *info = NULL;
 588         const struct common_firmware_header *header = NULL;
 589         const struct gfx_firmware_header_v1_0 *cp_hdr;
 590         const struct rlc_firmware_header_v2_0 *rlc_hdr;
 591         unsigned int *tmp = NULL;
 592         unsigned int i = 0;
 593         uint16_t version_major;
 594         uint16_t version_minor;
 595
 596         DRM_DEBUG("\n");
 597
 598         switch (adev->asic_type) {
 599         case CHIP_VEGA10:
 600                 chip_name = "vega10";
 601                 break;
 602         case CHIP_VEGA12:
 603                 chip_name = "vega12";
 604                 break;
 605         case CHIP_VEGA20:
 606                 chip_name = "vega20";
 607                 break;
 608         case CHIP_RAVEN:
 609                 if (adev->rev_id >= 8)
 610                         chip_name = "raven2";
 611                 else if (adev->pdev->device == 0x15d8)
 612                         chip_name = "picasso";
 613                 else
 614                         chip_name = "raven";
 615                 break;
 616         default:
 617                 BUG();
 618         }
 619
 620         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", chip_name);
 621         err = request_firmware(&adev->gfx.pfp_fw, fw_name, adev->dev);
 622         if (err)
 623                 goto out;
 624         err = amdgpu_ucode_validate(adev->gfx.pfp_fw);
 625         if (err)
 626                 goto out;
 627         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 628         adev->gfx.pfp_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 629         adev->gfx.pfp_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 630
 631         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", chip_name);
 632         err = request_firmware(&adev->gfx.me_fw, fw_name, adev->dev);
 633         if (err)
 634                 goto out;
 635         err = amdgpu_ucode_validate(adev->gfx.me_fw);
 636         if (err)
 637                 goto out;
 638         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 639         adev->gfx.me_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 640         adev->gfx.me_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 641
 642         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_ce.bin", chip_name);
 643         err = request_firmware(&adev->gfx.ce_fw, fw_name, adev->dev);
 644         if (err)
 645                 goto out;
 646         err = amdgpu_ucode_validate(adev->gfx.ce_fw);
 647         if (err)
 648                 goto out;
 649         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 650         adev->gfx.ce_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 651         adev->gfx.ce_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 652
 653         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", chip_name);
 654         err = request_firmware(&adev->gfx.rlc_fw, fw_name, adev->dev);
 655         if (err)
 656                 goto out;
 657         err = amdgpu_ucode_validate(adev->gfx.rlc_fw);
 658         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
 659
 660         version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
 661         version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
 662         if (version_major == 2 && version_minor == 1)
 663                 adev->gfx.rlc.is_rlc_v2_1 = true;
 664
 665         adev->gfx.rlc_fw_version = le32_to_cpu(rlc_hdr->header.ucode_version);
 666         adev->gfx.rlc_feature_version = le32_to_cpu(rlc_hdr->ucode_feature_version);
 667         adev->gfx.rlc.save_and_restore_offset =
 668                         le32_to_cpu(rlc_hdr->save_and_restore_offset);
 669         adev->gfx.rlc.clear_state_descriptor_offset =
 670                         le32_to_cpu(rlc_hdr->clear_state_descriptor_offset);
 671         adev->gfx.rlc.avail_scratch_ram_locations =
 672                         le32_to_cpu(rlc_hdr->avail_scratch_ram_locations);
 673         adev->gfx.rlc.reg_restore_list_size =
 674                         le32_to_cpu(rlc_hdr->reg_restore_list_size);
 675         adev->gfx.rlc.reg_list_format_start =
 676                         le32_to_cpu(rlc_hdr->reg_list_format_start);
 677         adev->gfx.rlc.reg_list_format_separate_start =
 678                         le32_to_cpu(rlc_hdr->reg_list_format_separate_start);
 679         adev->gfx.rlc.starting_offsets_start =
 680                         le32_to_cpu(rlc_hdr->starting_offsets_start);
 681         adev->gfx.rlc.reg_list_format_size_bytes =
 682                         le32_to_cpu(rlc_hdr->reg_list_format_size_bytes);
 683         adev->gfx.rlc.reg_list_size_bytes =
 684                         le32_to_cpu(rlc_hdr->reg_list_size_bytes);
 685         adev->gfx.rlc.register_list_format =
 686                         kmalloc(adev->gfx.rlc.reg_list_format_size_bytes +
 687                                 adev->gfx.rlc.reg_list_size_bytes, GFP_KERNEL);
 688         if (!adev->gfx.rlc.register_list_format) {
 689                 err = -ENOMEM;
 690                 goto out;
 691         }
 692
 693         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 694                         le32_to_cpu(rlc_hdr->reg_list_format_array_offset_bytes));
 695         for (i = 0 ; i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2); i++)
 696                 adev->gfx.rlc.register_list_format[i] = le32_to_cpu(tmp[i]);
 697
 698         adev->gfx.rlc.register_restore = adev->gfx.rlc.register_list_format + i;
 699
 700         tmp = (unsigned int *)((uintptr_t)rlc_hdr +
 701                         le32_to_cpu(rlc_hdr->reg_list_array_offset_bytes));
 702         for (i = 0 ; i < (adev->gfx.rlc.reg_list_size_bytes >> 2); i++)
 703                 adev->gfx.rlc.register_restore[i] = le32_to_cpu(tmp[i]);
 704
 705         if (adev->gfx.rlc.is_rlc_v2_1)
 706                 gfx_v9_0_init_rlc_ext_microcode(adev);
 707
 708         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", chip_name);
 709         err = request_firmware(&adev->gfx.mec_fw, fw_name, adev->dev);
 710         if (err)
 711                 goto out;
 712         err = amdgpu_ucode_validate(adev->gfx.mec_fw);
 713         if (err)
 714                 goto out;
 715         cp_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 716         adev->gfx.mec_fw_version = le32_to_cpu(cp_hdr->header.ucode_version);
 717         adev->gfx.mec_feature_version = le32_to_cpu(cp_hdr->ucode_feature_version);
 718
 719
 720         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec2.bin", chip_name);
 721         err = request_firmware(&adev->gfx.mec2_fw, fw_name, adev->dev);
 722         if (!err) {
 723                 err = amdgpu_ucode_validate(adev->gfx.mec2_fw);
 724                 if (err)
 725                         goto out;
 726                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
 727                 adev->gfx.mec2_fw->data;
 728                 adev->gfx.mec2_fw_version =
 729                 le32_to_cpu(cp_hdr->header.ucode_version);
 730                 adev->gfx.mec2_feature_version =
 731                 le32_to_cpu(cp_hdr->ucode_feature_version);
 732         } else {
 733                 err = 0;
 734                 adev->gfx.mec2_fw = NULL;
 735         }
 736
 737         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 738                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_PFP];
 739                 info->ucode_id = AMDGPU_UCODE_ID_CP_PFP;
 740                 info->fw = adev->gfx.pfp_fw;
 741                 header = (const struct common_firmware_header *)info->fw->data;
 742                 adev->firmware.fw_size +=
 743                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 744
 745                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_ME];
 746                 info->ucode_id = AMDGPU_UCODE_ID_CP_ME;
 747                 info->fw = adev->gfx.me_fw;
 748                 header = (const struct common_firmware_header *)info->fw->data;
 749                 adev->firmware.fw_size +=
 750                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 751
 752                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_CE];
 753                 info->ucode_id = AMDGPU_UCODE_ID_CP_CE;
 754                 info->fw = adev->gfx.ce_fw;
 755                 header = (const struct common_firmware_header *)info->fw->data;
 756                 adev->firmware.fw_size +=
 757                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 758
 759                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_G];
 760                 info->ucode_id = AMDGPU_UCODE_ID_RLC_G;
 761                 info->fw = adev->gfx.rlc_fw;
 762                 header = (const struct common_firmware_header *)info->fw->data;
 763                 adev->firmware.fw_size +=
 764                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 765
 766                 if (adev->gfx.rlc.is_rlc_v2_1 &&
 767                     adev->gfx.rlc.save_restore_list_cntl_size_bytes &&
 768                     adev->gfx.rlc.save_restore_list_gpm_size_bytes &&
 769                     adev->gfx.rlc.save_restore_list_srm_size_bytes) {
 770                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL];
 771                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_CNTL;
 772                         info->fw = adev->gfx.rlc_fw;
 773                         adev->firmware.fw_size +=
 774                                 ALIGN(adev->gfx.rlc.save_restore_list_cntl_size_bytes, PAGE_SIZE);
 775
 776                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM];
 777                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_GPM_MEM;
 778                         info->fw = adev->gfx.rlc_fw;
 779                         adev->firmware.fw_size +=
 780                                 ALIGN(adev->gfx.rlc.save_restore_list_gpm_size_bytes, PAGE_SIZE);
 781
 782                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM];
 783                         info->ucode_id = AMDGPU_UCODE_ID_RLC_RESTORE_LIST_SRM_MEM;
 784                         info->fw = adev->gfx.rlc_fw;
 785                         adev->firmware.fw_size +=
 786                                 ALIGN(adev->gfx.rlc.save_restore_list_srm_size_bytes, PAGE_SIZE);
 787                 }
 788
 789                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1];
 790                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1;
 791                 info->fw = adev->gfx.mec_fw;
 792                 header = (const struct common_firmware_header *)info->fw->data;
 793                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
 794                 adev->firmware.fw_size +=
 795                         ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 796
 797                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC1_JT];
 798                 info->ucode_id = AMDGPU_UCODE_ID_CP_MEC1_JT;
 799                 info->fw = adev->gfx.mec_fw;
 800                 adev->firmware.fw_size +=
 801                         ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 802
 803                 if (adev->gfx.mec2_fw) {
 804                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2];
 805                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2;
 806                         info->fw = adev->gfx.mec2_fw;
 807                         header = (const struct common_firmware_header *)info->fw->data;
 808                         cp_hdr = (const struct gfx_firmware_header_v1_0 *)info->fw->data;
 809                         adev->firmware.fw_size +=
 810                                 ALIGN(le32_to_cpu(header->ucode_size_bytes) - le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 811                         info = &adev->firmware.ucode[AMDGPU_UCODE_ID_CP_MEC2_JT];
 812                         info->ucode_id = AMDGPU_UCODE_ID_CP_MEC2_JT;
 813                         info->fw = adev->gfx.mec2_fw;
 814                         adev->firmware.fw_size +=
 815                                 ALIGN(le32_to_cpu(cp_hdr->jt_size) * 4, PAGE_SIZE);
 816                 }
 817
 818         }
 819
 820 out:
 821         gfx_v9_0_check_fw_write_wait(adev);
 822         if (err) {
 823                 dev_err(adev->dev,
 824                         "gfx9: Failed to load firmware \"%s\"\n",
 825                         fw_name);
 826                 release_firmware(adev->gfx.pfp_fw);
 827                 adev->gfx.pfp_fw = NULL;
 828                 release_firmware(adev->gfx.me_fw);
 829                 adev->gfx.me_fw = NULL;
 830                 release_firmware(adev->gfx.ce_fw);
 831                 adev->gfx.ce_fw = NULL;
 832                 release_firmware(adev->gfx.rlc_fw);
 833                 adev->gfx.rlc_fw = NULL;
 834                 release_firmware(adev->gfx.mec_fw);
 835                 adev->gfx.mec_fw = NULL;
 836                 release_firmware(adev->gfx.mec2_fw);
 837                 adev->gfx.mec2_fw = NULL;
 838         }
 839         return err;
 840 }
 841
 842 static u32 gfx_v9_0_get_csb_size(struct amdgpu_device *adev)
 843 {
 844         u32 count = 0;
 845         const struct cs_section_def *sect = NULL;
 846         const struct cs_extent_def *ext = NULL;
 847
 848         /* begin clear state */
 849         count += 2;
 850         /* context control state */
 851         count += 3;
 852
 853         for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
 854                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 855                         if (sect->id == SECT_CONTEXT)
 856                                 count += 2 + ext->reg_count;
 857                         else
 858                                 return 0;
 859                 }
 860         }
 861
 862         /* end clear state */
 863         count += 2;
 864         /* clear state */
 865         count += 2;
 866
 867         return count;
 868 }
 869
 870 static void gfx_v9_0_get_csb_buffer(struct amdgpu_device *adev,
 871                                     volatile u32 *buffer)
 872 {
 873         u32 count = 0, i;
 874         const struct cs_section_def *sect = NULL;
 875         const struct cs_extent_def *ext = NULL;
 876
 877         if (adev->gfx.rlc.cs_data == NULL)
 878                 return;
 879         if (buffer == NULL)
 880                 return;
 881
 882         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 883         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
 884
 885         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
 886         buffer[count++] = cpu_to_le32(0x80000000);
 887         buffer[count++] = cpu_to_le32(0x80000000);
 888
 889         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
 890                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 891                         if (sect->id == SECT_CONTEXT) {
 892                                 buffer[count++] =
 893                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
 894                                 buffer[count++] = cpu_to_le32(ext->reg_index -
 895                                                 PACKET3_SET_CONTEXT_REG_START);
 896                                 for (i = 0; i < ext->reg_count; i++)
 897                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
 898                         } else {
 899                                 return;
 900                         }
 901                 }
 902         }
 903
 904         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 905         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
 906
 907         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
 908         buffer[count++] = cpu_to_le32(0);
 909 }
 910
 911 static void gfx_v9_0_init_lbpw(struct amdgpu_device *adev)
 912 {
 913         uint32_t data;
 914
 915         /* set mmRLC_LB_THR_CONFIG_1/2/3/4 */
 916         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_1, 0x0000007F);
 917         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_2, 0x0333A5A7);
 918         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_3, 0x00000077);
 919         WREG32_SOC15(GC, 0, mmRLC_LB_THR_CONFIG_4, (0x30 | 0x40 << 8 | 0x02FA << 16));
 920
 921         /* set mmRLC_LB_CNTR_INIT = 0x0000_0000 */
 922         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_INIT, 0x00000000);
 923
 924         /* set mmRLC_LB_CNTR_MAX = 0x0000_0500 */
 925         WREG32_SOC15(GC, 0, mmRLC_LB_CNTR_MAX, 0x00000500);
 926
 927         mutex_lock(&adev->grbm_idx_mutex);
 928         /* set mmRLC_LB_INIT_CU_MASK thru broadcast mode to enable all SE/SH*/
 929         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
 930         WREG32_SOC15(GC, 0, mmRLC_LB_INIT_CU_MASK, 0xffffffff);
 931
 932         /* set mmRLC_LB_PARAMS = 0x003F_1006 */
 933         data = REG_SET_FIELD(0, RLC_LB_PARAMS, FIFO_SAMPLES, 0x0003);
 934         data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLES, 0x0010);
 935         data |= REG_SET_FIELD(data, RLC_LB_PARAMS, PG_IDLE_SAMPLE_INTERVAL, 0x033F);
 936         WREG32_SOC15(GC, 0, mmRLC_LB_PARAMS, data);
 937
 938         /* set mmRLC_GPM_GENERAL_7[31-16] = 0x00C0 */
 939         data = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7);
 940         data &= 0x0000FFFF;
 941         data |= 0x00C00000;
 942         WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_7, data);
 943
 944         /* set RLC_LB_ALWAYS_ACTIVE_CU_MASK = 0xFFF */
 945         WREG32_SOC15(GC, 0, mmRLC_LB_ALWAYS_ACTIVE_CU_MASK, 0xFFF);
 946
 947         /* set RLC_LB_CNTL = 0x8000_0095, 31 bit is reserved,
 948          * but used for RLC_LB_CNTL configuration */
 949         data = RLC_LB_CNTL__LB_CNT_SPIM_ACTIVE_MASK;
 950         data |= REG_SET_FIELD(data, RLC_LB_CNTL, CU_MASK_USED_OFF_HYST, 0x09);
 951         data |= REG_SET_FIELD(data, RLC_LB_CNTL, RESERVED, 0x80000);
 952         WREG32_SOC15(GC, 0, mmRLC_LB_CNTL, data);
 953         mutex_unlock(&adev->grbm_idx_mutex);
 954 }
 955
 956 static void gfx_v9_0_enable_lbpw(struct amdgpu_device *adev, bool enable)
 957 {
 958         WREG32_FIELD15(GC, 0, RLC_LB_CNTL, LOAD_BALANCE_ENABLE, enable ? 1 : 0);
 959 }
 960
 961 static void rv_init_cp_jump_table(struct amdgpu_device *adev)
 962 {
 963         const __le32 *fw_data;
 964         volatile u32 *dst_ptr;
 965         int me, i, max_me = 5;
 966         u32 bo_offset = 0;
 967         u32 table_offset, table_size;
 968
 969         /* write the cp table buffer */
 970         dst_ptr = adev->gfx.rlc.cp_table_ptr;
 971         for (me = 0; me < max_me; me++) {
 972                 if (me == 0) {
 973                         const struct gfx_firmware_header_v1_0 *hdr =
 974                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.ce_fw->data;
 975                         fw_data = (const __le32 *)
 976                                 (adev->gfx.ce_fw->data +
 977                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 978                         table_offset = le32_to_cpu(hdr->jt_offset);
 979                         table_size = le32_to_cpu(hdr->jt_size);
 980                 } else if (me == 1) {
 981                         const struct gfx_firmware_header_v1_0 *hdr =
 982                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.pfp_fw->data;
 983                         fw_data = (const __le32 *)
 984                                 (adev->gfx.pfp_fw->data +
 985                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 986                         table_offset = le32_to_cpu(hdr->jt_offset);
 987                         table_size = le32_to_cpu(hdr->jt_size);
 988                 } else if (me == 2) {
 989                         const struct gfx_firmware_header_v1_0 *hdr =
 990                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.me_fw->data;
 991                         fw_data = (const __le32 *)
 992                                 (adev->gfx.me_fw->data +
 993                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
 994                         table_offset = le32_to_cpu(hdr->jt_offset);
 995                         table_size = le32_to_cpu(hdr->jt_size);
 996                 } else if (me == 3) {
 997                         const struct gfx_firmware_header_v1_0 *hdr =
 998                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
 999                         fw_data = (const __le32 *)
1000                                 (adev->gfx.mec_fw->data +
1001                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1002                         table_offset = le32_to_cpu(hdr->jt_offset);
1003                         table_size = le32_to_cpu(hdr->jt_size);
1004                 } else  if (me == 4) {
1005                         const struct gfx_firmware_header_v1_0 *hdr =
1006                                 (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec2_fw->data;
1007                         fw_data = (const __le32 *)
1008                                 (adev->gfx.mec2_fw->data +
1009                                  le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1010                         table_offset = le32_to_cpu(hdr->jt_offset);
1011                         table_size = le32_to_cpu(hdr->jt_size);
1012                 }
1013
1014                 for (i = 0; i < table_size; i ++) {
1015                         dst_ptr[bo_offset + i] =
1016                                 cpu_to_le32(le32_to_cpu(fw_data[table_offset + i]));
1017                 }
1018
1019                 bo_offset += table_size;
1020         }
1021 }
1022
1023 static void gfx_v9_0_rlc_fini(struct amdgpu_device *adev)
1024 {
1025         /* clear state block */
1026         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
1027                         &adev->gfx.rlc.clear_state_gpu_addr,
1028                         (void **)&adev->gfx.rlc.cs_ptr);
1029
1030         /* jump table block */
1031         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
1032                         &adev->gfx.rlc.cp_table_gpu_addr,
1033                         (void **)&adev->gfx.rlc.cp_table_ptr);
1034 }
1035
1036 static int gfx_v9_0_rlc_init(struct amdgpu_device *adev)
1037 {
1038         volatile u32 *dst_ptr;
1039         u32 dws;
1040         const struct cs_section_def *cs_data;
1041         int r;
1042
1043         adev->gfx.rlc.cs_data = gfx9_cs_data;
1044
1045         cs_data = adev->gfx.rlc.cs_data;
1046
1047         if (cs_data) {
1048                 /* clear state block */
1049                 adev->gfx.rlc.clear_state_size = dws = gfx_v9_0_get_csb_size(adev);
1050                 r = amdgpu_bo_create_reserved(adev, dws * 4, PAGE_SIZE,
1051                                               AMDGPU_GEM_DOMAIN_VRAM,
1052                                               &adev->gfx.rlc.clear_state_obj,
1053                                               &adev->gfx.rlc.clear_state_gpu_addr,
1054                                               (void **)&adev->gfx.rlc.cs_ptr);
1055                 if (r) {
1056                         dev_err(adev->dev, "(%d) failed to create rlc csb bo\n",
1057                                 r);
1058                         gfx_v9_0_rlc_fini(adev);
1059                         return r;
1060                 }
1061                 /* set up the cs buffer */
1062                 dst_ptr = adev->gfx.rlc.cs_ptr;
1063                 gfx_v9_0_get_csb_buffer(adev, dst_ptr);
1064                 amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);
1065                 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
1066                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1067         }
1068
1069         if (adev->asic_type == CHIP_RAVEN) {
1070                 /* TODO: double check the cp_table_size for RV */
1071                 adev->gfx.rlc.cp_table_size = ALIGN(96 * 5 * 4, 2048) + (64 * 1024); /* JT + GDS */
1072                 r = amdgpu_bo_create_reserved(adev, adev->gfx.rlc.cp_table_size,
1073                                               PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1074                                               &adev->gfx.rlc.cp_table_obj,
1075                                               &adev->gfx.rlc.cp_table_gpu_addr,
1076                                               (void **)&adev->gfx.rlc.cp_table_ptr);
1077                 if (r) {
1078                         dev_err(adev->dev,
1079                                 "(%d) failed to create cp table bo\n", r);
1080                         gfx_v9_0_rlc_fini(adev);
1081                         return r;
1082                 }
1083
1084                 rv_init_cp_jump_table(adev);
1085                 amdgpu_bo_kunmap(adev->gfx.rlc.cp_table_obj);
1086                 amdgpu_bo_unreserve(adev->gfx.rlc.cp_table_obj);
1087
1088                 gfx_v9_0_init_lbpw(adev);
1089         }
1090
1091         return 0;
1092 }
1093
1094 static int gfx_v9_0_csb_vram_pin(struct amdgpu_device *adev)
1095 {
1096         int r;
1097
1098         r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, false);
1099         if (unlikely(r != 0))
1100                 return r;
1101
1102         r = amdgpu_bo_pin(adev->gfx.rlc.clear_state_obj,
1103                         AMDGPU_GEM_DOMAIN_VRAM);
1104         if (!r)
1105                 adev->gfx.rlc.clear_state_gpu_addr =
1106                         amdgpu_bo_gpu_offset(adev->gfx.rlc.clear_state_obj);
1107
1108         amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1109
1110         return r;
1111 }
1112
1113 static void gfx_v9_0_csb_vram_unpin(struct amdgpu_device *adev)
1114 {
1115         int r;
1116
1117         if (!adev->gfx.rlc.clear_state_obj)
1118                 return;
1119
1120         r = amdgpu_bo_reserve(adev->gfx.rlc.clear_state_obj, true);
1121         if (likely(r == 0)) {
1122                 amdgpu_bo_unpin(adev->gfx.rlc.clear_state_obj);
1123                 amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);
1124         }
1125 }
1126
1127 static void gfx_v9_0_mec_fini(struct amdgpu_device *adev)
1128 {
1129         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
1130         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
1131 }
1132
1133 static int gfx_v9_0_mec_init(struct amdgpu_device *adev)
1134 {
1135         int r;
1136         u32 *hpd;
1137         const __le32 *fw_data;
1138         unsigned fw_size;
1139         u32 *fw;
1140         size_t mec_hpd_size;
1141
1142         const struct gfx_firmware_header_v1_0 *mec_hdr;
1143
1144         bitmap_zero(adev->gfx.mec.queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
1145
1146         /* take ownership of the relevant compute queues */
1147         amdgpu_gfx_compute_queue_acquire(adev);
1148         mec_hpd_size = adev->gfx.num_compute_rings * GFX9_MEC_HPD_SIZE;
1149
1150         r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
1151                                       AMDGPU_GEM_DOMAIN_GTT,
1152                                       &adev->gfx.mec.hpd_eop_obj,
1153                                       &adev->gfx.mec.hpd_eop_gpu_addr,
1154                                       (void **)&hpd);
1155         if (r) {
1156                 dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
1157                 gfx_v9_0_mec_fini(adev);
1158                 return r;
1159         }
1160
1161         memset(hpd, 0, adev->gfx.mec.hpd_eop_obj->tbo.mem.size);
1162
1163         amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
1164         amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
1165
1166         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
1167
1168         fw_data = (const __le32 *)
1169                 (adev->gfx.mec_fw->data +
1170                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
1171         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes) / 4;
1172
1173         r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
1174                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
1175                                       &adev->gfx.mec.mec_fw_obj,
1176                                       &adev->gfx.mec.mec_fw_gpu_addr,
1177                                       (void **)&fw);
1178         if (r) {
1179                 dev_warn(adev->dev, "(%d) create mec firmware bo failed\n", r);
1180                 gfx_v9_0_mec_fini(adev);
1181                 return r;
1182         }
1183
1184         memcpy(fw, fw_data, fw_size);
1185
1186         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
1187         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
1188
1189         return 0;
1190 }
1191
1192 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t address)
1193 {
1194         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1195                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1196                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1197                 (address << SQ_IND_INDEX__INDEX__SHIFT) |
1198                 (SQ_IND_INDEX__FORCE_READ_MASK));
1199         return RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1200 }
1201
1202 static void wave_read_regs(struct amdgpu_device *adev, uint32_t simd,
1203                            uint32_t wave, uint32_t thread,
1204                            uint32_t regno, uint32_t num, uint32_t *out)
1205 {
1206         WREG32_SOC15(GC, 0, mmSQ_IND_INDEX,
1207                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
1208                 (simd << SQ_IND_INDEX__SIMD_ID__SHIFT) |
1209                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
1210                 (thread << SQ_IND_INDEX__THREAD_ID__SHIFT) |
1211                 (SQ_IND_INDEX__FORCE_READ_MASK) |
1212                 (SQ_IND_INDEX__AUTO_INCR_MASK));
1213         while (num--)
1214                 *(out++) = RREG32_SOC15(GC, 0, mmSQ_IND_DATA);
1215 }
1216
1217 static void gfx_v9_0_read_wave_data(struct amdgpu_device *adev, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
1218 {
1219         /* type 1 wave data */
1220         dst[(*no_fields)++] = 1;
1221         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_STATUS);
1222         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_LO);
1223         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_PC_HI);
1224         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_LO);
1225         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_EXEC_HI);
1226         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_HW_ID);
1227         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW0);
1228         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_INST_DW1);
1229         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_GPR_ALLOC);
1230         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_LDS_ALLOC);
1231         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_TRAPSTS);
1232         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_STS);
1233         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_IB_DBG0);
1234         dst[(*no_fields)++] = wave_read_ind(adev, simd, wave, ixSQ_WAVE_M0);
1235 }
1236
1237 static void gfx_v9_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t simd,
1238                                      uint32_t wave, uint32_t start,
1239                                      uint32_t size, uint32_t *dst)
1240 {
1241         wave_read_regs(
1242                 adev, simd, wave, 0,
1243                 start + SQIND_WAVE_SGPRS_OFFSET, size, dst);
1244 }
1245
1246 static void gfx_v9_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t simd,
1247                                      uint32_t wave, uint32_t thread,
1248                                      uint32_t start, uint32_t size,
1249                                      uint32_t *dst)
1250 {
1251         wave_read_regs(
1252                 adev, simd, wave, thread,
1253                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
1254 }
1255
1256 static void gfx_v9_0_select_me_pipe_q(struct amdgpu_device *adev,
1257                                   u32 me, u32 pipe, u32 q)
1258 {
1259         soc15_grbm_select(adev, me, pipe, q, 0);
1260 }
1261
1262 static const struct amdgpu_gfx_funcs gfx_v9_0_gfx_funcs = {
1263         .get_gpu_clock_counter = &gfx_v9_0_get_gpu_clock_counter,
1264         .select_se_sh = &gfx_v9_0_select_se_sh,
1265         .read_wave_data = &gfx_v9_0_read_wave_data,
1266         .read_wave_sgprs = &gfx_v9_0_read_wave_sgprs,
1267         .read_wave_vgprs = &gfx_v9_0_read_wave_vgprs,
1268         .select_me_pipe_q = &gfx_v9_0_select_me_pipe_q
1269 };
1270
1271 static int gfx_v9_0_gpu_early_init(struct amdgpu_device *adev)
1272 {
1273         u32 gb_addr_config;
1274         int err;
1275
1276         adev->gfx.funcs = &gfx_v9_0_gfx_funcs;
1277
1278         switch (adev->asic_type) {
1279         case CHIP_VEGA10:
1280                 adev->gfx.config.max_hw_contexts = 8;
1281                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1282                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1283                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1284                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1285                 gb_addr_config = VEGA10_GB_ADDR_CONFIG_GOLDEN;
1286                 break;
1287         case CHIP_VEGA12:
1288                 adev->gfx.config.max_hw_contexts = 8;
1289                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1290                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1291                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1292                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1293                 gb_addr_config = VEGA12_GB_ADDR_CONFIG_GOLDEN;
1294                 DRM_INFO("fix gfx.config for vega12\n");
1295                 break;
1296         case CHIP_VEGA20:
1297                 adev->gfx.config.max_hw_contexts = 8;
1298                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1299                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1300                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1301                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1302                 gb_addr_config = RREG32_SOC15(GC, 0, mmGB_ADDR_CONFIG);
1303                 gb_addr_config &= ~0xf3e777ff;
1304                 gb_addr_config |= 0x22014042;
1305                 /* check vbios table if gpu info is not available */
1306                 err = amdgpu_atomfirmware_get_gfx_info(adev);
1307                 if (err)
1308                         return err;
1309                 break;
1310         case CHIP_RAVEN:
1311                 adev->gfx.config.max_hw_contexts = 8;
1312                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
1313                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
1314                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x30;
1315                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
1316                 if (adev->rev_id >= 8)
1317                         gb_addr_config = RAVEN2_GB_ADDR_CONFIG_GOLDEN;
1318                 else
1319                         gb_addr_config = RAVEN_GB_ADDR_CONFIG_GOLDEN;
1320                 break;
1321         default:
1322                 BUG();
1323                 break;
1324         }
1325
1326         adev->gfx.config.gb_addr_config = gb_addr_config;
1327
1328         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
1329                         REG_GET_FIELD(
1330                                         adev->gfx.config.gb_addr_config,
1331                                         GB_ADDR_CONFIG,
1332                                         NUM_PIPES);
1333
1334         adev->gfx.config.max_tile_pipes =
1335                 adev->gfx.config.gb_addr_config_fields.num_pipes;
1336
1337         adev->gfx.config.gb_addr_config_fields.num_banks = 1 <<
1338                         REG_GET_FIELD(
1339                                         adev->gfx.config.gb_addr_config,
1340                                         GB_ADDR_CONFIG,
1341                                         NUM_BANKS);
1342         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
1343                         REG_GET_FIELD(
1344                                         adev->gfx.config.gb_addr_config,
1345                                         GB_ADDR_CONFIG,
1346                                         MAX_COMPRESSED_FRAGS);
1347         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
1348                         REG_GET_FIELD(
1349                                         adev->gfx.config.gb_addr_config,
1350                                         GB_ADDR_CONFIG,
1351                                         NUM_RB_PER_SE);
1352         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
1353                         REG_GET_FIELD(
1354                                         adev->gfx.config.gb_addr_config,
1355                                         GB_ADDR_CONFIG,
1356                                         NUM_SHADER_ENGINES);
1357         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
1358                         REG_GET_FIELD(
1359                                         adev->gfx.config.gb_addr_config,
1360                                         GB_ADDR_CONFIG,
1361                                         PIPE_INTERLEAVE_SIZE));
1362
1363         return 0;
1364 }
1365
1366 static int gfx_v9_0_ngg_create_buf(struct amdgpu_device *adev,
1367                                    struct amdgpu_ngg_buf *ngg_buf,
1368                                    int size_se,
1369                                    int default_size_se)
1370 {
1371         int r;
1372
1373         if (size_se < 0) {
1374                 dev_err(adev->dev, "Buffer size is invalid: %d\n", size_se);
1375                 return -EINVAL;
1376         }
1377         size_se = size_se ? size_se : default_size_se;
1378
1379         ngg_buf->size = size_se * adev->gfx.config.max_shader_engines;
1380         r = amdgpu_bo_create_kernel(adev, ngg_buf->size,
1381                                     PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
1382                                     &ngg_buf->bo,
1383                                     &ngg_buf->gpu_addr,
1384                                     NULL);
1385         if (r) {
1386                 dev_err(adev->dev, "(%d) failed to create NGG buffer\n", r);
1387                 return r;
1388         }
1389         ngg_buf->bo_size = amdgpu_bo_size(ngg_buf->bo);
1390
1391         return r;
1392 }
1393
1394 static int gfx_v9_0_ngg_fini(struct amdgpu_device *adev)
1395 {
1396         int i;
1397
1398         for (i = 0; i < NGG_BUF_MAX; i++)
1399                 amdgpu_bo_free_kernel(&adev->gfx.ngg.buf[i].bo,
1400                                       &adev->gfx.ngg.buf[i].gpu_addr,
1401                                       NULL);
1402
1403         memset(&adev->gfx.ngg.buf[0], 0,
1404                         sizeof(struct amdgpu_ngg_buf) * NGG_BUF_MAX);
1405
1406         adev->gfx.ngg.init = false;
1407
1408         return 0;
1409 }
1410
1411 static int gfx_v9_0_ngg_init(struct amdgpu_device *adev)
1412 {
1413         int r;
1414
1415         if (!amdgpu_ngg || adev->gfx.ngg.init == true)
1416                 return 0;
1417
1418         /* GDS reserve memory: 64 bytes alignment */
1419         adev->gfx.ngg.gds_reserve_size = ALIGN(5 * 4, 0x40);
1420         adev->gds.mem.total_size -= adev->gfx.ngg.gds_reserve_size;
1421         adev->gds.mem.gfx_partition_size -= adev->gfx.ngg.gds_reserve_size;
1422         adev->gfx.ngg.gds_reserve_addr = RREG32_SOC15(GC, 0, mmGDS_VMID0_BASE);
1423         adev->gfx.ngg.gds_reserve_addr += RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
1424
1425         /* Primitive Buffer */
1426         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PRIM],
1427                                     amdgpu_prim_buf_per_se,
1428                                     64 * 1024);
1429         if (r) {
1430                 dev_err(adev->dev, "Failed to create Primitive Buffer\n");
1431                 goto err;
1432         }
1433
1434         /* Position Buffer */
1435         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_POS],
1436                                     amdgpu_pos_buf_per_se,
1437                                     256 * 1024);
1438         if (r) {
1439                 dev_err(adev->dev, "Failed to create Position Buffer\n");
1440                 goto err;
1441         }
1442
1443         /* Control Sideband */
1444         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_CNTL],
1445                                     amdgpu_cntl_sb_buf_per_se,
1446                                     256);
1447         if (r) {
1448                 dev_err(adev->dev, "Failed to create Control Sideband Buffer\n");
1449                 goto err;
1450         }
1451
1452         /* Parameter Cache, not created by default */
1453         if (amdgpu_param_buf_per_se <= 0)
1454                 goto out;
1455
1456         r = gfx_v9_0_ngg_create_buf(adev, &adev->gfx.ngg.buf[NGG_PARAM],
1457                                     amdgpu_param_buf_per_se,
1458                                     512 * 1024);
1459         if (r) {
1460                 dev_err(adev->dev, "Failed to create Parameter Cache\n");
1461                 goto err;
1462         }
1463
1464 out:
1465         adev->gfx.ngg.init = true;
1466         return 0;
1467 err:
1468         gfx_v9_0_ngg_fini(adev);
1469         return r;
1470 }
1471
1472 static int gfx_v9_0_ngg_en(struct amdgpu_device *adev)
1473 {
1474         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
1475         int r;
1476         u32 data, base;
1477
1478         if (!amdgpu_ngg)
1479                 return 0;
1480
1481         /* Program buffer size */
1482         data = REG_SET_FIELD(0, WD_BUF_RESOURCE_1, INDEX_BUF_SIZE,
1483                              adev->gfx.ngg.buf[NGG_PRIM].size >> 8);
1484         data = REG_SET_FIELD(data, WD_BUF_RESOURCE_1, POS_BUF_SIZE,
1485                              adev->gfx.ngg.buf[NGG_POS].size >> 8);
1486         WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_1, data);
1487
1488         data = REG_SET_FIELD(0, WD_BUF_RESOURCE_2, CNTL_SB_BUF_SIZE,
1489                              adev->gfx.ngg.buf[NGG_CNTL].size >> 8);
1490         data = REG_SET_FIELD(data, WD_BUF_RESOURCE_2, PARAM_BUF_SIZE,
1491                              adev->gfx.ngg.buf[NGG_PARAM].size >> 10);
1492         WREG32_SOC15(GC, 0, mmWD_BUF_RESOURCE_2, data);
1493
1494         /* Program buffer base address */
1495         base = lower_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
1496         data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE, BASE, base);
1497         WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE, data);
1498
1499         base = upper_32_bits(adev->gfx.ngg.buf[NGG_PRIM].gpu_addr);
1500         data = REG_SET_FIELD(0, WD_INDEX_BUF_BASE_HI, BASE_HI, base);
1501         WREG32_SOC15(GC, 0, mmWD_INDEX_BUF_BASE_HI, data);
1502
1503         base = lower_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
1504         data = REG_SET_FIELD(0, WD_POS_BUF_BASE, BASE, base);
1505         WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE, data);
1506
1507         base = upper_32_bits(adev->gfx.ngg.buf[NGG_POS].gpu_addr);
1508         data = REG_SET_FIELD(0, WD_POS_BUF_BASE_HI, BASE_HI, base);
1509         WREG32_SOC15(GC, 0, mmWD_POS_BUF_BASE_HI, data);
1510
1511         base = lower_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
1512         data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE, BASE, base);
1513         WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE, data);
1514
1515         base = upper_32_bits(adev->gfx.ngg.buf[NGG_CNTL].gpu_addr);
1516         data = REG_SET_FIELD(0, WD_CNTL_SB_BUF_BASE_HI, BASE_HI, base);
1517         WREG32_SOC15(GC, 0, mmWD_CNTL_SB_BUF_BASE_HI, data);
1518
1519         /* Clear GDS reserved memory */
1520         r = amdgpu_ring_alloc(ring, 17);
1521         if (r) {
1522                 DRM_ERROR("amdgpu: NGG failed to lock ring %d (%d).\n",
1523                           ring->idx, r);
1524                 return r;
1525         }
1526
1527         gfx_v9_0_write_data_to_reg(ring, 0, false,
1528                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE),
1529                                    (adev->gds.mem.total_size +
1530                                     adev->gfx.ngg.gds_reserve_size));
1531
1532         amdgpu_ring_write(ring, PACKET3(PACKET3_DMA_DATA, 5));
1533         amdgpu_ring_write(ring, (PACKET3_DMA_DATA_CP_SYNC |
1534                                 PACKET3_DMA_DATA_DST_SEL(1) |
1535                                 PACKET3_DMA_DATA_SRC_SEL(2)));
1536         amdgpu_ring_write(ring, 0);
1537         amdgpu_ring_write(ring, 0);
1538         amdgpu_ring_write(ring, adev->gfx.ngg.gds_reserve_addr);
1539         amdgpu_ring_write(ring, 0);
1540         amdgpu_ring_write(ring, PACKET3_DMA_DATA_CMD_RAW_WAIT |
1541                                 adev->gfx.ngg.gds_reserve_size);
1542
1543         gfx_v9_0_write_data_to_reg(ring, 0, false,
1544                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE), 0);
1545
1546         amdgpu_ring_commit(ring);
1547
1548         return 0;
1549 }
1550
1551 static int gfx_v9_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
1552                                       int mec, int pipe, int queue)
1553 {
1554         int r;
1555         unsigned irq_type;
1556         struct amdgpu_ring *ring = &adev->gfx.compute_ring[ring_id];
1557
1558         ring = &adev->gfx.compute_ring[ring_id];
1559
1560         /* mec0 is me1 */
1561         ring->me = mec + 1;
1562         ring->pipe = pipe;
1563         ring->queue = queue;
1564
1565         ring->ring_obj = NULL;
1566         ring->use_doorbell = true;
1567         ring->doorbell_index = (AMDGPU_DOORBELL_MEC_RING0 + ring_id) << 1;
1568         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
1569                                 + (ring_id * GFX9_MEC_HPD_SIZE);
1570         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
1571
1572         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1573                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1574                 + ring->pipe;
1575
1576         /* type-2 packets are deprecated on MEC, use type-3 instead */
1577         r = amdgpu_ring_init(adev, ring, 1024,
1578                              &adev->gfx.eop_irq, irq_type);
1579         if (r)
1580                 return r;
1581
1582
1583         return 0;
1584 }
1585
1586 static int gfx_v9_0_sw_init(void *handle)
1587 {
1588         int i, j, k, r, ring_id;
1589         struct amdgpu_ring *ring;
1590         struct amdgpu_kiq *kiq;
1591         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1592
1593         switch (adev->asic_type) {
1594         case CHIP_VEGA10:
1595         case CHIP_VEGA12:
1596         case CHIP_VEGA20:
1597         case CHIP_RAVEN:
1598                 adev->gfx.mec.num_mec = 2;
1599                 break;
1600         default:
1601                 adev->gfx.mec.num_mec = 1;
1602                 break;
1603         }
1604
1605         adev->gfx.mec.num_pipe_per_mec = 4;
1606         adev->gfx.mec.num_queue_per_pipe = 8;
1607
1608         /* KIQ event */
1609         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_IB2_INTERRUPT_PKT, &adev->gfx.kiq.irq);
1610         if (r)
1611                 return r;
1612
1613         /* EOP Event */
1614         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_EOP_INTERRUPT, &adev->gfx.eop_irq);
1615         if (r)
1616                 return r;
1617
1618         /* Privileged reg */
1619         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_REG_FAULT,
1620                               &adev->gfx.priv_reg_irq);
1621         if (r)
1622                 return r;
1623
1624         /* Privileged inst */
1625         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_GRBM_CP, GFX_9_0__SRCID__CP_PRIV_INSTR_FAULT,
1626                               &adev->gfx.priv_inst_irq);
1627         if (r)
1628                 return r;
1629
1630         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1631
1632         gfx_v9_0_scratch_init(adev);
1633
1634         r = gfx_v9_0_init_microcode(adev);
1635         if (r) {
1636                 DRM_ERROR("Failed to load gfx firmware!\n");
1637                 return r;
1638         }
1639
1640         r = gfx_v9_0_rlc_init(adev);
1641         if (r) {
1642                 DRM_ERROR("Failed to init rlc BOs!\n");
1643                 return r;
1644         }
1645
1646         r = gfx_v9_0_mec_init(adev);
1647         if (r) {
1648                 DRM_ERROR("Failed to init MEC BOs!\n");
1649                 return r;
1650         }
1651
1652         /* set up the gfx ring */
1653         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
1654                 ring = &adev->gfx.gfx_ring[i];
1655                 ring->ring_obj = NULL;
1656                 if (!i)
1657                         sprintf(ring->name, "gfx");
1658                 else
1659                         sprintf(ring->name, "gfx_%d", i);
1660                 ring->use_doorbell = true;
1661                 ring->doorbell_index = AMDGPU_DOORBELL64_GFX_RING0 << 1;
1662                 r = amdgpu_ring_init(adev, ring, 1024,
1663                                      &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
1664                 if (r)
1665                         return r;
1666         }
1667
1668         /* set up the compute queues - allocate horizontally across pipes */
1669         ring_id = 0;
1670         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1671                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1672                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1673                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j))
1674                                         continue;
1675
1676                                 r = gfx_v9_0_compute_ring_init(adev,
1677                                                                ring_id,
1678                                                                i, k, j);
1679                                 if (r)
1680                                         return r;
1681
1682                                 ring_id++;
1683                         }
1684                 }
1685         }
1686
1687         r = amdgpu_gfx_kiq_init(adev, GFX9_MEC_HPD_SIZE);
1688         if (r) {
1689                 DRM_ERROR("Failed to init KIQ BOs!\n");
1690                 return r;
1691         }
1692
1693         kiq = &adev->gfx.kiq;
1694         r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
1695         if (r)
1696                 return r;
1697
1698         /* create MQD for all compute queues as wel as KIQ for SRIOV case */
1699         r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct v9_mqd_allocation));
1700         if (r)
1701                 return r;
1702
1703         adev->gfx.ce_ram_size = 0x8000;
1704
1705         r = gfx_v9_0_gpu_early_init(adev);
1706         if (r)
1707                 return r;
1708
1709         r = gfx_v9_0_ngg_init(adev);
1710         if (r)
1711                 return r;
1712
1713         return 0;
1714 }
1715
1716
1717 static int gfx_v9_0_sw_fini(void *handle)
1718 {
1719         int i;
1720         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1721
1722         amdgpu_bo_free_kernel(&adev->gds.oa_gfx_bo, NULL, NULL);
1723         amdgpu_bo_free_kernel(&adev->gds.gws_gfx_bo, NULL, NULL);
1724         amdgpu_bo_free_kernel(&adev->gds.gds_gfx_bo, NULL, NULL);
1725
1726         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1727                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1728         for (i = 0; i < adev->gfx.num_compute_rings; i++)
1729                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1730
1731         amdgpu_gfx_compute_mqd_sw_fini(adev);
1732         amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq.ring, &adev->gfx.kiq.irq);
1733         amdgpu_gfx_kiq_fini(adev);
1734
1735         gfx_v9_0_mec_fini(adev);
1736         gfx_v9_0_ngg_fini(adev);
1737         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
1738                                 &adev->gfx.rlc.clear_state_gpu_addr,
1739                                 (void **)&adev->gfx.rlc.cs_ptr);
1740         if (adev->asic_type == CHIP_RAVEN) {
1741                 amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
1742                                 &adev->gfx.rlc.cp_table_gpu_addr,
1743                                 (void **)&adev->gfx.rlc.cp_table_ptr);
1744         }
1745         gfx_v9_0_free_microcode(adev);
1746
1747         return 0;
1748 }
1749
1750
1751 static void gfx_v9_0_tiling_mode_table_init(struct amdgpu_device *adev)
1752 {
1753         /* TODO */
1754 }
1755
1756 static void gfx_v9_0_select_se_sh(struct amdgpu_device *adev, u32 se_num, u32 sh_num, u32 instance)
1757 {
1758         u32 data;
1759
1760         if (instance == 0xffffffff)
1761                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_BROADCAST_WRITES, 1);
1762         else
1763                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX, instance);
1764
1765         if (se_num == 0xffffffff)
1766                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES, 1);
1767         else
1768                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1769
1770         if (sh_num == 0xffffffff)
1771                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_BROADCAST_WRITES, 1);
1772         else
1773                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SH_INDEX, sh_num);
1774
1775         WREG32_SOC15(GC, 0, mmGRBM_GFX_INDEX, data);
1776 }
1777
1778 static u32 gfx_v9_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1779 {
1780         u32 data, mask;
1781
1782         data = RREG32_SOC15(GC, 0, mmCC_RB_BACKEND_DISABLE);
1783         data |= RREG32_SOC15(GC, 0, mmGC_USER_RB_BACKEND_DISABLE);
1784
1785         data &= CC_RB_BACKEND_DISABLE__BACKEND_DISABLE_MASK;
1786         data >>= GC_USER_RB_BACKEND_DISABLE__BACKEND_DISABLE__SHIFT;
1787
1788         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se /
1789                                          adev->gfx.config.max_sh_per_se);
1790
1791         return (~data) & mask;
1792 }
1793
1794 static void gfx_v9_0_setup_rb(struct amdgpu_device *adev)
1795 {
1796         int i, j;
1797         u32 data;
1798         u32 active_rbs = 0;
1799         u32 rb_bitmap_width_per_sh = adev->gfx.config.max_backends_per_se /
1800                                         adev->gfx.config.max_sh_per_se;
1801
1802         mutex_lock(&adev->grbm_idx_mutex);
1803         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1804                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1805                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1806                         data = gfx_v9_0_get_rb_active_bitmap(adev);
1807                         active_rbs |= data << ((i * adev->gfx.config.max_sh_per_se + j) *
1808                                                rb_bitmap_width_per_sh);
1809                 }
1810         }
1811         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1812         mutex_unlock(&adev->grbm_idx_mutex);
1813
1814         adev->gfx.config.backend_enable_mask = active_rbs;
1815         adev->gfx.config.num_rbs = hweight32(active_rbs);
1816 }
1817
1818 #define DEFAULT_SH_MEM_BASES    (0x6000)
1819 #define FIRST_COMPUTE_VMID      (8)
1820 #define LAST_COMPUTE_VMID       (16)
1821 static void gfx_v9_0_init_compute_vmid(struct amdgpu_device *adev)
1822 {
1823         int i;
1824         uint32_t sh_mem_config;
1825         uint32_t sh_mem_bases;
1826
1827         /*
1828          * Configure apertures:
1829          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1830          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1831          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1832          */
1833         sh_mem_bases = DEFAULT_SH_MEM_BASES | (DEFAULT_SH_MEM_BASES << 16);
1834
1835         sh_mem_config = SH_MEM_ADDRESS_MODE_64 |
1836                         SH_MEM_ALIGNMENT_MODE_UNALIGNED <<
1837                         SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT;
1838
1839         mutex_lock(&adev->srbm_mutex);
1840         for (i = FIRST_COMPUTE_VMID; i < LAST_COMPUTE_VMID; i++) {
1841                 soc15_grbm_select(adev, 0, 0, 0, i);
1842                 /* CP and shaders */
1843                 WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, sh_mem_config);
1844                 WREG32_SOC15(GC, 0, mmSH_MEM_BASES, sh_mem_bases);
1845         }
1846         soc15_grbm_select(adev, 0, 0, 0, 0);
1847         mutex_unlock(&adev->srbm_mutex);
1848 }
1849
1850 static void gfx_v9_0_gpu_init(struct amdgpu_device *adev)
1851 {
1852         u32 tmp;
1853         int i;
1854
1855         WREG32_FIELD15(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1856
1857         gfx_v9_0_tiling_mode_table_init(adev);
1858
1859         gfx_v9_0_setup_rb(adev);
1860         gfx_v9_0_get_cu_info(adev, &adev->gfx.cu_info);
1861         adev->gfx.config.db_debug2 = RREG32_SOC15(GC, 0, mmDB_DEBUG2);
1862
1863         /* XXX SH_MEM regs */
1864         /* where to put LDS, scratch, GPUVM in FSA64 space */
1865         mutex_lock(&adev->srbm_mutex);
1866         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB].num_ids; i++) {
1867                 soc15_grbm_select(adev, 0, 0, 0, i);
1868                 /* CP and shaders */
1869                 if (i == 0) {
1870                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1871                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1872                         WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1873                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, 0);
1874                 } else {
1875                         tmp = REG_SET_FIELD(0, SH_MEM_CONFIG, ALIGNMENT_MODE,
1876                                             SH_MEM_ALIGNMENT_MODE_UNALIGNED);
1877                         WREG32_SOC15(GC, 0, mmSH_MEM_CONFIG, tmp);
1878                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1879                                 (adev->gmc.private_aperture_start >> 48));
1880                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1881                                 (adev->gmc.shared_aperture_start >> 48));
1882                         WREG32_SOC15(GC, 0, mmSH_MEM_BASES, tmp);
1883                 }
1884         }
1885         soc15_grbm_select(adev, 0, 0, 0, 0);
1886
1887         mutex_unlock(&adev->srbm_mutex);
1888
1889         gfx_v9_0_init_compute_vmid(adev);
1890
1891         mutex_lock(&adev->grbm_idx_mutex);
1892         /*
1893          * making sure that the following register writes will be broadcasted
1894          * to all the shaders
1895          */
1896         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1897
1898         WREG32_SOC15(GC, 0, mmPA_SC_FIFO_SIZE,
1899                    (adev->gfx.config.sc_prim_fifo_size_frontend <<
1900                         PA_SC_FIFO_SIZE__SC_FRONTEND_PRIM_FIFO_SIZE__SHIFT) |
1901                    (adev->gfx.config.sc_prim_fifo_size_backend <<
1902                         PA_SC_FIFO_SIZE__SC_BACKEND_PRIM_FIFO_SIZE__SHIFT) |
1903                    (adev->gfx.config.sc_hiz_tile_fifo_size <<
1904                         PA_SC_FIFO_SIZE__SC_HIZ_TILE_FIFO_SIZE__SHIFT) |
1905                    (adev->gfx.config.sc_earlyz_tile_fifo_size <<
1906                         PA_SC_FIFO_SIZE__SC_EARLYZ_TILE_FIFO_SIZE__SHIFT));
1907         mutex_unlock(&adev->grbm_idx_mutex);
1908
1909 }
1910
1911 static void gfx_v9_0_wait_for_rlc_serdes(struct amdgpu_device *adev)
1912 {
1913         u32 i, j, k;
1914         u32 mask;
1915
1916         mutex_lock(&adev->grbm_idx_mutex);
1917         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
1918                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
1919                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
1920                         for (k = 0; k < adev->usec_timeout; k++) {
1921                                 if (RREG32_SOC15(GC, 0, mmRLC_SERDES_CU_MASTER_BUSY) == 0)
1922                                         break;
1923                                 udelay(1);
1924                         }
1925                         if (k == adev->usec_timeout) {
1926                                 gfx_v9_0_select_se_sh(adev, 0xffffffff,
1927                                                       0xffffffff, 0xffffffff);
1928                                 mutex_unlock(&adev->grbm_idx_mutex);
1929                                 DRM_INFO("Timeout wait for RLC serdes %u,%u\n",
1930                                          i, j);
1931                                 return;
1932                         }
1933                 }
1934         }
1935         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
1936         mutex_unlock(&adev->grbm_idx_mutex);
1937
1938         mask = RLC_SERDES_NONCU_MASTER_BUSY__SE_MASTER_BUSY_MASK |
1939                 RLC_SERDES_NONCU_MASTER_BUSY__GC_MASTER_BUSY_MASK |
1940                 RLC_SERDES_NONCU_MASTER_BUSY__TC0_MASTER_BUSY_MASK |
1941                 RLC_SERDES_NONCU_MASTER_BUSY__TC1_MASTER_BUSY_MASK;
1942         for (k = 0; k < adev->usec_timeout; k++) {
1943                 if ((RREG32_SOC15(GC, 0, mmRLC_SERDES_NONCU_MASTER_BUSY) & mask) == 0)
1944                         break;
1945                 udelay(1);
1946         }
1947 }
1948
1949 static void gfx_v9_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1950                                                bool enable)
1951 {
1952         u32 tmp = RREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0);
1953
1954         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE, enable ? 1 : 0);
1955         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE, enable ? 1 : 0);
1956         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE, enable ? 1 : 0);
1957         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE, enable ? 1 : 0);
1958
1959         WREG32_SOC15(GC, 0, mmCP_INT_CNTL_RING0, tmp);
1960 }
1961
1962 static void gfx_v9_0_init_csb(struct amdgpu_device *adev)
1963 {
1964         /* csib */
1965         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_HI),
1966                         adev->gfx.rlc.clear_state_gpu_addr >> 32);
1967         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_ADDR_LO),
1968                         adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1969         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_CSIB_LENGTH),
1970                         adev->gfx.rlc.clear_state_size);
1971 }
1972
1973 static void gfx_v9_1_parse_ind_reg_list(int *register_list_format,
1974                                 int indirect_offset,
1975                                 int list_size,
1976                                 int *unique_indirect_regs,
1977                                 int unique_indirect_reg_count,
1978                                 int *indirect_start_offsets,
1979                                 int *indirect_start_offsets_count,
1980                                 int max_start_offsets_count)
1981 {
1982         int idx;
1983
1984         for (; indirect_offset < list_size; indirect_offset++) {
1985                 WARN_ON(*indirect_start_offsets_count >= max_start_offsets_count);
1986                 indirect_start_offsets[*indirect_start_offsets_count] = indirect_offset;
1987                 *indirect_start_offsets_count = *indirect_start_offsets_count + 1;
1988
1989                 while (register_list_format[indirect_offset] != 0xFFFFFFFF) {
1990                         indirect_offset += 2;
1991
1992                         /* look for the matching indice */
1993                         for (idx = 0; idx < unique_indirect_reg_count; idx++) {
1994                                 if (unique_indirect_regs[idx] ==
1995                                         register_list_format[indirect_offset] ||
1996                                         !unique_indirect_regs[idx])
1997                                         break;
1998                         }
1999
2000                         BUG_ON(idx >= unique_indirect_reg_count);
2001
2002                         if (!unique_indirect_regs[idx])
2003                                 unique_indirect_regs[idx] = register_list_format[indirect_offset];
2004
2005                         indirect_offset++;
2006                 }
2007         }
2008 }
2009
2010 static int gfx_v9_1_init_rlc_save_restore_list(struct amdgpu_device *adev)
2011 {
2012         int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
2013         int unique_indirect_reg_count = 0;
2014
2015         int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
2016         int indirect_start_offsets_count = 0;
2017
2018         int list_size = 0;
2019         int i = 0, j = 0;
2020         u32 tmp = 0;
2021
2022         u32 *register_list_format =
2023                 kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
2024         if (!register_list_format)
2025                 return -ENOMEM;
2026         memcpy(register_list_format, adev->gfx.rlc.register_list_format,
2027                 adev->gfx.rlc.reg_list_format_size_bytes);
2028
2029         /* setup unique_indirect_regs array and indirect_start_offsets array */
2030         unique_indirect_reg_count = ARRAY_SIZE(unique_indirect_regs);
2031         gfx_v9_1_parse_ind_reg_list(register_list_format,
2032                                     adev->gfx.rlc.reg_list_format_direct_reg_list_length,
2033                                     adev->gfx.rlc.reg_list_format_size_bytes >> 2,
2034                                     unique_indirect_regs,
2035                                     unique_indirect_reg_count,
2036                                     indirect_start_offsets,
2037                                     &indirect_start_offsets_count,
2038                                     ARRAY_SIZE(indirect_start_offsets));
2039
2040         /* enable auto inc in case it is disabled */
2041         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
2042         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
2043         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
2044
2045         /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */
2046         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR),
2047                 RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET);
2048         for (i = 0; i < adev->gfx.rlc.reg_list_size_bytes >> 2; i++)
2049                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA),
2050                         adev->gfx.rlc.register_restore[i]);
2051
2052         /* load indirect register */
2053         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
2054                 adev->gfx.rlc.reg_list_format_start);
2055
2056         /* direct register portion */
2057         for (i = 0; i < adev->gfx.rlc.reg_list_format_direct_reg_list_length; i++)
2058                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
2059                         register_list_format[i]);
2060
2061         /* indirect register portion */
2062         while (i < (adev->gfx.rlc.reg_list_format_size_bytes >> 2)) {
2063                 if (register_list_format[i] == 0xFFFFFFFF) {
2064                         WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
2065                         continue;
2066                 }
2067
2068                 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
2069                 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, register_list_format[i++]);
2070
2071                 for (j = 0; j < unique_indirect_reg_count; j++) {
2072                         if (register_list_format[i] == unique_indirect_regs[j]) {
2073                                 WREG32_SOC15(GC, 0, mmRLC_GPM_SCRATCH_DATA, j);
2074                                 break;
2075                         }
2076                 }
2077
2078                 BUG_ON(j >= unique_indirect_reg_count);
2079
2080                 i++;
2081         }
2082
2083         /* set save/restore list size */
2084         list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
2085         list_size = list_size >> 1;
2086         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
2087                 adev->gfx.rlc.reg_restore_list_size);
2088         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
2089
2090         /* write the starting offsets to RLC scratch ram */
2091         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR),
2092                 adev->gfx.rlc.starting_offsets_start);
2093         for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)
2094                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA),
2095                        indirect_start_offsets[i]);
2096
2097         /* load unique indirect regs*/
2098         for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) {
2099                 if (unique_indirect_regs[i] != 0) {
2100                         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0)
2101                                + GFX_RLC_SRM_INDEX_CNTL_ADDR_OFFSETS[i],
2102                                unique_indirect_regs[i] & 0x3FFFF);
2103
2104                         WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0)
2105                                + GFX_RLC_SRM_INDEX_CNTL_DATA_OFFSETS[i],
2106                                unique_indirect_regs[i] >> 20);
2107                 }
2108         }
2109
2110         kfree(register_list_format);
2111         return 0;
2112 }
2113
2114 static void gfx_v9_0_enable_save_restore_machine(struct amdgpu_device *adev)
2115 {
2116         WREG32_FIELD15(GC, 0, RLC_SRM_CNTL, SRM_ENABLE, 1);
2117 }
2118
2119 static void pwr_10_0_gfxip_control_over_cgpg(struct amdgpu_device *adev,
2120                                              bool enable)
2121 {
2122         uint32_t data = 0;
2123         uint32_t default_data = 0;
2124
2125         default_data = data = RREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS));
2126         if (enable == true) {
2127                 /* enable GFXIP control over CGPG */
2128                 data |= PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
2129                 if(default_data != data)
2130                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2131
2132                 /* update status */
2133                 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS_MASK;
2134                 data |= (2 << PWR_MISC_CNTL_STATUS__PWR_GFXOFF_STATUS__SHIFT);
2135                 if(default_data != data)
2136                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2137         } else {
2138                 /* restore GFXIP control over GCPG */
2139                 data &= ~PWR_MISC_CNTL_STATUS__PWR_GFX_RLC_CGPG_EN_MASK;
2140                 if(default_data != data)
2141                         WREG32(SOC15_REG_OFFSET(PWR, 0, mmPWR_MISC_CNTL_STATUS), data);
2142         }
2143 }
2144
2145 static void gfx_v9_0_init_gfx_power_gating(struct amdgpu_device *adev)
2146 {
2147         uint32_t data = 0;
2148
2149         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2150                               AMD_PG_SUPPORT_GFX_SMG |
2151                               AMD_PG_SUPPORT_GFX_DMG)) {
2152                 /* init IDLE_POLL_COUNT = 60 */
2153                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL));
2154                 data &= ~CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK;
2155                 data |= (0x60 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
2156                 WREG32(SOC15_REG_OFFSET(GC, 0, mmCP_RB_WPTR_POLL_CNTL), data);
2157
2158                 /* init RLC PG Delay */
2159                 data = 0;
2160                 data |= (0x10 << RLC_PG_DELAY__POWER_UP_DELAY__SHIFT);
2161                 data |= (0x10 << RLC_PG_DELAY__POWER_DOWN_DELAY__SHIFT);
2162                 data |= (0x10 << RLC_PG_DELAY__CMD_PROPAGATE_DELAY__SHIFT);
2163                 data |= (0x40 << RLC_PG_DELAY__MEM_SLEEP_DELAY__SHIFT);
2164                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY), data);
2165
2166                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2));
2167                 data &= ~RLC_PG_DELAY_2__SERDES_CMD_DELAY_MASK;
2168                 data |= (0x4 << RLC_PG_DELAY_2__SERDES_CMD_DELAY__SHIFT);
2169                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_2), data);
2170
2171                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3));
2172                 data &= ~RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG_MASK;
2173                 data |= (0xff << RLC_PG_DELAY_3__CGCG_ACTIVE_BEFORE_CGPG__SHIFT);
2174                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_DELAY_3), data);
2175
2176                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL));
2177                 data &= ~RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD_MASK;
2178
2179                 /* program GRBM_REG_SAVE_GFX_IDLE_THRESHOLD to 0x55f0 */
2180                 data |= (0x55f0 << RLC_AUTO_PG_CTRL__GRBM_REG_SAVE_GFX_IDLE_THRESHOLD__SHIFT);
2181                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_AUTO_PG_CTRL), data);
2182
2183                 pwr_10_0_gfxip_control_over_cgpg(adev, true);
2184         }
2185 }
2186
2187 static void gfx_v9_0_enable_sck_slow_down_on_power_up(struct amdgpu_device *adev,
2188                                                 bool enable)
2189 {
2190         uint32_t data = 0;
2191         uint32_t default_data = 0;
2192
2193         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2194         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2195                              SMU_CLK_SLOWDOWN_ON_PU_ENABLE,
2196                              enable ? 1 : 0);
2197         if (default_data != data)
2198                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2199 }
2200
2201 static void gfx_v9_0_enable_sck_slow_down_on_power_down(struct amdgpu_device *adev,
2202                                                 bool enable)
2203 {
2204         uint32_t data = 0;
2205         uint32_t default_data = 0;
2206
2207         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2208         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2209                              SMU_CLK_SLOWDOWN_ON_PD_ENABLE,
2210                              enable ? 1 : 0);
2211         if(default_data != data)
2212                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2213 }
2214
2215 static void gfx_v9_0_enable_cp_power_gating(struct amdgpu_device *adev,
2216                                         bool enable)
2217 {
2218         uint32_t data = 0;
2219         uint32_t default_data = 0;
2220
2221         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2222         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2223                              CP_PG_DISABLE,
2224                              enable ? 0 : 1);
2225         if(default_data != data)
2226                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2227 }
2228
2229 static void gfx_v9_0_enable_gfx_cg_power_gating(struct amdgpu_device *adev,
2230                                                 bool enable)
2231 {
2232         uint32_t data, default_data;
2233
2234         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2235         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2236                              GFX_POWER_GATING_ENABLE,
2237                              enable ? 1 : 0);
2238         if(default_data != data)
2239                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2240 }
2241
2242 static void gfx_v9_0_enable_gfx_pipeline_powergating(struct amdgpu_device *adev,
2243                                                 bool enable)
2244 {
2245         uint32_t data, default_data;
2246
2247         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2248         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2249                              GFX_PIPELINE_PG_ENABLE,
2250                              enable ? 1 : 0);
2251         if(default_data != data)
2252                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2253
2254         if (!enable)
2255                 /* read any GFX register to wake up GFX */
2256                 data = RREG32(SOC15_REG_OFFSET(GC, 0, mmDB_RENDER_CONTROL));
2257 }
2258
2259 static void gfx_v9_0_enable_gfx_static_mg_power_gating(struct amdgpu_device *adev,
2260                                                        bool enable)
2261 {
2262         uint32_t data, default_data;
2263
2264         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2265         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2266                              STATIC_PER_CU_PG_ENABLE,
2267                              enable ? 1 : 0);
2268         if(default_data != data)
2269                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2270 }
2271
2272 static void gfx_v9_0_enable_gfx_dynamic_mg_power_gating(struct amdgpu_device *adev,
2273                                                 bool enable)
2274 {
2275         uint32_t data, default_data;
2276
2277         default_data = data = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL));
2278         data = REG_SET_FIELD(data, RLC_PG_CNTL,
2279                              DYN_PER_CU_PG_ENABLE,
2280                              enable ? 1 : 0);
2281         if(default_data != data)
2282                 WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_PG_CNTL), data);
2283 }
2284
2285 static void gfx_v9_0_init_pg(struct amdgpu_device *adev)
2286 {
2287         gfx_v9_0_init_csb(adev);
2288
2289         /*
2290          * Rlc save restore list is workable since v2_1.
2291          * And it's needed by gfxoff feature.
2292          */
2293         if (adev->gfx.rlc.is_rlc_v2_1) {
2294                 gfx_v9_1_init_rlc_save_restore_list(adev);
2295                 gfx_v9_0_enable_save_restore_machine(adev);
2296         }
2297
2298         if (adev->pg_flags & (AMD_PG_SUPPORT_GFX_PG |
2299                               AMD_PG_SUPPORT_GFX_SMG |
2300                               AMD_PG_SUPPORT_GFX_DMG |
2301                               AMD_PG_SUPPORT_CP |
2302                               AMD_PG_SUPPORT_GDS |
2303                               AMD_PG_SUPPORT_RLC_SMU_HS)) {
2304                 WREG32(mmRLC_JUMP_TABLE_RESTORE,
2305                        adev->gfx.rlc.cp_table_gpu_addr >> 8);
2306                 gfx_v9_0_init_gfx_power_gating(adev);
2307         }
2308 }
2309
2310 void gfx_v9_0_rlc_stop(struct amdgpu_device *adev)
2311 {
2312         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 0);
2313         gfx_v9_0_enable_gui_idle_interrupt(adev, false);
2314         gfx_v9_0_wait_for_rlc_serdes(adev);
2315 }
2316
2317 static void gfx_v9_0_rlc_reset(struct amdgpu_device *adev)
2318 {
2319         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
2320         udelay(50);
2321         WREG32_FIELD15(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
2322         udelay(50);
2323 }
2324
2325 static void gfx_v9_0_rlc_start(struct amdgpu_device *adev)
2326 {
2327 #ifdef AMDGPU_RLC_DEBUG_RETRY
2328         u32 rlc_ucode_ver;
2329 #endif
2330
2331         WREG32_FIELD15(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
2332
2333         /* carrizo do enable cp interrupt after cp inited */
2334         if (!(adev->flags & AMD_IS_APU))
2335                 gfx_v9_0_enable_gui_idle_interrupt(adev, true);
2336
2337         udelay(50);
2338
2339 #ifdef AMDGPU_RLC_DEBUG_RETRY
2340         /* RLC_GPM_GENERAL_6 : RLC Ucode version */
2341         rlc_ucode_ver = RREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_6);
2342         if(rlc_ucode_ver == 0x108) {
2343                 DRM_INFO("Using rlc debug ucode. mmRLC_GPM_GENERAL_6 ==0x08%x / fw_ver == %i \n",
2344                                 rlc_ucode_ver, adev->gfx.rlc_fw_version);
2345                 /* RLC_GPM_TIMER_INT_3 : Timer interval in RefCLK cycles,
2346                  * default is 0x9C4 to create a 100us interval */
2347                 WREG32_SOC15(GC, 0, mmRLC_GPM_TIMER_INT_3, 0x9C4);
2348                 /* RLC_GPM_GENERAL_12 : Minimum gap between wptr and rptr
2349                  * to disable the page fault retry interrupts, default is
2350                  * 0x100 (256) */
2351                 WREG32_SOC15(GC, 0, mmRLC_GPM_GENERAL_12, 0x100);
2352         }
2353 #endif
2354 }
2355
2356 static int gfx_v9_0_rlc_load_microcode(struct amdgpu_device *adev)
2357 {
2358         const struct rlc_firmware_header_v2_0 *hdr;
2359         const __le32 *fw_data;
2360         unsigned i, fw_size;
2361
2362         if (!adev->gfx.rlc_fw)
2363                 return -EINVAL;
2364
2365         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
2366         amdgpu_ucode_print_rlc_hdr(&hdr->header);
2367
2368         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
2369                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
2370         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
2371
2372         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR,
2373                         RLCG_UCODE_LOADING_START_ADDRESS);
2374         for (i = 0; i < fw_size; i++)
2375                 WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_DATA, le32_to_cpup(fw_data++));
2376         WREG32_SOC15(GC, 0, mmRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
2377
2378         return 0;
2379 }
2380
2381 static int gfx_v9_0_rlc_resume(struct amdgpu_device *adev)
2382 {
2383         int r;
2384
2385         if (amdgpu_sriov_vf(adev)) {
2386                 gfx_v9_0_init_csb(adev);
2387                 return 0;
2388         }
2389
2390         gfx_v9_0_rlc_stop(adev);
2391
2392         /* disable CG */
2393         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, 0);
2394
2395         gfx_v9_0_rlc_reset(adev);
2396
2397         gfx_v9_0_init_pg(adev);
2398
2399         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
2400                 /* legacy rlc firmware loading */
2401                 r = gfx_v9_0_rlc_load_microcode(adev);
2402                 if (r)
2403                         return r;
2404         }
2405
2406         if (adev->asic_type == CHIP_RAVEN) {
2407                 if (amdgpu_lbpw != 0)
2408                         gfx_v9_0_enable_lbpw(adev, true);
2409                 else
2410                         gfx_v9_0_enable_lbpw(adev, false);
2411         }
2412
2413         gfx_v9_0_rlc_start(adev);
2414
2415         return 0;
2416 }
2417
2418 static void gfx_v9_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2419 {
2420         int i;
2421         u32 tmp = RREG32_SOC15(GC, 0, mmCP_ME_CNTL);
2422
2423         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2424         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2425         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, enable ? 0 : 1);
2426         if (!enable) {
2427                 for (i = 0; i < adev->gfx.num_gfx_rings; i++)
2428                         adev->gfx.gfx_ring[i].ready = false;
2429         }
2430         WREG32_SOC15(GC, 0, mmCP_ME_CNTL, tmp);
2431         udelay(50);
2432 }
2433
2434 static int gfx_v9_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
2435 {
2436         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2437         const struct gfx_firmware_header_v1_0 *ce_hdr;
2438         const struct gfx_firmware_header_v1_0 *me_hdr;
2439         const __le32 *fw_data;
2440         unsigned i, fw_size;
2441
2442         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw || !adev->gfx.ce_fw)
2443                 return -EINVAL;
2444
2445         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2446                 adev->gfx.pfp_fw->data;
2447         ce_hdr = (const struct gfx_firmware_header_v1_0 *)
2448                 adev->gfx.ce_fw->data;
2449         me_hdr = (const struct gfx_firmware_header_v1_0 *)
2450                 adev->gfx.me_fw->data;
2451
2452         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2453         amdgpu_ucode_print_gfx_hdr(&ce_hdr->header);
2454         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2455
2456         gfx_v9_0_cp_gfx_enable(adev, false);
2457
2458         /* PFP */
2459         fw_data = (const __le32 *)
2460                 (adev->gfx.pfp_fw->data +
2461                  le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2462         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes) / 4;
2463         WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, 0);
2464         for (i = 0; i < fw_size; i++)
2465                 WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_DATA, le32_to_cpup(fw_data++));
2466         WREG32_SOC15(GC, 0, mmCP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2467
2468         /* CE */
2469         fw_data = (const __le32 *)
2470                 (adev->gfx.ce_fw->data +
2471                  le32_to_cpu(ce_hdr->header.ucode_array_offset_bytes));
2472         fw_size = le32_to_cpu(ce_hdr->header.ucode_size_bytes) / 4;
2473         WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, 0);
2474         for (i = 0; i < fw_size; i++)
2475                 WREG32_SOC15(GC, 0, mmCP_CE_UCODE_DATA, le32_to_cpup(fw_data++));
2476         WREG32_SOC15(GC, 0, mmCP_CE_UCODE_ADDR, adev->gfx.ce_fw_version);
2477
2478         /* ME */
2479         fw_data = (const __le32 *)
2480                 (adev->gfx.me_fw->data +
2481                  le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2482         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes) / 4;
2483         WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, 0);
2484         for (i = 0; i < fw_size; i++)
2485                 WREG32_SOC15(GC, 0, mmCP_ME_RAM_DATA, le32_to_cpup(fw_data++));
2486         WREG32_SOC15(GC, 0, mmCP_ME_RAM_WADDR, adev->gfx.me_fw_version);
2487
2488         return 0;
2489 }
2490
2491 static int gfx_v9_0_cp_gfx_start(struct amdgpu_device *adev)
2492 {
2493         struct amdgpu_ring *ring = &adev->gfx.gfx_ring[0];
2494         const struct cs_section_def *sect = NULL;
2495         const struct cs_extent_def *ext = NULL;
2496         int r, i, tmp;
2497
2498         /* init the CP */
2499         WREG32_SOC15(GC, 0, mmCP_MAX_CONTEXT, adev->gfx.config.max_hw_contexts - 1);
2500         WREG32_SOC15(GC, 0, mmCP_DEVICE_ID, 1);
2501
2502         gfx_v9_0_cp_gfx_enable(adev, true);
2503
2504         r = amdgpu_ring_alloc(ring, gfx_v9_0_get_csb_size(adev) + 4 + 3);
2505         if (r) {
2506                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
2507                 return r;
2508         }
2509
2510         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2511         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
2512
2513         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
2514         amdgpu_ring_write(ring, 0x80000000);
2515         amdgpu_ring_write(ring, 0x80000000);
2516
2517         for (sect = gfx9_cs_data; sect->section != NULL; ++sect) {
2518                 for (ext = sect->section; ext->extent != NULL; ++ext) {
2519                         if (sect->id == SECT_CONTEXT) {
2520                                 amdgpu_ring_write(ring,
2521                                        PACKET3(PACKET3_SET_CONTEXT_REG,
2522                                                ext->reg_count));
2523                                 amdgpu_ring_write(ring,
2524                                        ext->reg_index - PACKET3_SET_CONTEXT_REG_START);
2525                                 for (i = 0; i < ext->reg_count; i++)
2526                                         amdgpu_ring_write(ring, ext->extent[i]);
2527                         }
2528                 }
2529         }
2530
2531         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
2532         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
2533
2534         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
2535         amdgpu_ring_write(ring, 0);
2536
2537         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_BASE, 2));
2538         amdgpu_ring_write(ring, PACKET3_BASE_INDEX(CE_PARTITION_BASE));
2539         amdgpu_ring_write(ring, 0x8000);
2540         amdgpu_ring_write(ring, 0x8000);
2541
2542         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG,1));
2543         tmp = (PACKET3_SET_UCONFIG_REG_INDEX_TYPE |
2544                 (SOC15_REG_OFFSET(GC, 0, mmVGT_INDEX_TYPE) - PACKET3_SET_UCONFIG_REG_START));
2545         amdgpu_ring_write(ring, tmp);
2546         amdgpu_ring_write(ring, 0);
2547
2548         amdgpu_ring_commit(ring);
2549
2550         return 0;
2551 }
2552
2553 static int gfx_v9_0_cp_gfx_resume(struct amdgpu_device *adev)
2554 {
2555         struct amdgpu_ring *ring;
2556         u32 tmp;
2557         u32 rb_bufsz;
2558         u64 rb_addr, rptr_addr, wptr_gpu_addr;
2559
2560         /* Set the write pointer delay */
2561         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_DELAY, 0);
2562
2563         /* set the RB to use vmid 0 */
2564         WREG32_SOC15(GC, 0, mmCP_RB_VMID, 0);
2565
2566         /* Set ring buffer size */
2567         ring = &adev->gfx.gfx_ring[0];
2568         rb_bufsz = order_base_2(ring->ring_size / 8);
2569         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
2570         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
2571 #ifdef __BIG_ENDIAN
2572         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, BUF_SWAP, 1);
2573 #endif
2574         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2575
2576         /* Initialize the ring buffer's write pointers */
2577         ring->wptr = 0;
2578         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
2579         WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
2580
2581         /* set the wb address wether it's enabled or not */
2582         rptr_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2583         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
2584         WREG32_SOC15(GC, 0, mmCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) & CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
2585
2586         wptr_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2587         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_LO, lower_32_bits(wptr_gpu_addr));
2588         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_ADDR_HI, upper_32_bits(wptr_gpu_addr));
2589
2590         mdelay(1);
2591         WREG32_SOC15(GC, 0, mmCP_RB0_CNTL, tmp);
2592
2593         rb_addr = ring->gpu_addr >> 8;
2594         WREG32_SOC15(GC, 0, mmCP_RB0_BASE, rb_addr);
2595         WREG32_SOC15(GC, 0, mmCP_RB0_BASE_HI, upper_32_bits(rb_addr));
2596
2597         tmp = RREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL);
2598         if (ring->use_doorbell) {
2599                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2600                                     DOORBELL_OFFSET, ring->doorbell_index);
2601                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
2602                                     DOORBELL_EN, 1);
2603         } else {
2604                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL, DOORBELL_EN, 0);
2605         }
2606         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_CONTROL, tmp);
2607
2608         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
2609                         DOORBELL_RANGE_LOWER, ring->doorbell_index);
2610         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_LOWER, tmp);
2611
2612         WREG32_SOC15(GC, 0, mmCP_RB_DOORBELL_RANGE_UPPER,
2613                        CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
2614
2615
2616         /* start the ring */
2617         gfx_v9_0_cp_gfx_start(adev);
2618         ring->ready = true;
2619
2620         return 0;
2621 }
2622
2623 static void gfx_v9_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
2624 {
2625         int i;
2626
2627         if (enable) {
2628                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL, 0);
2629         } else {
2630                 WREG32_SOC15(GC, 0, mmCP_MEC_CNTL,
2631                         (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK));
2632                 for (i = 0; i < adev->gfx.num_compute_rings; i++)
2633                         adev->gfx.compute_ring[i].ready = false;
2634                 adev->gfx.kiq.ring.ready = false;
2635         }
2636         udelay(50);
2637 }
2638
2639 static int gfx_v9_0_cp_compute_load_microcode(struct amdgpu_device *adev)
2640 {
2641         const struct gfx_firmware_header_v1_0 *mec_hdr;
2642         const __le32 *fw_data;
2643         unsigned i;
2644         u32 tmp;
2645
2646         if (!adev->gfx.mec_fw)
2647                 return -EINVAL;
2648
2649         gfx_v9_0_cp_compute_enable(adev, false);
2650
2651         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
2652         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
2653
2654         fw_data = (const __le32 *)
2655                 (adev->gfx.mec_fw->data +
2656                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
2657         tmp = 0;
2658         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2659         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2660         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_CNTL, tmp);
2661
2662         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_LO,
2663                 adev->gfx.mec.mec_fw_gpu_addr & 0xFFFFF000);
2664         WREG32_SOC15(GC, 0, mmCP_CPC_IC_BASE_HI,
2665                 upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
2666
2667         /* MEC1 */
2668         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
2669                          mec_hdr->jt_offset);
2670         for (i = 0; i < mec_hdr->jt_size; i++)
2671                 WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_DATA,
2672                         le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
2673
2674         WREG32_SOC15(GC, 0, mmCP_MEC_ME1_UCODE_ADDR,
2675                         adev->gfx.mec_fw_version);
2676         /* Todo : Loading MEC2 firmware is only necessary if MEC2 should run different microcode than MEC1. */
2677
2678         return 0;
2679 }
2680
2681 /* KIQ functions */
2682 static void gfx_v9_0_kiq_setting(struct amdgpu_ring *ring)
2683 {
2684         uint32_t tmp;
2685         struct amdgpu_device *adev = ring->adev;
2686
2687         /* tell RLC which is KIQ queue */
2688         tmp = RREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS);
2689         tmp &= 0xffffff00;
2690         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
2691         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2692         tmp |= 0x80;
2693         WREG32_SOC15(GC, 0, mmRLC_CP_SCHEDULERS, tmp);
2694 }
2695
2696 static int gfx_v9_0_kiq_kcq_enable(struct amdgpu_device *adev)
2697 {
2698         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
2699         uint64_t queue_mask = 0;
2700         int r, i;
2701
2702         for (i = 0; i < AMDGPU_MAX_COMPUTE_QUEUES; ++i) {
2703                 if (!test_bit(i, adev->gfx.mec.queue_bitmap))
2704                         continue;
2705
2706                 /* This situation may be hit in the future if a new HW
2707                  * generation exposes more than 64 queues. If so, the
2708                  * definition of queue_mask needs updating */
2709                 if (WARN_ON(i >= (sizeof(queue_mask)*8))) {
2710                         DRM_ERROR("Invalid KCQ enabled: %d\n", i);
2711                         break;
2712                 }
2713
2714                 queue_mask |= (1ull << i);
2715         }
2716
2717         r = amdgpu_ring_alloc(kiq_ring, (7 * adev->gfx.num_compute_rings) + 8);
2718         if (r) {
2719                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
2720                 return r;
2721         }
2722
2723         /* set resources */
2724         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
2725         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
2726                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
2727         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
2728         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
2729         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
2730         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
2731         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
2732         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
2733         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
2734                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
2735                 uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
2736                 uint64_t wptr_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2737
2738                 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
2739                 /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
2740                 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
2741                                   PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
2742                                   PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
2743                                   PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
2744                                   PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
2745                                   PACKET3_MAP_QUEUES_ME((ring->me == 1 ? 0 : 1)) |
2746                                   PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
2747                                   PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
2748                                   PACKET3_MAP_QUEUES_ENGINE_SEL(0) | /* engine_sel: compute */
2749                                   PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
2750                 amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
2751                 amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
2752                 amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
2753                 amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
2754                 amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
2755         }
2756
2757         r = amdgpu_ring_test_ring(kiq_ring);
2758         if (r) {
2759                 DRM_ERROR("KCQ enable failed\n");
2760                 kiq_ring->ready = false;
2761         }
2762
2763         return r;
2764 }
2765
2766 static int gfx_v9_0_mqd_init(struct amdgpu_ring *ring)
2767 {
2768         struct amdgpu_device *adev = ring->adev;
2769         struct v9_mqd *mqd = ring->mqd_ptr;
2770         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
2771         uint32_t tmp;
2772
2773         mqd->header = 0xC0310800;
2774         mqd->compute_pipelinestat_enable = 0x00000001;
2775         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
2776         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
2777         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
2778         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
2779         mqd->compute_misc_reserved = 0x00000003;
2780
2781         mqd->dynamic_cu_mask_addr_lo =
2782                 lower_32_bits(ring->mqd_gpu_addr
2783                               + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2784         mqd->dynamic_cu_mask_addr_hi =
2785                 upper_32_bits(ring->mqd_gpu_addr
2786                               + offsetof(struct v9_mqd_allocation, dynamic_cu_mask));
2787
2788         eop_base_addr = ring->eop_gpu_addr >> 8;
2789         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
2790         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
2791
2792         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2793         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL);
2794         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
2795                         (order_base_2(GFX9_MEC_HPD_SIZE / 4) - 1));
2796
2797         mqd->cp_hqd_eop_control = tmp;
2798
2799         /* enable doorbell? */
2800         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
2801
2802         if (ring->use_doorbell) {
2803                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2804                                     DOORBELL_OFFSET, ring->doorbell_index);
2805                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2806                                     DOORBELL_EN, 1);
2807                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2808                                     DOORBELL_SOURCE, 0);
2809                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2810                                     DOORBELL_HIT, 0);
2811         } else {
2812                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2813                                          DOORBELL_EN, 0);
2814         }
2815
2816         mqd->cp_hqd_pq_doorbell_control = tmp;
2817
2818         /* disable the queue if it's active */
2819         ring->wptr = 0;
2820         mqd->cp_hqd_dequeue_request = 0;
2821         mqd->cp_hqd_pq_rptr = 0;
2822         mqd->cp_hqd_pq_wptr_lo = 0;
2823         mqd->cp_hqd_pq_wptr_hi = 0;
2824
2825         /* set the pointer to the MQD */
2826         mqd->cp_mqd_base_addr_lo = ring->mqd_gpu_addr & 0xfffffffc;
2827         mqd->cp_mqd_base_addr_hi = upper_32_bits(ring->mqd_gpu_addr);
2828
2829         /* set MQD vmid to 0 */
2830         tmp = RREG32_SOC15(GC, 0, mmCP_MQD_CONTROL);
2831         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
2832         mqd->cp_mqd_control = tmp;
2833
2834         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2835         hqd_gpu_addr = ring->gpu_addr >> 8;
2836         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
2837         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
2838
2839         /* set up the HQD, this is similar to CP_RB0_CNTL */
2840         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL);
2841         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
2842                             (order_base_2(ring->ring_size / 4) - 1));
2843         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
2844                         ((order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1) << 8));
2845 #ifdef __BIG_ENDIAN
2846         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ENDIAN_SWAP, 1);
2847 #endif
2848         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
2849         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, ROQ_PQ_IB_FLIP, 0);
2850         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
2851         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
2852         mqd->cp_hqd_pq_control = tmp;
2853
2854         /* set the wb address whether it's enabled or not */
2855         wb_gpu_addr = adev->wb.gpu_addr + (ring->rptr_offs * 4);
2856         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
2857         mqd->cp_hqd_pq_rptr_report_addr_hi =
2858                 upper_32_bits(wb_gpu_addr) & 0xffff;
2859
2860         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2861         wb_gpu_addr = adev->wb.gpu_addr + (ring->wptr_offs * 4);
2862         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
2863         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
2864
2865         tmp = 0;
2866         /* enable the doorbell if requested */
2867         if (ring->use_doorbell) {
2868                 tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL);
2869                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2870                                 DOORBELL_OFFSET, ring->doorbell_index);
2871
2872                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2873                                          DOORBELL_EN, 1);
2874                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2875                                          DOORBELL_SOURCE, 0);
2876                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
2877                                          DOORBELL_HIT, 0);
2878         }
2879
2880         mqd->cp_hqd_pq_doorbell_control = tmp;
2881
2882         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2883         ring->wptr = 0;
2884         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR);
2885
2886         /* set the vmid for the queue */
2887         mqd->cp_hqd_vmid = 0;
2888
2889         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE);
2890         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x53);
2891         mqd->cp_hqd_persistent_state = tmp;
2892
2893         /* set MIN_IB_AVAIL_SIZE */
2894         tmp = RREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL);
2895         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
2896         mqd->cp_hqd_ib_control = tmp;
2897
2898         /* activate the queue */
2899         mqd->cp_hqd_active = 1;
2900
2901         return 0;
2902 }
2903
2904 static int gfx_v9_0_kiq_init_register(struct amdgpu_ring *ring)
2905 {
2906         struct amdgpu_device *adev = ring->adev;
2907         struct v9_mqd *mqd = ring->mqd_ptr;
2908         int j;
2909
2910         /* disable wptr polling */
2911         WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
2912
2913         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR,
2914                mqd->cp_hqd_eop_base_addr_lo);
2915         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_BASE_ADDR_HI,
2916                mqd->cp_hqd_eop_base_addr_hi);
2917
2918         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
2919         WREG32_SOC15(GC, 0, mmCP_HQD_EOP_CONTROL,
2920                mqd->cp_hqd_eop_control);
2921
2922         /* enable doorbell? */
2923         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
2924                mqd->cp_hqd_pq_doorbell_control);
2925
2926         /* disable the queue if it's active */
2927         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
2928                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
2929                 for (j = 0; j < adev->usec_timeout; j++) {
2930                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
2931                                 break;
2932                         udelay(1);
2933                 }
2934                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
2935                        mqd->cp_hqd_dequeue_request);
2936                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR,
2937                        mqd->cp_hqd_pq_rptr);
2938                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
2939                        mqd->cp_hqd_pq_wptr_lo);
2940                 WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
2941                        mqd->cp_hqd_pq_wptr_hi);
2942         }
2943
2944         /* set the pointer to the MQD */
2945         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR,
2946                mqd->cp_mqd_base_addr_lo);
2947         WREG32_SOC15(GC, 0, mmCP_MQD_BASE_ADDR_HI,
2948                mqd->cp_mqd_base_addr_hi);
2949
2950         /* set MQD vmid to 0 */
2951         WREG32_SOC15(GC, 0, mmCP_MQD_CONTROL,
2952                mqd->cp_mqd_control);
2953
2954         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
2955         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE,
2956                mqd->cp_hqd_pq_base_lo);
2957         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_BASE_HI,
2958                mqd->cp_hqd_pq_base_hi);
2959
2960         /* set up the HQD, this is similar to CP_RB0_CNTL */
2961         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_CONTROL,
2962                mqd->cp_hqd_pq_control);
2963
2964         /* set the wb address whether it's enabled or not */
2965         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR,
2966                                 mqd->cp_hqd_pq_rptr_report_addr_lo);
2967         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
2968                                 mqd->cp_hqd_pq_rptr_report_addr_hi);
2969
2970         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
2971         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR,
2972                mqd->cp_hqd_pq_wptr_poll_addr_lo);
2973         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_POLL_ADDR_HI,
2974                mqd->cp_hqd_pq_wptr_poll_addr_hi);
2975
2976         /* enable the doorbell if requested */
2977         if (ring->use_doorbell) {
2978                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_LOWER,
2979                                         (AMDGPU_DOORBELL64_KIQ *2) << 2);
2980                 WREG32_SOC15(GC, 0, mmCP_MEC_DOORBELL_RANGE_UPPER,
2981                                         (AMDGPU_DOORBELL64_USERQUEUE_END * 2) << 2);
2982         }
2983
2984         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL,
2985                mqd->cp_hqd_pq_doorbell_control);
2986
2987         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
2988         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO,
2989                mqd->cp_hqd_pq_wptr_lo);
2990         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI,
2991                mqd->cp_hqd_pq_wptr_hi);
2992
2993         /* set the vmid for the queue */
2994         WREG32_SOC15(GC, 0, mmCP_HQD_VMID, mqd->cp_hqd_vmid);
2995
2996         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE,
2997                mqd->cp_hqd_persistent_state);
2998
2999         /* activate the queue */
3000         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE,
3001                mqd->cp_hqd_active);
3002
3003         if (ring->use_doorbell)
3004                 WREG32_FIELD15(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
3005
3006         return 0;
3007 }
3008
3009 static int gfx_v9_0_kiq_fini_register(struct amdgpu_ring *ring)
3010 {
3011         struct amdgpu_device *adev = ring->adev;
3012         int j;
3013
3014         /* disable the queue if it's active */
3015         if (RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1) {
3016
3017                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST, 1);
3018
3019                 for (j = 0; j < adev->usec_timeout; j++) {
3020                         if (!(RREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE) & 1))
3021                                 break;
3022                         udelay(1);
3023                 }
3024
3025                 if (j == AMDGPU_MAX_USEC_TIMEOUT) {
3026                         DRM_DEBUG("KIQ dequeue request failed.\n");
3027
3028                         /* Manual disable if dequeue request times out */
3029                         WREG32_SOC15(GC, 0, mmCP_HQD_ACTIVE, 0);
3030                 }
3031
3032                 WREG32_SOC15(GC, 0, mmCP_HQD_DEQUEUE_REQUEST,
3033                       0);
3034         }
3035
3036         WREG32_SOC15(GC, 0, mmCP_HQD_IQ_TIMER, 0);
3037         WREG32_SOC15(GC, 0, mmCP_HQD_IB_CONTROL, 0);
3038         WREG32_SOC15(GC, 0, mmCP_HQD_PERSISTENT_STATE, 0);
3039         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0x40000000);
3040         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_DOORBELL_CONTROL, 0);
3041         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_RPTR, 0);
3042         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_HI, 0);
3043         WREG32_SOC15(GC, 0, mmCP_HQD_PQ_WPTR_LO, 0);
3044
3045         return 0;
3046 }
3047
3048 static int gfx_v9_0_kiq_init_queue(struct amdgpu_ring *ring)
3049 {
3050         struct amdgpu_device *adev = ring->adev;
3051         struct v9_mqd *mqd = ring->mqd_ptr;
3052         int mqd_idx = AMDGPU_MAX_COMPUTE_RINGS;
3053
3054         gfx_v9_0_kiq_setting(ring);
3055
3056         if (adev->in_gpu_reset) { /* for GPU_RESET case */
3057                 /* reset MQD to a clean status */
3058                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3059                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
3060
3061                 /* reset ring buffer */
3062                 ring->wptr = 0;
3063                 amdgpu_ring_clear_ring(ring);
3064
3065                 mutex_lock(&adev->srbm_mutex);
3066                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3067                 gfx_v9_0_kiq_init_register(ring);
3068                 soc15_grbm_select(adev, 0, 0, 0, 0);
3069                 mutex_unlock(&adev->srbm_mutex);
3070         } else {
3071                 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
3072                 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
3073                 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
3074                 mutex_lock(&adev->srbm_mutex);
3075                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3076                 gfx_v9_0_mqd_init(ring);
3077                 gfx_v9_0_kiq_init_register(ring);
3078                 soc15_grbm_select(adev, 0, 0, 0, 0);
3079                 mutex_unlock(&adev->srbm_mutex);
3080
3081                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3082                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
3083         }
3084
3085         return 0;
3086 }
3087
3088 static int gfx_v9_0_kcq_init_queue(struct amdgpu_ring *ring)
3089 {
3090         struct amdgpu_device *adev = ring->adev;
3091         struct v9_mqd *mqd = ring->mqd_ptr;
3092         int mqd_idx = ring - &adev->gfx.compute_ring[0];
3093
3094         if (!adev->in_gpu_reset && !adev->gfx.in_suspend) {
3095                 memset((void *)mqd, 0, sizeof(struct v9_mqd_allocation));
3096                 ((struct v9_mqd_allocation *)mqd)->dynamic_cu_mask = 0xFFFFFFFF;
3097                 ((struct v9_mqd_allocation *)mqd)->dynamic_rb_mask = 0xFFFFFFFF;
3098                 mutex_lock(&adev->srbm_mutex);
3099                 soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3100                 gfx_v9_0_mqd_init(ring);
3101                 soc15_grbm_select(adev, 0, 0, 0, 0);
3102                 mutex_unlock(&adev->srbm_mutex);
3103
3104                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3105                         memcpy(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(struct v9_mqd_allocation));
3106         } else if (adev->in_gpu_reset) { /* for GPU_RESET case */
3107                 /* reset MQD to a clean status */
3108                 if (adev->gfx.mec.mqd_backup[mqd_idx])
3109                         memcpy(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(struct v9_mqd_allocation));
3110
3111                 /* reset ring buffer */
3112                 ring->wptr = 0;
3113                 amdgpu_ring_clear_ring(ring);
3114         } else {
3115                 amdgpu_ring_clear_ring(ring);
3116         }
3117
3118         return 0;
3119 }
3120
3121 static int gfx_v9_0_kiq_resume(struct amdgpu_device *adev)
3122 {
3123         struct amdgpu_ring *ring;
3124         int r;
3125
3126         ring = &adev->gfx.kiq.ring;
3127
3128         r = amdgpu_bo_reserve(ring->mqd_obj, false);
3129         if (unlikely(r != 0))
3130                 return r;
3131
3132         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3133         if (unlikely(r != 0))
3134                 return r;
3135
3136         gfx_v9_0_kiq_init_queue(ring);
3137         amdgpu_bo_kunmap(ring->mqd_obj);
3138         ring->mqd_ptr = NULL;
3139         amdgpu_bo_unreserve(ring->mqd_obj);
3140         ring->ready = true;
3141         return 0;
3142 }
3143
3144 static int gfx_v9_0_kcq_resume(struct amdgpu_device *adev)
3145 {
3146         struct amdgpu_ring *ring = NULL;
3147         int r = 0, i;
3148
3149         gfx_v9_0_cp_compute_enable(adev, true);
3150
3151         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3152                 ring = &adev->gfx.compute_ring[i];
3153
3154                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3155                 if (unlikely(r != 0))
3156                         goto done;
3157                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3158                 if (!r) {
3159                         r = gfx_v9_0_kcq_init_queue(ring);
3160                         amdgpu_bo_kunmap(ring->mqd_obj);
3161                         ring->mqd_ptr = NULL;
3162                 }
3163                 amdgpu_bo_unreserve(ring->mqd_obj);
3164                 if (r)
3165                         goto done;
3166         }
3167
3168         r = gfx_v9_0_kiq_kcq_enable(adev);
3169 done:
3170         return r;
3171 }
3172
3173 static int gfx_v9_0_cp_resume(struct amdgpu_device *adev)
3174 {
3175         int r, i;
3176         struct amdgpu_ring *ring;
3177
3178         if (!(adev->flags & AMD_IS_APU))
3179                 gfx_v9_0_enable_gui_idle_interrupt(adev, false);
3180
3181         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
3182                 /* legacy firmware loading */
3183                 r = gfx_v9_0_cp_gfx_load_microcode(adev);
3184                 if (r)
3185                         return r;
3186
3187                 r = gfx_v9_0_cp_compute_load_microcode(adev);
3188                 if (r)
3189                         return r;
3190         }
3191
3192         r = gfx_v9_0_kiq_resume(adev);
3193         if (r)
3194                 return r;
3195
3196         r = gfx_v9_0_cp_gfx_resume(adev);
3197         if (r)
3198                 return r;
3199
3200         r = gfx_v9_0_kcq_resume(adev);
3201         if (r)
3202                 return r;
3203
3204         ring = &adev->gfx.gfx_ring[0];
3205         r = amdgpu_ring_test_ring(ring);
3206         if (r) {
3207                 ring->ready = false;
3208                 return r;
3209         }
3210
3211         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3212                 ring = &adev->gfx.compute_ring[i];
3213
3214                 ring->ready = true;
3215                 r = amdgpu_ring_test_ring(ring);
3216                 if (r)
3217                         ring->ready = false;
3218         }
3219
3220         gfx_v9_0_enable_gui_idle_interrupt(adev, true);
3221
3222         return 0;
3223 }
3224
3225 static void gfx_v9_0_cp_enable(struct amdgpu_device *adev, bool enable)
3226 {
3227         gfx_v9_0_cp_gfx_enable(adev, enable);
3228         gfx_v9_0_cp_compute_enable(adev, enable);
3229 }
3230
3231 static int gfx_v9_0_hw_init(void *handle)
3232 {
3233         int r;
3234         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3235
3236         gfx_v9_0_init_golden_registers(adev);
3237
3238         gfx_v9_0_gpu_init(adev);
3239
3240         r = gfx_v9_0_csb_vram_pin(adev);
3241         if (r)
3242                 return r;
3243
3244         r = gfx_v9_0_rlc_resume(adev);
3245         if (r)
3246                 return r;
3247
3248         r = gfx_v9_0_cp_resume(adev);
3249         if (r)
3250                 return r;
3251
3252         r = gfx_v9_0_ngg_en(adev);
3253         if (r)
3254                 return r;
3255
3256         return r;
3257 }
3258
3259 static int gfx_v9_0_kcq_disable(struct amdgpu_device *adev)
3260 {
3261         int r, i;
3262         struct amdgpu_ring *kiq_ring = &adev->gfx.kiq.ring;
3263
3264         r = amdgpu_ring_alloc(kiq_ring, 6 * adev->gfx.num_compute_rings);
3265         if (r)
3266                 DRM_ERROR("Failed to lock KIQ (%d).\n", r);
3267
3268         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
3269                 struct amdgpu_ring *ring = &adev->gfx.compute_ring[i];
3270
3271                 amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
3272                 amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
3273                                                 PACKET3_UNMAP_QUEUES_ACTION(1) | /* RESET_QUEUES */
3274                                                 PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
3275                                                 PACKET3_UNMAP_QUEUES_ENGINE_SEL(0) |
3276                                                 PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
3277                 amdgpu_ring_write(kiq_ring, PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
3278                 amdgpu_ring_write(kiq_ring, 0);
3279                 amdgpu_ring_write(kiq_ring, 0);
3280                 amdgpu_ring_write(kiq_ring, 0);
3281         }
3282         r = amdgpu_ring_test_ring(kiq_ring);
3283         if (r)
3284                 DRM_ERROR("KCQ disable failed\n");
3285
3286         return r;
3287 }
3288
3289 static int gfx_v9_0_hw_fini(void *handle)
3290 {
3291         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3292
3293         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
3294         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
3295
3296         /* disable KCQ to avoid CPC touch memory not valid anymore */
3297         gfx_v9_0_kcq_disable(adev);
3298
3299         if (amdgpu_sriov_vf(adev)) {
3300                 gfx_v9_0_cp_gfx_enable(adev, false);
3301                 /* must disable polling for SRIOV when hw finished, otherwise
3302                  * CPC engine may still keep fetching WB address which is already
3303                  * invalid after sw finished and trigger DMAR reading error in
3304                  * hypervisor side.
3305                  */
3306                 WREG32_FIELD15(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3307                 return 0;
3308         }
3309
3310         /* Use deinitialize sequence from CAIL when unbinding device from driver,
3311          * otherwise KIQ is hanging when binding back
3312          */
3313         if (!adev->in_gpu_reset && !adev->gfx.in_suspend) {
3314                 mutex_lock(&adev->srbm_mutex);
3315                 soc15_grbm_select(adev, adev->gfx.kiq.ring.me,
3316                                 adev->gfx.kiq.ring.pipe,
3317                                 adev->gfx.kiq.ring.queue, 0);
3318                 gfx_v9_0_kiq_fini_register(&adev->gfx.kiq.ring);
3319                 soc15_grbm_select(adev, 0, 0, 0, 0);
3320                 mutex_unlock(&adev->srbm_mutex);
3321         }
3322
3323         gfx_v9_0_cp_enable(adev, false);
3324         gfx_v9_0_rlc_stop(adev);
3325
3326         gfx_v9_0_csb_vram_unpin(adev);
3327
3328         return 0;
3329 }
3330
3331 static int gfx_v9_0_suspend(void *handle)
3332 {
3333         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3334
3335         adev->gfx.in_suspend = true;
3336         return gfx_v9_0_hw_fini(adev);
3337 }
3338
3339 static int gfx_v9_0_resume(void *handle)
3340 {
3341         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3342         int r;
3343
3344         r = gfx_v9_0_hw_init(adev);
3345         adev->gfx.in_suspend = false;
3346         return r;
3347 }
3348
3349 static bool gfx_v9_0_is_idle(void *handle)
3350 {
3351         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3352
3353         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, mmGRBM_STATUS),
3354                                 GRBM_STATUS, GUI_ACTIVE))
3355                 return false;
3356         else
3357                 return true;
3358 }
3359
3360 static int gfx_v9_0_wait_for_idle(void *handle)
3361 {
3362         unsigned i;
3363         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3364
3365         for (i = 0; i < adev->usec_timeout; i++) {
3366                 if (gfx_v9_0_is_idle(handle))
3367                         return 0;
3368                 udelay(1);
3369         }
3370         return -ETIMEDOUT;
3371 }
3372
3373 static int gfx_v9_0_soft_reset(void *handle)
3374 {
3375         u32 grbm_soft_reset = 0;
3376         u32 tmp;
3377         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3378
3379         /* GRBM_STATUS */
3380         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS);
3381         if (tmp & (GRBM_STATUS__PA_BUSY_MASK | GRBM_STATUS__SC_BUSY_MASK |
3382                    GRBM_STATUS__BCI_BUSY_MASK | GRBM_STATUS__SX_BUSY_MASK |
3383                    GRBM_STATUS__TA_BUSY_MASK | GRBM_STATUS__VGT_BUSY_MASK |
3384                    GRBM_STATUS__DB_BUSY_MASK | GRBM_STATUS__CB_BUSY_MASK |
3385                    GRBM_STATUS__GDS_BUSY_MASK | GRBM_STATUS__SPI_BUSY_MASK |
3386                    GRBM_STATUS__IA_BUSY_MASK | GRBM_STATUS__IA_BUSY_NO_DMA_MASK)) {
3387                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3388                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3389                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3390                                                 GRBM_SOFT_RESET, SOFT_RESET_GFX, 1);
3391         }
3392
3393         if (tmp & (GRBM_STATUS__CP_BUSY_MASK | GRBM_STATUS__CP_COHERENCY_BUSY_MASK)) {
3394                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3395                                                 GRBM_SOFT_RESET, SOFT_RESET_CP, 1);
3396         }
3397
3398         /* GRBM_STATUS2 */
3399         tmp = RREG32_SOC15(GC, 0, mmGRBM_STATUS2);
3400         if (REG_GET_FIELD(tmp, GRBM_STATUS2, RLC_BUSY))
3401                 grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset,
3402                                                 GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
3403
3404
3405         if (grbm_soft_reset) {
3406                 /* stop the rlc */
3407                 gfx_v9_0_rlc_stop(adev);
3408
3409                 /* Disable GFX parsing/prefetching */
3410                 gfx_v9_0_cp_gfx_enable(adev, false);
3411
3412                 /* Disable MEC parsing/prefetching */
3413                 gfx_v9_0_cp_compute_enable(adev, false);
3414
3415                 if (grbm_soft_reset) {
3416                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3417                         tmp |= grbm_soft_reset;
3418                         dev_info(adev->dev, "GRBM_SOFT_RESET=0x%08X\n", tmp);
3419                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3420                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3421
3422                         udelay(50);
3423
3424                         tmp &= ~grbm_soft_reset;
3425                         WREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET, tmp);
3426                         tmp = RREG32_SOC15(GC, 0, mmGRBM_SOFT_RESET);
3427                 }
3428
3429                 /* Wait a little for things to settle down */
3430                 udelay(50);
3431         }
3432         return 0;
3433 }
3434
3435 static uint64_t gfx_v9_0_get_gpu_clock_counter(struct amdgpu_device *adev)
3436 {
3437         uint64_t clock;
3438
3439         mutex_lock(&adev->gfx.gpu_clock_mutex);
3440         WREG32_SOC15(GC, 0, mmRLC_CAPTURE_GPU_CLOCK_COUNT, 1);
3441         clock = (uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_LSB) |
3442                 ((uint64_t)RREG32_SOC15(GC, 0, mmRLC_GPU_CLOCK_COUNT_MSB) << 32ULL);
3443         mutex_unlock(&adev->gfx.gpu_clock_mutex);
3444         return clock;
3445 }
3446
3447 static void gfx_v9_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
3448                                           uint32_t vmid,
3449                                           uint32_t gds_base, uint32_t gds_size,
3450                                           uint32_t gws_base, uint32_t gws_size,
3451                                           uint32_t oa_base, uint32_t oa_size)
3452 {
3453         struct amdgpu_device *adev = ring->adev;
3454
3455         /* GDS Base */
3456         gfx_v9_0_write_data_to_reg(ring, 0, false,
3457                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_BASE) + 2 * vmid,
3458                                    gds_base);
3459
3460         /* GDS Size */
3461         gfx_v9_0_write_data_to_reg(ring, 0, false,
3462                                    SOC15_REG_OFFSET(GC, 0, mmGDS_VMID0_SIZE) + 2 * vmid,
3463                                    gds_size);
3464
3465         /* GWS */
3466         gfx_v9_0_write_data_to_reg(ring, 0, false,
3467                                    SOC15_REG_OFFSET(GC, 0, mmGDS_GWS_VMID0) + vmid,
3468                                    gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
3469
3470         /* OA */
3471         gfx_v9_0_write_data_to_reg(ring, 0, false,
3472                                    SOC15_REG_OFFSET(GC, 0, mmGDS_OA_VMID0) + vmid,
3473                                    (1 << (oa_size + oa_base)) - (1 << oa_base));
3474 }
3475
3476 static int gfx_v9_0_early_init(void *handle)
3477 {
3478         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3479
3480         adev->gfx.num_gfx_rings = GFX9_NUM_GFX_RINGS;
3481         adev->gfx.num_compute_rings = AMDGPU_MAX_COMPUTE_RINGS;
3482         gfx_v9_0_set_ring_funcs(adev);
3483         gfx_v9_0_set_irq_funcs(adev);
3484         gfx_v9_0_set_gds_init(adev);
3485         gfx_v9_0_set_rlc_funcs(adev);
3486
3487         return 0;
3488 }
3489
3490 static int gfx_v9_0_late_init(void *handle)
3491 {
3492         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3493         int r;
3494
3495         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
3496         if (r)
3497                 return r;
3498
3499         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
3500         if (r)
3501                 return r;
3502
3503         return 0;
3504 }
3505
3506 static void gfx_v9_0_enter_rlc_safe_mode(struct amdgpu_device *adev)
3507 {
3508         uint32_t rlc_setting, data;
3509         unsigned i;
3510
3511         if (adev->gfx.rlc.in_safe_mode)
3512                 return;
3513
3514         /* if RLC is not enabled, do nothing */
3515         rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
3516         if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3517                 return;
3518
3519         if (adev->cg_flags &
3520             (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG |
3521              AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3522                 data = RLC_SAFE_MODE__CMD_MASK;
3523                 data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
3524                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3525
3526                 /* wait for RLC_SAFE_MODE */
3527                 for (i = 0; i < adev->usec_timeout; i++) {
3528                         if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, mmRLC_SAFE_MODE), RLC_SAFE_MODE, CMD))
3529                                 break;
3530                         udelay(1);
3531                 }
3532                 adev->gfx.rlc.in_safe_mode = true;
3533         }
3534 }
3535
3536 static void gfx_v9_0_exit_rlc_safe_mode(struct amdgpu_device *adev)
3537 {
3538         uint32_t rlc_setting, data;
3539
3540         if (!adev->gfx.rlc.in_safe_mode)
3541                 return;
3542
3543         /* if RLC is not enabled, do nothing */
3544         rlc_setting = RREG32_SOC15(GC, 0, mmRLC_CNTL);
3545         if (!(rlc_setting & RLC_CNTL__RLC_ENABLE_F32_MASK))
3546                 return;
3547
3548         if (adev->cg_flags &
3549             (AMD_CG_SUPPORT_GFX_CGCG | AMD_CG_SUPPORT_GFX_MGCG)) {
3550                 /*
3551                  * Try to exit safe mode only if it is already in safe
3552                  * mode.
3553                  */
3554                 data = RLC_SAFE_MODE__CMD_MASK;
3555                 WREG32_SOC15(GC, 0, mmRLC_SAFE_MODE, data);
3556                 adev->gfx.rlc.in_safe_mode = false;
3557         }
3558 }
3559
3560 static void gfx_v9_0_update_gfx_cg_power_gating(struct amdgpu_device *adev,
3561                                                 bool enable)
3562 {
3563         gfx_v9_0_enter_rlc_safe_mode(adev);
3564
3565         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_PG) && enable) {
3566                 gfx_v9_0_enable_gfx_cg_power_gating(adev, true);
3567                 if (adev->pg_flags & AMD_PG_SUPPORT_GFX_PIPELINE)
3568                         gfx_v9_0_enable_gfx_pipeline_powergating(adev, true);
3569         } else {
3570                 gfx_v9_0_enable_gfx_cg_power_gating(adev, false);
3571                 gfx_v9_0_enable_gfx_pipeline_powergating(adev, false);
3572         }
3573
3574         gfx_v9_0_exit_rlc_safe_mode(adev);
3575 }
3576
3577 static void gfx_v9_0_update_gfx_mg_power_gating(struct amdgpu_device *adev,
3578                                                 bool enable)
3579 {
3580         /* TODO: double check if we need to perform under safe mode */
3581         /* gfx_v9_0_enter_rlc_safe_mode(adev); */
3582
3583         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_SMG) && enable)
3584                 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, true);
3585         else
3586                 gfx_v9_0_enable_gfx_static_mg_power_gating(adev, false);
3587
3588         if ((adev->pg_flags & AMD_PG_SUPPORT_GFX_DMG) && enable)
3589                 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, true);
3590         else
3591                 gfx_v9_0_enable_gfx_dynamic_mg_power_gating(adev, false);
3592
3593         /* gfx_v9_0_exit_rlc_safe_mode(adev); */
3594 }
3595
3596 static void gfx_v9_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
3597                                                       bool enable)
3598 {
3599         uint32_t data, def;
3600
3601         /* It is disabled by HW by default */
3602         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG)) {
3603                 /* 1 - RLC_CGTT_MGCG_OVERRIDE */
3604                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3605
3606                 if (adev->asic_type != CHIP_VEGA12)
3607                         data &= ~RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
3608
3609                 data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3610                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3611                           RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3612
3613                 /* only for Vega10 & Raven1 */
3614                 data |= RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK;
3615
3616                 if (def != data)
3617                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3618
3619                 /* MGLS is a global flag to control all MGLS in GFX */
3620                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGLS) {
3621                         /* 2 - RLC memory Light sleep */
3622                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_RLC_LS) {
3623                                 def = data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3624                                 data |= RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3625                                 if (def != data)
3626                                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
3627                         }
3628                         /* 3 - CP memory Light sleep */
3629                         if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CP_LS) {
3630                                 def = data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3631                                 data |= CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3632                                 if (def != data)
3633                                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
3634                         }
3635                 }
3636         } else {
3637                 /* 1 - MGCG_OVERRIDE */
3638                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3639
3640                 if (adev->asic_type != CHIP_VEGA12)
3641                         data |= RLC_CGTT_MGCG_OVERRIDE__CPF_CGTT_SCLK_OVERRIDE_MASK;
3642
3643                 data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
3644                          RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
3645                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK |
3646                          RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGLS_OVERRIDE_MASK);
3647
3648                 if (def != data)
3649                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3650
3651                 /* 2 - disable MGLS in RLC */
3652                 data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3653                 if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK) {
3654                         data &= ~RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK;
3655                         WREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL, data);
3656                 }
3657
3658                 /* 3 - disable MGLS in CP */
3659                 data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3660                 if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK) {
3661                         data &= ~CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK;
3662                         WREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL, data);
3663                 }
3664         }
3665 }
3666
3667 static void gfx_v9_0_update_3d_clock_gating(struct amdgpu_device *adev,
3668                                            bool enable)
3669 {
3670         uint32_t data, def;
3671
3672         adev->gfx.rlc.funcs->enter_safe_mode(adev);
3673
3674         /* Enable 3D CGCG/CGLS */
3675         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)) {
3676                 /* write cmd to clear cgcg/cgls ov */
3677                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3678                 /* unset CGCG override */
3679                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
3680                 /* update CGCG and CGLS override bits */
3681                 if (def != data)
3682                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3683
3684                 /* enable 3Dcgcg FSM(0x0000363f) */
3685                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3686
3687                 data = (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3688                         RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
3689                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
3690                         data |= (0x000F << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3691                                 RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
3692                 if (def != data)
3693                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
3694
3695                 /* set IDLE_POLL_COUNT(0x00900100) */
3696                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
3697                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3698                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3699                 if (def != data)
3700                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
3701         } else {
3702                 /* Disable CGCG/CGLS */
3703                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3704                 /* disable cgcg, cgls should be disabled */
3705                 data &= ~(RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK |
3706                           RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK);
3707                 /* disable cgcg and cgls in FSM */
3708                 if (def != data)
3709                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D, data);
3710         }
3711
3712         adev->gfx.rlc.funcs->exit_safe_mode(adev);
3713 }
3714
3715 static void gfx_v9_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
3716                                                       bool enable)
3717 {
3718         uint32_t def, data;
3719
3720         adev->gfx.rlc.funcs->enter_safe_mode(adev);
3721
3722         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)) {
3723                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3724                 /* unset CGCG override */
3725                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
3726                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3727                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3728                 else
3729                         data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
3730                 /* update CGCG and CGLS override bits */
3731                 if (def != data)
3732                         WREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE, data);
3733
3734                 /* enable cgcg FSM(0x0000363F) */
3735                 def = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3736
3737                 data = (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
3738                         RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
3739                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
3740                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
3741                                 RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
3742                 if (def != data)
3743                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
3744
3745                 /* set IDLE_POLL_COUNT(0x00900100) */
3746                 def = RREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL);
3747                 data = (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
3748                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
3749                 if (def != data)
3750                         WREG32_SOC15(GC, 0, mmCP_RB_WPTR_POLL_CNTL, data);
3751         } else {
3752                 def = data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3753                 /* reset CGCG/CGLS bits */
3754                 data &= ~(RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK | RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK);
3755                 /* disable cgcg and cgls in FSM */
3756                 if (def != data)
3757                         WREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL, data);
3758         }
3759
3760         adev->gfx.rlc.funcs->exit_safe_mode(adev);
3761 }
3762
3763 static int gfx_v9_0_update_gfx_clock_gating(struct amdgpu_device *adev,
3764                                             bool enable)
3765 {
3766         if (enable) {
3767                 /* CGCG/CGLS should be enabled after MGCG/MGLS
3768                  * ===  MGCG + MGLS ===
3769                  */
3770                 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3771                 /* ===  CGCG /CGLS for GFX 3D Only === */
3772                 gfx_v9_0_update_3d_clock_gating(adev, enable);
3773                 /* ===  CGCG + CGLS === */
3774                 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3775         } else {
3776                 /* CGCG/CGLS should be disabled before MGCG/MGLS
3777                  * ===  CGCG + CGLS ===
3778                  */
3779                 gfx_v9_0_update_coarse_grain_clock_gating(adev, enable);
3780                 /* ===  CGCG /CGLS for GFX 3D Only === */
3781                 gfx_v9_0_update_3d_clock_gating(adev, enable);
3782                 /* ===  MGCG + MGLS === */
3783                 gfx_v9_0_update_medium_grain_clock_gating(adev, enable);
3784         }
3785         return 0;
3786 }
3787
3788 static const struct amdgpu_rlc_funcs gfx_v9_0_rlc_funcs = {
3789         .enter_safe_mode = gfx_v9_0_enter_rlc_safe_mode,
3790         .exit_safe_mode = gfx_v9_0_exit_rlc_safe_mode
3791 };
3792
3793 static int gfx_v9_0_set_powergating_state(void *handle,
3794                                           enum amd_powergating_state state)
3795 {
3796         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3797         bool enable = (state == AMD_PG_STATE_GATE) ? true : false;
3798
3799         switch (adev->asic_type) {
3800         case CHIP_RAVEN:
3801                 if (!enable) {
3802                         amdgpu_gfx_off_ctrl(adev, false);
3803                         cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
3804                 }
3805                 if (adev->pg_flags & AMD_PG_SUPPORT_RLC_SMU_HS) {
3806                         gfx_v9_0_enable_sck_slow_down_on_power_up(adev, true);
3807                         gfx_v9_0_enable_sck_slow_down_on_power_down(adev, true);
3808                 } else {
3809                         gfx_v9_0_enable_sck_slow_down_on_power_up(adev, false);
3810                         gfx_v9_0_enable_sck_slow_down_on_power_down(adev, false);
3811                 }
3812
3813                 if (adev->pg_flags & AMD_PG_SUPPORT_CP)
3814                         gfx_v9_0_enable_cp_power_gating(adev, true);
3815                 else
3816                         gfx_v9_0_enable_cp_power_gating(adev, false);
3817
3818                 /* update gfx cgpg state */
3819                 gfx_v9_0_update_gfx_cg_power_gating(adev, enable);
3820
3821                 /* update mgcg state */
3822                 gfx_v9_0_update_gfx_mg_power_gating(adev, enable);
3823
3824                 if (enable)
3825                         amdgpu_gfx_off_ctrl(adev, true);
3826                 break;
3827         case CHIP_VEGA12:
3828                 if (!enable) {
3829                         amdgpu_gfx_off_ctrl(adev, false);
3830                         cancel_delayed_work_sync(&adev->gfx.gfx_off_delay_work);
3831                 } else {
3832                         amdgpu_gfx_off_ctrl(adev, true);
3833                 }
3834                 break;
3835         default:
3836                 break;
3837         }
3838
3839         return 0;
3840 }
3841
3842 static int gfx_v9_0_set_clockgating_state(void *handle,
3843                                           enum amd_clockgating_state state)
3844 {
3845         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3846
3847         if (amdgpu_sriov_vf(adev))
3848                 return 0;
3849
3850         switch (adev->asic_type) {
3851         case CHIP_VEGA10:
3852         case CHIP_VEGA12:
3853         case CHIP_VEGA20:
3854         case CHIP_RAVEN:
3855                 gfx_v9_0_update_gfx_clock_gating(adev,
3856                                                  state == AMD_CG_STATE_GATE ? true : false);
3857                 break;
3858         default:
3859                 break;
3860         }
3861         return 0;
3862 }
3863
3864 static void gfx_v9_0_get_clockgating_state(void *handle, u32 *flags)
3865 {
3866         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
3867         int data;
3868
3869         if (amdgpu_sriov_vf(adev))
3870                 *flags = 0;
3871
3872         /* AMD_CG_SUPPORT_GFX_MGCG */
3873         data = RREG32_SOC15(GC, 0, mmRLC_CGTT_MGCG_OVERRIDE);
3874         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
3875                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
3876
3877         /* AMD_CG_SUPPORT_GFX_CGCG */
3878         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL);
3879         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
3880                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
3881
3882         /* AMD_CG_SUPPORT_GFX_CGLS */
3883         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
3884                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
3885
3886         /* AMD_CG_SUPPORT_GFX_RLC_LS */
3887         data = RREG32_SOC15(GC, 0, mmRLC_MEM_SLP_CNTL);
3888         if (data & RLC_MEM_SLP_CNTL__RLC_MEM_LS_EN_MASK)
3889                 *flags |= AMD_CG_SUPPORT_GFX_RLC_LS | AMD_CG_SUPPORT_GFX_MGLS;
3890
3891         /* AMD_CG_SUPPORT_GFX_CP_LS */
3892         data = RREG32_SOC15(GC, 0, mmCP_MEM_SLP_CNTL);
3893         if (data & CP_MEM_SLP_CNTL__CP_MEM_LS_EN_MASK)
3894                 *flags |= AMD_CG_SUPPORT_GFX_CP_LS | AMD_CG_SUPPORT_GFX_MGLS;
3895
3896         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
3897         data = RREG32_SOC15(GC, 0, mmRLC_CGCG_CGLS_CTRL_3D);
3898         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
3899                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
3900
3901         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
3902         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
3903                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
3904 }
3905
3906 static u64 gfx_v9_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
3907 {
3908         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 is 32bit rptr*/
3909 }
3910
3911 static u64 gfx_v9_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
3912 {
3913         struct amdgpu_device *adev = ring->adev;
3914         u64 wptr;
3915
3916         /* XXX check if swapping is necessary on BE */
3917         if (ring->use_doorbell) {
3918                 wptr = atomic64_read((atomic64_t *)&adev->wb.wb[ring->wptr_offs]);
3919         } else {
3920                 wptr = RREG32_SOC15(GC, 0, mmCP_RB0_WPTR);
3921                 wptr += (u64)RREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI) << 32;
3922         }
3923
3924         return wptr;
3925 }
3926
3927 static void gfx_v9_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
3928 {
3929         struct amdgpu_device *adev = ring->adev;
3930
3931         if (ring->use_doorbell) {
3932                 /* XXX check if swapping is necessary on BE */
3933                 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
3934                 WDOORBELL64(ring->doorbell_index, ring->wptr);
3935         } else {
3936                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR, lower_32_bits(ring->wptr));
3937                 WREG32_SOC15(GC, 0, mmCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
3938         }
3939 }
3940
3941 static void gfx_v9_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
3942 {
3943         struct amdgpu_device *adev = ring->adev;
3944         u32 ref_and_mask, reg_mem_engine;
3945         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio_funcs->hdp_flush_reg;
3946
3947         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
3948                 switch (ring->me) {
3949                 case 1:
3950                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
3951                         break;
3952                 case 2:
3953                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
3954                         break;
3955                 default:
3956                         return;
3957                 }
3958                 reg_mem_engine = 0;
3959         } else {
3960                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
3961                 reg_mem_engine = 1; /* pfp */
3962         }
3963
3964         gfx_v9_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
3965                               adev->nbio_funcs->get_hdp_flush_req_offset(adev),
3966                               adev->nbio_funcs->get_hdp_flush_done_offset(adev),
3967                               ref_and_mask, ref_and_mask, 0x20);
3968 }
3969
3970 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
3971                                       struct amdgpu_ib *ib,
3972                                       unsigned vmid, bool ctx_switch)
3973 {
3974         u32 header, control = 0;
3975
3976         if (ib->flags & AMDGPU_IB_FLAG_CE)
3977                 header = PACKET3(PACKET3_INDIRECT_BUFFER_CONST, 2);
3978         else
3979                 header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
3980
3981         control |= ib->length_dw | (vmid << 24);
3982
3983         if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
3984                 control |= INDIRECT_BUFFER_PRE_ENB(1);
3985
3986                 if (!(ib->flags & AMDGPU_IB_FLAG_CE))
3987                         gfx_v9_0_ring_emit_de_meta(ring);
3988         }
3989
3990         amdgpu_ring_write(ring, header);
3991         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
3992         amdgpu_ring_write(ring,
3993 #ifdef __BIG_ENDIAN
3994                 (2 << 0) |
3995 #endif
3996                 lower_32_bits(ib->gpu_addr));
3997         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
3998         amdgpu_ring_write(ring, control);
3999 }
4000
4001 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
4002                                           struct amdgpu_ib *ib,
4003                                           unsigned vmid, bool ctx_switch)
4004 {
4005         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
4006
4007         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
4008         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
4009         amdgpu_ring_write(ring,
4010 #ifdef __BIG_ENDIAN
4011                                 (2 << 0) |
4012 #endif
4013                                 lower_32_bits(ib->gpu_addr));
4014         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
4015         amdgpu_ring_write(ring, control);
4016 }
4017
4018 static void gfx_v9_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
4019                                      u64 seq, unsigned flags)
4020 {
4021         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
4022         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
4023         bool writeback = flags & AMDGPU_FENCE_FLAG_TC_WB_ONLY;
4024
4025         /* RELEASE_MEM - flush caches, send int */
4026         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
4027         amdgpu_ring_write(ring, ((writeback ? (EOP_TC_WB_ACTION_EN |
4028                                                EOP_TC_NC_ACTION_EN) :
4029                                               (EOP_TCL1_ACTION_EN |
4030                                                EOP_TC_ACTION_EN |
4031                                                EOP_TC_WB_ACTION_EN |
4032                                                EOP_TC_MD_ACTION_EN)) |
4033                                  EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
4034                                  EVENT_INDEX(5)));
4035         amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0));
4036
4037         /*
4038          * the address should be Qword aligned if 64bit write, Dword
4039          * aligned if only send 32bit data low (discard data high)
4040          */
4041         if (write64bit)
4042                 BUG_ON(addr & 0x7);
4043         else
4044                 BUG_ON(addr & 0x3);
4045         amdgpu_ring_write(ring, lower_32_bits(addr));
4046         amdgpu_ring_write(ring, upper_32_bits(addr));
4047         amdgpu_ring_write(ring, lower_32_bits(seq));
4048         amdgpu_ring_write(ring, upper_32_bits(seq));
4049         amdgpu_ring_write(ring, 0);
4050 }
4051
4052 static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
4053 {
4054         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4055         uint32_t seq = ring->fence_drv.sync_seq;
4056         uint64_t addr = ring->fence_drv.gpu_addr;
4057
4058         gfx_v9_0_wait_reg_mem(ring, usepfp, 1, 0,
4059                               lower_32_bits(addr), upper_32_bits(addr),
4060                               seq, 0xffffffff, 4);
4061 }
4062
4063 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
4064                                         unsigned vmid, uint64_t pd_addr)
4065 {
4066         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
4067
4068         /* compute doesn't have PFP */
4069         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
4070                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
4071                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
4072                 amdgpu_ring_write(ring, 0x0);
4073         }
4074 }
4075
4076 static u64 gfx_v9_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
4077 {
4078         return ring->adev->wb.wb[ring->rptr_offs]; /* gfx9 hardware is 32bit rptr */
4079 }
4080
4081 static u64 gfx_v9_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
4082 {
4083         u64 wptr;
4084
4085         /* XXX check if swapping is necessary on BE */
4086         if (ring->use_doorbell)
4087                 wptr = atomic64_read((atomic64_t *)&ring->adev->wb.wb[ring->wptr_offs]);
4088         else
4089                 BUG();
4090         return wptr;
4091 }
4092
4093 static void gfx_v9_0_ring_set_pipe_percent(struct amdgpu_ring *ring,
4094                                            bool acquire)
4095 {
4096         struct amdgpu_device *adev = ring->adev;
4097         int pipe_num, tmp, reg;
4098         int pipe_percent = acquire ? SPI_WCL_PIPE_PERCENT_GFX__VALUE_MASK : 0x1;
4099
4100         pipe_num = ring->me * adev->gfx.mec.num_pipe_per_mec + ring->pipe;
4101
4102         /* first me only has 2 entries, GFX and HP3D */
4103         if (ring->me > 0)
4104                 pipe_num -= 2;
4105
4106         reg = SOC15_REG_OFFSET(GC, 0, mmSPI_WCL_PIPE_PERCENT_GFX) + pipe_num;
4107         tmp = RREG32(reg);
4108         tmp = REG_SET_FIELD(tmp, SPI_WCL_PIPE_PERCENT_GFX, VALUE, pipe_percent);
4109         WREG32(reg, tmp);
4110 }
4111
4112 static void gfx_v9_0_pipe_reserve_resources(struct amdgpu_device *adev,
4113                                             struct amdgpu_ring *ring,
4114                                             bool acquire)
4115 {
4116         int i, pipe;
4117         bool reserve;
4118         struct amdgpu_ring *iring;
4119
4120         mutex_lock(&adev->gfx.pipe_reserve_mutex);
4121         pipe = amdgpu_gfx_queue_to_bit(adev, ring->me, ring->pipe, 0);
4122         if (acquire)
4123                 set_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4124         else
4125                 clear_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4126
4127         if (!bitmap_weight(adev->gfx.pipe_reserve_bitmap, AMDGPU_MAX_COMPUTE_QUEUES)) {
4128                 /* Clear all reservations - everyone reacquires all resources */
4129                 for (i = 0; i < adev->gfx.num_gfx_rings; ++i)
4130                         gfx_v9_0_ring_set_pipe_percent(&adev->gfx.gfx_ring[i],
4131                                                        true);
4132
4133                 for (i = 0; i < adev->gfx.num_compute_rings; ++i)
4134                         gfx_v9_0_ring_set_pipe_percent(&adev->gfx.compute_ring[i],
4135                                                        true);
4136         } else {
4137                 /* Lower all pipes without a current reservation */
4138                 for (i = 0; i < adev->gfx.num_gfx_rings; ++i) {
4139                         iring = &adev->gfx.gfx_ring[i];
4140                         pipe = amdgpu_gfx_queue_to_bit(adev,
4141                                                        iring->me,
4142                                                        iring->pipe,
4143                                                        0);
4144                         reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4145                         gfx_v9_0_ring_set_pipe_percent(iring, reserve);
4146                 }
4147
4148                 for (i = 0; i < adev->gfx.num_compute_rings; ++i) {
4149                         iring = &adev->gfx.compute_ring[i];
4150                         pipe = amdgpu_gfx_queue_to_bit(adev,
4151                                                        iring->me,
4152                                                        iring->pipe,
4153                                                        0);
4154                         reserve = test_bit(pipe, adev->gfx.pipe_reserve_bitmap);
4155                         gfx_v9_0_ring_set_pipe_percent(iring, reserve);
4156                 }
4157         }
4158
4159         mutex_unlock(&adev->gfx.pipe_reserve_mutex);
4160 }
4161
4162 static void gfx_v9_0_hqd_set_priority(struct amdgpu_device *adev,
4163                                       struct amdgpu_ring *ring,
4164                                       bool acquire)
4165 {
4166         uint32_t pipe_priority = acquire ? 0x2 : 0x0;
4167         uint32_t queue_priority = acquire ? 0xf : 0x0;
4168
4169         mutex_lock(&adev->srbm_mutex);
4170         soc15_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4171
4172         WREG32_SOC15(GC, 0, mmCP_HQD_PIPE_PRIORITY, pipe_priority);
4173         WREG32_SOC15(GC, 0, mmCP_HQD_QUEUE_PRIORITY, queue_priority);
4174
4175         soc15_grbm_select(adev, 0, 0, 0, 0);
4176         mutex_unlock(&adev->srbm_mutex);
4177 }
4178
4179 static void gfx_v9_0_ring_set_priority_compute(struct amdgpu_ring *ring,
4180                                                enum drm_sched_priority priority)
4181 {
4182         struct amdgpu_device *adev = ring->adev;
4183         bool acquire = priority == DRM_SCHED_PRIORITY_HIGH_HW;
4184
4185         if (ring->funcs->type != AMDGPU_RING_TYPE_COMPUTE)
4186                 return;
4187
4188         gfx_v9_0_hqd_set_priority(adev, ring, acquire);
4189         gfx_v9_0_pipe_reserve_resources(adev, ring, acquire);
4190 }
4191
4192 static void gfx_v9_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
4193 {
4194         struct amdgpu_device *adev = ring->adev;
4195
4196         /* XXX check if swapping is necessary on BE */
4197         if (ring->use_doorbell) {
4198                 atomic64_set((atomic64_t*)&adev->wb.wb[ring->wptr_offs], ring->wptr);
4199                 WDOORBELL64(ring->doorbell_index, ring->wptr);
4200         } else{
4201                 BUG(); /* only DOORBELL method supported on gfx9 now */
4202         }
4203 }
4204
4205 static void gfx_v9_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
4206                                          u64 seq, unsigned int flags)
4207 {
4208         struct amdgpu_device *adev = ring->adev;
4209
4210         /* we only allocate 32bit for each seq wb address */
4211         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
4212
4213         /* write fence seq to the "addr" */
4214         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4215         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4216                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
4217         amdgpu_ring_write(ring, lower_32_bits(addr));
4218         amdgpu_ring_write(ring, upper_32_bits(addr));
4219         amdgpu_ring_write(ring, lower_32_bits(seq));
4220
4221         if (flags & AMDGPU_FENCE_FLAG_INT) {
4222                 /* set register to trigger INT */
4223                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4224                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
4225                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
4226                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, mmCPC_INT_STATUS));
4227                 amdgpu_ring_write(ring, 0);
4228                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
4229         }
4230 }
4231
4232 static void gfx_v9_ring_emit_sb(struct amdgpu_ring *ring)
4233 {
4234         amdgpu_ring_write(ring, PACKET3(PACKET3_SWITCH_BUFFER, 0));
4235         amdgpu_ring_write(ring, 0);
4236 }
4237
4238 static void gfx_v9_0_ring_emit_ce_meta(struct amdgpu_ring *ring)
4239 {
4240         struct v9_ce_ib_state ce_payload = {0};
4241         uint64_t csa_addr;
4242         int cnt;
4243
4244         cnt = (sizeof(ce_payload) >> 2) + 4 - 2;
4245         csa_addr = amdgpu_csa_vaddr(ring->adev);
4246
4247         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4248         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(2) |
4249                                  WRITE_DATA_DST_SEL(8) |
4250                                  WR_CONFIRM) |
4251                                  WRITE_DATA_CACHE_POLICY(0));
4252         amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
4253         amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, ce_payload)));
4254         amdgpu_ring_write_multiple(ring, (void *)&ce_payload, sizeof(ce_payload) >> 2);
4255 }
4256
4257 static void gfx_v9_0_ring_emit_de_meta(struct amdgpu_ring *ring)
4258 {
4259         struct v9_de_ib_state de_payload = {0};
4260         uint64_t csa_addr, gds_addr;
4261         int cnt;
4262
4263         csa_addr = amdgpu_csa_vaddr(ring->adev);
4264         gds_addr = csa_addr + 4096;
4265         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
4266         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
4267
4268         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
4269         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
4270         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
4271                                  WRITE_DATA_DST_SEL(8) |
4272                                  WR_CONFIRM) |
4273                                  WRITE_DATA_CACHE_POLICY(0));
4274         amdgpu_ring_write(ring, lower_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
4275         amdgpu_ring_write(ring, upper_32_bits(csa_addr + offsetof(struct v9_gfx_meta_data, de_payload)));
4276         amdgpu_ring_write_multiple(ring, (void *)&de_payload, sizeof(de_payload) >> 2);
4277 }
4278
4279 static void gfx_v9_0_ring_emit_tmz(struct amdgpu_ring *ring, bool start)
4280 {
4281         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
4282         amdgpu_ring_write(ring, FRAME_CMD(start ? 0 : 1)); /* frame_end */
4283 }
4284
4285 static void gfx_v9_ring_emit_cntxcntl(struct amdgpu_ring *ring, uint32_t flags)
4286 {
4287         uint32_t dw2 = 0;
4288
4289         if (amdgpu_sriov_vf(ring->adev))
4290                 gfx_v9_0_ring_emit_ce_meta(ring);
4291
4292         gfx_v9_0_ring_emit_tmz(ring, true);
4293
4294         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
4295         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
4296                 /* set load_global_config & load_global_uconfig */
4297                 dw2 |= 0x8001;
4298                 /* set load_cs_sh_regs */
4299                 dw2 |= 0x01000000;
4300                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
4301                 dw2 |= 0x10002;
4302
4303                 /* set load_ce_ram if preamble presented */
4304                 if (AMDGPU_PREAMBLE_IB_PRESENT & flags)
4305                         dw2 |= 0x10000000;
4306         } else {
4307                 /* still load_ce_ram if this is the first time preamble presented
4308                  * although there is no context switch happens.
4309                  */
4310                 if (AMDGPU_PREAMBLE_IB_PRESENT_FIRST & flags)
4311                         dw2 |= 0x10000000;
4312         }
4313
4314         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
4315         amdgpu_ring_write(ring, dw2);
4316         amdgpu_ring_write(ring, 0);
4317 }
4318
4319 static unsigned gfx_v9_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
4320 {
4321         unsigned ret;
4322         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
4323         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
4324         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
4325         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
4326         ret = ring->wptr & ring->buf_mask;
4327         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
4328         return ret;
4329 }
4330
4331 static void gfx_v9_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
4332 {
4333         unsigned cur;
4334         BUG_ON(offset > ring->buf_mask);
4335         BUG_ON(ring->ring[offset] != 0x55aa55aa);
4336
4337         cur = (ring->wptr & ring->buf_mask) - 1;
4338         if (likely(cur > offset))
4339                 ring->ring[offset] = cur - offset;
4340         else
4341                 ring->ring[offset] = (ring->ring_size>>2) - offset + cur;
4342 }
4343
4344 static void gfx_v9_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg)
4345 {
4346         struct amdgpu_device *adev = ring->adev;
4347
4348         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
4349         amdgpu_ring_write(ring, 0 |     /* src: register*/
4350                                 (5 << 8) |      /* dst: memory */
4351                                 (1 << 20));     /* write confirm */
4352         amdgpu_ring_write(ring, reg);
4353         amdgpu_ring_write(ring, 0);
4354         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
4355                                 adev->virt.reg_val_offs * 4));
4356         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
4357                                 adev->virt.reg_val_offs * 4));
4358 }
4359
4360 static void gfx_v9_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
4361                                     uint32_t val)
4362 {
4363         uint32_t cmd = 0;
4364
4365         switch (ring->funcs->type) {
4366         case AMDGPU_RING_TYPE_GFX:
4367                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
4368                 break;
4369         case AMDGPU_RING_TYPE_KIQ:
4370                 cmd = (1 << 16); /* no inc addr */
4371                 break;
4372         default:
4373                 cmd = WR_CONFIRM;
4374                 break;
4375         }
4376         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
4377         amdgpu_ring_write(ring, cmd);
4378         amdgpu_ring_write(ring, reg);
4379         amdgpu_ring_write(ring, 0);
4380         amdgpu_ring_write(ring, val);
4381 }
4382
4383 static void gfx_v9_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
4384                                         uint32_t val, uint32_t mask)
4385 {
4386         gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
4387 }
4388
4389 static void gfx_v9_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
4390                                                   uint32_t reg0, uint32_t reg1,
4391                                                   uint32_t ref, uint32_t mask)
4392 {
4393         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
4394         struct amdgpu_device *adev = ring->adev;
4395         bool fw_version_ok = (ring->funcs->type == AMDGPU_RING_TYPE_GFX) ?
4396                 adev->gfx.me_fw_write_wait : adev->gfx.mec_fw_write_wait;
4397
4398         if (fw_version_ok)
4399                 gfx_v9_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
4400                                       ref, mask, 0x20);
4401         else
4402                 amdgpu_ring_emit_reg_write_reg_wait_helper(ring, reg0, reg1,
4403                                                            ref, mask);
4404 }
4405
4406 static void gfx_v9_0_ring_soft_recovery(struct amdgpu_ring *ring, unsigned vmid)
4407 {
4408         struct amdgpu_device *adev = ring->adev;
4409         uint32_t value = 0;
4410
4411         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
4412         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
4413         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
4414         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
4415         WREG32(mmSQ_CMD, value);
4416 }
4417
4418 static void gfx_v9_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
4419                                                  enum amdgpu_interrupt_state state)
4420 {
4421         switch (state) {
4422         case AMDGPU_IRQ_STATE_DISABLE:
4423         case AMDGPU_IRQ_STATE_ENABLE:
4424                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4425                                TIME_STAMP_INT_ENABLE,
4426                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4427                 break;
4428         default:
4429                 break;
4430         }
4431 }
4432
4433 static void gfx_v9_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
4434                                                      int me, int pipe,
4435                                                      enum amdgpu_interrupt_state state)
4436 {
4437         u32 mec_int_cntl, mec_int_cntl_reg;
4438
4439         /*
4440          * amdgpu controls only the first MEC. That's why this function only
4441          * handles the setting of interrupts for this specific MEC. All other
4442          * pipes' interrupts are set by amdkfd.
4443          */
4444
4445         if (me == 1) {
4446                 switch (pipe) {
4447                 case 0:
4448                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4449                         break;
4450                 case 1:
4451                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE1_INT_CNTL);
4452                         break;
4453                 case 2:
4454                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE2_INT_CNTL);
4455                         break;
4456                 case 3:
4457                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE3_INT_CNTL);
4458                         break;
4459                 default:
4460                         DRM_DEBUG("invalid pipe %d\n", pipe);
4461                         return;
4462                 }
4463         } else {
4464                 DRM_DEBUG("invalid me %d\n", me);
4465                 return;
4466         }
4467
4468         switch (state) {
4469         case AMDGPU_IRQ_STATE_DISABLE:
4470                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4471                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4472                                              TIME_STAMP_INT_ENABLE, 0);
4473                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4474                 break;
4475         case AMDGPU_IRQ_STATE_ENABLE:
4476                 mec_int_cntl = RREG32(mec_int_cntl_reg);
4477                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
4478                                              TIME_STAMP_INT_ENABLE, 1);
4479                 WREG32(mec_int_cntl_reg, mec_int_cntl);
4480                 break;
4481         default:
4482                 break;
4483         }
4484 }
4485
4486 static int gfx_v9_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
4487                                              struct amdgpu_irq_src *source,
4488                                              unsigned type,
4489                                              enum amdgpu_interrupt_state state)
4490 {
4491         switch (state) {
4492         case AMDGPU_IRQ_STATE_DISABLE:
4493         case AMDGPU_IRQ_STATE_ENABLE:
4494                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4495                                PRIV_REG_INT_ENABLE,
4496                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4497                 break;
4498         default:
4499                 break;
4500         }
4501
4502         return 0;
4503 }
4504
4505 static int gfx_v9_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
4506                                               struct amdgpu_irq_src *source,
4507                                               unsigned type,
4508                                               enum amdgpu_interrupt_state state)
4509 {
4510         switch (state) {
4511         case AMDGPU_IRQ_STATE_DISABLE:
4512         case AMDGPU_IRQ_STATE_ENABLE:
4513                 WREG32_FIELD15(GC, 0, CP_INT_CNTL_RING0,
4514                                PRIV_INSTR_INT_ENABLE,
4515                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
4516         default:
4517                 break;
4518         }
4519
4520         return 0;
4521 }
4522
4523 static int gfx_v9_0_set_eop_interrupt_state(struct amdgpu_device *adev,
4524                                             struct amdgpu_irq_src *src,
4525                                             unsigned type,
4526                                             enum amdgpu_interrupt_state state)
4527 {
4528         switch (type) {
4529         case AMDGPU_CP_IRQ_GFX_EOP:
4530                 gfx_v9_0_set_gfx_eop_interrupt_state(adev, state);
4531                 break;
4532         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
4533                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
4534                 break;
4535         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
4536                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
4537                 break;
4538         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
4539                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
4540                 break;
4541         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
4542                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
4543                 break;
4544         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE0_EOP:
4545                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 0, state);
4546                 break;
4547         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE1_EOP:
4548                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 1, state);
4549                 break;
4550         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE2_EOP:
4551                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 2, state);
4552                 break;
4553         case AMDGPU_CP_IRQ_COMPUTE_MEC2_PIPE3_EOP:
4554                 gfx_v9_0_set_compute_eop_interrupt_state(adev, 2, 3, state);
4555                 break;
4556         default:
4557                 break;
4558         }
4559         return 0;
4560 }
4561
4562 static int gfx_v9_0_eop_irq(struct amdgpu_device *adev,
4563                             struct amdgpu_irq_src *source,
4564                             struct amdgpu_iv_entry *entry)
4565 {
4566         int i;
4567         u8 me_id, pipe_id, queue_id;
4568         struct amdgpu_ring *ring;
4569
4570         DRM_DEBUG("IH: CP EOP\n");
4571         me_id = (entry->ring_id & 0x0c) >> 2;
4572         pipe_id = (entry->ring_id & 0x03) >> 0;
4573         queue_id = (entry->ring_id & 0x70) >> 4;
4574
4575         switch (me_id) {
4576         case 0:
4577                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
4578                 break;
4579         case 1:
4580         case 2:
4581                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4582                         ring = &adev->gfx.compute_ring[i];
4583                         /* Per-queue interrupt is supported for MEC starting from VI.
4584                           * The interrupt can only be enabled/disabled per pipe instead of per queue.
4585                           */
4586                         if ((ring->me == me_id) && (ring->pipe == pipe_id) && (ring->queue == queue_id))
4587                                 amdgpu_fence_process(ring);
4588                 }
4589                 break;
4590         }
4591         return 0;
4592 }
4593
4594 static int gfx_v9_0_priv_reg_irq(struct amdgpu_device *adev,
4595                                  struct amdgpu_irq_src *source,
4596                                  struct amdgpu_iv_entry *entry)
4597 {
4598         DRM_ERROR("Illegal register access in command stream\n");
4599         schedule_work(&adev->reset_work);
4600         return 0;
4601 }
4602
4603 static int gfx_v9_0_priv_inst_irq(struct amdgpu_device *adev,
4604                                   struct amdgpu_irq_src *source,
4605                                   struct amdgpu_iv_entry *entry)
4606 {
4607         DRM_ERROR("Illegal instruction in command stream\n");
4608         schedule_work(&adev->reset_work);
4609         return 0;
4610 }
4611
4612 static int gfx_v9_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
4613                                             struct amdgpu_irq_src *src,
4614                                             unsigned int type,
4615                                             enum amdgpu_interrupt_state state)
4616 {
4617         uint32_t tmp, target;
4618         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
4619
4620         if (ring->me == 1)
4621                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME1_PIPE0_INT_CNTL);
4622         else
4623                 target = SOC15_REG_OFFSET(GC, 0, mmCP_ME2_PIPE0_INT_CNTL);
4624         target += ring->pipe;
4625
4626         switch (type) {
4627         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
4628                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
4629                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
4630                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4631                                                  GENERIC2_INT_ENABLE, 0);
4632                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
4633
4634                         tmp = RREG32(target);
4635                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4636                                                  GENERIC2_INT_ENABLE, 0);
4637                         WREG32(target, tmp);
4638                 } else {
4639                         tmp = RREG32_SOC15(GC, 0, mmCPC_INT_CNTL);
4640                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
4641                                                  GENERIC2_INT_ENABLE, 1);
4642                         WREG32_SOC15(GC, 0, mmCPC_INT_CNTL, tmp);
4643
4644                         tmp = RREG32(target);
4645                         tmp = REG_SET_FIELD(tmp, CP_ME2_PIPE0_INT_CNTL,
4646                                                  GENERIC2_INT_ENABLE, 1);
4647                         WREG32(target, tmp);
4648                 }
4649                 break;
4650         default:
4651                 BUG(); /* kiq only support GENERIC2_INT now */
4652                 break;
4653         }
4654         return 0;
4655 }
4656
4657 static int gfx_v9_0_kiq_irq(struct amdgpu_device *adev,
4658                             struct amdgpu_irq_src *source,
4659                             struct amdgpu_iv_entry *entry)
4660 {
4661         u8 me_id, pipe_id, queue_id;
4662         struct amdgpu_ring *ring = &(adev->gfx.kiq.ring);
4663
4664         me_id = (entry->ring_id & 0x0c) >> 2;
4665         pipe_id = (entry->ring_id & 0x03) >> 0;
4666         queue_id = (entry->ring_id & 0x70) >> 4;
4667         DRM_DEBUG("IH: CPC GENERIC2_INT, me:%d, pipe:%d, queue:%d\n",
4668                    me_id, pipe_id, queue_id);
4669
4670         amdgpu_fence_process(ring);
4671         return 0;
4672 }
4673
4674 static const struct amd_ip_funcs gfx_v9_0_ip_funcs = {
4675         .name = "gfx_v9_0",
4676         .early_init = gfx_v9_0_early_init,
4677         .late_init = gfx_v9_0_late_init,
4678         .sw_init = gfx_v9_0_sw_init,
4679         .sw_fini = gfx_v9_0_sw_fini,
4680         .hw_init = gfx_v9_0_hw_init,
4681         .hw_fini = gfx_v9_0_hw_fini,
4682         .suspend = gfx_v9_0_suspend,
4683         .resume = gfx_v9_0_resume,
4684         .is_idle = gfx_v9_0_is_idle,
4685         .wait_for_idle = gfx_v9_0_wait_for_idle,
4686         .soft_reset = gfx_v9_0_soft_reset,
4687         .set_clockgating_state = gfx_v9_0_set_clockgating_state,
4688         .set_powergating_state = gfx_v9_0_set_powergating_state,
4689         .get_clockgating_state = gfx_v9_0_get_clockgating_state,
4690 };
4691
4692 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_gfx = {
4693         .type = AMDGPU_RING_TYPE_GFX,
4694         .align_mask = 0xff,
4695         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4696         .support_64bit_ptrs = true,
4697         .vmhub = AMDGPU_GFXHUB,
4698         .get_rptr = gfx_v9_0_ring_get_rptr_gfx,
4699         .get_wptr = gfx_v9_0_ring_get_wptr_gfx,
4700         .set_wptr = gfx_v9_0_ring_set_wptr_gfx,
4701         .emit_frame_size = /* totally 242 maximum if 16 IBs */
4702                 5 +  /* COND_EXEC */
4703                 7 +  /* PIPELINE_SYNC */
4704                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4705                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4706                 2 + /* VM_FLUSH */
4707                 8 +  /* FENCE for VM_FLUSH */
4708                 20 + /* GDS switch */
4709                 4 + /* double SWITCH_BUFFER,
4710                        the first COND_EXEC jump to the place just
4711                            prior to this double SWITCH_BUFFER  */
4712                 5 + /* COND_EXEC */
4713                 7 +      /*     HDP_flush */
4714                 4 +      /*     VGT_flush */
4715                 14 + /* CE_META */
4716                 31 + /* DE_META */
4717                 3 + /* CNTX_CTRL */
4718                 5 + /* HDP_INVL */
4719                 8 + 8 + /* FENCE x2 */
4720                 2, /* SWITCH_BUFFER */
4721         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_gfx */
4722         .emit_ib = gfx_v9_0_ring_emit_ib_gfx,
4723         .emit_fence = gfx_v9_0_ring_emit_fence,
4724         .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4725         .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4726         .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4727         .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4728         .test_ring = gfx_v9_0_ring_test_ring,
4729         .test_ib = gfx_v9_0_ring_test_ib,
4730         .insert_nop = amdgpu_ring_insert_nop,
4731         .pad_ib = amdgpu_ring_generic_pad_ib,
4732         .emit_switch_buffer = gfx_v9_ring_emit_sb,
4733         .emit_cntxcntl = gfx_v9_ring_emit_cntxcntl,
4734         .init_cond_exec = gfx_v9_0_ring_emit_init_cond_exec,
4735         .patch_cond_exec = gfx_v9_0_ring_emit_patch_cond_exec,
4736         .emit_tmz = gfx_v9_0_ring_emit_tmz,
4737         .emit_wreg = gfx_v9_0_ring_emit_wreg,
4738         .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4739         .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4740         .soft_recovery = gfx_v9_0_ring_soft_recovery,
4741 };
4742
4743 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_compute = {
4744         .type = AMDGPU_RING_TYPE_COMPUTE,
4745         .align_mask = 0xff,
4746         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4747         .support_64bit_ptrs = true,
4748         .vmhub = AMDGPU_GFXHUB,
4749         .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4750         .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4751         .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4752         .emit_frame_size =
4753                 20 + /* gfx_v9_0_ring_emit_gds_switch */
4754                 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4755                 5 + /* hdp invalidate */
4756                 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
4757                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4758                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4759                 2 + /* gfx_v9_0_ring_emit_vm_flush */
4760                 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence x3 for user fence, vm fence */
4761         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4762         .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4763         .emit_fence = gfx_v9_0_ring_emit_fence,
4764         .emit_pipeline_sync = gfx_v9_0_ring_emit_pipeline_sync,
4765         .emit_vm_flush = gfx_v9_0_ring_emit_vm_flush,
4766         .emit_gds_switch = gfx_v9_0_ring_emit_gds_switch,
4767         .emit_hdp_flush = gfx_v9_0_ring_emit_hdp_flush,
4768         .test_ring = gfx_v9_0_ring_test_ring,
4769         .test_ib = gfx_v9_0_ring_test_ib,
4770         .insert_nop = amdgpu_ring_insert_nop,
4771         .pad_ib = amdgpu_ring_generic_pad_ib,
4772         .set_priority = gfx_v9_0_ring_set_priority_compute,
4773         .emit_wreg = gfx_v9_0_ring_emit_wreg,
4774         .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4775         .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4776 };
4777
4778 static const struct amdgpu_ring_funcs gfx_v9_0_ring_funcs_kiq = {
4779         .type = AMDGPU_RING_TYPE_KIQ,
4780         .align_mask = 0xff,
4781         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
4782         .support_64bit_ptrs = true,
4783         .vmhub = AMDGPU_GFXHUB,
4784         .get_rptr = gfx_v9_0_ring_get_rptr_compute,
4785         .get_wptr = gfx_v9_0_ring_get_wptr_compute,
4786         .set_wptr = gfx_v9_0_ring_set_wptr_compute,
4787         .emit_frame_size =
4788                 20 + /* gfx_v9_0_ring_emit_gds_switch */
4789                 7 + /* gfx_v9_0_ring_emit_hdp_flush */
4790                 5 + /* hdp invalidate */
4791                 7 + /* gfx_v9_0_ring_emit_pipeline_sync */
4792                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
4793                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
4794                 2 + /* gfx_v9_0_ring_emit_vm_flush */
4795                 8 + 8 + 8, /* gfx_v9_0_ring_emit_fence_kiq x3 for user fence, vm fence */
4796         .emit_ib_size = 4, /* gfx_v9_0_ring_emit_ib_compute */
4797         .emit_ib = gfx_v9_0_ring_emit_ib_compute,
4798         .emit_fence = gfx_v9_0_ring_emit_fence_kiq,
4799         .test_ring = gfx_v9_0_ring_test_ring,
4800         .test_ib = gfx_v9_0_ring_test_ib,
4801         .insert_nop = amdgpu_ring_insert_nop,
4802         .pad_ib = amdgpu_ring_generic_pad_ib,
4803         .emit_rreg = gfx_v9_0_ring_emit_rreg,
4804         .emit_wreg = gfx_v9_0_ring_emit_wreg,
4805         .emit_reg_wait = gfx_v9_0_ring_emit_reg_wait,
4806         .emit_reg_write_reg_wait = gfx_v9_0_ring_emit_reg_write_reg_wait,
4807 };
4808
4809 static void gfx_v9_0_set_ring_funcs(struct amdgpu_device *adev)
4810 {
4811         int i;
4812
4813         adev->gfx.kiq.ring.funcs = &gfx_v9_0_ring_funcs_kiq;
4814
4815         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
4816                 adev->gfx.gfx_ring[i].funcs = &gfx_v9_0_ring_funcs_gfx;
4817
4818         for (i = 0; i < adev->gfx.num_compute_rings; i++)
4819                 adev->gfx.compute_ring[i].funcs = &gfx_v9_0_ring_funcs_compute;
4820 }
4821
4822 static const struct amdgpu_irq_src_funcs gfx_v9_0_kiq_irq_funcs = {
4823         .set = gfx_v9_0_kiq_set_interrupt_state,
4824         .process = gfx_v9_0_kiq_irq,
4825 };
4826
4827 static const struct amdgpu_irq_src_funcs gfx_v9_0_eop_irq_funcs = {
4828         .set = gfx_v9_0_set_eop_interrupt_state,
4829         .process = gfx_v9_0_eop_irq,
4830 };
4831
4832 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_reg_irq_funcs = {
4833         .set = gfx_v9_0_set_priv_reg_fault_state,
4834         .process = gfx_v9_0_priv_reg_irq,
4835 };
4836
4837 static const struct amdgpu_irq_src_funcs gfx_v9_0_priv_inst_irq_funcs = {
4838         .set = gfx_v9_0_set_priv_inst_fault_state,
4839         .process = gfx_v9_0_priv_inst_irq,
4840 };
4841
4842 static void gfx_v9_0_set_irq_funcs(struct amdgpu_device *adev)
4843 {
4844         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
4845         adev->gfx.eop_irq.funcs = &gfx_v9_0_eop_irq_funcs;
4846
4847         adev->gfx.priv_reg_irq.num_types = 1;
4848         adev->gfx.priv_reg_irq.funcs = &gfx_v9_0_priv_reg_irq_funcs;
4849
4850         adev->gfx.priv_inst_irq.num_types = 1;
4851         adev->gfx.priv_inst_irq.funcs = &gfx_v9_0_priv_inst_irq_funcs;
4852
4853         adev->gfx.kiq.irq.num_types = AMDGPU_CP_KIQ_IRQ_LAST;
4854         adev->gfx.kiq.irq.funcs = &gfx_v9_0_kiq_irq_funcs;
4855 }
4856
4857 static void gfx_v9_0_set_rlc_funcs(struct amdgpu_device *adev)
4858 {
4859         switch (adev->asic_type) {
4860         case CHIP_VEGA10:
4861         case CHIP_VEGA12:
4862         case CHIP_VEGA20:
4863         case CHIP_RAVEN:
4864                 adev->gfx.rlc.funcs = &gfx_v9_0_rlc_funcs;
4865                 break;
4866         default:
4867                 break;
4868         }
4869 }
4870
4871 static void gfx_v9_0_set_gds_init(struct amdgpu_device *adev)
4872 {
4873         /* init asci gds info */
4874         adev->gds.mem.total_size = RREG32_SOC15(GC, 0, mmGDS_VMID0_SIZE);
4875         adev->gds.gws.total_size = 64;
4876         adev->gds.oa.total_size = 16;
4877
4878         if (adev->gds.mem.total_size == 64 * 1024) {
4879                 adev->gds.mem.gfx_partition_size = 4096;
4880                 adev->gds.mem.cs_partition_size = 4096;
4881
4882                 adev->gds.gws.gfx_partition_size = 4;
4883                 adev->gds.gws.cs_partition_size = 4;
4884
4885                 adev->gds.oa.gfx_partition_size = 4;
4886                 adev->gds.oa.cs_partition_size = 1;
4887         } else {
4888                 adev->gds.mem.gfx_partition_size = 1024;
4889                 adev->gds.mem.cs_partition_size = 1024;
4890
4891                 adev->gds.gws.gfx_partition_size = 16;
4892                 adev->gds.gws.cs_partition_size = 16;
4893
4894                 adev->gds.oa.gfx_partition_size = 4;
4895                 adev->gds.oa.cs_partition_size = 4;
4896         }
4897 }
4898
4899 static void gfx_v9_0_set_user_cu_inactive_bitmap(struct amdgpu_device *adev,
4900                                                  u32 bitmap)
4901 {
4902         u32 data;
4903
4904         if (!bitmap)
4905                 return;
4906
4907         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4908         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4909
4910         WREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG, data);
4911 }
4912
4913 static u32 gfx_v9_0_get_cu_active_bitmap(struct amdgpu_device *adev)
4914 {
4915         u32 data, mask;
4916
4917         data = RREG32_SOC15(GC, 0, mmCC_GC_SHADER_ARRAY_CONFIG);
4918         data |= RREG32_SOC15(GC, 0, mmGC_USER_SHADER_ARRAY_CONFIG);
4919
4920         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS_MASK;
4921         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_CUS__SHIFT;
4922
4923         mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh);
4924
4925         return (~data) & mask;
4926 }
4927
4928 static int gfx_v9_0_get_cu_info(struct amdgpu_device *adev,
4929                                  struct amdgpu_cu_info *cu_info)
4930 {
4931         int i, j, k, counter, active_cu_number = 0;
4932         u32 mask, bitmap, ao_bitmap, ao_cu_mask = 0;
4933         unsigned disable_masks[4 * 2];
4934
4935         if (!adev || !cu_info)
4936                 return -EINVAL;
4937
4938         amdgpu_gfx_parse_disable_cu(disable_masks, 4, 2);
4939
4940         mutex_lock(&adev->grbm_idx_mutex);
4941         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
4942                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
4943                         mask = 1;
4944                         ao_bitmap = 0;
4945                         counter = 0;
4946                         gfx_v9_0_select_se_sh(adev, i, j, 0xffffffff);
4947                         if (i < 4 && j < 2)
4948                                 gfx_v9_0_set_user_cu_inactive_bitmap(
4949                                         adev, disable_masks[i * 2 + j]);
4950                         bitmap = gfx_v9_0_get_cu_active_bitmap(adev);
4951                         cu_info->bitmap[i][j] = bitmap;
4952
4953                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k ++) {
4954                                 if (bitmap & mask) {
4955                                         if (counter < adev->gfx.config.max_cu_per_sh)
4956                                                 ao_bitmap |= mask;
4957                                         counter ++;
4958                                 }
4959                                 mask <<= 1;
4960                         }
4961                         active_cu_number += counter;
4962                         if (i < 2 && j < 2)
4963                                 ao_cu_mask |= (ao_bitmap << (i * 16 + j * 8));
4964                         cu_info->ao_cu_bitmap[i][j] = ao_bitmap;
4965                 }
4966         }
4967         gfx_v9_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff);
4968         mutex_unlock(&adev->grbm_idx_mutex);
4969
4970         cu_info->number = active_cu_number;
4971         cu_info->ao_cu_mask = ao_cu_mask;
4972         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
4973
4974         return 0;
4975 }
4976
4977 const struct amdgpu_ip_block_version gfx_v9_0_ip_block =
4978 {
4979         .type = AMD_IP_BLOCK_TYPE_GFX,
4980         .major = 9,
4981         .minor = 0,
4982         .rev = 0,
4983         .funcs = &gfx_v9_0_ip_funcs,
4984 };