drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c

   1 /*
   2  * Copyright 2009 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the
   7  * "Software"), to deal in the Software without restriction, including
   8  * without limitation the rights to use, copy, modify, merge, publish,
   9  * distribute, sub license, and/or sell copies of the Software, and to
  10  * permit persons to whom the Software is furnished to do so, subject to
  11  * the following conditions:
  12  *
  13  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  14  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  15  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  16  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  17  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  18  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  19  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  20  *
  21  * The above copyright notice and this permission notice (including the
  22  * next paragraph) shall be included in all copies or substantial portions
  23  * of the Software.
  24  *
  25  */
  26 /*
  27  * Authors:
  28  *    Jerome Glisse <[email protected]>
  29  *    Dave Airlie
  30  */
  31 #include <linux/seq_file.h>
  32 #include <linux/atomic.h>
  33 #include <linux/wait.h>
  34 #include <linux/kref.h>
  35 #include <linux/slab.h>
  36 #include <linux/firmware.h>
  37 #include <drm/drmP.h>
  38 #include "amdgpu.h"
  39 #include "amdgpu_trace.h"
  40
  41 /*
  42  * Fences
  43  * Fences mark an event in the GPUs pipeline and are used
  44  * for GPU/CPU synchronization.  When the fence is written,
  45  * it is expected that all buffers associated with that fence
  46  * are no longer in use by the associated ring on the GPU and
  47  * that the the relevant GPU caches have been flushed.
  48  */
  49
  50 struct amdgpu_fence {
  51         struct dma_fence base;
  52
  53         /* RB, DMA, etc. */
  54         struct amdgpu_ring              *ring;
  55 };
  56
  57 static struct kmem_cache *amdgpu_fence_slab;
  58
  59 int amdgpu_fence_slab_init(void)
  60 {
  61         amdgpu_fence_slab = kmem_cache_create(
  62                 "amdgpu_fence", sizeof(struct amdgpu_fence), 0,
  63                 SLAB_HWCACHE_ALIGN, NULL);
  64         if (!amdgpu_fence_slab)
  65                 return -ENOMEM;
  66         return 0;
  67 }
  68
  69 void amdgpu_fence_slab_fini(void)
  70 {
  71         rcu_barrier();
  72         kmem_cache_destroy(amdgpu_fence_slab);
  73 }
  74 /*
  75  * Cast helper
  76  */
  77 static const struct dma_fence_ops amdgpu_fence_ops;
  78 static inline struct amdgpu_fence *to_amdgpu_fence(struct dma_fence *f)
  79 {
  80         struct amdgpu_fence *__f = container_of(f, struct amdgpu_fence, base);
  81
  82         if (__f->base.ops == &amdgpu_fence_ops)
  83                 return __f;
  84
  85         return NULL;
  86 }
  87
  88 /**
  89  * amdgpu_fence_write - write a fence value
  90  *
  91  * @ring: ring the fence is associated with
  92  * @seq: sequence number to write
  93  *
  94  * Writes a fence value to memory (all asics).
  95  */
  96 static void amdgpu_fence_write(struct amdgpu_ring *ring, u32 seq)
  97 {
  98         struct amdgpu_fence_driver *drv = &ring->fence_drv;
  99
 100         if (drv->cpu_addr)
 101                 *drv->cpu_addr = cpu_to_le32(seq);
 102 }
 103
 104 /**
 105  * amdgpu_fence_read - read a fence value
 106  *
 107  * @ring: ring the fence is associated with
 108  *
 109  * Reads a fence value from memory (all asics).
 110  * Returns the value of the fence read from memory.
 111  */
 112 static u32 amdgpu_fence_read(struct amdgpu_ring *ring)
 113 {
 114         struct amdgpu_fence_driver *drv = &ring->fence_drv;
 115         u32 seq = 0;
 116
 117         if (drv->cpu_addr)
 118                 seq = le32_to_cpu(*drv->cpu_addr);
 119         else
 120                 seq = atomic_read(&drv->last_seq);
 121
 122         return seq;
 123 }
 124
 125 /**
 126  * amdgpu_fence_emit - emit a fence on the requested ring
 127  *
 128  * @ring: ring the fence is associated with
 129  * @f: resulting fence object
 130  *
 131  * Emits a fence command on the requested ring (all asics).
 132  * Returns 0 on success, -ENOMEM on failure.
 133  */
 134 int amdgpu_fence_emit(struct amdgpu_ring *ring, struct dma_fence **f,
 135                       unsigned flags)
 136 {
 137         struct amdgpu_device *adev = ring->adev;
 138         struct amdgpu_fence *fence;
 139         struct dma_fence *old, **ptr;
 140         uint32_t seq;
 141
 142         fence = kmem_cache_alloc(amdgpu_fence_slab, GFP_KERNEL);
 143         if (fence == NULL)
 144                 return -ENOMEM;
 145
 146         seq = ++ring->fence_drv.sync_seq;
 147         fence->ring = ring;
 148         dma_fence_init(&fence->base, &amdgpu_fence_ops,
 149                        &ring->fence_drv.lock,
 150                        adev->fence_context + ring->idx,
 151                        seq);
 152         amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
 153                                seq, flags | AMDGPU_FENCE_FLAG_INT);
 154
 155         ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
 156         /* This function can't be called concurrently anyway, otherwise
 157          * emitting the fence would mess up the hardware ring buffer.
 158          */
 159         old = rcu_dereference_protected(*ptr, 1);
 160         if (old && !dma_fence_is_signaled(old)) {
 161                 DRM_INFO("rcu slot is busy\n");
 162                 dma_fence_wait(old, false);
 163         }
 164
 165         rcu_assign_pointer(*ptr, dma_fence_get(&fence->base));
 166
 167         *f = &fence->base;
 168
 169         return 0;
 170 }
 171
 172 /**
 173  * amdgpu_fence_emit_polling - emit a fence on the requeste ring
 174  *
 175  * @ring: ring the fence is associated with
 176  * @s: resulting sequence number
 177  *
 178  * Emits a fence command on the requested ring (all asics).
 179  * Used For polling fence.
 180  * Returns 0 on success, -ENOMEM on failure.
 181  */
 182 int amdgpu_fence_emit_polling(struct amdgpu_ring *ring, uint32_t *s)
 183 {
 184         uint32_t seq;
 185
 186         if (!s)
 187                 return -EINVAL;
 188
 189         seq = ++ring->fence_drv.sync_seq;
 190         amdgpu_ring_emit_fence(ring, ring->fence_drv.gpu_addr,
 191                                seq, 0);
 192
 193         *s = seq;
 194
 195         return 0;
 196 }
 197
 198 /**
 199  * amdgpu_fence_schedule_fallback - schedule fallback check
 200  *
 201  * @ring: pointer to struct amdgpu_ring
 202  *
 203  * Start a timer as fallback to our interrupts.
 204  */
 205 static void amdgpu_fence_schedule_fallback(struct amdgpu_ring *ring)
 206 {
 207         mod_timer(&ring->fence_drv.fallback_timer,
 208                   jiffies + AMDGPU_FENCE_JIFFIES_TIMEOUT);
 209 }
 210
 211 /**
 212  * amdgpu_fence_process - check for fence activity
 213  *
 214  * @ring: pointer to struct amdgpu_ring
 215  *
 216  * Checks the current fence value and calculates the last
 217  * signalled fence value. Wakes the fence queue if the
 218  * sequence number has increased.
 219  */
 220 void amdgpu_fence_process(struct amdgpu_ring *ring)
 221 {
 222         struct amdgpu_fence_driver *drv = &ring->fence_drv;
 223         uint32_t seq, last_seq;
 224         int r;
 225
 226         do {
 227                 last_seq = atomic_read(&ring->fence_drv.last_seq);
 228                 seq = amdgpu_fence_read(ring);
 229
 230         } while (atomic_cmpxchg(&drv->last_seq, last_seq, seq) != last_seq);
 231
 232         if (seq != ring->fence_drv.sync_seq)
 233                 amdgpu_fence_schedule_fallback(ring);
 234
 235         if (unlikely(seq == last_seq))
 236                 return;
 237
 238         last_seq &= drv->num_fences_mask;
 239         seq &= drv->num_fences_mask;
 240
 241         do {
 242                 struct dma_fence *fence, **ptr;
 243
 244                 ++last_seq;
 245                 last_seq &= drv->num_fences_mask;
 246                 ptr = &drv->fences[last_seq];
 247
 248                 /* There is always exactly one thread signaling this fence slot */
 249                 fence = rcu_dereference_protected(*ptr, 1);
 250                 RCU_INIT_POINTER(*ptr, NULL);
 251
 252                 if (!fence)
 253                         continue;
 254
 255                 r = dma_fence_signal(fence);
 256                 if (!r)
 257                         DMA_FENCE_TRACE(fence, "signaled from irq context\n");
 258                 else
 259                         BUG();
 260
 261                 dma_fence_put(fence);
 262         } while (last_seq != seq);
 263 }
 264
 265 /**
 266  * amdgpu_fence_fallback - fallback for hardware interrupts
 267  *
 268  * @work: delayed work item
 269  *
 270  * Checks for fence activity.
 271  */
 272 static void amdgpu_fence_fallback(struct timer_list *t)
 273 {
 274         struct amdgpu_ring *ring = from_timer(ring, t,
 275                                               fence_drv.fallback_timer);
 276
 277         DRM_INFO("Fallback to SW interrupt on ring %s due to HW interrupt time out", ring->name);
 278         amdgpu_fence_process(ring);
 279 }
 280
 281 /**
 282  * amdgpu_fence_wait_empty - wait for all fences to signal
 283  *
 284  * @adev: amdgpu device pointer
 285  * @ring: ring index the fence is associated with
 286  *
 287  * Wait for all fences on the requested ring to signal (all asics).
 288  * Returns 0 if the fences have passed, error for all other cases.
 289  */
 290 int amdgpu_fence_wait_empty(struct amdgpu_ring *ring)
 291 {
 292         uint64_t seq = READ_ONCE(ring->fence_drv.sync_seq);
 293         struct dma_fence *fence, **ptr;
 294         int r;
 295
 296         if (!seq)
 297                 return 0;
 298
 299         ptr = &ring->fence_drv.fences[seq & ring->fence_drv.num_fences_mask];
 300         rcu_read_lock();
 301         fence = rcu_dereference(*ptr);
 302         if (!fence || !dma_fence_get_rcu(fence)) {
 303                 rcu_read_unlock();
 304                 return 0;
 305         }
 306         rcu_read_unlock();
 307
 308         r = dma_fence_wait(fence, false);
 309         dma_fence_put(fence);
 310         return r;
 311 }
 312
 313 /**
 314  * amdgpu_fence_wait_polling - busy wait for givn sequence number
 315  *
 316  * @ring: ring index the fence is associated with
 317  * @wait_seq: sequence number to wait
 318  * @timeout: the timeout for waiting in usecs
 319  *
 320  * Wait for all fences on the requested ring to signal (all asics).
 321  * Returns left time if no timeout, 0 or minus if timeout.
 322  */
 323 signed long amdgpu_fence_wait_polling(struct amdgpu_ring *ring,
 324                                       uint32_t wait_seq,
 325                                       signed long timeout)
 326 {
 327         uint32_t seq;
 328
 329         do {
 330                 seq = amdgpu_fence_read(ring);
 331                 udelay(5);
 332                 timeout -= 5;
 333         } while ((int32_t)(wait_seq - seq) > 0 && timeout > 0);
 334
 335         return timeout > 0 ? timeout : 0;
 336 }
 337 /**
 338  * amdgpu_fence_count_emitted - get the count of emitted fences
 339  *
 340  * @ring: ring the fence is associated with
 341  *
 342  * Get the number of fences emitted on the requested ring (all asics).
 343  * Returns the number of emitted fences on the ring.  Used by the
 344  * dynpm code to ring track activity.
 345  */
 346 unsigned amdgpu_fence_count_emitted(struct amdgpu_ring *ring)
 347 {
 348         uint64_t emitted;
 349
 350         /* We are not protected by ring lock when reading the last sequence
 351          * but it's ok to report slightly wrong fence count here.
 352          */
 353         amdgpu_fence_process(ring);
 354         emitted = 0x100000000ull;
 355         emitted -= atomic_read(&ring->fence_drv.last_seq);
 356         emitted += READ_ONCE(ring->fence_drv.sync_seq);
 357         return lower_32_bits(emitted);
 358 }
 359
 360 /**
 361  * amdgpu_fence_driver_start_ring - make the fence driver
 362  * ready for use on the requested ring.
 363  *
 364  * @ring: ring to start the fence driver on
 365  * @irq_src: interrupt source to use for this ring
 366  * @irq_type: interrupt type to use for this ring
 367  *
 368  * Make the fence driver ready for processing (all asics).
 369  * Not all asics have all rings, so each asic will only
 370  * start the fence driver on the rings it has.
 371  * Returns 0 for success, errors for failure.
 372  */
 373 int amdgpu_fence_driver_start_ring(struct amdgpu_ring *ring,
 374                                    struct amdgpu_irq_src *irq_src,
 375                                    unsigned irq_type)
 376 {
 377         struct amdgpu_device *adev = ring->adev;
 378         uint64_t index;
 379
 380         if (ring->funcs->type != AMDGPU_RING_TYPE_UVD) {
 381                 ring->fence_drv.cpu_addr = &adev->wb.wb[ring->fence_offs];
 382                 ring->fence_drv.gpu_addr = adev->wb.gpu_addr + (ring->fence_offs * 4);
 383         } else {
 384                 /* put fence directly behind firmware */
 385                 index = ALIGN(adev->uvd.fw->size, 8);
 386                 ring->fence_drv.cpu_addr = adev->uvd.inst[ring->me].cpu_addr + index;
 387                 ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index;
 388         }
 389         amdgpu_fence_write(ring, atomic_read(&ring->fence_drv.last_seq));
 390         amdgpu_irq_get(adev, irq_src, irq_type);
 391
 392         ring->fence_drv.irq_src = irq_src;
 393         ring->fence_drv.irq_type = irq_type;
 394         ring->fence_drv.initialized = true;
 395
 396         dev_dbg(adev->dev, "fence driver on ring %d use gpu addr 0x%016llx, "
 397                 "cpu addr 0x%p\n", ring->idx,
 398                 ring->fence_drv.gpu_addr, ring->fence_drv.cpu_addr);
 399         return 0;
 400 }
 401
 402 /**
 403  * amdgpu_fence_driver_init_ring - init the fence driver
 404  * for the requested ring.
 405  *
 406  * @ring: ring to init the fence driver on
 407  * @num_hw_submission: number of entries on the hardware queue
 408  *
 409  * Init the fence driver for the requested ring (all asics).
 410  * Helper function for amdgpu_fence_driver_init().
 411  */
 412 int amdgpu_fence_driver_init_ring(struct amdgpu_ring *ring,
 413                                   unsigned num_hw_submission)
 414 {
 415         long timeout;
 416         int r;
 417
 418         /* Check that num_hw_submission is a power of two */
 419         if ((num_hw_submission & (num_hw_submission - 1)) != 0)
 420                 return -EINVAL;
 421
 422         ring->fence_drv.cpu_addr = NULL;
 423         ring->fence_drv.gpu_addr = 0;
 424         ring->fence_drv.sync_seq = 0;
 425         atomic_set(&ring->fence_drv.last_seq, 0);
 426         ring->fence_drv.initialized = false;
 427
 428         timer_setup(&ring->fence_drv.fallback_timer, amdgpu_fence_fallback, 0);
 429
 430         ring->fence_drv.num_fences_mask = num_hw_submission * 2 - 1;
 431         spin_lock_init(&ring->fence_drv.lock);
 432         ring->fence_drv.fences = kcalloc(num_hw_submission * 2, sizeof(void *),
 433                                          GFP_KERNEL);
 434         if (!ring->fence_drv.fences)
 435                 return -ENOMEM;
 436
 437         /* No need to setup the GPU scheduler for KIQ ring */
 438         if (ring->funcs->type != AMDGPU_RING_TYPE_KIQ) {
 439                 /* for non-sriov case, no timeout enforce on compute ring */
 440                 if ((ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE)
 441                                 && !amdgpu_sriov_vf(ring->adev))
 442                         timeout = MAX_SCHEDULE_TIMEOUT;
 443                 else
 444                         timeout = msecs_to_jiffies(amdgpu_lockup_timeout);
 445
 446                 r = drm_sched_init(&ring->sched, &amdgpu_sched_ops,
 447                                    num_hw_submission, amdgpu_job_hang_limit,
 448                                    timeout, ring->name);
 449                 if (r) {
 450                         DRM_ERROR("Failed to create scheduler on ring %s.\n",
 451                                   ring->name);
 452                         return r;
 453                 }
 454         }
 455
 456         return 0;
 457 }
 458
 459 /**
 460  * amdgpu_fence_driver_init - init the fence driver
 461  * for all possible rings.
 462  *
 463  * @adev: amdgpu device pointer
 464  *
 465  * Init the fence driver for all possible rings (all asics).
 466  * Not all asics have all rings, so each asic will only
 467  * start the fence driver on the rings it has using
 468  * amdgpu_fence_driver_start_ring().
 469  * Returns 0 for success.
 470  */
 471 int amdgpu_fence_driver_init(struct amdgpu_device *adev)
 472 {
 473         if (amdgpu_debugfs_fence_init(adev))
 474                 dev_err(adev->dev, "fence debugfs file creation failed\n");
 475
 476         return 0;
 477 }
 478
 479 /**
 480  * amdgpu_fence_driver_fini - tear down the fence driver
 481  * for all possible rings.
 482  *
 483  * @adev: amdgpu device pointer
 484  *
 485  * Tear down the fence driver for all possible rings (all asics).
 486  */
 487 void amdgpu_fence_driver_fini(struct amdgpu_device *adev)
 488 {
 489         unsigned i, j;
 490         int r;
 491
 492         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 493                 struct amdgpu_ring *ring = adev->rings[i];
 494
 495                 if (!ring || !ring->fence_drv.initialized)
 496                         continue;
 497                 r = amdgpu_fence_wait_empty(ring);
 498                 if (r) {
 499                         /* no need to trigger GPU reset as we are unloading */
 500                         amdgpu_fence_driver_force_completion(ring);
 501                 }
 502                 amdgpu_irq_put(adev, ring->fence_drv.irq_src,
 503                                ring->fence_drv.irq_type);
 504                 drm_sched_fini(&ring->sched);
 505                 del_timer_sync(&ring->fence_drv.fallback_timer);
 506                 for (j = 0; j <= ring->fence_drv.num_fences_mask; ++j)
 507                         dma_fence_put(ring->fence_drv.fences[j]);
 508                 kfree(ring->fence_drv.fences);
 509                 ring->fence_drv.fences = NULL;
 510                 ring->fence_drv.initialized = false;
 511         }
 512 }
 513
 514 /**
 515  * amdgpu_fence_driver_suspend - suspend the fence driver
 516  * for all possible rings.
 517  *
 518  * @adev: amdgpu device pointer
 519  *
 520  * Suspend the fence driver for all possible rings (all asics).
 521  */
 522 void amdgpu_fence_driver_suspend(struct amdgpu_device *adev)
 523 {
 524         int i, r;
 525
 526         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 527                 struct amdgpu_ring *ring = adev->rings[i];
 528                 if (!ring || !ring->fence_drv.initialized)
 529                         continue;
 530
 531                 /* wait for gpu to finish processing current batch */
 532                 r = amdgpu_fence_wait_empty(ring);
 533                 if (r) {
 534                         /* delay GPU reset to resume */
 535                         amdgpu_fence_driver_force_completion(ring);
 536                 }
 537
 538                 /* disable the interrupt */
 539                 amdgpu_irq_put(adev, ring->fence_drv.irq_src,
 540                                ring->fence_drv.irq_type);
 541         }
 542 }
 543
 544 /**
 545  * amdgpu_fence_driver_resume - resume the fence driver
 546  * for all possible rings.
 547  *
 548  * @adev: amdgpu device pointer
 549  *
 550  * Resume the fence driver for all possible rings (all asics).
 551  * Not all asics have all rings, so each asic will only
 552  * start the fence driver on the rings it has using
 553  * amdgpu_fence_driver_start_ring().
 554  * Returns 0 for success.
 555  */
 556 void amdgpu_fence_driver_resume(struct amdgpu_device *adev)
 557 {
 558         int i;
 559
 560         for (i = 0; i < AMDGPU_MAX_RINGS; i++) {
 561                 struct amdgpu_ring *ring = adev->rings[i];
 562                 if (!ring || !ring->fence_drv.initialized)
 563                         continue;
 564
 565                 /* enable the interrupt */
 566                 amdgpu_irq_get(adev, ring->fence_drv.irq_src,
 567                                ring->fence_drv.irq_type);
 568         }
 569 }
 570
 571 /**
 572  * amdgpu_fence_driver_force_completion - force signal latest fence of ring
 573  *
 574  * @ring: fence of the ring to signal
 575  *
 576  */
 577 void amdgpu_fence_driver_force_completion(struct amdgpu_ring *ring)
 578 {
 579         amdgpu_fence_write(ring, ring->fence_drv.sync_seq);
 580         amdgpu_fence_process(ring);
 581 }
 582
 583 /*
 584  * Common fence implementation
 585  */
 586
 587 static const char *amdgpu_fence_get_driver_name(struct dma_fence *fence)
 588 {
 589         return "amdgpu";
 590 }
 591
 592 static const char *amdgpu_fence_get_timeline_name(struct dma_fence *f)
 593 {
 594         struct amdgpu_fence *fence = to_amdgpu_fence(f);
 595         return (const char *)fence->ring->name;
 596 }
 597
 598 /**
 599  * amdgpu_fence_enable_signaling - enable signalling on fence
 600  * @fence: fence
 601  *
 602  * This function is called with fence_queue lock held, and adds a callback
 603  * to fence_queue that checks if this fence is signaled, and if so it
 604  * signals the fence and removes itself.
 605  */
 606 static bool amdgpu_fence_enable_signaling(struct dma_fence *f)
 607 {
 608         struct amdgpu_fence *fence = to_amdgpu_fence(f);
 609         struct amdgpu_ring *ring = fence->ring;
 610
 611         if (!timer_pending(&ring->fence_drv.fallback_timer))
 612                 amdgpu_fence_schedule_fallback(ring);
 613
 614         DMA_FENCE_TRACE(&fence->base, "armed on ring %i!\n", ring->idx);
 615
 616         return true;
 617 }
 618
 619 /**
 620  * amdgpu_fence_free - free up the fence memory
 621  *
 622  * @rcu: RCU callback head
 623  *
 624  * Free up the fence memory after the RCU grace period.
 625  */
 626 static void amdgpu_fence_free(struct rcu_head *rcu)
 627 {
 628         struct dma_fence *f = container_of(rcu, struct dma_fence, rcu);
 629         struct amdgpu_fence *fence = to_amdgpu_fence(f);
 630         kmem_cache_free(amdgpu_fence_slab, fence);
 631 }
 632
 633 /**
 634  * amdgpu_fence_release - callback that fence can be freed
 635  *
 636  * @fence: fence
 637  *
 638  * This function is called when the reference count becomes zero.
 639  * It just RCU schedules freeing up the fence.
 640  */
 641 static void amdgpu_fence_release(struct dma_fence *f)
 642 {
 643         call_rcu(&f->rcu, amdgpu_fence_free);
 644 }
 645
 646 static const struct dma_fence_ops amdgpu_fence_ops = {
 647         .get_driver_name = amdgpu_fence_get_driver_name,
 648         .get_timeline_name = amdgpu_fence_get_timeline_name,
 649         .enable_signaling = amdgpu_fence_enable_signaling,
 650         .release = amdgpu_fence_release,
 651 };
 652
 653 /*
 654  * Fence debugfs
 655  */
 656 #if defined(CONFIG_DEBUG_FS)
 657 static int amdgpu_debugfs_fence_info(struct seq_file *m, void *data)
 658 {
 659         struct drm_info_node *node = (struct drm_info_node *)m->private;
 660         struct drm_device *dev = node->minor->dev;
 661         struct amdgpu_device *adev = dev->dev_private;
 662         int i;
 663
 664         for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
 665                 struct amdgpu_ring *ring = adev->rings[i];
 666                 if (!ring || !ring->fence_drv.initialized)
 667                         continue;
 668
 669                 amdgpu_fence_process(ring);
 670
 671                 seq_printf(m, "--- ring %d (%s) ---\n", i, ring->name);
 672                 seq_printf(m, "Last signaled fence 0x%08x\n",
 673                            atomic_read(&ring->fence_drv.last_seq));
 674                 seq_printf(m, "Last emitted        0x%08x\n",
 675                            ring->fence_drv.sync_seq);
 676
 677                 if (ring->funcs->type != AMDGPU_RING_TYPE_GFX)
 678                         continue;
 679
 680                 /* set in CP_VMID_PREEMPT and preemption occurred */
 681                 seq_printf(m, "Last preempted      0x%08x\n",
 682                            le32_to_cpu(*(ring->fence_drv.cpu_addr + 2)));
 683                 /* set in CP_VMID_RESET and reset occurred */
 684                 seq_printf(m, "Last reset          0x%08x\n",
 685                            le32_to_cpu(*(ring->fence_drv.cpu_addr + 4)));
 686                 /* Both preemption and reset occurred */
 687                 seq_printf(m, "Last both           0x%08x\n",
 688                            le32_to_cpu(*(ring->fence_drv.cpu_addr + 6)));
 689         }
 690         return 0;
 691 }
 692
 693 /**
 694  * amdgpu_debugfs_gpu_recover - manually trigger a gpu reset & recover
 695  *
 696  * Manually trigger a gpu reset at the next fence wait.
 697  */
 698 static int amdgpu_debugfs_gpu_recover(struct seq_file *m, void *data)
 699 {
 700         struct drm_info_node *node = (struct drm_info_node *) m->private;
 701         struct drm_device *dev = node->minor->dev;
 702         struct amdgpu_device *adev = dev->dev_private;
 703
 704         seq_printf(m, "gpu recover\n");
 705         amdgpu_device_gpu_recover(adev, NULL);
 706
 707         return 0;
 708 }
 709
 710 static const struct drm_info_list amdgpu_debugfs_fence_list[] = {
 711         {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL},
 712         {"amdgpu_gpu_recover", &amdgpu_debugfs_gpu_recover, 0, NULL}
 713 };
 714
 715 static const struct drm_info_list amdgpu_debugfs_fence_list_sriov[] = {
 716         {"amdgpu_fence_info", &amdgpu_debugfs_fence_info, 0, NULL},
 717 };
 718 #endif
 719
 720 int amdgpu_debugfs_fence_init(struct amdgpu_device *adev)
 721 {
 722 #if defined(CONFIG_DEBUG_FS)
 723         if (amdgpu_sriov_vf(adev))
 724                 return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list_sriov, 1);
 725         return amdgpu_debugfs_add_files(adev, amdgpu_debugfs_fence_list, 2);
 726 #else
 727         return 0;
 728 #endif
 729 }
 730