drivers/gpu/drm/meson/meson_overlay.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2018 BayLibre, SAS
   4  * Author: Neil Armstrong <[email protected]>
   5  * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
   6  */
   7
   8 #include <linux/bitfield.h>
   9
  10 #include <drm/drm_atomic.h>
  11 #include <drm/drm_atomic_helper.h>
  12 #include <drm/drm_device.h>
  13 #include <drm/drm_fb_cma_helper.h>
  14 #include <drm/drm_fourcc.h>
  15 #include <drm/drm_gem_atomic_helper.h>
  16 #include <drm/drm_gem_cma_helper.h>
  17 #include <drm/drm_plane_helper.h>
  18
  19 #include "meson_overlay.h"
  20 #include "meson_registers.h"
  21 #include "meson_viu.h"
  22 #include "meson_vpp.h"
  23
  24 /* VD1_IF0_GEN_REG */
  25 #define VD_URGENT_CHROMA                BIT(28)
  26 #define VD_URGENT_LUMA                  BIT(27)
  27 #define VD_HOLD_LINES(lines)            FIELD_PREP(GENMASK(24, 19), lines)
  28 #define VD_DEMUX_MODE_RGB               BIT(16)
  29 #define VD_BYTES_PER_PIXEL(val)         FIELD_PREP(GENMASK(15, 14), val)
  30 #define VD_CHRO_RPT_LASTL_CTRL          BIT(6)
  31 #define VD_LITTLE_ENDIAN                BIT(4)
  32 #define VD_SEPARATE_EN                  BIT(1)
  33 #define VD_ENABLE                       BIT(0)
  34
  35 /* VD1_IF0_CANVAS0 */
  36 #define CANVAS_ADDR2(addr)              FIELD_PREP(GENMASK(23, 16), addr)
  37 #define CANVAS_ADDR1(addr)              FIELD_PREP(GENMASK(15, 8), addr)
  38 #define CANVAS_ADDR0(addr)              FIELD_PREP(GENMASK(7, 0), addr)
  39
  40 /* VD1_IF0_LUMA_X0 VD1_IF0_CHROMA_X0 */
  41 #define VD_X_START(value)               FIELD_PREP(GENMASK(14, 0), value)
  42 #define VD_X_END(value)                 FIELD_PREP(GENMASK(30, 16), value)
  43
  44 /* VD1_IF0_LUMA_Y0 VD1_IF0_CHROMA_Y0 */
  45 #define VD_Y_START(value)               FIELD_PREP(GENMASK(12, 0), value)
  46 #define VD_Y_END(value)                 FIELD_PREP(GENMASK(28, 16), value)
  47
  48 /* VD1_IF0_GEN_REG2 */
  49 #define VD_COLOR_MAP(value)             FIELD_PREP(GENMASK(1, 0), value)
  50
  51 /* VIU_VD1_FMT_CTRL */
  52 #define VD_HORZ_Y_C_RATIO(value)        FIELD_PREP(GENMASK(22, 21), value)
  53 #define VD_HORZ_FMT_EN                  BIT(20)
  54 #define VD_VERT_RPT_LINE0               BIT(16)
  55 #define VD_VERT_INITIAL_PHASE(value)    FIELD_PREP(GENMASK(11, 8), value)
  56 #define VD_VERT_PHASE_STEP(value)       FIELD_PREP(GENMASK(7, 1), value)
  57 #define VD_VERT_FMT_EN                  BIT(0)
  58
  59 /* VPP_POSTBLEND_VD1_H_START_END */
  60 #define VD_H_END(value)                 FIELD_PREP(GENMASK(11, 0), value)
  61 #define VD_H_START(value)               FIELD_PREP(GENMASK(27, 16), \
  62                                                    ((value) & GENMASK(13, 0)))
  63
  64 /* VPP_POSTBLEND_VD1_V_START_END */
  65 #define VD_V_END(value)                 FIELD_PREP(GENMASK(11, 0), value)
  66 #define VD_V_START(value)               FIELD_PREP(GENMASK(27, 16), value)
  67
  68 /* VPP_BLEND_VD2_V_START_END */
  69 #define VD2_V_END(value)                FIELD_PREP(GENMASK(11, 0), value)
  70 #define VD2_V_START(value)              FIELD_PREP(GENMASK(27, 16), value)
  71
  72 /* VIU_VD1_FMT_W */
  73 #define VD_V_WIDTH(value)               FIELD_PREP(GENMASK(11, 0), value)
  74 #define VD_H_WIDTH(value)               FIELD_PREP(GENMASK(27, 16), value)
  75
  76 /* VPP_HSC_REGION12_STARTP VPP_HSC_REGION34_STARTP */
  77 #define VD_REGION24_START(value)        FIELD_PREP(GENMASK(11, 0), value)
  78 #define VD_REGION13_END(value)          FIELD_PREP(GENMASK(27, 16), value)
  79
  80 /* AFBC_ENABLE */
  81 #define AFBC_DEC_ENABLE                 BIT(8)
  82 #define AFBC_FRM_START                  BIT(0)
  83
  84 /* AFBC_MODE */
  85 #define AFBC_HORZ_SKIP_UV(value)        FIELD_PREP(GENMASK(1, 0), value)
  86 #define AFBC_VERT_SKIP_UV(value)        FIELD_PREP(GENMASK(3, 2), value)
  87 #define AFBC_HORZ_SKIP_Y(value)         FIELD_PREP(GENMASK(5, 4), value)
  88 #define AFBC_VERT_SKIP_Y(value)         FIELD_PREP(GENMASK(7, 6), value)
  89 #define AFBC_COMPBITS_YUV(value)        FIELD_PREP(GENMASK(13, 8), value)
  90 #define AFBC_COMPBITS_8BIT              0
  91 #define AFBC_COMPBITS_10BIT             (2 | (2 << 2) | (2 << 4))
  92 #define AFBC_BURST_LEN(value)           FIELD_PREP(GENMASK(15, 14), value)
  93 #define AFBC_HOLD_LINE_NUM(value)       FIELD_PREP(GENMASK(22, 16), value)
  94 #define AFBC_MIF_URGENT(value)          FIELD_PREP(GENMASK(25, 24), value)
  95 #define AFBC_REV_MODE(value)            FIELD_PREP(GENMASK(27, 26), value)
  96 #define AFBC_BLK_MEM_MODE               BIT(28)
  97 #define AFBC_SCATTER_MODE               BIT(29)
  98 #define AFBC_SOFT_RESET                 BIT(31)
  99
 100 /* AFBC_SIZE_IN */
 101 #define AFBC_HSIZE_IN(value)            FIELD_PREP(GENMASK(28, 16), value)
 102 #define AFBC_VSIZE_IN(value)            FIELD_PREP(GENMASK(12, 0), value)
 103
 104 /* AFBC_DEC_DEF_COLOR */
 105 #define AFBC_DEF_COLOR_Y(value)         FIELD_PREP(GENMASK(29, 20), value)
 106 #define AFBC_DEF_COLOR_U(value)         FIELD_PREP(GENMASK(19, 10), value)
 107 #define AFBC_DEF_COLOR_V(value)         FIELD_PREP(GENMASK(9, 0), value)
 108
 109 /* AFBC_CONV_CTRL */
 110 #define AFBC_CONV_LBUF_LEN(value)       FIELD_PREP(GENMASK(11, 0), value)
 111
 112 /* AFBC_LBUF_DEPTH */
 113 #define AFBC_DEC_LBUF_DEPTH(value)      FIELD_PREP(GENMASK(27, 16), value)
 114 #define AFBC_MIF_LBUF_DEPTH(value)      FIELD_PREP(GENMASK(11, 0), value)
 115
 116 /* AFBC_OUT_XSCOPE/AFBC_SIZE_OUT */
 117 #define AFBC_HSIZE_OUT(value)           FIELD_PREP(GENMASK(28, 16), value)
 118 #define AFBC_VSIZE_OUT(value)           FIELD_PREP(GENMASK(12, 0), value)
 119 #define AFBC_OUT_HORZ_BGN(value)        FIELD_PREP(GENMASK(28, 16), value)
 120 #define AFBC_OUT_HORZ_END(value)        FIELD_PREP(GENMASK(12, 0), value)
 121
 122 /* AFBC_OUT_YSCOPE */
 123 #define AFBC_OUT_VERT_BGN(value)        FIELD_PREP(GENMASK(28, 16), value)
 124 #define AFBC_OUT_VERT_END(value)        FIELD_PREP(GENMASK(12, 0), value)
 125
 126 /* AFBC_VD_CFMT_CTRL */
 127 #define AFBC_HORZ_RPT_PIXEL0            BIT(23)
 128 #define AFBC_HORZ_Y_C_RATIO(value)      FIELD_PREP(GENMASK(22, 21), value)
 129 #define AFBC_HORZ_FMT_EN                BIT(20)
 130 #define AFBC_VERT_RPT_LINE0             BIT(16)
 131 #define AFBC_VERT_INITIAL_PHASE(value)  FIELD_PREP(GENMASK(11, 8), value)
 132 #define AFBC_VERT_PHASE_STEP(value)     FIELD_PREP(GENMASK(7, 1), value)
 133 #define AFBC_VERT_FMT_EN                BIT(0)
 134
 135 /* AFBC_VD_CFMT_W */
 136 #define AFBC_VD_V_WIDTH(value)          FIELD_PREP(GENMASK(11, 0), value)
 137 #define AFBC_VD_H_WIDTH(value)          FIELD_PREP(GENMASK(27, 16), value)
 138
 139 /* AFBC_MIF_HOR_SCOPE */
 140 #define AFBC_MIF_BLK_BGN_H(value)       FIELD_PREP(GENMASK(25, 16), value)
 141 #define AFBC_MIF_BLK_END_H(value)       FIELD_PREP(GENMASK(9, 0), value)
 142
 143 /* AFBC_MIF_VER_SCOPE */
 144 #define AFBC_MIF_BLK_BGN_V(value)       FIELD_PREP(GENMASK(27, 16), value)
 145 #define AFBC_MIF_BLK_END_V(value)       FIELD_PREP(GENMASK(11, 0), value)
 146
 147 /* AFBC_PIXEL_HOR_SCOPE */
 148 #define AFBC_DEC_PIXEL_BGN_H(value)     FIELD_PREP(GENMASK(28, 16), \
 149                                                    ((value) & GENMASK(12, 0)))
 150 #define AFBC_DEC_PIXEL_END_H(value)     FIELD_PREP(GENMASK(12, 0), value)
 151
 152 /* AFBC_PIXEL_VER_SCOPE */
 153 #define AFBC_DEC_PIXEL_BGN_V(value)     FIELD_PREP(GENMASK(28, 16), value)
 154 #define AFBC_DEC_PIXEL_END_V(value)     FIELD_PREP(GENMASK(12, 0), value)
 155
 156 /* AFBC_VD_CFMT_H */
 157 #define AFBC_VD_HEIGHT(value)           FIELD_PREP(GENMASK(12, 0), value)
 158
 159 struct meson_overlay {
 160         struct drm_plane base;
 161         struct meson_drm *priv;
 162 };
 163 #define to_meson_overlay(x) container_of(x, struct meson_overlay, base)
 164
 165 #define FRAC_16_16(mult, div)    (((mult) << 16) / (div))
 166
 167 static int meson_overlay_atomic_check(struct drm_plane *plane,
 168                                       struct drm_atomic_state *state)
 169 {
 170         struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
 171                                                                                  plane);
 172         struct drm_crtc_state *crtc_state;
 173
 174         if (!new_plane_state->crtc)
 175                 return 0;
 176
 177         crtc_state = drm_atomic_get_crtc_state(state,
 178                                                new_plane_state->crtc);
 179         if (IS_ERR(crtc_state))
 180                 return PTR_ERR(crtc_state);
 181
 182         return drm_atomic_helper_check_plane_state(new_plane_state,
 183                                                    crtc_state,
 184                                                    FRAC_16_16(1, 5),
 185                                                    FRAC_16_16(5, 1),
 186                                                    true, true);
 187 }
 188
 189 /* Takes a fixed 16.16 number and converts it to integer. */
 190 static inline int64_t fixed16_to_int(int64_t value)
 191 {
 192         return value >> 16;
 193 }
 194
 195 static const uint8_t skip_tab[6] = {
 196         0x24, 0x04, 0x68, 0x48, 0x28, 0x08,
 197 };
 198
 199 static void meson_overlay_get_vertical_phase(unsigned int ratio_y, int *phase,
 200                                              int *repeat, bool interlace)
 201 {
 202         int offset_in = 0;
 203         int offset_out = 0;
 204         int repeat_skip = 0;
 205
 206         if (!interlace && ratio_y > (1 << 18))
 207                 offset_out = (1 * ratio_y) >> 10;
 208
 209         while ((offset_in + (4 << 8)) <= offset_out) {
 210                 repeat_skip++;
 211                 offset_in += 4 << 8;
 212         }
 213
 214         *phase = (offset_out - offset_in) >> 2;
 215
 216         if (*phase > 0x100)
 217                 repeat_skip++;
 218
 219         *phase = *phase & 0xff;
 220
 221         if (repeat_skip > 5)
 222                 repeat_skip = 5;
 223
 224         *repeat = skip_tab[repeat_skip];
 225 }
 226
 227 static void meson_overlay_setup_scaler_params(struct meson_drm *priv,
 228                                               struct drm_plane *plane,
 229                                               bool interlace_mode)
 230 {
 231         struct drm_crtc_state *crtc_state = priv->crtc->state;
 232         int video_top, video_left, video_width, video_height;
 233         struct drm_plane_state *state = plane->state;
 234         unsigned int vd_start_lines, vd_end_lines;
 235         unsigned int hd_start_lines, hd_end_lines;
 236         unsigned int crtc_height, crtc_width;
 237         unsigned int vsc_startp, vsc_endp;
 238         unsigned int hsc_startp, hsc_endp;
 239         unsigned int crop_top, crop_left;
 240         int vphase, vphase_repeat_skip;
 241         unsigned int ratio_x, ratio_y;
 242         int temp_height, temp_width;
 243         unsigned int w_in, h_in;
 244         int afbc_left, afbc_right;
 245         int afbc_top_src, afbc_bottom_src;
 246         int afbc_top, afbc_bottom;
 247         int temp, start, end;
 248
 249         if (!crtc_state) {
 250                 DRM_ERROR("Invalid crtc_state\n");
 251                 return;
 252         }
 253
 254         crtc_height = crtc_state->mode.vdisplay;
 255         crtc_width = crtc_state->mode.hdisplay;
 256
 257         w_in = fixed16_to_int(state->src_w);
 258         h_in = fixed16_to_int(state->src_h);
 259         crop_top = fixed16_to_int(state->src_y);
 260         crop_left = fixed16_to_int(state->src_x);
 261
 262         video_top = state->crtc_y;
 263         video_left = state->crtc_x;
 264         video_width = state->crtc_w;
 265         video_height = state->crtc_h;
 266
 267         DRM_DEBUG("crtc_width %d crtc_height %d interlace %d\n",
 268                   crtc_width, crtc_height, interlace_mode);
 269         DRM_DEBUG("w_in %d h_in %d crop_top %d crop_left %d\n",
 270                   w_in, h_in, crop_top, crop_left);
 271         DRM_DEBUG("video top %d left %d width %d height %d\n",
 272                   video_top, video_left, video_width, video_height);
 273
 274         ratio_x = (w_in << 18) / video_width;
 275         ratio_y = (h_in << 18) / video_height;
 276
 277         if (ratio_x * video_width < (w_in << 18))
 278                 ratio_x++;
 279
 280         DRM_DEBUG("ratio x 0x%x y 0x%x\n", ratio_x, ratio_y);
 281
 282         meson_overlay_get_vertical_phase(ratio_y, &vphase, &vphase_repeat_skip,
 283                                          interlace_mode);
 284
 285         DRM_DEBUG("vphase 0x%x skip %d\n", vphase, vphase_repeat_skip);
 286
 287         /* Vertical */
 288
 289         start = video_top + video_height / 2 - ((h_in << 17) / ratio_y);
 290         end = (h_in << 18) / ratio_y + start - 1;
 291
 292         if (video_top < 0 && start < 0)
 293                 vd_start_lines = (-(start) * ratio_y) >> 18;
 294         else if (start < video_top)
 295                 vd_start_lines = ((video_top - start) * ratio_y) >> 18;
 296         else
 297                 vd_start_lines = 0;
 298
 299         if (video_top < 0)
 300                 temp_height = min_t(unsigned int,
 301                                     video_top + video_height - 1,
 302                                     crtc_height - 1);
 303         else
 304                 temp_height = min_t(unsigned int,
 305                                     video_top + video_height - 1,
 306                                     crtc_height - 1) - video_top + 1;
 307
 308         temp = vd_start_lines + (temp_height * ratio_y >> 18);
 309         vd_end_lines = (temp <= (h_in - 1)) ? temp : (h_in - 1);
 310
 311         vd_start_lines += crop_left;
 312         vd_end_lines += crop_left;
 313
 314         /*
 315          * TOFIX: Input frames are handled and scaled like progressive frames,
 316          * proper handling of interlaced field input frames need to be figured
 317          * out using the proper framebuffer flags set by userspace.
 318          */
 319         if (interlace_mode) {
 320                 start >>= 1;
 321                 end >>= 1;
 322         }
 323
 324         vsc_startp = max_t(int, start,
 325                            max_t(int, 0, video_top));
 326         vsc_endp = min_t(int, end,
 327                          min_t(int, crtc_height - 1,
 328                                video_top + video_height - 1));
 329
 330         DRM_DEBUG("vsc startp %d endp %d start_lines %d end_lines %d\n",
 331                  vsc_startp, vsc_endp, vd_start_lines, vd_end_lines);
 332
 333         afbc_top = round_down(vd_start_lines, 4);
 334         afbc_bottom = round_up(vd_end_lines + 1, 4);
 335         afbc_top_src = 0;
 336         afbc_bottom_src = round_up(h_in + 1, 4);
 337
 338         DRM_DEBUG("afbc top %d (src %d) bottom %d (src %d)\n",
 339                   afbc_top, afbc_top_src, afbc_bottom, afbc_bottom_src);
 340
 341         /* Horizontal */
 342
 343         start = video_left + video_width / 2 - ((w_in << 17) / ratio_x);
 344         end = (w_in << 18) / ratio_x + start - 1;
 345
 346         if (video_left < 0 && start < 0)
 347                 hd_start_lines = (-(start) * ratio_x) >> 18;
 348         else if (start < video_left)
 349                 hd_start_lines = ((video_left - start) * ratio_x) >> 18;
 350         else
 351                 hd_start_lines = 0;
 352
 353         if (video_left < 0)
 354                 temp_width = min_t(unsigned int,
 355                                    video_left + video_width - 1,
 356                                    crtc_width - 1);
 357         else
 358                 temp_width = min_t(unsigned int,
 359                                    video_left + video_width - 1,
 360                                    crtc_width - 1) - video_left + 1;
 361
 362         temp = hd_start_lines + (temp_width * ratio_x >> 18);
 363         hd_end_lines = (temp <= (w_in - 1)) ? temp : (w_in - 1);
 364
 365         priv->viu.vpp_line_in_length = hd_end_lines - hd_start_lines + 1;
 366         hsc_startp = max_t(int, start, max_t(int, 0, video_left));
 367         hsc_endp = min_t(int, end, min_t(int, crtc_width - 1,
 368                                          video_left + video_width - 1));
 369
 370         hd_start_lines += crop_top;
 371         hd_end_lines += crop_top;
 372
 373         DRM_DEBUG("hsc startp %d endp %d start_lines %d end_lines %d\n",
 374                  hsc_startp, hsc_endp, hd_start_lines, hd_end_lines);
 375
 376         if (hd_start_lines > 0 || (hd_end_lines < w_in)) {
 377                 afbc_left = 0;
 378                 afbc_right = round_up(w_in, 32);
 379         } else {
 380                 afbc_left = round_down(hd_start_lines, 32);
 381                 afbc_right = round_up(hd_end_lines + 1, 32);
 382         }
 383
 384         DRM_DEBUG("afbc left %d right %d\n", afbc_left, afbc_right);
 385
 386         priv->viu.vpp_vsc_start_phase_step = ratio_y << 6;
 387
 388         priv->viu.vpp_vsc_ini_phase = vphase << 8;
 389         priv->viu.vpp_vsc_phase_ctrl = (1 << 13) | (4 << 8) |
 390                                        vphase_repeat_skip;
 391
 392         priv->viu.vd1_if0_luma_x0 = VD_X_START(hd_start_lines) |
 393                                     VD_X_END(hd_end_lines);
 394         priv->viu.vd1_if0_chroma_x0 = VD_X_START(hd_start_lines >> 1) |
 395                                       VD_X_END(hd_end_lines >> 1);
 396
 397         priv->viu.viu_vd1_fmt_w =
 398                         VD_H_WIDTH(hd_end_lines - hd_start_lines + 1) |
 399                         VD_V_WIDTH(hd_end_lines/2 - hd_start_lines/2 + 1);
 400
 401         priv->viu.vd1_afbc_vd_cfmt_w =
 402                         AFBC_VD_H_WIDTH(afbc_right - afbc_left) |
 403                         AFBC_VD_V_WIDTH(afbc_right / 2 - afbc_left / 2);
 404
 405         priv->viu.vd1_afbc_vd_cfmt_h =
 406                         AFBC_VD_HEIGHT((afbc_bottom - afbc_top) / 2);
 407
 408         priv->viu.vd1_afbc_mif_hor_scope = AFBC_MIF_BLK_BGN_H(afbc_left / 32) |
 409                                 AFBC_MIF_BLK_END_H((afbc_right / 32) - 1);
 410
 411         priv->viu.vd1_afbc_mif_ver_scope = AFBC_MIF_BLK_BGN_V(afbc_top / 4) |
 412                                 AFBC_MIF_BLK_END_H((afbc_bottom / 4) - 1);
 413
 414         priv->viu.vd1_afbc_size_out =
 415                         AFBC_HSIZE_OUT(afbc_right - afbc_left) |
 416                         AFBC_VSIZE_OUT(afbc_bottom - afbc_top);
 417
 418         priv->viu.vd1_afbc_pixel_hor_scope =
 419                         AFBC_DEC_PIXEL_BGN_H(hd_start_lines - afbc_left) |
 420                         AFBC_DEC_PIXEL_END_H(hd_end_lines - afbc_left);
 421
 422         priv->viu.vd1_afbc_pixel_ver_scope =
 423                         AFBC_DEC_PIXEL_BGN_V(vd_start_lines - afbc_top) |
 424                         AFBC_DEC_PIXEL_END_V(vd_end_lines - afbc_top);
 425
 426         priv->viu.vd1_afbc_size_in =
 427                                 AFBC_HSIZE_IN(afbc_right - afbc_left) |
 428                                 AFBC_VSIZE_IN(afbc_bottom_src - afbc_top_src);
 429
 430         priv->viu.vd1_if0_luma_y0 = VD_Y_START(vd_start_lines) |
 431                                     VD_Y_END(vd_end_lines);
 432
 433         priv->viu.vd1_if0_chroma_y0 = VD_Y_START(vd_start_lines >> 1) |
 434                                       VD_Y_END(vd_end_lines >> 1);
 435
 436         priv->viu.vpp_pic_in_height = h_in;
 437
 438         priv->viu.vpp_postblend_vd1_h_start_end = VD_H_START(hsc_startp) |
 439                                                   VD_H_END(hsc_endp);
 440         priv->viu.vpp_blend_vd2_h_start_end = VD_H_START(hd_start_lines) |
 441                                               VD_H_END(hd_end_lines);
 442         priv->viu.vpp_hsc_region12_startp = VD_REGION13_END(0) |
 443                                             VD_REGION24_START(hsc_startp);
 444         priv->viu.vpp_hsc_region34_startp =
 445                                 VD_REGION13_END(hsc_startp) |
 446                                 VD_REGION24_START(hsc_endp - hsc_startp);
 447         priv->viu.vpp_hsc_region4_endp = hsc_endp - hsc_startp;
 448         priv->viu.vpp_hsc_start_phase_step = ratio_x << 6;
 449         priv->viu.vpp_hsc_region1_phase_slope = 0;
 450         priv->viu.vpp_hsc_region3_phase_slope = 0;
 451         priv->viu.vpp_hsc_phase_ctrl = (1 << 21) | (4 << 16);
 452
 453         priv->viu.vpp_line_in_length = hd_end_lines - hd_start_lines + 1;
 454         priv->viu.vpp_preblend_h_size = hd_end_lines - hd_start_lines + 1;
 455
 456         priv->viu.vpp_postblend_vd1_v_start_end = VD_V_START(vsc_startp) |
 457                                                   VD_V_END(vsc_endp);
 458         priv->viu.vpp_blend_vd2_v_start_end =
 459                                 VD2_V_START((vd_end_lines + 1) >> 1) |
 460                                 VD2_V_END(vd_end_lines);
 461
 462         priv->viu.vpp_vsc_region12_startp = 0;
 463         priv->viu.vpp_vsc_region34_startp =
 464                                 VD_REGION13_END(vsc_endp - vsc_startp) |
 465                                 VD_REGION24_START(vsc_endp - vsc_startp);
 466         priv->viu.vpp_vsc_region4_endp = vsc_endp - vsc_startp;
 467         priv->viu.vpp_vsc_start_phase_step = ratio_y << 6;
 468 }
 469
 470 static void meson_overlay_atomic_update(struct drm_plane *plane,
 471                                         struct drm_atomic_state *state)
 472 {
 473         struct meson_overlay *meson_overlay = to_meson_overlay(plane);
 474         struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
 475                                                                            plane);
 476         struct drm_framebuffer *fb = new_state->fb;
 477         struct meson_drm *priv = meson_overlay->priv;
 478         struct drm_gem_cma_object *gem;
 479         unsigned long flags;
 480         bool interlace_mode;
 481
 482         DRM_DEBUG_DRIVER("\n");
 483
 484         interlace_mode = new_state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE;
 485
 486         spin_lock_irqsave(&priv->drm->event_lock, flags);
 487
 488         if ((fb->modifier & DRM_FORMAT_MOD_AMLOGIC_FBC(0, 0)) ==
 489                             DRM_FORMAT_MOD_AMLOGIC_FBC(0, 0)) {
 490                 priv->viu.vd1_afbc = true;
 491
 492                 priv->viu.vd1_afbc_mode = AFBC_MIF_URGENT(3) |
 493                                           AFBC_HOLD_LINE_NUM(8) |
 494                                           AFBC_BURST_LEN(2);
 495
 496                 if (fb->modifier & DRM_FORMAT_MOD_AMLOGIC_FBC(0,
 497                                                 AMLOGIC_FBC_OPTION_MEM_SAVING))
 498                         priv->viu.vd1_afbc_mode |= AFBC_BLK_MEM_MODE;
 499
 500                 if ((fb->modifier & __fourcc_mod_amlogic_layout_mask) ==
 501                                 AMLOGIC_FBC_LAYOUT_SCATTER)
 502                         priv->viu.vd1_afbc_mode |= AFBC_SCATTER_MODE;
 503
 504                 priv->viu.vd1_afbc_en = 0x1600 | AFBC_DEC_ENABLE;
 505
 506                 priv->viu.vd1_afbc_conv_ctrl = AFBC_CONV_LBUF_LEN(256);
 507
 508                 priv->viu.vd1_afbc_dec_def_color = AFBC_DEF_COLOR_Y(1023);
 509
 510                 /* 420: horizontal / 2, vertical / 4 */
 511                 priv->viu.vd1_afbc_vd_cfmt_ctrl = AFBC_HORZ_RPT_PIXEL0 |
 512                                                   AFBC_HORZ_Y_C_RATIO(1) |
 513                                                   AFBC_HORZ_FMT_EN |
 514                                                   AFBC_VERT_RPT_LINE0 |
 515                                                   AFBC_VERT_INITIAL_PHASE(12) |
 516                                                   AFBC_VERT_PHASE_STEP(8) |
 517                                                   AFBC_VERT_FMT_EN;
 518
 519                 switch (fb->format->format) {
 520                 /* AFBC Only formats */
 521                 case DRM_FORMAT_YUV420_10BIT:
 522                         priv->viu.vd1_afbc_mode |=
 523                                 AFBC_COMPBITS_YUV(AFBC_COMPBITS_10BIT);
 524                         priv->viu.vd1_afbc_dec_def_color |=
 525                                         AFBC_DEF_COLOR_U(512) |
 526                                         AFBC_DEF_COLOR_V(512);
 527                         break;
 528                 case DRM_FORMAT_YUV420_8BIT:
 529                         priv->viu.vd1_afbc_dec_def_color |=
 530                                         AFBC_DEF_COLOR_U(128) |
 531                                         AFBC_DEF_COLOR_V(128);
 532                         break;
 533                 }
 534
 535                 priv->viu.vd1_if0_gen_reg = 0;
 536                 priv->viu.vd1_if0_canvas0 = 0;
 537                 priv->viu.viu_vd1_fmt_ctrl = 0;
 538         } else {
 539                 priv->viu.vd1_afbc = false;
 540
 541                 priv->viu.vd1_if0_gen_reg = VD_URGENT_CHROMA |
 542                                             VD_URGENT_LUMA |
 543                                             VD_HOLD_LINES(9) |
 544                                             VD_CHRO_RPT_LASTL_CTRL |
 545                                             VD_ENABLE;
 546         }
 547
 548         /* Setup scaler params */
 549         meson_overlay_setup_scaler_params(priv, plane, interlace_mode);
 550
 551         priv->viu.vd1_if0_repeat_loop = 0;
 552         priv->viu.vd1_if0_luma0_rpt_pat = interlace_mode ? 8 : 0;
 553         priv->viu.vd1_if0_chroma0_rpt_pat = interlace_mode ? 8 : 0;
 554         priv->viu.vd1_range_map_y = 0;
 555         priv->viu.vd1_range_map_cb = 0;
 556         priv->viu.vd1_range_map_cr = 0;
 557
 558         /* Default values for RGB888/YUV444 */
 559         priv->viu.vd1_if0_gen_reg2 = 0;
 560         priv->viu.viu_vd1_fmt_ctrl = 0;
 561
 562         /* None will match for AFBC Only formats */
 563         switch (fb->format->format) {
 564         /* TOFIX DRM_FORMAT_RGB888 should be supported */
 565         case DRM_FORMAT_YUYV:
 566                 priv->viu.vd1_if0_gen_reg |= VD_BYTES_PER_PIXEL(1);
 567                 priv->viu.vd1_if0_canvas0 =
 568                                         CANVAS_ADDR2(priv->canvas_id_vd1_0) |
 569                                         CANVAS_ADDR1(priv->canvas_id_vd1_0) |
 570                                         CANVAS_ADDR0(priv->canvas_id_vd1_0);
 571                 priv->viu.viu_vd1_fmt_ctrl = VD_HORZ_Y_C_RATIO(1) | /* /2 */
 572                                              VD_HORZ_FMT_EN |
 573                                              VD_VERT_RPT_LINE0 |
 574                                              VD_VERT_INITIAL_PHASE(12) |
 575                                              VD_VERT_PHASE_STEP(16) | /* /2 */
 576                                              VD_VERT_FMT_EN;
 577                 break;
 578         case DRM_FORMAT_NV12:
 579         case DRM_FORMAT_NV21:
 580                 priv->viu.vd1_if0_gen_reg |= VD_SEPARATE_EN;
 581                 priv->viu.vd1_if0_canvas0 =
 582                                         CANVAS_ADDR2(priv->canvas_id_vd1_1) |
 583                                         CANVAS_ADDR1(priv->canvas_id_vd1_1) |
 584                                         CANVAS_ADDR0(priv->canvas_id_vd1_0);
 585                 if (fb->format->format == DRM_FORMAT_NV12)
 586                         priv->viu.vd1_if0_gen_reg2 = VD_COLOR_MAP(1);
 587                 else
 588                         priv->viu.vd1_if0_gen_reg2 = VD_COLOR_MAP(2);
 589                 priv->viu.viu_vd1_fmt_ctrl = VD_HORZ_Y_C_RATIO(1) | /* /2 */
 590                                              VD_HORZ_FMT_EN |
 591                                              VD_VERT_RPT_LINE0 |
 592                                              VD_VERT_INITIAL_PHASE(12) |
 593                                              VD_VERT_PHASE_STEP(8) | /* /4 */
 594                                              VD_VERT_FMT_EN;
 595                 break;
 596         case DRM_FORMAT_YUV444:
 597         case DRM_FORMAT_YUV422:
 598         case DRM_FORMAT_YUV420:
 599         case DRM_FORMAT_YUV411:
 600         case DRM_FORMAT_YUV410:
 601                 priv->viu.vd1_if0_gen_reg |= VD_SEPARATE_EN;
 602                 priv->viu.vd1_if0_canvas0 =
 603                                         CANVAS_ADDR2(priv->canvas_id_vd1_2) |
 604                                         CANVAS_ADDR1(priv->canvas_id_vd1_1) |
 605                                         CANVAS_ADDR0(priv->canvas_id_vd1_0);
 606                 switch (fb->format->format) {
 607                 case DRM_FORMAT_YUV422:
 608                         priv->viu.viu_vd1_fmt_ctrl =
 609                                         VD_HORZ_Y_C_RATIO(1) | /* /2 */
 610                                         VD_HORZ_FMT_EN |
 611                                         VD_VERT_RPT_LINE0 |
 612                                         VD_VERT_INITIAL_PHASE(12) |
 613                                         VD_VERT_PHASE_STEP(16) | /* /2 */
 614                                         VD_VERT_FMT_EN;
 615                         break;
 616                 case DRM_FORMAT_YUV420:
 617                         priv->viu.viu_vd1_fmt_ctrl =
 618                                         VD_HORZ_Y_C_RATIO(1) | /* /2 */
 619                                         VD_HORZ_FMT_EN |
 620                                         VD_VERT_RPT_LINE0 |
 621                                         VD_VERT_INITIAL_PHASE(12) |
 622                                         VD_VERT_PHASE_STEP(8) | /* /4 */
 623                                         VD_VERT_FMT_EN;
 624                         break;
 625                 case DRM_FORMAT_YUV411:
 626                         priv->viu.viu_vd1_fmt_ctrl =
 627                                         VD_HORZ_Y_C_RATIO(2) | /* /4 */
 628                                         VD_HORZ_FMT_EN |
 629                                         VD_VERT_RPT_LINE0 |
 630                                         VD_VERT_INITIAL_PHASE(12) |
 631                                         VD_VERT_PHASE_STEP(16) | /* /2 */
 632                                         VD_VERT_FMT_EN;
 633                         break;
 634                 case DRM_FORMAT_YUV410:
 635                         priv->viu.viu_vd1_fmt_ctrl =
 636                                         VD_HORZ_Y_C_RATIO(2) | /* /4 */
 637                                         VD_HORZ_FMT_EN |
 638                                         VD_VERT_RPT_LINE0 |
 639                                         VD_VERT_INITIAL_PHASE(12) |
 640                                         VD_VERT_PHASE_STEP(8) | /* /4 */
 641                                         VD_VERT_FMT_EN;
 642                         break;
 643                 }
 644                 break;
 645         }
 646
 647         /* Update Canvas with buffer address */
 648         priv->viu.vd1_planes = fb->format->num_planes;
 649
 650         switch (priv->viu.vd1_planes) {
 651         case 3:
 652                 gem = drm_fb_cma_get_gem_obj(fb, 2);
 653                 priv->viu.vd1_addr2 = gem->paddr + fb->offsets[2];
 654                 priv->viu.vd1_stride2 = fb->pitches[2];
 655                 priv->viu.vd1_height2 =
 656                         drm_format_info_plane_height(fb->format,
 657                                                 fb->height, 2);
 658                 DRM_DEBUG("plane 2 addr 0x%x stride %d height %d\n",
 659                          priv->viu.vd1_addr2,
 660                          priv->viu.vd1_stride2,
 661                          priv->viu.vd1_height2);
 662                 fallthrough;
 663         case 2:
 664                 gem = drm_fb_cma_get_gem_obj(fb, 1);
 665                 priv->viu.vd1_addr1 = gem->paddr + fb->offsets[1];
 666                 priv->viu.vd1_stride1 = fb->pitches[1];
 667                 priv->viu.vd1_height1 =
 668                         drm_format_info_plane_height(fb->format,
 669                                                 fb->height, 1);
 670                 DRM_DEBUG("plane 1 addr 0x%x stride %d height %d\n",
 671                          priv->viu.vd1_addr1,
 672                          priv->viu.vd1_stride1,
 673                          priv->viu.vd1_height1);
 674                 fallthrough;
 675         case 1:
 676                 gem = drm_fb_cma_get_gem_obj(fb, 0);
 677                 priv->viu.vd1_addr0 = gem->paddr + fb->offsets[0];
 678                 priv->viu.vd1_stride0 = fb->pitches[0];
 679                 priv->viu.vd1_height0 =
 680                         drm_format_info_plane_height(fb->format,
 681                                                      fb->height, 0);
 682                 DRM_DEBUG("plane 0 addr 0x%x stride %d height %d\n",
 683                          priv->viu.vd1_addr0,
 684                          priv->viu.vd1_stride0,
 685                          priv->viu.vd1_height0);
 686         }
 687
 688         if (priv->viu.vd1_afbc) {
 689                 if (priv->viu.vd1_afbc_mode & AFBC_SCATTER_MODE) {
 690                         /*
 691                          * In Scatter mode, the header contains the physical
 692                          * body content layout, thus the body content
 693                          * size isn't needed.
 694                          */
 695                         priv->viu.vd1_afbc_head_addr = priv->viu.vd1_addr0 >> 4;
 696                         priv->viu.vd1_afbc_body_addr = 0;
 697                 } else {
 698                         /* Default mode is 4k per superblock */
 699                         unsigned long block_size = 4096;
 700                         unsigned long body_size;
 701
 702                         /* 8bit mem saving mode is 3072bytes per superblock */
 703                         if (priv->viu.vd1_afbc_mode & AFBC_BLK_MEM_MODE)
 704                                 block_size = 3072;
 705
 706                         body_size = (ALIGN(priv->viu.vd1_stride0, 64) / 64) *
 707                                     (ALIGN(priv->viu.vd1_height0, 32) / 32) *
 708                                     block_size;
 709
 710                         priv->viu.vd1_afbc_body_addr = priv->viu.vd1_addr0 >> 4;
 711                         /* Header is after body content */
 712                         priv->viu.vd1_afbc_head_addr = (priv->viu.vd1_addr0 +
 713                                                         body_size) >> 4;
 714                 }
 715         }
 716
 717         priv->viu.vd1_enabled = true;
 718
 719         spin_unlock_irqrestore(&priv->drm->event_lock, flags);
 720
 721         DRM_DEBUG_DRIVER("\n");
 722 }
 723
 724 static void meson_overlay_atomic_disable(struct drm_plane *plane,
 725                                        struct drm_atomic_state *state)
 726 {
 727         struct meson_overlay *meson_overlay = to_meson_overlay(plane);
 728         struct meson_drm *priv = meson_overlay->priv;
 729
 730         DRM_DEBUG_DRIVER("\n");
 731
 732         priv->viu.vd1_enabled = false;
 733
 734         /* Disable VD1 */
 735         if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
 736                 writel_relaxed(0, priv->io_base + _REG(VD1_BLEND_SRC_CTRL));
 737                 writel_relaxed(0, priv->io_base + _REG(VD2_BLEND_SRC_CTRL));
 738                 writel_relaxed(0, priv->io_base + _REG(VD1_IF0_GEN_REG + 0x17b0));
 739                 writel_relaxed(0, priv->io_base + _REG(VD2_IF0_GEN_REG + 0x17b0));
 740         } else
 741                 writel_bits_relaxed(VPP_VD1_POSTBLEND | VPP_VD1_PREBLEND, 0,
 742                                     priv->io_base + _REG(VPP_MISC));
 743
 744 }
 745
 746 static const struct drm_plane_helper_funcs meson_overlay_helper_funcs = {
 747         .atomic_check   = meson_overlay_atomic_check,
 748         .atomic_disable = meson_overlay_atomic_disable,
 749         .atomic_update  = meson_overlay_atomic_update,
 750         .prepare_fb     = drm_gem_plane_helper_prepare_fb,
 751 };
 752
 753 static bool meson_overlay_format_mod_supported(struct drm_plane *plane,
 754                                                u32 format, u64 modifier)
 755 {
 756         if (modifier == DRM_FORMAT_MOD_LINEAR &&
 757             format != DRM_FORMAT_YUV420_8BIT &&
 758             format != DRM_FORMAT_YUV420_10BIT)
 759                 return true;
 760
 761         if ((modifier & DRM_FORMAT_MOD_AMLOGIC_FBC(0, 0)) ==
 762                         DRM_FORMAT_MOD_AMLOGIC_FBC(0, 0)) {
 763                 unsigned int layout = modifier &
 764                         DRM_FORMAT_MOD_AMLOGIC_FBC(
 765                                 __fourcc_mod_amlogic_layout_mask, 0);
 766                 unsigned int options =
 767                         (modifier >> __fourcc_mod_amlogic_options_shift) &
 768                         __fourcc_mod_amlogic_options_mask;
 769
 770                 if (format != DRM_FORMAT_YUV420_8BIT &&
 771                     format != DRM_FORMAT_YUV420_10BIT) {
 772                         DRM_DEBUG_KMS("%llx invalid format 0x%08x\n",
 773                                       modifier, format);
 774                         return false;
 775                 }
 776
 777                 if (layout != AMLOGIC_FBC_LAYOUT_BASIC &&
 778                     layout != AMLOGIC_FBC_LAYOUT_SCATTER) {
 779                         DRM_DEBUG_KMS("%llx invalid layout %x\n",
 780                                       modifier, layout);
 781                         return false;
 782                 }
 783
 784                 if (options &&
 785                     options != AMLOGIC_FBC_OPTION_MEM_SAVING) {
 786                         DRM_DEBUG_KMS("%llx invalid layout %x\n",
 787                                       modifier, layout);
 788                         return false;
 789                 }
 790
 791                 return true;
 792         }
 793
 794         DRM_DEBUG_KMS("invalid modifier %llx for format 0x%08x\n",
 795                       modifier, format);
 796
 797         return false;
 798 }
 799
 800 static const struct drm_plane_funcs meson_overlay_funcs = {
 801         .update_plane           = drm_atomic_helper_update_plane,
 802         .disable_plane          = drm_atomic_helper_disable_plane,
 803         .destroy                = drm_plane_cleanup,
 804         .reset                  = drm_atomic_helper_plane_reset,
 805         .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
 806         .atomic_destroy_state   = drm_atomic_helper_plane_destroy_state,
 807         .format_mod_supported   = meson_overlay_format_mod_supported,
 808 };
 809
 810 static const uint32_t supported_drm_formats[] = {
 811         DRM_FORMAT_YUYV,
 812         DRM_FORMAT_NV12,
 813         DRM_FORMAT_NV21,
 814         DRM_FORMAT_YUV444,
 815         DRM_FORMAT_YUV422,
 816         DRM_FORMAT_YUV420,
 817         DRM_FORMAT_YUV411,
 818         DRM_FORMAT_YUV410,
 819         DRM_FORMAT_YUV420_8BIT, /* Amlogic FBC Only */
 820         DRM_FORMAT_YUV420_10BIT, /* Amlogic FBC Only */
 821 };
 822
 823 static const uint64_t format_modifiers[] = {
 824         DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_SCATTER,
 825                                    AMLOGIC_FBC_OPTION_MEM_SAVING),
 826         DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC,
 827                                    AMLOGIC_FBC_OPTION_MEM_SAVING),
 828         DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_SCATTER, 0),
 829         DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC, 0),
 830         DRM_FORMAT_MOD_LINEAR,
 831         DRM_FORMAT_MOD_INVALID,
 832 };
 833
 834 int meson_overlay_create(struct meson_drm *priv)
 835 {
 836         struct meson_overlay *meson_overlay;
 837         struct drm_plane *plane;
 838
 839         DRM_DEBUG_DRIVER("\n");
 840
 841         meson_overlay = devm_kzalloc(priv->drm->dev, sizeof(*meson_overlay),
 842                                    GFP_KERNEL);
 843         if (!meson_overlay)
 844                 return -ENOMEM;
 845
 846         meson_overlay->priv = priv;
 847         plane = &meson_overlay->base;
 848
 849         drm_universal_plane_init(priv->drm, plane, 0xFF,
 850                                  &meson_overlay_funcs,
 851                                  supported_drm_formats,
 852                                  ARRAY_SIZE(supported_drm_formats),
 853                                  format_modifiers,
 854                                  DRM_PLANE_TYPE_OVERLAY, "meson_overlay_plane");
 855
 856         drm_plane_helper_add(plane, &meson_overlay_helper_funcs);
 857
 858         /* For now, VD Overlay plane is always on the back */
 859         drm_plane_create_zpos_immutable_property(plane, 0);
 860
 861         priv->overlay_plane = plane;
 862
 863         DRM_DEBUG_DRIVER("\n");
 864
 865         return 0;
 866 }