drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "amdgpu_ras.h"
  25 #include "mmhub_v1_7.h"
  26
  27 #include "mmhub/mmhub_1_7_offset.h"
  28 #include "mmhub/mmhub_1_7_sh_mask.h"
  29 #include "vega10_enum.h"
  30
  31 #include "soc15_common.h"
  32 #include "soc15.h"
  33
  34 #define regVM_L2_CNTL3_DEFAULT  0x80100007
  35 #define regVM_L2_CNTL4_DEFAULT  0x000000c1
  36
  37 static u64 mmhub_v1_7_get_fb_location(struct amdgpu_device *adev)
  38 {
  39         u64 base = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE);
  40         u64 top = RREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP);
  41
  42         base &= MC_VM_FB_LOCATION_BASE__FB_BASE_MASK;
  43         base <<= 24;
  44
  45         top &= MC_VM_FB_LOCATION_TOP__FB_TOP_MASK;
  46         top <<= 24;
  47
  48         adev->gmc.fb_start = base;
  49         adev->gmc.fb_end = top;
  50
  51         return base;
  52 }
  53
  54 static void mmhub_v1_7_setup_vm_pt_regs(struct amdgpu_device *adev, uint32_t vmid,
  55                                 uint64_t page_table_base)
  56 {
  57         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
  58
  59         WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32,
  60                         hub->ctx_addr_distance * vmid, lower_32_bits(page_table_base));
  61
  62         WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32,
  63                         hub->ctx_addr_distance * vmid, upper_32_bits(page_table_base));
  64 }
  65
  66 static void mmhub_v1_7_init_gart_aperture_regs(struct amdgpu_device *adev)
  67 {
  68         uint64_t pt_base;
  69
  70         if (adev->gmc.pdb0_bo)
  71                 pt_base = amdgpu_gmc_pd_addr(adev->gmc.pdb0_bo);
  72         else
  73                 pt_base = amdgpu_gmc_pd_addr(adev->gart.bo);
  74
  75         mmhub_v1_7_setup_vm_pt_regs(adev, 0, pt_base);
  76
  77         /* If use GART for FB translation, vmid0 page table covers both
  78          * vram and system memory (gart)
  79          */
  80         if (adev->gmc.pdb0_bo) {
  81                 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
  82                                 (u32)(adev->gmc.fb_start >> 12));
  83                 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
  84                                 (u32)(adev->gmc.fb_start >> 44));
  85
  86                 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
  87                                 (u32)(adev->gmc.gart_end >> 12));
  88                 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
  89                                 (u32)(adev->gmc.gart_end >> 44));
  90
  91         } else {
  92                 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_LO32,
  93                                 (u32)(adev->gmc.gart_start >> 12));
  94                 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_START_ADDR_HI32,
  95                                 (u32)(adev->gmc.gart_start >> 44));
  96
  97                 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_LO32,
  98                                 (u32)(adev->gmc.gart_end >> 12));
  99                 WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_PAGE_TABLE_END_ADDR_HI32,
 100                                 (u32)(adev->gmc.gart_end >> 44));
 101         }
 102 }
 103
 104 static void mmhub_v1_7_init_system_aperture_regs(struct amdgpu_device *adev)
 105 {
 106         uint64_t value;
 107         uint32_t tmp;
 108
 109         /* Program the AGP BAR */
 110         WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BASE, 0);
 111         WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BOT, adev->gmc.agp_start >> 24);
 112         WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_TOP, adev->gmc.agp_end >> 24);
 113
 114         /* Program the system aperture low logical page number. */
 115         WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR,
 116                      min(adev->gmc.fb_start, adev->gmc.agp_start) >> 18);
 117
 118         WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 119                      max(adev->gmc.fb_end, adev->gmc.agp_end) >> 18);
 120
 121         /* In the case squeezing vram into GART aperture, we don't use
 122          * FB aperture and AGP aperture. Disable them.
 123          */
 124         if (adev->gmc.pdb0_bo) {
 125                 WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_BOT, 0xFFFFFF);
 126                 WREG32_SOC15(MMHUB, 0, regMC_VM_AGP_TOP, 0);
 127                 WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP, 0);
 128                 WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE, 0x00FFFFFF);
 129                 WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_LOW_ADDR, 0x3FFFFFFF);
 130                 WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_HIGH_ADDR, 0);
 131         }
 132         if (amdgpu_sriov_vf(adev))
 133                 return;
 134
 135         /* Set default page address. */
 136         value = amdgpu_gmc_vram_mc2pa(adev, adev->vram_scratch.gpu_addr);
 137         WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_LSB,
 138                      (u32)(value >> 12));
 139         WREG32_SOC15(MMHUB, 0, regMC_VM_SYSTEM_APERTURE_DEFAULT_ADDR_MSB,
 140                      (u32)(value >> 44));
 141
 142         /* Program "protection fault". */
 143         WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_LO32,
 144                      (u32)(adev->dummy_page_addr >> 12));
 145         WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_DEFAULT_ADDR_HI32,
 146                      (u32)((u64)adev->dummy_page_addr >> 44));
 147
 148         tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL2);
 149         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL2,
 150                             ACTIVE_PAGE_MIGRATION_PTE_READ_RETRY, 1);
 151         WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL2, tmp);
 152 }
 153
 154 static void mmhub_v1_7_init_tlb_regs(struct amdgpu_device *adev)
 155 {
 156         uint32_t tmp;
 157
 158         /* Setup TLB control */
 159         tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL);
 160
 161         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 1);
 162         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, SYSTEM_ACCESS_MODE, 3);
 163         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 164                             ENABLE_ADVANCED_DRIVER_MODEL, 1);
 165         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 166                             SYSTEM_APERTURE_UNMAPPED_ACCESS, 0);
 167         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ECO_BITS, 0);
 168         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL,
 169                             MTYPE, MTYPE_UC);/* XXX for emulation. */
 170         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ATC_EN, 1);
 171
 172         WREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL, tmp);
 173 }
 174
 175 static void mmhub_v1_7_init_cache_regs(struct amdgpu_device *adev)
 176 {
 177         uint32_t tmp;
 178
 179         if (amdgpu_sriov_vf(adev))
 180                 return;
 181
 182         /* Setup L2 cache */
 183         tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL);
 184         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1);
 185         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING, 1);
 186         /* XXX for emulation, Refer to closed source code.*/
 187         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, L2_PDE0_CACHE_TAG_GENERATION_MODE,
 188                             0);
 189         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, PDE_FAULT_CLASSIFICATION, 0);
 190         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, CONTEXT1_IDENTITY_ACCESS_MODE, 1);
 191         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, IDENTITY_MODE_FRAGMENT_SIZE, 0);
 192         WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL, tmp);
 193
 194         tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL2);
 195         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_ALL_L1_TLBS, 1);
 196         tmp = REG_SET_FIELD(tmp, VM_L2_CNTL2, INVALIDATE_L2_CACHE, 1);
 197         WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL2, tmp);
 198
 199         tmp = regVM_L2_CNTL3_DEFAULT;
 200         if (adev->gmc.translate_further) {
 201                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 12);
 202                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
 203                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 9);
 204         } else {
 205                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3, BANK_SELECT, 9);
 206                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL3,
 207                                     L2_CACHE_BIGK_FRAGMENT_SIZE, 6);
 208         }
 209         WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL3, tmp);
 210
 211         tmp = regVM_L2_CNTL4_DEFAULT;
 212         if (adev->gmc.xgmi.connected_to_cpu) {
 213                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
 214                                     VMC_TAP_PDE_REQUEST_PHYSICAL, 1);
 215                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
 216                                     VMC_TAP_PTE_REQUEST_PHYSICAL, 1);
 217         } else {
 218                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
 219                                     VMC_TAP_PDE_REQUEST_PHYSICAL, 0);
 220                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL4,
 221                                     VMC_TAP_PTE_REQUEST_PHYSICAL, 0);
 222         }
 223         WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL4, tmp);
 224 }
 225
 226 static void mmhub_v1_7_enable_system_domain(struct amdgpu_device *adev)
 227 {
 228         uint32_t tmp;
 229
 230         tmp = RREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_CNTL);
 231         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, ENABLE_CONTEXT, 1);
 232         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_DEPTH,
 233                         adev->gmc.vmid0_page_table_depth);
 234         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL, PAGE_TABLE_BLOCK_SIZE,
 235                         adev->gmc.vmid0_page_table_block_size);
 236         tmp = REG_SET_FIELD(tmp, VM_CONTEXT0_CNTL,
 237                             RETRY_PERMISSION_OR_INVALID_PAGE_FAULT, 0);
 238         WREG32_SOC15(MMHUB, 0, regVM_CONTEXT0_CNTL, tmp);
 239 }
 240
 241 static void mmhub_v1_7_disable_identity_aperture(struct amdgpu_device *adev)
 242 {
 243         if (amdgpu_sriov_vf(adev))
 244                 return;
 245
 246         WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_LO32,
 247                      0XFFFFFFFF);
 248         WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT1_IDENTITY_APERTURE_LOW_ADDR_HI32,
 249                      0x0000000F);
 250
 251         WREG32_SOC15(MMHUB, 0,
 252                      regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_LO32, 0);
 253         WREG32_SOC15(MMHUB, 0,
 254                      regVM_L2_CONTEXT1_IDENTITY_APERTURE_HIGH_ADDR_HI32, 0);
 255
 256         WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_LO32,
 257                      0);
 258         WREG32_SOC15(MMHUB, 0, regVM_L2_CONTEXT_IDENTITY_PHYSICAL_OFFSET_HI32,
 259                      0);
 260 }
 261
 262 static void mmhub_v1_7_setup_vmid_config(struct amdgpu_device *adev)
 263 {
 264         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 265         unsigned num_level, block_size;
 266         uint32_t tmp;
 267         int i;
 268
 269         num_level = adev->vm_manager.num_level;
 270         block_size = adev->vm_manager.block_size;
 271         if (adev->gmc.translate_further)
 272                 num_level -= 1;
 273         else
 274                 block_size -= 9;
 275
 276         for (i = 0; i <= 14; i++) {
 277                 tmp = RREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL, i);
 278                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, ENABLE_CONTEXT, 1);
 279                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL, PAGE_TABLE_DEPTH,
 280                                     num_level);
 281                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 282                                     RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 283                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 284                                     DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT,
 285                                     1);
 286                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 287                                     PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 288                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 289                                     VALID_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 290                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 291                                     READ_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 292                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 293                                     WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 294                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 295                                     EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, 1);
 296                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 297                                     PAGE_TABLE_BLOCK_SIZE,
 298                                     block_size);
 299                 /* Send no-retry XNACK on fault to suppress VM fault storm. */
 300                 tmp = REG_SET_FIELD(tmp, VM_CONTEXT1_CNTL,
 301                                     RETRY_PERMISSION_OR_INVALID_PAGE_FAULT,
 302                                     !adev->gmc.noretry);
 303                 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_CNTL,
 304                                     i * hub->ctx_distance, tmp);
 305                 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_START_ADDR_LO32,
 306                                     i * hub->ctx_addr_distance, 0);
 307                 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_START_ADDR_HI32,
 308                                     i * hub->ctx_addr_distance, 0);
 309                 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_END_ADDR_LO32,
 310                                     i * hub->ctx_addr_distance,
 311                                     lower_32_bits(adev->vm_manager.max_pfn - 1));
 312                 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT1_PAGE_TABLE_END_ADDR_HI32,
 313                                     i * hub->ctx_addr_distance,
 314                                     upper_32_bits(adev->vm_manager.max_pfn - 1));
 315         }
 316 }
 317
 318 static void mmhub_v1_7_program_invalidation(struct amdgpu_device *adev)
 319 {
 320         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 321         unsigned i;
 322
 323         for (i = 0; i < 18; ++i) {
 324                 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32,
 325                                     i * hub->eng_addr_distance, 0xffffffff);
 326                 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ADDR_RANGE_HI32,
 327                                     i * hub->eng_addr_distance, 0x1f);
 328         }
 329 }
 330
 331 static int mmhub_v1_7_gart_enable(struct amdgpu_device *adev)
 332 {
 333         if (amdgpu_sriov_vf(adev)) {
 334                 /*
 335                  * MC_VM_FB_LOCATION_BASE/TOP is NULL for VF, becuase they are
 336                  * VF copy registers so vbios post doesn't program them, for
 337                  * SRIOV driver need to program them
 338                  */
 339                 WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_BASE,
 340                              adev->gmc.vram_start >> 24);
 341                 WREG32_SOC15(MMHUB, 0, regMC_VM_FB_LOCATION_TOP,
 342                              adev->gmc.vram_end >> 24);
 343         }
 344
 345         /* GART Enable. */
 346         mmhub_v1_7_init_gart_aperture_regs(adev);
 347         mmhub_v1_7_init_system_aperture_regs(adev);
 348         mmhub_v1_7_init_tlb_regs(adev);
 349         mmhub_v1_7_init_cache_regs(adev);
 350
 351         mmhub_v1_7_enable_system_domain(adev);
 352         mmhub_v1_7_disable_identity_aperture(adev);
 353         mmhub_v1_7_setup_vmid_config(adev);
 354         mmhub_v1_7_program_invalidation(adev);
 355
 356         return 0;
 357 }
 358
 359 static void mmhub_v1_7_gart_disable(struct amdgpu_device *adev)
 360 {
 361         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 362         u32 tmp;
 363         u32 i;
 364
 365         /* Disable all tables */
 366         for (i = 0; i < 16; i++)
 367                 WREG32_SOC15_OFFSET(MMHUB, 0, regVM_CONTEXT0_CNTL,
 368                                     i * hub->ctx_distance, 0);
 369
 370         /* Setup TLB control */
 371         tmp = RREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL);
 372         tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);
 373         tmp = REG_SET_FIELD(tmp,
 374                                 MC_VM_MX_L1_TLB_CNTL,
 375                                 ENABLE_ADVANCED_DRIVER_MODEL,
 376                                 0);
 377         WREG32_SOC15(MMHUB, 0, regMC_VM_MX_L1_TLB_CNTL, tmp);
 378
 379         if (!amdgpu_sriov_vf(adev)) {
 380                 /* Setup L2 cache */
 381                 tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_CNTL);
 382                 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0);
 383                 WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL, tmp);
 384                 WREG32_SOC15(MMHUB, 0, regVM_L2_CNTL3, 0);
 385         }
 386 }
 387
 388 /**
 389  * mmhub_v1_7_set_fault_enable_default - update GART/VM fault handling
 390  *
 391  * @adev: amdgpu_device pointer
 392  * @value: true redirects VM faults to the default page
 393  */
 394 static void mmhub_v1_7_set_fault_enable_default(struct amdgpu_device *adev, bool value)
 395 {
 396         u32 tmp;
 397
 398         if (amdgpu_sriov_vf(adev))
 399                 return;
 400
 401         tmp = RREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL);
 402         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 403                         RANGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 404         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 405                         PDE0_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 406         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 407                         PDE1_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 408         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 409                         PDE2_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 410         tmp = REG_SET_FIELD(tmp,
 411                         VM_L2_PROTECTION_FAULT_CNTL,
 412                         TRANSLATE_FURTHER_PROTECTION_FAULT_ENABLE_DEFAULT,
 413                         value);
 414         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 415                         NACK_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 416         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 417                         DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 418         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 419                         VALID_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 420         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 421                         READ_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 422         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 423                         WRITE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 424         tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 425                         EXECUTE_PROTECTION_FAULT_ENABLE_DEFAULT, value);
 426         if (!value) {
 427                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 428                                 CRASH_ON_NO_RETRY_FAULT, 1);
 429                 tmp = REG_SET_FIELD(tmp, VM_L2_PROTECTION_FAULT_CNTL,
 430                                 CRASH_ON_RETRY_FAULT, 1);
 431     }
 432
 433         WREG32_SOC15(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL, tmp);
 434 }
 435
 436 static void mmhub_v1_7_init(struct amdgpu_device *adev)
 437 {
 438         struct amdgpu_vmhub *hub = &adev->vmhub[AMDGPU_MMHUB_0];
 439
 440         hub->ctx0_ptb_addr_lo32 =
 441                 SOC15_REG_OFFSET(MMHUB, 0,
 442                                  regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32);
 443         hub->ctx0_ptb_addr_hi32 =
 444                 SOC15_REG_OFFSET(MMHUB, 0,
 445                                  regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_HI32);
 446         hub->vm_inv_eng0_req =
 447                 SOC15_REG_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_REQ);
 448         hub->vm_inv_eng0_ack =
 449                 SOC15_REG_OFFSET(MMHUB, 0, regVM_INVALIDATE_ENG0_ACK);
 450         hub->vm_context0_cntl =
 451                 SOC15_REG_OFFSET(MMHUB, 0, regVM_CONTEXT0_CNTL);
 452         hub->vm_l2_pro_fault_status =
 453                 SOC15_REG_OFFSET(MMHUB, 0, regVM_L2_PROTECTION_FAULT_STATUS);
 454         hub->vm_l2_pro_fault_cntl =
 455                 SOC15_REG_OFFSET(MMHUB, 0, regVM_L2_PROTECTION_FAULT_CNTL);
 456
 457         hub->ctx_distance = regVM_CONTEXT1_CNTL - regVM_CONTEXT0_CNTL;
 458         hub->ctx_addr_distance = regVM_CONTEXT1_PAGE_TABLE_BASE_ADDR_LO32 -
 459                 regVM_CONTEXT0_PAGE_TABLE_BASE_ADDR_LO32;
 460         hub->eng_distance = regVM_INVALIDATE_ENG1_REQ - regVM_INVALIDATE_ENG0_REQ;
 461         hub->eng_addr_distance = regVM_INVALIDATE_ENG1_ADDR_RANGE_LO32 -
 462                 regVM_INVALIDATE_ENG0_ADDR_RANGE_LO32;
 463
 464 }
 465
 466 static void mmhub_v1_7_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 467                                                         bool enable)
 468 {
 469         uint32_t def, data, def1, data1, def2 = 0, data2 = 0;
 470
 471         def  = data  = RREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG);
 472
 473         def1 = data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2);
 474         def2 = data2 = RREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2);
 475
 476         if (enable) {
 477                 data |= ATC_L2_MISC_CG__ENABLE_MASK;
 478
 479                 data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 480                            DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 481                            DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 482                            DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 483                            DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 484                            DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 485
 486                 data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 487                            DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 488                            DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 489                            DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 490                            DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 491                            DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 492         } else {
 493                 data &= ~ATC_L2_MISC_CG__ENABLE_MASK;
 494
 495                 data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 496                           DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 497                           DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 498                           DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 499                           DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 500                           DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 501
 502                 data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 503                           DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 504                           DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 505                           DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 506                           DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 507                           DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
 508         }
 509
 510         if (def != data)
 511                 WREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG, data);
 512
 513         if (def1 != data1)
 514                 WREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2, data1);
 515
 516         if (def2 != data2)
 517                 WREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2, data2);
 518 }
 519
 520 static void mmhub_v1_7_update_medium_grain_light_sleep(struct amdgpu_device *adev,
 521                                                        bool enable)
 522 {
 523         uint32_t def, data;
 524
 525         def = data = RREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG);
 526
 527         if (enable)
 528                 data |= ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
 529         else
 530                 data &= ~ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
 531
 532         if (def != data)
 533                 WREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG, data);
 534 }
 535
 536 static int mmhub_v1_7_set_clockgating(struct amdgpu_device *adev,
 537                                enum amd_clockgating_state state)
 538 {
 539         if (amdgpu_sriov_vf(adev))
 540                 return 0;
 541
 542         /* Change state only if MCCG support is enabled through driver */
 543         if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)
 544                 mmhub_v1_7_update_medium_grain_clock_gating(adev,
 545                                 state == AMD_CG_STATE_GATE);
 546
 547         /* Change state only if LS support is enabled through driver */
 548         if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)
 549                 mmhub_v1_7_update_medium_grain_light_sleep(adev,
 550                                 state == AMD_CG_STATE_GATE);
 551
 552         return 0;
 553 }
 554
 555 static void mmhub_v1_7_get_clockgating(struct amdgpu_device *adev, u32 *flags)
 556 {
 557         int data, data1;
 558
 559         if (amdgpu_sriov_vf(adev))
 560                 *flags = 0;
 561
 562         data = RREG32_SOC15(MMHUB, 0, regATC_L2_MISC_CG);
 563
 564         data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2);
 565
 566         /* AMD_CG_SUPPORT_MC_MGCG */
 567         if ((data & ATC_L2_MISC_CG__ENABLE_MASK) &&
 568             !(data1 & (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
 569                        DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
 570                        DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
 571                        DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
 572                        DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
 573                        DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK)))
 574                 *flags |= AMD_CG_SUPPORT_MC_MGCG;
 575
 576         /* AMD_CG_SUPPORT_MC_LS */
 577         if (data & ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
 578                 *flags |= AMD_CG_SUPPORT_MC_LS;
 579 }
 580
 581 static const struct soc15_ras_field_entry mmhub_v1_7_ras_fields[] = {
 582         /* MMHUB Range 0 */
 583         { "MMEA0_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
 584         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
 585         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
 586         },
 587         { "MMEA0_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
 588         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
 589         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
 590         },
 591         { "MMEA0_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
 592         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
 593         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
 594         },
 595         { "MMEA0_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
 596         SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
 597         SOC15_REG_FIELD(MMEA0_EDC_CNT, RRET_TAGMEM_DED_COUNT),
 598         },
 599         { "MMEA0_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
 600         SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
 601         SOC15_REG_FIELD(MMEA0_EDC_CNT, WRET_TAGMEM_DED_COUNT),
 602         },
 603         { "MMEA0_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
 604         SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
 605         SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_DATAMEM_DED_COUNT),
 606         },
 607         { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
 608         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
 609         0, 0,
 610         },
 611         { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
 612         SOC15_REG_FIELD(MMEA0_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
 613         0, 0,
 614         },
 615         { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
 616         SOC15_REG_FIELD(MMEA0_EDC_CNT, IORD_CMDMEM_SED_COUNT),
 617         0, 0,
 618         },
 619         { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT),
 620         SOC15_REG_FIELD(MMEA0_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
 621         0, 0,
 622         },
 623         { "MMEA0_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
 624         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
 625         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
 626         },
 627         { "MMEA0_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
 628         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
 629         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
 630         },
 631         { "MMEA0_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
 632         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
 633         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
 634         },
 635         { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
 636         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
 637         0, 0,
 638         },
 639         { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
 640         SOC15_REG_FIELD(MMEA0_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
 641         0, 0,
 642         },
 643         { "MMEA0_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
 644         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_SED_COUNT),
 645         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_DED_COUNT),
 646         },
 647         { "MMEA0_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
 648         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D1MEM_SED_COUNT),
 649         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D1MEM_DED_COUNT),
 650         },
 651         { "MMEA0_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
 652         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D2MEM_SED_COUNT),
 653         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D2MEM_DED_COUNT),
 654         },
 655         { "MMEA0_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2),
 656         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D3MEM_SED_COUNT),
 657         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D3MEM_DED_COUNT),
 658         },
 659         { "MMEA0_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3),
 660         0, 0,
 661         SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
 662         },
 663         { "MMEA0_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3),
 664         0, 0,
 665         SOC15_REG_FIELD(MMEA0_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
 666         },
 667         { "MMEA0_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3),
 668         0, 0,
 669         SOC15_REG_FIELD(MMEA0_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
 670         },
 671         { "MMEA0_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3),
 672         0, 0,
 673         SOC15_REG_FIELD(MMEA0_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
 674         },
 675         { "MMEA0_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3),
 676         0, 0,
 677         SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
 678         },
 679         { "MMEA0_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3),
 680         0, 0,
 681         SOC15_REG_FIELD(MMEA0_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
 682         },
 683
 684         /* MMHUB Range 1 */
 685         { "MMEA1_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
 686         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
 687         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
 688         },
 689         { "MMEA1_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
 690         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
 691         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
 692         },
 693         { "MMEA1_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
 694         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
 695         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
 696         },
 697         { "MMEA1_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
 698         SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
 699         SOC15_REG_FIELD(MMEA1_EDC_CNT, RRET_TAGMEM_DED_COUNT),
 700         },
 701         { "MMEA1_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
 702         SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
 703         SOC15_REG_FIELD(MMEA1_EDC_CNT, WRET_TAGMEM_DED_COUNT),
 704         },
 705         { "MMEA1_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
 706         SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
 707         SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_DATAMEM_DED_COUNT),
 708         },
 709         { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
 710         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
 711         0, 0,
 712         },
 713         { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
 714         SOC15_REG_FIELD(MMEA1_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
 715         0, 0,
 716         },
 717         { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
 718         SOC15_REG_FIELD(MMEA1_EDC_CNT, IORD_CMDMEM_SED_COUNT),
 719         0, 0,
 720         },
 721         { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT),
 722         SOC15_REG_FIELD(MMEA1_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
 723         0, 0,
 724         },
 725         { "MMEA1_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
 726         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
 727         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
 728         },
 729         { "MMEA1_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
 730         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
 731         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
 732         },
 733         { "MMEA1_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
 734         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
 735         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
 736         },
 737         { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
 738         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
 739         0, 0,
 740         },
 741         { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
 742         SOC15_REG_FIELD(MMEA1_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
 743         0, 0,
 744         },
 745         { "MMEA1_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
 746         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D0MEM_SED_COUNT),
 747         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D0MEM_DED_COUNT),
 748         },
 749         { "MMEA1_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
 750         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D1MEM_SED_COUNT),
 751         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D1MEM_DED_COUNT),
 752         },
 753         { "MMEA1_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
 754         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D2MEM_SED_COUNT),
 755         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D2MEM_DED_COUNT),
 756         },
 757         { "MMEA1_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2),
 758         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D3MEM_SED_COUNT),
 759         SOC15_REG_FIELD(MMEA1_EDC_CNT2, MAM_D3MEM_DED_COUNT),
 760         },
 761         { "MMEA1_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3),
 762         0, 0,
 763         SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
 764         },
 765         { "MMEA1_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3),
 766         0, 0,
 767         SOC15_REG_FIELD(MMEA1_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
 768         },
 769         { "MMEA1_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3),
 770         0, 0,
 771         SOC15_REG_FIELD(MMEA1_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
 772         },
 773         { "MMEA1_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3),
 774         0, 0,
 775         SOC15_REG_FIELD(MMEA1_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
 776         },
 777         { "MMEA1_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3),
 778         0, 0,
 779         SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
 780         },
 781         { "MMEA1_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3),
 782         0, 0,
 783         SOC15_REG_FIELD(MMEA1_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
 784         },
 785
 786         /* MMHAB Range 2*/
 787         { "MMEA2_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
 788         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
 789         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
 790         },
 791         { "MMEA2_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
 792         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
 793         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
 794         },
 795         { "MMEA2_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
 796         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
 797         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
 798         },
 799         { "MMEA2_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
 800         SOC15_REG_FIELD(MMEA2_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
 801         SOC15_REG_FIELD(MMEA2_EDC_CNT, RRET_TAGMEM_DED_COUNT),
 802         },
 803         { "MMEA2_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
 804         SOC15_REG_FIELD(MMEA2_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
 805         SOC15_REG_FIELD(MMEA2_EDC_CNT, WRET_TAGMEM_DED_COUNT),
 806         },
 807         { "MMEA2_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
 808         SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
 809         SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_DATAMEM_DED_COUNT),
 810         },
 811         { "MMEA2_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
 812         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
 813         0, 0,
 814         },
 815         { "MMEA2_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
 816         SOC15_REG_FIELD(MMEA2_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
 817         0, 0,
 818         },
 819         { "MMEA2_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
 820         SOC15_REG_FIELD(MMEA2_EDC_CNT, IORD_CMDMEM_SED_COUNT),
 821         0, 0,
 822         },
 823         { "MMEA2_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT),
 824         SOC15_REG_FIELD(MMEA2_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
 825         0, 0,
 826         },
 827         { "MMEA2_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
 828         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
 829         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
 830         },
 831         { "MMEA2_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
 832         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
 833         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
 834         },
 835         { "MMEA2_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
 836         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
 837         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
 838         },
 839         { "MMEA2_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
 840         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
 841         0, 0,
 842         },
 843         { "MMEA2_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
 844         SOC15_REG_FIELD(MMEA2_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
 845         0, 0,
 846         },
 847         { "MMEA2_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
 848         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_SED_COUNT),
 849         SOC15_REG_FIELD(MMEA0_EDC_CNT2, MAM_D0MEM_DED_COUNT),
 850         },
 851         { "MMEA2_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
 852         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D1MEM_SED_COUNT),
 853         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D1MEM_DED_COUNT),
 854         },
 855         { "MMEA2_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
 856         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D2MEM_SED_COUNT),
 857         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D2MEM_DED_COUNT),
 858         },
 859         { "MMEA2_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2),
 860         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D3MEM_SED_COUNT),
 861         SOC15_REG_FIELD(MMEA2_EDC_CNT2, MAM_D3MEM_DED_COUNT),
 862         },
 863         { "MMEA2_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3),
 864         0, 0,
 865         SOC15_REG_FIELD(MMEA2_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
 866         },
 867         { "MMEA2_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3),
 868         0, 0,
 869         SOC15_REG_FIELD(MMEA2_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
 870         },
 871         { "MMEA2_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3),
 872         0, 0,
 873         SOC15_REG_FIELD(MMEA2_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
 874         },
 875         { "MMEA2_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3),
 876         0, 0,
 877         SOC15_REG_FIELD(MMEA2_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
 878         },
 879         { "MMEA2_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3),
 880         0, 0,
 881         SOC15_REG_FIELD(MMEA2_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
 882         },
 883         { "MMEA2_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3),
 884         0, 0,
 885         SOC15_REG_FIELD(MMEA2_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
 886         },
 887
 888         /* MMHUB Rang 3 */
 889         { "MMEA3_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
 890         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
 891         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
 892         },
 893         { "MMEA3_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
 894         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
 895         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
 896         },
 897         { "MMEA3_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
 898         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
 899         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
 900         },
 901         { "MMEA3_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
 902         SOC15_REG_FIELD(MMEA3_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
 903         SOC15_REG_FIELD(MMEA3_EDC_CNT, RRET_TAGMEM_DED_COUNT),
 904         },
 905         { "MMEA3_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
 906         SOC15_REG_FIELD(MMEA3_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
 907         SOC15_REG_FIELD(MMEA3_EDC_CNT, WRET_TAGMEM_DED_COUNT),
 908         },
 909         { "MMEA3_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
 910         SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
 911         SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_DATAMEM_DED_COUNT),
 912         },
 913         { "MMEA3_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
 914         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
 915         0, 0,
 916         },
 917         { "MMEA3_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
 918         SOC15_REG_FIELD(MMEA3_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
 919         0, 0,
 920         },
 921         { "MMEA3_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
 922         SOC15_REG_FIELD(MMEA3_EDC_CNT, IORD_CMDMEM_SED_COUNT),
 923         0, 0,
 924         },
 925         { "MMEA3_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT),
 926         SOC15_REG_FIELD(MMEA3_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
 927         0, 0,
 928         },
 929         { "MMEA3_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
 930         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
 931         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
 932         },
 933         { "MMEA3_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
 934         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
 935         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
 936         },
 937         { "MMEA3_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
 938         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
 939         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
 940         },
 941         { "MMEA3_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
 942         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
 943         0, 0,
 944         },
 945         { "MMEA3_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
 946         SOC15_REG_FIELD(MMEA3_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
 947         0, 0,
 948         },
 949         { "MMEA3_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
 950         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D0MEM_SED_COUNT),
 951         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D0MEM_DED_COUNT),
 952         },
 953         { "MMEA3_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
 954         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D1MEM_SED_COUNT),
 955         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D1MEM_DED_COUNT),
 956         },
 957         { "MMEA3_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
 958         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D2MEM_SED_COUNT),
 959         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D2MEM_DED_COUNT),
 960         },
 961         { "MMEA3_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2),
 962         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D3MEM_SED_COUNT),
 963         SOC15_REG_FIELD(MMEA3_EDC_CNT2, MAM_D3MEM_DED_COUNT),
 964         },
 965         { "MMEA3_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3),
 966         0, 0,
 967         SOC15_REG_FIELD(MMEA3_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
 968         },
 969         { "MMEA3_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3),
 970         0, 0,
 971         SOC15_REG_FIELD(MMEA3_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
 972         },
 973         { "MMEA3_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3),
 974         0, 0,
 975         SOC15_REG_FIELD(MMEA3_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
 976         },
 977         { "MMEA3_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3),
 978         0, 0,
 979         SOC15_REG_FIELD(MMEA3_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
 980         },
 981         { "MMEA3_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3),
 982         0, 0,
 983         SOC15_REG_FIELD(MMEA3_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
 984         },
 985         { "MMEA3_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3),
 986         0, 0,
 987         SOC15_REG_FIELD(MMEA3_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
 988         },
 989
 990         /* MMHUB Range 4 */
 991         { "MMEA4_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
 992         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
 993         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
 994         },
 995         { "MMEA4_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
 996         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
 997         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
 998         },
 999         { "MMEA4_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1000         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1001         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1002         },
1003         { "MMEA4_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1004         SOC15_REG_FIELD(MMEA4_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1005         SOC15_REG_FIELD(MMEA4_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1006         },
1007         { "MMEA4_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1008         SOC15_REG_FIELD(MMEA4_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1009         SOC15_REG_FIELD(MMEA4_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1010         },
1011         { "MMEA4_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1012         SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
1013         SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_DATAMEM_DED_COUNT),
1014         },
1015         { "MMEA4_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1016         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1017         0, 0,
1018         },
1019         { "MMEA4_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1020         SOC15_REG_FIELD(MMEA4_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1021         0, 0,
1022         },
1023         { "MMEA4_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1024         SOC15_REG_FIELD(MMEA4_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1025         0, 0,
1026         },
1027         { "MMEA4_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT),
1028         SOC15_REG_FIELD(MMEA4_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1029         0, 0,
1030         },
1031         { "MMEA4_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1032         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1033         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1034         },
1035         { "MMEA4_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1036         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1037         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1038         },
1039         { "MMEA4_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1040         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1041         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1042         },
1043         { "MMEA4_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1044         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1045         0, 0,
1046         },
1047         { "MMEA4_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1048         SOC15_REG_FIELD(MMEA4_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1049         0, 0,
1050         },
1051         { "MMEA4_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1052         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1053         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1054         },
1055         { "MMEA4_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1056         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1057         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1058         },
1059         { "MMEA4_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1060         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1061         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1062         },
1063         { "MMEA4_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2),
1064         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1065         SOC15_REG_FIELD(MMEA4_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1066         },
1067         { "MMEA4_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3),
1068         0, 0,
1069         SOC15_REG_FIELD(MMEA4_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1070         },
1071         { "MMEA4_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3),
1072         0, 0,
1073         SOC15_REG_FIELD(MMEA4_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1074         },
1075         { "MMEA4_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3),
1076         0, 0,
1077         SOC15_REG_FIELD(MMEA4_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1078         },
1079         { "MMEA4_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3),
1080         0, 0,
1081         SOC15_REG_FIELD(MMEA4_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1082         },
1083         { "MMEA4_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3),
1084         0, 0,
1085         SOC15_REG_FIELD(MMEA4_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1086         },
1087         { "MMEA4_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3),
1088         0, 0,
1089         SOC15_REG_FIELD(MMEA4_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1090         },
1091
1092         /* MMHUAB Range 5 */
1093         { "MMEA5_DRAMRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1094         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_CMDMEM_SEC_COUNT),
1095         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_CMDMEM_DED_COUNT),
1096         },
1097         { "MMEA5_DRAMWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1098         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_CMDMEM_SEC_COUNT),
1099         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_CMDMEM_DED_COUNT),
1100         },
1101         { "MMEA5_DRAMWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1102         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_DATAMEM_SEC_COUNT),
1103         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_DATAMEM_DED_COUNT),
1104         },
1105         { "MMEA5_RRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1106         SOC15_REG_FIELD(MMEA5_EDC_CNT, RRET_TAGMEM_SEC_COUNT),
1107         SOC15_REG_FIELD(MMEA5_EDC_CNT, RRET_TAGMEM_DED_COUNT),
1108         },
1109         { "MMEA5_WRET_TAGMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1110         SOC15_REG_FIELD(MMEA5_EDC_CNT, WRET_TAGMEM_SEC_COUNT),
1111         SOC15_REG_FIELD(MMEA5_EDC_CNT, WRET_TAGMEM_DED_COUNT),
1112         },
1113         { "MMEA5_IOWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1114         SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_DATAMEM_SEC_COUNT),
1115         SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_DATAMEM_DED_COUNT),
1116         },
1117         { "MMEA5_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1118         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMRD_PAGEMEM_SED_COUNT),
1119         0, 0,
1120         },
1121         { "MMEA5_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1122         SOC15_REG_FIELD(MMEA5_EDC_CNT, DRAMWR_PAGEMEM_SED_COUNT),
1123         0, 0,
1124         },
1125         { "MMEA5_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1126         SOC15_REG_FIELD(MMEA5_EDC_CNT, IORD_CMDMEM_SED_COUNT),
1127         0, 0,
1128         },
1129         { "MMEA5_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT),
1130         SOC15_REG_FIELD(MMEA5_EDC_CNT, IOWR_CMDMEM_SED_COUNT),
1131         0, 0,
1132         },
1133         { "MMEA5_GMIRD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1134         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_CMDMEM_SEC_COUNT),
1135         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_CMDMEM_DED_COUNT),
1136         },
1137         { "MMEA5_GMIWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1138         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_CMDMEM_SEC_COUNT),
1139         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_CMDMEM_DED_COUNT),
1140         },
1141         { "MMEA5_GMIWR_DATAMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1142         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_DATAMEM_SEC_COUNT),
1143         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_DATAMEM_DED_COUNT),
1144         },
1145         { "MMEA5_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1146         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIRD_PAGEMEM_SED_COUNT),
1147         0, 0,
1148         },
1149         { "MMEA5_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1150         SOC15_REG_FIELD(MMEA5_EDC_CNT2, GMIWR_PAGEMEM_SED_COUNT),
1151         0, 0,
1152         },
1153         { "MMEA5_MAM_D0MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1154         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D0MEM_SED_COUNT),
1155         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D0MEM_DED_COUNT),
1156         },
1157         { "MMEA5_MAM_D1MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1158         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D1MEM_SED_COUNT),
1159         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D1MEM_DED_COUNT),
1160         },
1161         { "MMEA5_MAM_D2MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1162         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D2MEM_SED_COUNT),
1163         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D2MEM_DED_COUNT),
1164         },
1165         { "MMEA5_MAM_D3MEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2),
1166         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D3MEM_SED_COUNT),
1167         SOC15_REG_FIELD(MMEA5_EDC_CNT2, MAM_D3MEM_DED_COUNT),
1168         },
1169         { "MMEA5_DRAMRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3),
1170         0, 0,
1171         SOC15_REG_FIELD(MMEA5_EDC_CNT3, DRAMRD_PAGEMEM_DED_COUNT),
1172         },
1173         { "MMEA5_DRAMWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3),
1174         0, 0,
1175         SOC15_REG_FIELD(MMEA5_EDC_CNT3, DRAMWR_PAGEMEM_DED_COUNT),
1176         },
1177         { "MMEA5_IORD_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3),
1178         0, 0,
1179         SOC15_REG_FIELD(MMEA5_EDC_CNT3, IORD_CMDMEM_DED_COUNT),
1180         },
1181         { "MMEA5_IOWR_CMDMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3),
1182         0, 0,
1183         SOC15_REG_FIELD(MMEA5_EDC_CNT3, IOWR_CMDMEM_DED_COUNT),
1184         },
1185         { "MMEA5_GMIRD_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3),
1186         0, 0,
1187         SOC15_REG_FIELD(MMEA5_EDC_CNT3, GMIRD_PAGEMEM_DED_COUNT),
1188         },
1189         { "MMEA5_GMIWR_PAGEMEM", SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3),
1190         0, 0,
1191         SOC15_REG_FIELD(MMEA5_EDC_CNT3, GMIWR_PAGEMEM_DED_COUNT),
1192         },
1193 };
1194
1195 static const struct soc15_reg_entry mmhub_v1_7_edc_cnt_regs[] = {
1196         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT), 0, 0, 0 },
1197         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT2), 0, 0, 0 },
1198         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_EDC_CNT3), 0, 0, 0 },
1199         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT), 0, 0, 0 },
1200         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT2), 0, 0, 0 },
1201         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_EDC_CNT3), 0, 0, 0 },
1202         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT), 0, 0, 0 },
1203         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT2), 0, 0, 0 },
1204         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_EDC_CNT3), 0, 0, 0 },
1205         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT), 0, 0, 0 },
1206         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT2), 0, 0, 0 },
1207         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_EDC_CNT3), 0, 0, 0 },
1208         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT), 0, 0, 0 },
1209         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT2), 0, 0, 0 },
1210         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_EDC_CNT3), 0, 0, 0 },
1211         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT), 0, 0, 0 },
1212         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT2), 0, 0, 0 },
1213         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_EDC_CNT3), 0, 0, 0 },
1214 };
1215
1216 static int mmhub_v1_7_get_ras_error_count(struct amdgpu_device *adev,
1217                                           const struct soc15_reg_entry *reg,
1218                                           uint32_t value,
1219                                           uint32_t *sec_count,
1220                                           uint32_t *ded_count)
1221 {
1222         uint32_t i;
1223         uint32_t sec_cnt, ded_cnt;
1224
1225         for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_ras_fields); i++) {
1226                 if(mmhub_v1_7_ras_fields[i].reg_offset != reg->reg_offset)
1227                         continue;
1228
1229                 sec_cnt = (value &
1230                                 mmhub_v1_7_ras_fields[i].sec_count_mask) >>
1231                                 mmhub_v1_7_ras_fields[i].sec_count_shift;
1232                 if (sec_cnt) {
1233                         dev_info(adev->dev, "MMHUB SubBlock %s, SEC %d\n",
1234                                  mmhub_v1_7_ras_fields[i].name,
1235                                  sec_cnt);
1236                         *sec_count += sec_cnt;
1237                 }
1238
1239                 ded_cnt = (value &
1240                                 mmhub_v1_7_ras_fields[i].ded_count_mask) >>
1241                                 mmhub_v1_7_ras_fields[i].ded_count_shift;
1242                 if (ded_cnt) {
1243                         dev_info(adev->dev, "MMHUB SubBlock %s, DED %d\n",
1244                                  mmhub_v1_7_ras_fields[i].name,
1245                                  ded_cnt);
1246                         *ded_count += ded_cnt;
1247                 }
1248         }
1249
1250         return 0;
1251 }
1252
1253 static void mmhub_v1_7_query_ras_error_count(struct amdgpu_device *adev,
1254                                              void *ras_error_status)
1255 {
1256         struct ras_err_data *err_data = (struct ras_err_data *)ras_error_status;
1257         uint32_t sec_count = 0, ded_count = 0;
1258         uint32_t i;
1259         uint32_t reg_value;
1260
1261         err_data->ue_count = 0;
1262         err_data->ce_count = 0;
1263
1264         for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_edc_cnt_regs); i++) {
1265                 reg_value =
1266                         RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_edc_cnt_regs[i]));
1267                 if (reg_value)
1268                         mmhub_v1_7_get_ras_error_count(adev, &mmhub_v1_7_edc_cnt_regs[i],
1269                                 reg_value, &sec_count, &ded_count);
1270         }
1271
1272         err_data->ce_count += sec_count;
1273         err_data->ue_count += ded_count;
1274 }
1275
1276 static void mmhub_v1_7_reset_ras_error_count(struct amdgpu_device *adev)
1277 {
1278         uint32_t i;
1279
1280         /* write 0 to reset the edc counters */
1281         if (amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB)) {
1282                 for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_edc_cnt_regs); i++)
1283                         WREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_edc_cnt_regs[i]), 0);
1284         }
1285 }
1286
1287 static const struct soc15_reg_entry mmhub_v1_7_ea_err_status_regs[] = {
1288         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA0_ERR_STATUS), 0, 0, 0 },
1289         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA1_ERR_STATUS), 0, 0, 0 },
1290         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA2_ERR_STATUS), 0, 0, 0 },
1291         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA3_ERR_STATUS), 0, 0, 0 },
1292         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA4_ERR_STATUS), 0, 0, 0 },
1293         { SOC15_REG_ENTRY(MMHUB, 0, regMMEA5_ERR_STATUS), 0, 0, 0 },
1294 };
1295
1296 static void mmhub_v1_7_query_ras_error_status(struct amdgpu_device *adev)
1297 {
1298         int i;
1299         uint32_t reg_value;
1300
1301         if (!amdgpu_ras_is_supported(adev, AMDGPU_RAS_BLOCK__MMHUB))
1302                 return;
1303
1304         for (i = 0; i < ARRAY_SIZE(mmhub_v1_7_ea_err_status_regs); i++) {
1305                 reg_value =
1306                         RREG32(SOC15_REG_ENTRY_OFFSET(mmhub_v1_7_ea_err_status_regs[i]));
1307                 if (REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_STATUS) ||
1308                     REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_WRRSP_STATUS) ||
1309                     REG_GET_FIELD(reg_value, MMEA0_ERR_STATUS, SDP_RDRSP_DATAPARITY_ERROR)) {
1310                         dev_warn(adev->dev, "MMHUB EA err detected at instance: %d, status: 0x%x!\n",
1311                                         i, reg_value);
1312                 }
1313         }
1314 }
1315
1316 const struct amdgpu_mmhub_ras_funcs mmhub_v1_7_ras_funcs = {
1317         .ras_late_init = amdgpu_mmhub_ras_late_init,
1318         .ras_fini = amdgpu_mmhub_ras_fini,
1319         .query_ras_error_count = mmhub_v1_7_query_ras_error_count,
1320         .reset_ras_error_count = mmhub_v1_7_reset_ras_error_count,
1321         .query_ras_error_status = mmhub_v1_7_query_ras_error_status,
1322 };
1323
1324 const struct amdgpu_mmhub_funcs mmhub_v1_7_funcs = {
1325         .get_fb_location = mmhub_v1_7_get_fb_location,
1326         .init = mmhub_v1_7_init,
1327         .gart_enable = mmhub_v1_7_gart_enable,
1328         .set_fault_enable_default = mmhub_v1_7_set_fault_enable_default,
1329         .gart_disable = mmhub_v1_7_gart_disable,
1330         .set_clockgating = mmhub_v1_7_set_clockgating,
1331         .get_clockgating = mmhub_v1_7_get_clockgating,
1332         .setup_vm_pt_regs = mmhub_v1_7_setup_vm_pt_regs,
1333 };