drivers/gpu/drm/amd/amdgpu/hdp_v5_0.c

   1 /*
   2  * Copyright 2020 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include "amdgpu.h"
  24 #include "amdgpu_atombios.h"
  25 #include "hdp_v5_0.h"
  26
  27 #include "hdp/hdp_5_0_0_offset.h"
  28 #include "hdp/hdp_5_0_0_sh_mask.h"
  29 #include <uapi/linux/kfd_ioctl.h>
  30
  31 static void hdp_v5_0_flush_hdp(struct amdgpu_device *adev,
  32                                 struct amdgpu_ring *ring)
  33 {
  34         if (!ring || !ring->funcs->emit_wreg) {
  35                 WREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
  36                 RREG32((adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2);
  37         } else {
  38                 amdgpu_ring_emit_wreg(ring, (adev->rmmio_remap.reg_offset + KFD_MMIO_REMAP_HDP_MEM_FLUSH_CNTL) >> 2, 0);
  39         }
  40 }
  41
  42 static void hdp_v5_0_invalidate_hdp(struct amdgpu_device *adev,
  43                                     struct amdgpu_ring *ring)
  44 {
  45         if (!ring || !ring->funcs->emit_wreg) {
  46                 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1);
  47                 RREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE);
  48         } else {
  49                 amdgpu_ring_emit_wreg(ring, SOC15_REG_OFFSET(
  50                                         HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1);
  51         }
  52 }
  53
  54 static void hdp_v5_0_update_mem_power_gating(struct amdgpu_device *adev,
  55                                           bool enable)
  56 {
  57         uint32_t hdp_clk_cntl, hdp_clk_cntl1;
  58         uint32_t hdp_mem_pwr_cntl;
  59
  60         if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS |
  61                                 AMD_CG_SUPPORT_HDP_DS |
  62                                 AMD_CG_SUPPORT_HDP_SD)))
  63                 return;
  64
  65         hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
  66         hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);
  67
  68         /* Before doing clock/power mode switch,
  69          * forced on IPH & RC clock */
  70         hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
  71                                      IPH_MEM_CLK_SOFT_OVERRIDE, 1);
  72         hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
  73                                      RC_MEM_CLK_SOFT_OVERRIDE, 1);
  74         WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);
  75
  76         /* HDP 5.0 doesn't support dynamic power mode switch,
  77          * disable clock and power gating before any changing */
  78         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
  79                                          IPH_MEM_POWER_CTRL_EN, 0);
  80         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
  81                                          IPH_MEM_POWER_LS_EN, 0);
  82         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
  83                                          IPH_MEM_POWER_DS_EN, 0);
  84         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
  85                                          IPH_MEM_POWER_SD_EN, 0);
  86         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
  87                                          RC_MEM_POWER_CTRL_EN, 0);
  88         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
  89                                          RC_MEM_POWER_LS_EN, 0);
  90         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
  91                                          RC_MEM_POWER_DS_EN, 0);
  92         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
  93                                          RC_MEM_POWER_SD_EN, 0);
  94         WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
  95
  96         /* Already disabled above. The actions below are for "enabled" only */
  97         if (enable) {
  98                 /* only one clock gating mode (LS/DS/SD) can be enabled */
  99                 if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
 100                         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 101                                                          HDP_MEM_POWER_CTRL,
 102                                                          IPH_MEM_POWER_LS_EN, 1);
 103                         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 104                                                          HDP_MEM_POWER_CTRL,
 105                                                          RC_MEM_POWER_LS_EN, 1);
 106                 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) {
 107                         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 108                                                          HDP_MEM_POWER_CTRL,
 109                                                          IPH_MEM_POWER_DS_EN, 1);
 110                         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 111                                                          HDP_MEM_POWER_CTRL,
 112                                                          RC_MEM_POWER_DS_EN, 1);
 113                 } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) {
 114                         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 115                                                          HDP_MEM_POWER_CTRL,
 116                                                          IPH_MEM_POWER_SD_EN, 1);
 117                         /* RC should not use shut down mode, fallback to ds  or ls if allowed */
 118                         if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS)
 119                                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 120                                                                  HDP_MEM_POWER_CTRL,
 121                                                                  RC_MEM_POWER_DS_EN, 1);
 122                         else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS)
 123                                 hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
 124                                                                  HDP_MEM_POWER_CTRL,
 125                                                                  RC_MEM_POWER_LS_EN, 1);
 126                 }
 127
 128                 /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to
 129                  * be set for SRAM LS/DS/SD */
 130                 if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS |
 131                                       AMD_CG_SUPPORT_HDP_SD)) {
 132                         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 133                                                          IPH_MEM_POWER_CTRL_EN, 1);
 134                         hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
 135                                                          RC_MEM_POWER_CTRL_EN, 1);
 136                         WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
 137                 }
 138         }
 139
 140         /* disable IPH & RC clock override after clock/power mode changing */
 141         hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
 142                                      IPH_MEM_CLK_SOFT_OVERRIDE, 0);
 143         hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
 144                                      RC_MEM_CLK_SOFT_OVERRIDE, 0);
 145         WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);
 146 }
 147
 148 static void hdp_v5_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
 149                                                       bool enable)
 150 {
 151         uint32_t hdp_clk_cntl;
 152
 153         if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
 154                 return;
 155
 156         hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
 157
 158         if (enable) {
 159                 hdp_clk_cntl &=
 160                         ~(uint32_t)
 161                         (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
 162                          HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
 163                          HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
 164                          HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
 165                          HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
 166                          HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK);
 167         } else {
 168                 hdp_clk_cntl |= HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
 169                         HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
 170                         HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
 171                         HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
 172                         HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
 173                         HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK;
 174         }
 175
 176         WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl);
 177 }
 178
 179 static void hdp_v5_0_update_clock_gating(struct amdgpu_device *adev,
 180                                               bool enable)
 181 {
 182         hdp_v5_0_update_mem_power_gating(adev, enable);
 183         hdp_v5_0_update_medium_grain_clock_gating(adev, enable);
 184 }
 185
 186 static void hdp_v5_0_get_clockgating_state(struct amdgpu_device *adev,
 187                                             u64 *flags)
 188 {
 189         uint32_t tmp;
 190
 191         /* AMD_CG_SUPPORT_HDP_MGCG */
 192         tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL);
 193         if (!(tmp & (HDP_CLK_CNTL__IPH_MEM_CLK_SOFT_OVERRIDE_MASK |
 194                      HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
 195                      HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
 196                      HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
 197                      HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
 198                      HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK)))
 199                 *flags |= AMD_CG_SUPPORT_HDP_MGCG;
 200
 201         /* AMD_CG_SUPPORT_HDP_LS/DS/SD */
 202         tmp = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL);
 203         if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_LS_EN_MASK)
 204                 *flags |= AMD_CG_SUPPORT_HDP_LS;
 205         else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_DS_EN_MASK)
 206                 *flags |= AMD_CG_SUPPORT_HDP_DS;
 207         else if (tmp & HDP_MEM_POWER_CTRL__IPH_MEM_POWER_SD_EN_MASK)
 208                 *flags |= AMD_CG_SUPPORT_HDP_SD;
 209 }
 210
 211 static void hdp_v5_0_init_registers(struct amdgpu_device *adev)
 212 {
 213         u32 tmp;
 214
 215         tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL);
 216         tmp |= HDP_MISC_CNTL__FLUSH_INVALIDATE_CACHE_MASK;
 217         WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp);
 218 }
 219
 220 const struct amdgpu_hdp_funcs hdp_v5_0_funcs = {
 221         .flush_hdp = hdp_v5_0_flush_hdp,
 222         .invalidate_hdp = hdp_v5_0_invalidate_hdp,
 223         .update_clock_gating = hdp_v5_0_update_clock_gating,
 224         .get_clock_gating_state = hdp_v5_0_get_clockgating_state,
 225         .init_registers = hdp_v5_0_init_registers,
 226 };