drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <[email protected]>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <linux/notifier.h>
  32 #include <linux/reboot.h>
  33 #include <drm/drmP.h>
  34 #include <drm/drm_atomic_helper.h>
  35 #include <drm/drm_crtc.h>
  36 #include <drm/drm_crtc_helper.h>
  37 #include <drm/drm_edid.h>
  38 #include "intel_drv.h"
  39 #include <drm/i915_drm.h>
  40 #include "i915_drv.h"
  41
  42 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  43
  44 /* Compliance test status bits  */
  45 #define INTEL_DP_RESOLUTION_SHIFT_MASK  0
  46 #define INTEL_DP_RESOLUTION_PREFERRED   (1 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  47 #define INTEL_DP_RESOLUTION_STANDARD    (2 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  48 #define INTEL_DP_RESOLUTION_FAILSAFE    (3 << INTEL_DP_RESOLUTION_SHIFT_MASK)
  49
  50 struct dp_link_dpll {
  51         int clock;
  52         struct dpll dpll;
  53 };
  54
  55 static const struct dp_link_dpll gen4_dpll[] = {
  56         { 162000,
  57                 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } },
  58         { 270000,
  59                 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } }
  60 };
  61
  62 static const struct dp_link_dpll pch_dpll[] = {
  63         { 162000,
  64                 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } },
  65         { 270000,
  66                 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } }
  67 };
  68
  69 static const struct dp_link_dpll vlv_dpll[] = {
  70         { 162000,
  71                 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } },
  72         { 270000,
  73                 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } }
  74 };
  75
  76 /*
  77  * CHV supports eDP 1.4 that have  more link rates.
  78  * Below only provides the fixed rate but exclude variable rate.
  79  */
  80 static const struct dp_link_dpll chv_dpll[] = {
  81         /*
  82          * CHV requires to program fractional division for m2.
  83          * m2 is stored in fixed point format using formula below
  84          * (m2_int << 22) | m2_fraction
  85          */
  86         { 162000,       /* m2_int = 32, m2_fraction = 1677722 */
  87                 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } },
  88         { 270000,       /* m2_int = 27, m2_fraction = 0 */
  89                 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } },
  90         { 540000,       /* m2_int = 27, m2_fraction = 0 */
  91                 { .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }
  92 };
  93
  94 static const int bxt_rates[] = { 162000, 216000, 243000, 270000,
  95                                   324000, 432000, 540000 };
  96 static const int skl_rates[] = { 162000, 216000, 270000,
  97                                   324000, 432000, 540000 };
  98 static const int default_rates[] = { 162000, 270000, 540000 };
  99
 100 /**
 101  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
 102  * @intel_dp: DP struct
 103  *
 104  * If a CPU or PCH DP output is attached to an eDP panel, this function
 105  * will return true, and false otherwise.
 106  */
 107 static bool is_edp(struct intel_dp *intel_dp)
 108 {
 109         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 110
 111         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
 112 }
 113
 114 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
 115 {
 116         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 117
 118         return intel_dig_port->base.base.dev;
 119 }
 120
 121 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
 122 {
 123         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
 124 }
 125
 126 static void intel_dp_link_down(struct intel_dp *intel_dp);
 127 static bool edp_panel_vdd_on(struct intel_dp *intel_dp);
 128 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync);
 129 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp);
 130 static void vlv_steal_power_sequencer(struct drm_device *dev,
 131                                       enum pipe pipe);
 132
 133 static unsigned int intel_dp_unused_lane_mask(int lane_count)
 134 {
 135         return ~((1 << lane_count) - 1) & 0xf;
 136 }
 137
 138 static int
 139 intel_dp_max_link_bw(struct intel_dp  *intel_dp)
 140 {
 141         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 142
 143         switch (max_link_bw) {
 144         case DP_LINK_BW_1_62:
 145         case DP_LINK_BW_2_7:
 146         case DP_LINK_BW_5_4:
 147                 break;
 148         default:
 149                 WARN(1, "invalid max DP link bw val %x, using 1.62Gbps\n",
 150                      max_link_bw);
 151                 max_link_bw = DP_LINK_BW_1_62;
 152                 break;
 153         }
 154         return max_link_bw;
 155 }
 156
 157 static u8 intel_dp_max_lane_count(struct intel_dp *intel_dp)
 158 {
 159         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 160         struct drm_device *dev = intel_dig_port->base.base.dev;
 161         u8 source_max, sink_max;
 162
 163         source_max = 4;
 164         if (HAS_DDI(dev) && intel_dig_port->port == PORT_A &&
 165             (intel_dig_port->saved_port_bits & DDI_A_4_LANES) == 0)
 166                 source_max = 2;
 167
 168         sink_max = drm_dp_max_lane_count(intel_dp->dpcd);
 169
 170         return min(source_max, sink_max);
 171 }
 172
 173 /*
 174  * The units on the numbers in the next two are... bizarre.  Examples will
 175  * make it clearer; this one parallels an example in the eDP spec.
 176  *
 177  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 178  *
 179  *     270000 * 1 * 8 / 10 == 216000
 180  *
 181  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 182  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 183  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 184  * 119000.  At 18bpp that's 2142000 kilobits per second.
 185  *
 186  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 187  * get the result in decakilobits instead of kilobits.
 188  */
 189
 190 static int
 191 intel_dp_link_required(int pixel_clock, int bpp)
 192 {
 193         return (pixel_clock * bpp + 9) / 10;
 194 }
 195
 196 static int
 197 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 198 {
 199         return (max_link_clock * max_lanes * 8) / 10;
 200 }
 201
 202 static enum drm_mode_status
 203 intel_dp_mode_valid(struct drm_connector *connector,
 204                     struct drm_display_mode *mode)
 205 {
 206         struct intel_dp *intel_dp = intel_attached_dp(connector);
 207         struct intel_connector *intel_connector = to_intel_connector(connector);
 208         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 209         int target_clock = mode->clock;
 210         int max_rate, mode_rate, max_lanes, max_link_clock;
 211
 212         if (is_edp(intel_dp) && fixed_mode) {
 213                 if (mode->hdisplay > fixed_mode->hdisplay)
 214                         return MODE_PANEL;
 215
 216                 if (mode->vdisplay > fixed_mode->vdisplay)
 217                         return MODE_PANEL;
 218
 219                 target_clock = fixed_mode->clock;
 220         }
 221
 222         max_link_clock = intel_dp_max_link_rate(intel_dp);
 223         max_lanes = intel_dp_max_lane_count(intel_dp);
 224
 225         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 226         mode_rate = intel_dp_link_required(target_clock, 18);
 227
 228         if (mode_rate > max_rate)
 229                 return MODE_CLOCK_HIGH;
 230
 231         if (mode->clock < 10000)
 232                 return MODE_CLOCK_LOW;
 233
 234         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 235                 return MODE_H_ILLEGAL;
 236
 237         return MODE_OK;
 238 }
 239
 240 uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes)
 241 {
 242         int     i;
 243         uint32_t v = 0;
 244
 245         if (src_bytes > 4)
 246                 src_bytes = 4;
 247         for (i = 0; i < src_bytes; i++)
 248                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 249         return v;
 250 }
 251
 252 static void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 253 {
 254         int i;
 255         if (dst_bytes > 4)
 256                 dst_bytes = 4;
 257         for (i = 0; i < dst_bytes; i++)
 258                 dst[i] = src >> ((3-i) * 8);
 259 }
 260
 261 static void
 262 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
 263                                     struct intel_dp *intel_dp);
 264 static void
 265 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
 266                                               struct intel_dp *intel_dp);
 267
 268 static void pps_lock(struct intel_dp *intel_dp)
 269 {
 270         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 271         struct intel_encoder *encoder = &intel_dig_port->base;
 272         struct drm_device *dev = encoder->base.dev;
 273         struct drm_i915_private *dev_priv = dev->dev_private;
 274         enum intel_display_power_domain power_domain;
 275
 276         /*
 277          * See vlv_power_sequencer_reset() why we need
 278          * a power domain reference here.
 279          */
 280         power_domain = intel_display_port_aux_power_domain(encoder);
 281         intel_display_power_get(dev_priv, power_domain);
 282
 283         mutex_lock(&dev_priv->pps_mutex);
 284 }
 285
 286 static void pps_unlock(struct intel_dp *intel_dp)
 287 {
 288         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 289         struct intel_encoder *encoder = &intel_dig_port->base;
 290         struct drm_device *dev = encoder->base.dev;
 291         struct drm_i915_private *dev_priv = dev->dev_private;
 292         enum intel_display_power_domain power_domain;
 293
 294         mutex_unlock(&dev_priv->pps_mutex);
 295
 296         power_domain = intel_display_port_aux_power_domain(encoder);
 297         intel_display_power_put(dev_priv, power_domain);
 298 }
 299
 300 static void
 301 vlv_power_sequencer_kick(struct intel_dp *intel_dp)
 302 {
 303         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 304         struct drm_device *dev = intel_dig_port->base.base.dev;
 305         struct drm_i915_private *dev_priv = dev->dev_private;
 306         enum pipe pipe = intel_dp->pps_pipe;
 307         bool pll_enabled, release_cl_override = false;
 308         enum dpio_phy phy = DPIO_PHY(pipe);
 309         enum dpio_channel ch = vlv_pipe_to_channel(pipe);
 310         uint32_t DP;
 311
 312         if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN,
 313                  "skipping pipe %c power seqeuncer kick due to port %c being active\n",
 314                  pipe_name(pipe), port_name(intel_dig_port->port)))
 315                 return;
 316
 317         DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n",
 318                       pipe_name(pipe), port_name(intel_dig_port->port));
 319
 320         /* Preserve the BIOS-computed detected bit. This is
 321          * supposed to be read-only.
 322          */
 323         DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 324         DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 325         DP |= DP_PORT_WIDTH(1);
 326         DP |= DP_LINK_TRAIN_PAT_1;
 327
 328         if (IS_CHERRYVIEW(dev))
 329                 DP |= DP_PIPE_SELECT_CHV(pipe);
 330         else if (pipe == PIPE_B)
 331                 DP |= DP_PIPEB_SELECT;
 332
 333         pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE;
 334
 335         /*
 336          * The DPLL for the pipe must be enabled for this to work.
 337          * So enable temporarily it if it's not already enabled.
 338          */
 339         if (!pll_enabled) {
 340                 release_cl_override = IS_CHERRYVIEW(dev) &&
 341                         !chv_phy_powergate_ch(dev_priv, phy, ch, true);
 342
 343                 vlv_force_pll_on(dev, pipe, IS_CHERRYVIEW(dev) ?
 344                                  &chv_dpll[0].dpll : &vlv_dpll[0].dpll);
 345         }
 346
 347         /*
 348          * Similar magic as in intel_dp_enable_port().
 349          * We _must_ do this port enable + disable trick
 350          * to make this power seqeuencer lock onto the port.
 351          * Otherwise even VDD force bit won't work.
 352          */
 353         I915_WRITE(intel_dp->output_reg, DP);
 354         POSTING_READ(intel_dp->output_reg);
 355
 356         I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN);
 357         POSTING_READ(intel_dp->output_reg);
 358
 359         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
 360         POSTING_READ(intel_dp->output_reg);
 361
 362         if (!pll_enabled) {
 363                 vlv_force_pll_off(dev, pipe);
 364
 365                 if (release_cl_override)
 366                         chv_phy_powergate_ch(dev_priv, phy, ch, false);
 367         }
 368 }
 369
 370 static enum pipe
 371 vlv_power_sequencer_pipe(struct intel_dp *intel_dp)
 372 {
 373         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 374         struct drm_device *dev = intel_dig_port->base.base.dev;
 375         struct drm_i915_private *dev_priv = dev->dev_private;
 376         struct intel_encoder *encoder;
 377         unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B);
 378         enum pipe pipe;
 379
 380         lockdep_assert_held(&dev_priv->pps_mutex);
 381
 382         /* We should never land here with regular DP ports */
 383         WARN_ON(!is_edp(intel_dp));
 384
 385         if (intel_dp->pps_pipe != INVALID_PIPE)
 386                 return intel_dp->pps_pipe;
 387
 388         /*
 389          * We don't have power sequencer currently.
 390          * Pick one that's not used by other ports.
 391          */
 392         for_each_intel_encoder(dev, encoder) {
 393                 struct intel_dp *tmp;
 394
 395                 if (encoder->type != INTEL_OUTPUT_EDP)
 396                         continue;
 397
 398                 tmp = enc_to_intel_dp(&encoder->base);
 399
 400                 if (tmp->pps_pipe != INVALID_PIPE)
 401                         pipes &= ~(1 << tmp->pps_pipe);
 402         }
 403
 404         /*
 405          * Didn't find one. This should not happen since there
 406          * are two power sequencers and up to two eDP ports.
 407          */
 408         if (WARN_ON(pipes == 0))
 409                 pipe = PIPE_A;
 410         else
 411                 pipe = ffs(pipes) - 1;
 412
 413         vlv_steal_power_sequencer(dev, pipe);
 414         intel_dp->pps_pipe = pipe;
 415
 416         DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n",
 417                       pipe_name(intel_dp->pps_pipe),
 418                       port_name(intel_dig_port->port));
 419
 420         /* init power sequencer on this pipe and port */
 421         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 422         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 423
 424         /*
 425          * Even vdd force doesn't work until we've made
 426          * the power sequencer lock in on the port.
 427          */
 428         vlv_power_sequencer_kick(intel_dp);
 429
 430         return intel_dp->pps_pipe;
 431 }
 432
 433 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv,
 434                                enum pipe pipe);
 435
 436 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv,
 437                                enum pipe pipe)
 438 {
 439         return I915_READ(VLV_PIPE_PP_STATUS(pipe)) & PP_ON;
 440 }
 441
 442 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv,
 443                                 enum pipe pipe)
 444 {
 445         return I915_READ(VLV_PIPE_PP_CONTROL(pipe)) & EDP_FORCE_VDD;
 446 }
 447
 448 static bool vlv_pipe_any(struct drm_i915_private *dev_priv,
 449                          enum pipe pipe)
 450 {
 451         return true;
 452 }
 453
 454 static enum pipe
 455 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv,
 456                      enum port port,
 457                      vlv_pipe_check pipe_check)
 458 {
 459         enum pipe pipe;
 460
 461         for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) {
 462                 u32 port_sel = I915_READ(VLV_PIPE_PP_ON_DELAYS(pipe)) &
 463                         PANEL_PORT_SELECT_MASK;
 464
 465                 if (port_sel != PANEL_PORT_SELECT_VLV(port))
 466                         continue;
 467
 468                 if (!pipe_check(dev_priv, pipe))
 469                         continue;
 470
 471                 return pipe;
 472         }
 473
 474         return INVALID_PIPE;
 475 }
 476
 477 static void
 478 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp)
 479 {
 480         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 481         struct drm_device *dev = intel_dig_port->base.base.dev;
 482         struct drm_i915_private *dev_priv = dev->dev_private;
 483         enum port port = intel_dig_port->port;
 484
 485         lockdep_assert_held(&dev_priv->pps_mutex);
 486
 487         /* try to find a pipe with this port selected */
 488         /* first pick one where the panel is on */
 489         intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 490                                                   vlv_pipe_has_pp_on);
 491         /* didn't find one? pick one where vdd is on */
 492         if (intel_dp->pps_pipe == INVALID_PIPE)
 493                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 494                                                           vlv_pipe_has_vdd_on);
 495         /* didn't find one? pick one with just the correct port */
 496         if (intel_dp->pps_pipe == INVALID_PIPE)
 497                 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port,
 498                                                           vlv_pipe_any);
 499
 500         /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */
 501         if (intel_dp->pps_pipe == INVALID_PIPE) {
 502                 DRM_DEBUG_KMS("no initial power sequencer for port %c\n",
 503                               port_name(port));
 504                 return;
 505         }
 506
 507         DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n",
 508                       port_name(port), pipe_name(intel_dp->pps_pipe));
 509
 510         intel_dp_init_panel_power_sequencer(dev, intel_dp);
 511         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
 512 }
 513
 514 void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv)
 515 {
 516         struct drm_device *dev = dev_priv->dev;
 517         struct intel_encoder *encoder;
 518
 519         if (WARN_ON(!IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)))
 520                 return;
 521
 522         /*
 523          * We can't grab pps_mutex here due to deadlock with power_domain
 524          * mutex when power_domain functions are called while holding pps_mutex.
 525          * That also means that in order to use pps_pipe the code needs to
 526          * hold both a power domain reference and pps_mutex, and the power domain
 527          * reference get/put must be done while _not_ holding pps_mutex.
 528          * pps_{lock,unlock}() do these steps in the correct order, so one
 529          * should use them always.
 530          */
 531
 532         for_each_intel_encoder(dev, encoder) {
 533                 struct intel_dp *intel_dp;
 534
 535                 if (encoder->type != INTEL_OUTPUT_EDP)
 536                         continue;
 537
 538                 intel_dp = enc_to_intel_dp(&encoder->base);
 539                 intel_dp->pps_pipe = INVALID_PIPE;
 540         }
 541 }
 542
 543 static i915_reg_t
 544 _pp_ctrl_reg(struct intel_dp *intel_dp)
 545 {
 546         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 547
 548         if (IS_BROXTON(dev))
 549                 return BXT_PP_CONTROL(0);
 550         else if (HAS_PCH_SPLIT(dev))
 551                 return PCH_PP_CONTROL;
 552         else
 553                 return VLV_PIPE_PP_CONTROL(vlv_power_sequencer_pipe(intel_dp));
 554 }
 555
 556 static i915_reg_t
 557 _pp_stat_reg(struct intel_dp *intel_dp)
 558 {
 559         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 560
 561         if (IS_BROXTON(dev))
 562                 return BXT_PP_STATUS(0);
 563         else if (HAS_PCH_SPLIT(dev))
 564                 return PCH_PP_STATUS;
 565         else
 566                 return VLV_PIPE_PP_STATUS(vlv_power_sequencer_pipe(intel_dp));
 567 }
 568
 569 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing
 570    This function only applicable when panel PM state is not to be tracked */
 571 static int edp_notify_handler(struct notifier_block *this, unsigned long code,
 572                               void *unused)
 573 {
 574         struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp),
 575                                                  edp_notifier);
 576         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 577         struct drm_i915_private *dev_priv = dev->dev_private;
 578
 579         if (!is_edp(intel_dp) || code != SYS_RESTART)
 580                 return 0;
 581
 582         pps_lock(intel_dp);
 583
 584         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
 585                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
 586                 i915_reg_t pp_ctrl_reg, pp_div_reg;
 587                 u32 pp_div;
 588
 589                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
 590                 pp_div_reg  = VLV_PIPE_PP_DIVISOR(pipe);
 591                 pp_div = I915_READ(pp_div_reg);
 592                 pp_div &= PP_REFERENCE_DIVIDER_MASK;
 593
 594                 /* 0x1F write to PP_DIV_REG sets max cycle delay */
 595                 I915_WRITE(pp_div_reg, pp_div | 0x1F);
 596                 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS | PANEL_POWER_OFF);
 597                 msleep(intel_dp->panel_power_cycle_delay);
 598         }
 599
 600         pps_unlock(intel_dp);
 601
 602         return 0;
 603 }
 604
 605 static bool edp_have_panel_power(struct intel_dp *intel_dp)
 606 {
 607         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 608         struct drm_i915_private *dev_priv = dev->dev_private;
 609
 610         lockdep_assert_held(&dev_priv->pps_mutex);
 611
 612         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 613             intel_dp->pps_pipe == INVALID_PIPE)
 614                 return false;
 615
 616         return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0;
 617 }
 618
 619 static bool edp_have_panel_vdd(struct intel_dp *intel_dp)
 620 {
 621         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 622         struct drm_i915_private *dev_priv = dev->dev_private;
 623
 624         lockdep_assert_held(&dev_priv->pps_mutex);
 625
 626         if ((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
 627             intel_dp->pps_pipe == INVALID_PIPE)
 628                 return false;
 629
 630         return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD;
 631 }
 632
 633 static void
 634 intel_dp_check_edp(struct intel_dp *intel_dp)
 635 {
 636         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 637         struct drm_i915_private *dev_priv = dev->dev_private;
 638
 639         if (!is_edp(intel_dp))
 640                 return;
 641
 642         if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) {
 643                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 644                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 645                               I915_READ(_pp_stat_reg(intel_dp)),
 646                               I915_READ(_pp_ctrl_reg(intel_dp)));
 647         }
 648 }
 649
 650 static uint32_t
 651 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 652 {
 653         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 654         struct drm_device *dev = intel_dig_port->base.base.dev;
 655         struct drm_i915_private *dev_priv = dev->dev_private;
 656         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 657         uint32_t status;
 658         bool done;
 659
 660 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 661         if (has_aux_irq)
 662                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
 663                                           msecs_to_jiffies_timeout(10));
 664         else
 665                 done = wait_for_atomic(C, 10) == 0;
 666         if (!done)
 667                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 668                           has_aux_irq);
 669 #undef C
 670
 671         return status;
 672 }
 673
 674 static uint32_t i9xx_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 675 {
 676         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 677         struct drm_device *dev = intel_dig_port->base.base.dev;
 678
 679         /*
 680          * The clock divider is based off the hrawclk, and would like to run at
 681          * 2MHz.  So, take the hrawclk value and divide by 2 and use that
 682          */
 683         return index ? 0 : DIV_ROUND_CLOSEST(intel_hrawclk(dev), 2);
 684 }
 685
 686 static uint32_t ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 687 {
 688         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 689         struct drm_device *dev = intel_dig_port->base.base.dev;
 690         struct drm_i915_private *dev_priv = dev->dev_private;
 691
 692         if (index)
 693                 return 0;
 694
 695         if (intel_dig_port->port == PORT_A) {
 696                 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
 697
 698         } else {
 699                 return DIV_ROUND_CLOSEST(intel_pch_rawclk(dev), 2);
 700         }
 701 }
 702
 703 static uint32_t hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 704 {
 705         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 706         struct drm_device *dev = intel_dig_port->base.base.dev;
 707         struct drm_i915_private *dev_priv = dev->dev_private;
 708
 709         if (intel_dig_port->port == PORT_A) {
 710                 if (index)
 711                         return 0;
 712                 return DIV_ROUND_CLOSEST(dev_priv->cdclk_freq, 2000);
 713         } else if (HAS_PCH_LPT_H(dev_priv)) {
 714                 /* Workaround for non-ULT HSW */
 715                 switch (index) {
 716                 case 0: return 63;
 717                 case 1: return 72;
 718                 default: return 0;
 719                 }
 720         } else  {
 721                 return index ? 0 : DIV_ROUND_CLOSEST(intel_pch_rawclk(dev), 2);
 722         }
 723 }
 724
 725 static uint32_t vlv_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 726 {
 727         return index ? 0 : 100;
 728 }
 729
 730 static uint32_t skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index)
 731 {
 732         /*
 733          * SKL doesn't need us to program the AUX clock divider (Hardware will
 734          * derive the clock from CDCLK automatically). We still implement the
 735          * get_aux_clock_divider vfunc to plug-in into the existing code.
 736          */
 737         return index ? 0 : 1;
 738 }
 739
 740 static uint32_t i9xx_get_aux_send_ctl(struct intel_dp *intel_dp,
 741                                       bool has_aux_irq,
 742                                       int send_bytes,
 743                                       uint32_t aux_clock_divider)
 744 {
 745         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 746         struct drm_device *dev = intel_dig_port->base.base.dev;
 747         uint32_t precharge, timeout;
 748
 749         if (IS_GEN6(dev))
 750                 precharge = 3;
 751         else
 752                 precharge = 5;
 753
 754         if (IS_BROADWELL(dev) && intel_dig_port->port == PORT_A)
 755                 timeout = DP_AUX_CH_CTL_TIME_OUT_600us;
 756         else
 757                 timeout = DP_AUX_CH_CTL_TIME_OUT_400us;
 758
 759         return DP_AUX_CH_CTL_SEND_BUSY |
 760                DP_AUX_CH_CTL_DONE |
 761                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 762                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 763                timeout |
 764                DP_AUX_CH_CTL_RECEIVE_ERROR |
 765                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 766                (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 767                (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT);
 768 }
 769
 770 static uint32_t skl_get_aux_send_ctl(struct intel_dp *intel_dp,
 771                                       bool has_aux_irq,
 772                                       int send_bytes,
 773                                       uint32_t unused)
 774 {
 775         return DP_AUX_CH_CTL_SEND_BUSY |
 776                DP_AUX_CH_CTL_DONE |
 777                (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 778                DP_AUX_CH_CTL_TIME_OUT_ERROR |
 779                DP_AUX_CH_CTL_TIME_OUT_1600us |
 780                DP_AUX_CH_CTL_RECEIVE_ERROR |
 781                (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 782                DP_AUX_CH_CTL_SYNC_PULSE_SKL(32);
 783 }
 784
 785 static int
 786 intel_dp_aux_ch(struct intel_dp *intel_dp,
 787                 const uint8_t *send, int send_bytes,
 788                 uint8_t *recv, int recv_size)
 789 {
 790         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 791         struct drm_device *dev = intel_dig_port->base.base.dev;
 792         struct drm_i915_private *dev_priv = dev->dev_private;
 793         i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg;
 794         uint32_t aux_clock_divider;
 795         int i, ret, recv_bytes;
 796         uint32_t status;
 797         int try, clock = 0;
 798         bool has_aux_irq = HAS_AUX_IRQ(dev);
 799         bool vdd;
 800
 801         pps_lock(intel_dp);
 802
 803         /*
 804          * We will be called with VDD already enabled for dpcd/edid/oui reads.
 805          * In such cases we want to leave VDD enabled and it's up to upper layers
 806          * to turn it off. But for eg. i2c-dev access we need to turn it on/off
 807          * ourselves.
 808          */
 809         vdd = edp_panel_vdd_on(intel_dp);
 810
 811         /* dp aux is extremely sensitive to irq latency, hence request the
 812          * lowest possible wakeup latency and so prevent the cpu from going into
 813          * deep sleep states.
 814          */
 815         pm_qos_update_request(&dev_priv->pm_qos, 0);
 816
 817         intel_dp_check_edp(intel_dp);
 818
 819         /* Try to wait for any previous AUX channel activity */
 820         for (try = 0; try < 3; try++) {
 821                 status = I915_READ_NOTRACE(ch_ctl);
 822                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 823                         break;
 824                 msleep(1);
 825         }
 826
 827         if (try == 3) {
 828                 static u32 last_status = -1;
 829                 const u32 status = I915_READ(ch_ctl);
 830
 831                 if (status != last_status) {
 832                         WARN(1, "dp_aux_ch not started status 0x%08x\n",
 833                              status);
 834                         last_status = status;
 835                 }
 836
 837                 ret = -EBUSY;
 838                 goto out;
 839         }
 840
 841         /* Only 5 data registers! */
 842         if (WARN_ON(send_bytes > 20 || recv_size > 20)) {
 843                 ret = -E2BIG;
 844                 goto out;
 845         }
 846
 847         while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) {
 848                 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp,
 849                                                           has_aux_irq,
 850                                                           send_bytes,
 851                                                           aux_clock_divider);
 852
 853                 /* Must try at least 3 times according to DP spec */
 854                 for (try = 0; try < 5; try++) {
 855                         /* Load the send data into the aux channel data registers */
 856                         for (i = 0; i < send_bytes; i += 4)
 857                                 I915_WRITE(intel_dp->aux_ch_data_reg[i >> 2],
 858                                            intel_dp_pack_aux(send + i,
 859                                                              send_bytes - i));
 860
 861                         /* Send the command and wait for it to complete */
 862                         I915_WRITE(ch_ctl, send_ctl);
 863
 864                         status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 865
 866                         /* Clear done status and any errors */
 867                         I915_WRITE(ch_ctl,
 868                                    status |
 869                                    DP_AUX_CH_CTL_DONE |
 870                                    DP_AUX_CH_CTL_TIME_OUT_ERROR |
 871                                    DP_AUX_CH_CTL_RECEIVE_ERROR);
 872
 873                         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR)
 874                                 continue;
 875
 876                         /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2
 877                          *   400us delay required for errors and timeouts
 878                          *   Timeout errors from the HW already meet this
 879                          *   requirement so skip to next iteration
 880                          */
 881                         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 882                                 usleep_range(400, 500);
 883                                 continue;
 884                         }
 885                         if (status & DP_AUX_CH_CTL_DONE)
 886                                 goto done;
 887                 }
 888         }
 889
 890         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 891                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 892                 ret = -EBUSY;
 893                 goto out;
 894         }
 895
 896 done:
 897         /* Check for timeout or receive error.
 898          * Timeouts occur when the sink is not connected
 899          */
 900         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 901                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 902                 ret = -EIO;
 903                 goto out;
 904         }
 905
 906         /* Timeouts occur when the device isn't connected, so they're
 907          * "normal" -- don't fill the kernel log with these */
 908         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 909                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 910                 ret = -ETIMEDOUT;
 911                 goto out;
 912         }
 913
 914         /* Unload any bytes sent back from the other side */
 915         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 916                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 917
 918         /*
 919          * By BSpec: "Message sizes of 0 or >20 are not allowed."
 920          * We have no idea of what happened so we return -EBUSY so
 921          * drm layer takes care for the necessary retries.
 922          */
 923         if (recv_bytes == 0 || recv_bytes > 20) {
 924                 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n",
 925                               recv_bytes);
 926                 /*
 927                  * FIXME: This patch was created on top of a series that
 928                  * organize the retries at drm level. There EBUSY should
 929                  * also take care for 1ms wait before retrying.
 930                  * That aux retries re-org is still needed and after that is
 931                  * merged we remove this sleep from here.
 932                  */
 933                 usleep_range(1000, 1500);
 934                 ret = -EBUSY;
 935                 goto out;
 936         }
 937
 938         if (recv_bytes > recv_size)
 939                 recv_bytes = recv_size;
 940
 941         for (i = 0; i < recv_bytes; i += 4)
 942                 intel_dp_unpack_aux(I915_READ(intel_dp->aux_ch_data_reg[i >> 2]),
 943                                     recv + i, recv_bytes - i);
 944
 945         ret = recv_bytes;
 946 out:
 947         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 948
 949         if (vdd)
 950                 edp_panel_vdd_off(intel_dp, false);
 951
 952         pps_unlock(intel_dp);
 953
 954         return ret;
 955 }
 956
 957 #define BARE_ADDRESS_SIZE       3
 958 #define HEADER_SIZE             (BARE_ADDRESS_SIZE + 1)
 959 static ssize_t
 960 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg)
 961 {
 962         struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux);
 963         uint8_t txbuf[20], rxbuf[20];
 964         size_t txsize, rxsize;
 965         int ret;
 966
 967         txbuf[0] = (msg->request << 4) |
 968                 ((msg->address >> 16) & 0xf);
 969         txbuf[1] = (msg->address >> 8) & 0xff;
 970         txbuf[2] = msg->address & 0xff;
 971         txbuf[3] = msg->size - 1;
 972
 973         switch (msg->request & ~DP_AUX_I2C_MOT) {
 974         case DP_AUX_NATIVE_WRITE:
 975         case DP_AUX_I2C_WRITE:
 976         case DP_AUX_I2C_WRITE_STATUS_UPDATE:
 977                 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE;
 978                 rxsize = 2; /* 0 or 1 data bytes */
 979
 980                 if (WARN_ON(txsize > 20))
 981                         return -E2BIG;
 982
 983                 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size);
 984
 985                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
 986                 if (ret > 0) {
 987                         msg->reply = rxbuf[0] >> 4;
 988
 989                         if (ret > 1) {
 990                                 /* Number of bytes written in a short write. */
 991                                 ret = clamp_t(int, rxbuf[1], 0, msg->size);
 992                         } else {
 993                                 /* Return payload size. */
 994                                 ret = msg->size;
 995                         }
 996                 }
 997                 break;
 998
 999         case DP_AUX_NATIVE_READ:
1000         case DP_AUX_I2C_READ:
1001                 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE;
1002                 rxsize = msg->size + 1;
1003
1004                 if (WARN_ON(rxsize > 20))
1005                         return -E2BIG;
1006
1007                 ret = intel_dp_aux_ch(intel_dp, txbuf, txsize, rxbuf, rxsize);
1008                 if (ret > 0) {
1009                         msg->reply = rxbuf[0] >> 4;
1010                         /*
1011                          * Assume happy day, and copy the data. The caller is
1012                          * expected to check msg->reply before touching it.
1013                          *
1014                          * Return payload size.
1015                          */
1016                         ret--;
1017                         memcpy(msg->buffer, rxbuf + 1, ret);
1018                 }
1019                 break;
1020
1021         default:
1022                 ret = -EINVAL;
1023                 break;
1024         }
1025
1026         return ret;
1027 }
1028
1029 static i915_reg_t g4x_aux_ctl_reg(struct drm_i915_private *dev_priv,
1030                                        enum port port)
1031 {
1032         switch (port) {
1033         case PORT_B:
1034         case PORT_C:
1035         case PORT_D:
1036                 return DP_AUX_CH_CTL(port);
1037         default:
1038                 MISSING_CASE(port);
1039                 return DP_AUX_CH_CTL(PORT_B);
1040         }
1041 }
1042
1043 static i915_reg_t g4x_aux_data_reg(struct drm_i915_private *dev_priv,
1044                                         enum port port, int index)
1045 {
1046         switch (port) {
1047         case PORT_B:
1048         case PORT_C:
1049         case PORT_D:
1050                 return DP_AUX_CH_DATA(port, index);
1051         default:
1052                 MISSING_CASE(port);
1053                 return DP_AUX_CH_DATA(PORT_B, index);
1054         }
1055 }
1056
1057 static i915_reg_t ilk_aux_ctl_reg(struct drm_i915_private *dev_priv,
1058                                        enum port port)
1059 {
1060         switch (port) {
1061         case PORT_A:
1062                 return DP_AUX_CH_CTL(port);
1063         case PORT_B:
1064         case PORT_C:
1065         case PORT_D:
1066                 return PCH_DP_AUX_CH_CTL(port);
1067         default:
1068                 MISSING_CASE(port);
1069                 return DP_AUX_CH_CTL(PORT_A);
1070         }
1071 }
1072
1073 static i915_reg_t ilk_aux_data_reg(struct drm_i915_private *dev_priv,
1074                                         enum port port, int index)
1075 {
1076         switch (port) {
1077         case PORT_A:
1078                 return DP_AUX_CH_DATA(port, index);
1079         case PORT_B:
1080         case PORT_C:
1081         case PORT_D:
1082                 return PCH_DP_AUX_CH_DATA(port, index);
1083         default:
1084                 MISSING_CASE(port);
1085                 return DP_AUX_CH_DATA(PORT_A, index);
1086         }
1087 }
1088
1089 /*
1090  * On SKL we don't have Aux for port E so we rely
1091  * on VBT to set a proper alternate aux channel.
1092  */
1093 static enum port skl_porte_aux_port(struct drm_i915_private *dev_priv)
1094 {
1095         const struct ddi_vbt_port_info *info =
1096                 &dev_priv->vbt.ddi_port_info[PORT_E];
1097
1098         switch (info->alternate_aux_channel) {
1099         case DP_AUX_A:
1100                 return PORT_A;
1101         case DP_AUX_B:
1102                 return PORT_B;
1103         case DP_AUX_C:
1104                 return PORT_C;
1105         case DP_AUX_D:
1106                 return PORT_D;
1107         default:
1108                 MISSING_CASE(info->alternate_aux_channel);
1109                 return PORT_A;
1110         }
1111 }
1112
1113 static i915_reg_t skl_aux_ctl_reg(struct drm_i915_private *dev_priv,
1114                                        enum port port)
1115 {
1116         if (port == PORT_E)
1117                 port = skl_porte_aux_port(dev_priv);
1118
1119         switch (port) {
1120         case PORT_A:
1121         case PORT_B:
1122         case PORT_C:
1123         case PORT_D:
1124                 return DP_AUX_CH_CTL(port);
1125         default:
1126                 MISSING_CASE(port);
1127                 return DP_AUX_CH_CTL(PORT_A);
1128         }
1129 }
1130
1131 static i915_reg_t skl_aux_data_reg(struct drm_i915_private *dev_priv,
1132                                         enum port port, int index)
1133 {
1134         if (port == PORT_E)
1135                 port = skl_porte_aux_port(dev_priv);
1136
1137         switch (port) {
1138         case PORT_A:
1139         case PORT_B:
1140         case PORT_C:
1141         case PORT_D:
1142                 return DP_AUX_CH_DATA(port, index);
1143         default:
1144                 MISSING_CASE(port);
1145                 return DP_AUX_CH_DATA(PORT_A, index);
1146         }
1147 }
1148
1149 static i915_reg_t intel_aux_ctl_reg(struct drm_i915_private *dev_priv,
1150                                          enum port port)
1151 {
1152         if (INTEL_INFO(dev_priv)->gen >= 9)
1153                 return skl_aux_ctl_reg(dev_priv, port);
1154         else if (HAS_PCH_SPLIT(dev_priv))
1155                 return ilk_aux_ctl_reg(dev_priv, port);
1156         else
1157                 return g4x_aux_ctl_reg(dev_priv, port);
1158 }
1159
1160 static i915_reg_t intel_aux_data_reg(struct drm_i915_private *dev_priv,
1161                                           enum port port, int index)
1162 {
1163         if (INTEL_INFO(dev_priv)->gen >= 9)
1164                 return skl_aux_data_reg(dev_priv, port, index);
1165         else if (HAS_PCH_SPLIT(dev_priv))
1166                 return ilk_aux_data_reg(dev_priv, port, index);
1167         else
1168                 return g4x_aux_data_reg(dev_priv, port, index);
1169 }
1170
1171 static void intel_aux_reg_init(struct intel_dp *intel_dp)
1172 {
1173         struct drm_i915_private *dev_priv = to_i915(intel_dp_to_dev(intel_dp));
1174         enum port port = dp_to_dig_port(intel_dp)->port;
1175         int i;
1176
1177         intel_dp->aux_ch_ctl_reg = intel_aux_ctl_reg(dev_priv, port);
1178         for (i = 0; i < ARRAY_SIZE(intel_dp->aux_ch_data_reg); i++)
1179                 intel_dp->aux_ch_data_reg[i] = intel_aux_data_reg(dev_priv, port, i);
1180 }
1181
1182 static void
1183 intel_dp_aux_fini(struct intel_dp *intel_dp)
1184 {
1185         drm_dp_aux_unregister(&intel_dp->aux);
1186         kfree(intel_dp->aux.name);
1187 }
1188
1189 static int
1190 intel_dp_aux_init(struct intel_dp *intel_dp, struct intel_connector *connector)
1191 {
1192         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1193         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1194         enum port port = intel_dig_port->port;
1195         int ret;
1196
1197         intel_aux_reg_init(intel_dp);
1198
1199         intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", port_name(port));
1200         if (!intel_dp->aux.name)
1201                 return -ENOMEM;
1202
1203         intel_dp->aux.dev = dev->dev;
1204         intel_dp->aux.transfer = intel_dp_aux_transfer;
1205
1206         DRM_DEBUG_KMS("registering %s bus for %s\n",
1207                       intel_dp->aux.name,
1208                       connector->base.kdev->kobj.name);
1209
1210         ret = drm_dp_aux_register(&intel_dp->aux);
1211         if (ret < 0) {
1212                 DRM_ERROR("drm_dp_aux_register() for %s failed (%d)\n",
1213                           intel_dp->aux.name, ret);
1214                 kfree(intel_dp->aux.name);
1215                 return ret;
1216         }
1217
1218         ret = sysfs_create_link(&connector->base.kdev->kobj,
1219                                 &intel_dp->aux.ddc.dev.kobj,
1220                                 intel_dp->aux.ddc.dev.kobj.name);
1221         if (ret < 0) {
1222                 DRM_ERROR("sysfs_create_link() for %s failed (%d)\n",
1223                           intel_dp->aux.name, ret);
1224                 intel_dp_aux_fini(intel_dp);
1225                 return ret;
1226         }
1227
1228         return 0;
1229 }
1230
1231 static void
1232 intel_dp_connector_unregister(struct intel_connector *intel_connector)
1233 {
1234         struct intel_dp *intel_dp = intel_attached_dp(&intel_connector->base);
1235
1236         if (!intel_connector->mst_port)
1237                 sysfs_remove_link(&intel_connector->base.kdev->kobj,
1238                                   intel_dp->aux.ddc.dev.kobj.name);
1239         intel_connector_unregister(intel_connector);
1240 }
1241
1242 static void
1243 skl_edp_set_pll_config(struct intel_crtc_state *pipe_config)
1244 {
1245         u32 ctrl1;
1246
1247         memset(&pipe_config->dpll_hw_state, 0,
1248                sizeof(pipe_config->dpll_hw_state));
1249
1250         pipe_config->ddi_pll_sel = SKL_DPLL0;
1251         pipe_config->dpll_hw_state.cfgcr1 = 0;
1252         pipe_config->dpll_hw_state.cfgcr2 = 0;
1253
1254         ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
1255         switch (pipe_config->port_clock / 2) {
1256         case 81000:
1257                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
1258                                               SKL_DPLL0);
1259                 break;
1260         case 135000:
1261                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350,
1262                                               SKL_DPLL0);
1263                 break;
1264         case 270000:
1265                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700,
1266                                               SKL_DPLL0);
1267                 break;
1268         case 162000:
1269                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620,
1270                                               SKL_DPLL0);
1271                 break;
1272         /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
1273         results in CDCLK change. Need to handle the change of CDCLK by
1274         disabling pipes and re-enabling them */
1275         case 108000:
1276                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
1277                                               SKL_DPLL0);
1278                 break;
1279         case 216000:
1280                 ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
1281                                               SKL_DPLL0);
1282                 break;
1283
1284         }
1285         pipe_config->dpll_hw_state.ctrl1 = ctrl1;
1286 }
1287
1288 void
1289 hsw_dp_set_ddi_pll_sel(struct intel_crtc_state *pipe_config)
1290 {
1291         memset(&pipe_config->dpll_hw_state, 0,
1292                sizeof(pipe_config->dpll_hw_state));
1293
1294         switch (pipe_config->port_clock / 2) {
1295         case 81000:
1296                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
1297                 break;
1298         case 135000:
1299                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
1300                 break;
1301         case 270000:
1302                 pipe_config->ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
1303                 break;
1304         }
1305 }
1306
1307 static int
1308 intel_dp_sink_rates(struct intel_dp *intel_dp, const int **sink_rates)
1309 {
1310         if (intel_dp->num_sink_rates) {
1311                 *sink_rates = intel_dp->sink_rates;
1312                 return intel_dp->num_sink_rates;
1313         }
1314
1315         *sink_rates = default_rates;
1316
1317         return (intel_dp_max_link_bw(intel_dp) >> 3) + 1;
1318 }
1319
1320 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp)
1321 {
1322         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1323         struct drm_device *dev = dig_port->base.base.dev;
1324
1325         /* WaDisableHBR2:skl */
1326         if (IS_SKL_REVID(dev, 0, SKL_REVID_B0))
1327                 return false;
1328
1329         if ((IS_HASWELL(dev) && !IS_HSW_ULX(dev)) || IS_BROADWELL(dev) ||
1330             (INTEL_INFO(dev)->gen >= 9))
1331                 return true;
1332         else
1333                 return false;
1334 }
1335
1336 static int
1337 intel_dp_source_rates(struct intel_dp *intel_dp, const int **source_rates)
1338 {
1339         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1340         struct drm_device *dev = dig_port->base.base.dev;
1341         int size;
1342
1343         if (IS_BROXTON(dev)) {
1344                 *source_rates = bxt_rates;
1345                 size = ARRAY_SIZE(bxt_rates);
1346         } else if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
1347                 *source_rates = skl_rates;
1348                 size = ARRAY_SIZE(skl_rates);
1349         } else {
1350                 *source_rates = default_rates;
1351                 size = ARRAY_SIZE(default_rates);
1352         }
1353
1354         /* This depends on the fact that 5.4 is last value in the array */
1355         if (!intel_dp_source_supports_hbr2(intel_dp))
1356                 size--;
1357
1358         return size;
1359 }
1360
1361 static void
1362 intel_dp_set_clock(struct intel_encoder *encoder,
1363                    struct intel_crtc_state *pipe_config)
1364 {
1365         struct drm_device *dev = encoder->base.dev;
1366         const struct dp_link_dpll *divisor = NULL;
1367         int i, count = 0;
1368
1369         if (IS_G4X(dev)) {
1370                 divisor = gen4_dpll;
1371                 count = ARRAY_SIZE(gen4_dpll);
1372         } else if (HAS_PCH_SPLIT(dev)) {
1373                 divisor = pch_dpll;
1374                 count = ARRAY_SIZE(pch_dpll);
1375         } else if (IS_CHERRYVIEW(dev)) {
1376                 divisor = chv_dpll;
1377                 count = ARRAY_SIZE(chv_dpll);
1378         } else if (IS_VALLEYVIEW(dev)) {
1379                 divisor = vlv_dpll;
1380                 count = ARRAY_SIZE(vlv_dpll);
1381         }
1382
1383         if (divisor && count) {
1384                 for (i = 0; i < count; i++) {
1385                         if (pipe_config->port_clock == divisor[i].clock) {
1386                                 pipe_config->dpll = divisor[i].dpll;
1387                                 pipe_config->clock_set = true;
1388                                 break;
1389                         }
1390                 }
1391         }
1392 }
1393
1394 static int intersect_rates(const int *source_rates, int source_len,
1395                            const int *sink_rates, int sink_len,
1396                            int *common_rates)
1397 {
1398         int i = 0, j = 0, k = 0;
1399
1400         while (i < source_len && j < sink_len) {
1401                 if (source_rates[i] == sink_rates[j]) {
1402                         if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES))
1403                                 return k;
1404                         common_rates[k] = source_rates[i];
1405                         ++k;
1406                         ++i;
1407                         ++j;
1408                 } else if (source_rates[i] < sink_rates[j]) {
1409                         ++i;
1410                 } else {
1411                         ++j;
1412                 }
1413         }
1414         return k;
1415 }
1416
1417 static int intel_dp_common_rates(struct intel_dp *intel_dp,
1418                                  int *common_rates)
1419 {
1420         const int *source_rates, *sink_rates;
1421         int source_len, sink_len;
1422
1423         sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1424         source_len = intel_dp_source_rates(intel_dp, &source_rates);
1425
1426         return intersect_rates(source_rates, source_len,
1427                                sink_rates, sink_len,
1428                                common_rates);
1429 }
1430
1431 static void snprintf_int_array(char *str, size_t len,
1432                                const int *array, int nelem)
1433 {
1434         int i;
1435
1436         str[0] = '\0';
1437
1438         for (i = 0; i < nelem; i++) {
1439                 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]);
1440                 if (r >= len)
1441                         return;
1442                 str += r;
1443                 len -= r;
1444         }
1445 }
1446
1447 static void intel_dp_print_rates(struct intel_dp *intel_dp)
1448 {
1449         const int *source_rates, *sink_rates;
1450         int source_len, sink_len, common_len;
1451         int common_rates[DP_MAX_SUPPORTED_RATES];
1452         char str[128]; /* FIXME: too big for stack? */
1453
1454         if ((drm_debug & DRM_UT_KMS) == 0)
1455                 return;
1456
1457         source_len = intel_dp_source_rates(intel_dp, &source_rates);
1458         snprintf_int_array(str, sizeof(str), source_rates, source_len);
1459         DRM_DEBUG_KMS("source rates: %s\n", str);
1460
1461         sink_len = intel_dp_sink_rates(intel_dp, &sink_rates);
1462         snprintf_int_array(str, sizeof(str), sink_rates, sink_len);
1463         DRM_DEBUG_KMS("sink rates: %s\n", str);
1464
1465         common_len = intel_dp_common_rates(intel_dp, common_rates);
1466         snprintf_int_array(str, sizeof(str), common_rates, common_len);
1467         DRM_DEBUG_KMS("common rates: %s\n", str);
1468 }
1469
1470 static int rate_to_index(int find, const int *rates)
1471 {
1472         int i = 0;
1473
1474         for (i = 0; i < DP_MAX_SUPPORTED_RATES; ++i)
1475                 if (find == rates[i])
1476                         break;
1477
1478         return i;
1479 }
1480
1481 int
1482 intel_dp_max_link_rate(struct intel_dp *intel_dp)
1483 {
1484         int rates[DP_MAX_SUPPORTED_RATES] = {};
1485         int len;
1486
1487         len = intel_dp_common_rates(intel_dp, rates);
1488         if (WARN_ON(len <= 0))
1489                 return 162000;
1490
1491         return rates[rate_to_index(0, rates) - 1];
1492 }
1493
1494 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate)
1495 {
1496         return rate_to_index(rate, intel_dp->sink_rates);
1497 }
1498
1499 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock,
1500                            uint8_t *link_bw, uint8_t *rate_select)
1501 {
1502         if (intel_dp->num_sink_rates) {
1503                 *link_bw = 0;
1504                 *rate_select =
1505                         intel_dp_rate_select(intel_dp, port_clock);
1506         } else {
1507                 *link_bw = drm_dp_link_rate_to_bw_code(port_clock);
1508                 *rate_select = 0;
1509         }
1510 }
1511
1512 bool
1513 intel_dp_compute_config(struct intel_encoder *encoder,
1514                         struct intel_crtc_state *pipe_config)
1515 {
1516         struct drm_device *dev = encoder->base.dev;
1517         struct drm_i915_private *dev_priv = dev->dev_private;
1518         struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
1519         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1520         enum port port = dp_to_dig_port(intel_dp)->port;
1521         struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
1522         struct intel_connector *intel_connector = intel_dp->attached_connector;
1523         int lane_count, clock;
1524         int min_lane_count = 1;
1525         int max_lane_count = intel_dp_max_lane_count(intel_dp);
1526         /* Conveniently, the link BW constants become indices with a shift...*/
1527         int min_clock = 0;
1528         int max_clock;
1529         int bpp, mode_rate;
1530         int link_avail, link_clock;
1531         int common_rates[DP_MAX_SUPPORTED_RATES] = {};
1532         int common_len;
1533         uint8_t link_bw, rate_select;
1534
1535         common_len = intel_dp_common_rates(intel_dp, common_rates);
1536
1537         /* No common link rates between source and sink */
1538         WARN_ON(common_len <= 0);
1539
1540         max_clock = common_len - 1;
1541
1542         if (HAS_PCH_SPLIT(dev) && !HAS_DDI(dev) && port != PORT_A)
1543                 pipe_config->has_pch_encoder = true;
1544
1545         pipe_config->has_dp_encoder = true;
1546         pipe_config->has_drrs = false;
1547         pipe_config->has_audio = intel_dp->has_audio && port != PORT_A;
1548
1549         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
1550                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
1551                                        adjusted_mode);
1552
1553                 if (INTEL_INFO(dev)->gen >= 9) {
1554                         int ret;
1555                         ret = skl_update_scaler_crtc(pipe_config);
1556                         if (ret)
1557                                 return ret;
1558                 }
1559
1560                 if (HAS_GMCH_DISPLAY(dev))
1561                         intel_gmch_panel_fitting(intel_crtc, pipe_config,
1562                                                  intel_connector->panel.fitting_mode);
1563                 else
1564                         intel_pch_panel_fitting(intel_crtc, pipe_config,
1565                                                 intel_connector->panel.fitting_mode);
1566         }
1567
1568         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
1569                 return false;
1570
1571         DRM_DEBUG_KMS("DP link computation with max lane count %i "
1572                       "max bw %d pixel clock %iKHz\n",
1573                       max_lane_count, common_rates[max_clock],
1574                       adjusted_mode->crtc_clock);
1575
1576         /* Walk through all bpp values. Luckily they're all nicely spaced with 2
1577          * bpc in between. */
1578         bpp = pipe_config->pipe_bpp;
1579         if (is_edp(intel_dp)) {
1580
1581                 /* Get bpp from vbt only for panels that dont have bpp in edid */
1582                 if (intel_connector->base.display_info.bpc == 0 &&
1583                         (dev_priv->vbt.edp_bpp && dev_priv->vbt.edp_bpp < bpp)) {
1584                         DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n",
1585                                       dev_priv->vbt.edp_bpp);
1586                         bpp = dev_priv->vbt.edp_bpp;
1587                 }
1588
1589                 /*
1590                  * Use the maximum clock and number of lanes the eDP panel
1591                  * advertizes being capable of. The panels are generally
1592                  * designed to support only a single clock and lane
1593                  * configuration, and typically these values correspond to the
1594                  * native resolution of the panel.
1595                  */
1596                 min_lane_count = max_lane_count;
1597                 min_clock = max_clock;
1598         }
1599
1600         for (; bpp >= 6*3; bpp -= 2*3) {
1601                 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock,
1602                                                    bpp);
1603
1604                 for (clock = min_clock; clock <= max_clock; clock++) {
1605                         for (lane_count = min_lane_count;
1606                                 lane_count <= max_lane_count;
1607                                 lane_count <<= 1) {
1608
1609                                 link_clock = common_rates[clock];
1610                                 link_avail = intel_dp_max_data_rate(link_clock,
1611                                                                     lane_count);
1612
1613                                 if (mode_rate <= link_avail) {
1614                                         goto found;
1615                                 }
1616                         }
1617                 }
1618         }
1619
1620         return false;
1621
1622 found:
1623         if (intel_dp->color_range_auto) {
1624                 /*
1625                  * See:
1626                  * CEA-861-E - 5.1 Default Encoding Parameters
1627                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
1628                  */
1629                 pipe_config->limited_color_range =
1630                         bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1;
1631         } else {
1632                 pipe_config->limited_color_range =
1633                         intel_dp->limited_color_range;
1634         }
1635
1636         pipe_config->lane_count = lane_count;
1637
1638         pipe_config->pipe_bpp = bpp;
1639         pipe_config->port_clock = common_rates[clock];
1640
1641         intel_dp_compute_rate(intel_dp, pipe_config->port_clock,
1642                               &link_bw, &rate_select);
1643
1644         DRM_DEBUG_KMS("DP link bw %02x rate select %02x lane count %d clock %d bpp %d\n",
1645                       link_bw, rate_select, pipe_config->lane_count,
1646                       pipe_config->port_clock, bpp);
1647         DRM_DEBUG_KMS("DP link bw required %i available %i\n",
1648                       mode_rate, link_avail);
1649
1650         intel_link_compute_m_n(bpp, lane_count,
1651                                adjusted_mode->crtc_clock,
1652                                pipe_config->port_clock,
1653                                &pipe_config->dp_m_n);
1654
1655         if (intel_connector->panel.downclock_mode != NULL &&
1656                 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) {
1657                         pipe_config->has_drrs = true;
1658                         intel_link_compute_m_n(bpp, lane_count,
1659                                 intel_connector->panel.downclock_mode->clock,
1660                                 pipe_config->port_clock,
1661                                 &pipe_config->dp_m2_n2);
1662         }
1663
1664         if ((IS_SKYLAKE(dev)  || IS_KABYLAKE(dev)) && is_edp(intel_dp))
1665                 skl_edp_set_pll_config(pipe_config);
1666         else if (IS_BROXTON(dev))
1667                 /* handled in ddi */;
1668         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
1669                 hsw_dp_set_ddi_pll_sel(pipe_config);
1670         else
1671                 intel_dp_set_clock(encoder, pipe_config);
1672
1673         return true;
1674 }
1675
1676 void intel_dp_set_link_params(struct intel_dp *intel_dp,
1677                               const struct intel_crtc_state *pipe_config)
1678 {
1679         intel_dp->link_rate = pipe_config->port_clock;
1680         intel_dp->lane_count = pipe_config->lane_count;
1681 }
1682
1683 static void intel_dp_prepare(struct intel_encoder *encoder)
1684 {
1685         struct drm_device *dev = encoder->base.dev;
1686         struct drm_i915_private *dev_priv = dev->dev_private;
1687         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1688         enum port port = dp_to_dig_port(intel_dp)->port;
1689         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
1690         const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
1691
1692         intel_dp_set_link_params(intel_dp, crtc->config);
1693
1694         /*
1695          * There are four kinds of DP registers:
1696          *
1697          *      IBX PCH
1698          *      SNB CPU
1699          *      IVB CPU
1700          *      CPT PCH
1701          *
1702          * IBX PCH and CPU are the same for almost everything,
1703          * except that the CPU DP PLL is configured in this
1704          * register
1705          *
1706          * CPT PCH is quite different, having many bits moved
1707          * to the TRANS_DP_CTL register instead. That
1708          * configuration happens (oddly) in ironlake_pch_enable
1709          */
1710
1711         /* Preserve the BIOS-computed detected bit. This is
1712          * supposed to be read-only.
1713          */
1714         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
1715
1716         /* Handle DP bits in common between all three register formats */
1717         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
1718         intel_dp->DP |= DP_PORT_WIDTH(crtc->config->lane_count);
1719
1720         /* Split out the IBX/CPU vs CPT settings */
1721
1722         if (IS_GEN7(dev) && port == PORT_A) {
1723                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1724                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1725                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1726                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1727                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1728
1729                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1730                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1731
1732                 intel_dp->DP |= crtc->pipe << 29;
1733         } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
1734                 u32 trans_dp;
1735
1736                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1737
1738                 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
1739                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1740                         trans_dp |= TRANS_DP_ENH_FRAMING;
1741                 else
1742                         trans_dp &= ~TRANS_DP_ENH_FRAMING;
1743                 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp);
1744         } else {
1745                 if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
1746                     !IS_CHERRYVIEW(dev) && crtc->config->limited_color_range)
1747                         intel_dp->DP |= DP_COLOR_RANGE_16_235;
1748
1749                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
1750                         intel_dp->DP |= DP_SYNC_HS_HIGH;
1751                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
1752                         intel_dp->DP |= DP_SYNC_VS_HIGH;
1753                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
1754
1755                 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
1756                         intel_dp->DP |= DP_ENHANCED_FRAMING;
1757
1758                 if (IS_CHERRYVIEW(dev))
1759                         intel_dp->DP |= DP_PIPE_SELECT_CHV(crtc->pipe);
1760                 else if (crtc->pipe == PIPE_B)
1761                         intel_dp->DP |= DP_PIPEB_SELECT;
1762         }
1763 }
1764
1765 #define IDLE_ON_MASK            (PP_ON | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1766 #define IDLE_ON_VALUE           (PP_ON | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1767
1768 #define IDLE_OFF_MASK           (PP_ON | PP_SEQUENCE_MASK | 0                     | 0)
1769 #define IDLE_OFF_VALUE          (0     | PP_SEQUENCE_NONE | 0                     | 0)
1770
1771 #define IDLE_CYCLE_MASK         (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1772 #define IDLE_CYCLE_VALUE        (0     | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1773
1774 static void wait_panel_status(struct intel_dp *intel_dp,
1775                                        u32 mask,
1776                                        u32 value)
1777 {
1778         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1779         struct drm_i915_private *dev_priv = dev->dev_private;
1780         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1781
1782         lockdep_assert_held(&dev_priv->pps_mutex);
1783
1784         pp_stat_reg = _pp_stat_reg(intel_dp);
1785         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1786
1787         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1788                         mask, value,
1789                         I915_READ(pp_stat_reg),
1790                         I915_READ(pp_ctrl_reg));
1791
1792         if (_wait_for((I915_READ(pp_stat_reg) & mask) == value, 5000, 10)) {
1793                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1794                                 I915_READ(pp_stat_reg),
1795                                 I915_READ(pp_ctrl_reg));
1796         }
1797
1798         DRM_DEBUG_KMS("Wait complete\n");
1799 }
1800
1801 static void wait_panel_on(struct intel_dp *intel_dp)
1802 {
1803         DRM_DEBUG_KMS("Wait for panel power on\n");
1804         wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1805 }
1806
1807 static void wait_panel_off(struct intel_dp *intel_dp)
1808 {
1809         DRM_DEBUG_KMS("Wait for panel power off time\n");
1810         wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1811 }
1812
1813 static void wait_panel_power_cycle(struct intel_dp *intel_dp)
1814 {
1815         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1816
1817         /* When we disable the VDD override bit last we have to do the manual
1818          * wait. */
1819         wait_remaining_ms_from_jiffies(intel_dp->last_power_cycle,
1820                                        intel_dp->panel_power_cycle_delay);
1821
1822         wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1823 }
1824
1825 static void wait_backlight_on(struct intel_dp *intel_dp)
1826 {
1827         wait_remaining_ms_from_jiffies(intel_dp->last_power_on,
1828                                        intel_dp->backlight_on_delay);
1829 }
1830
1831 static void edp_wait_backlight_off(struct intel_dp *intel_dp)
1832 {
1833         wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off,
1834                                        intel_dp->backlight_off_delay);
1835 }
1836
1837 /* Read the current pp_control value, unlocking the register if it
1838  * is locked
1839  */
1840
1841 static  u32 ironlake_get_pp_control(struct intel_dp *intel_dp)
1842 {
1843         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1844         struct drm_i915_private *dev_priv = dev->dev_private;
1845         u32 control;
1846
1847         lockdep_assert_held(&dev_priv->pps_mutex);
1848
1849         control = I915_READ(_pp_ctrl_reg(intel_dp));
1850         if (!IS_BROXTON(dev)) {
1851                 control &= ~PANEL_UNLOCK_MASK;
1852                 control |= PANEL_UNLOCK_REGS;
1853         }
1854         return control;
1855 }
1856
1857 /*
1858  * Must be paired with edp_panel_vdd_off().
1859  * Must hold pps_mutex around the whole on/off sequence.
1860  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
1861  */
1862 static bool edp_panel_vdd_on(struct intel_dp *intel_dp)
1863 {
1864         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1865         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1866         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1867         struct drm_i915_private *dev_priv = dev->dev_private;
1868         enum intel_display_power_domain power_domain;
1869         u32 pp;
1870         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1871         bool need_to_disable = !intel_dp->want_panel_vdd;
1872
1873         lockdep_assert_held(&dev_priv->pps_mutex);
1874
1875         if (!is_edp(intel_dp))
1876                 return false;
1877
1878         cancel_delayed_work(&intel_dp->panel_vdd_work);
1879         intel_dp->want_panel_vdd = true;
1880
1881         if (edp_have_panel_vdd(intel_dp))
1882                 return need_to_disable;
1883
1884         power_domain = intel_display_port_aux_power_domain(intel_encoder);
1885         intel_display_power_get(dev_priv, power_domain);
1886
1887         DRM_DEBUG_KMS("Turning eDP port %c VDD on\n",
1888                       port_name(intel_dig_port->port));
1889
1890         if (!edp_have_panel_power(intel_dp))
1891                 wait_panel_power_cycle(intel_dp);
1892
1893         pp = ironlake_get_pp_control(intel_dp);
1894         pp |= EDP_FORCE_VDD;
1895
1896         pp_stat_reg = _pp_stat_reg(intel_dp);
1897         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1898
1899         I915_WRITE(pp_ctrl_reg, pp);
1900         POSTING_READ(pp_ctrl_reg);
1901         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1902                         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1903         /*
1904          * If the panel wasn't on, delay before accessing aux channel
1905          */
1906         if (!edp_have_panel_power(intel_dp)) {
1907                 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n",
1908                               port_name(intel_dig_port->port));
1909                 msleep(intel_dp->panel_power_up_delay);
1910         }
1911
1912         return need_to_disable;
1913 }
1914
1915 /*
1916  * Must be paired with intel_edp_panel_vdd_off() or
1917  * intel_edp_panel_off().
1918  * Nested calls to these functions are not allowed since
1919  * we drop the lock. Caller must use some higher level
1920  * locking to prevent nested calls from other threads.
1921  */
1922 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp)
1923 {
1924         bool vdd;
1925
1926         if (!is_edp(intel_dp))
1927                 return;
1928
1929         pps_lock(intel_dp);
1930         vdd = edp_panel_vdd_on(intel_dp);
1931         pps_unlock(intel_dp);
1932
1933         I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n",
1934              port_name(dp_to_dig_port(intel_dp)->port));
1935 }
1936
1937 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp)
1938 {
1939         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1940         struct drm_i915_private *dev_priv = dev->dev_private;
1941         struct intel_digital_port *intel_dig_port =
1942                 dp_to_dig_port(intel_dp);
1943         struct intel_encoder *intel_encoder = &intel_dig_port->base;
1944         enum intel_display_power_domain power_domain;
1945         u32 pp;
1946         i915_reg_t pp_stat_reg, pp_ctrl_reg;
1947
1948         lockdep_assert_held(&dev_priv->pps_mutex);
1949
1950         WARN_ON(intel_dp->want_panel_vdd);
1951
1952         if (!edp_have_panel_vdd(intel_dp))
1953                 return;
1954
1955         DRM_DEBUG_KMS("Turning eDP port %c VDD off\n",
1956                       port_name(intel_dig_port->port));
1957
1958         pp = ironlake_get_pp_control(intel_dp);
1959         pp &= ~EDP_FORCE_VDD;
1960
1961         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
1962         pp_stat_reg = _pp_stat_reg(intel_dp);
1963
1964         I915_WRITE(pp_ctrl_reg, pp);
1965         POSTING_READ(pp_ctrl_reg);
1966
1967         /* Make sure sequencer is idle before allowing subsequent activity */
1968         DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n",
1969         I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg));
1970
1971         if ((pp & POWER_TARGET_ON) == 0)
1972                 intel_dp->last_power_cycle = jiffies;
1973
1974         power_domain = intel_display_port_aux_power_domain(intel_encoder);
1975         intel_display_power_put(dev_priv, power_domain);
1976 }
1977
1978 static void edp_panel_vdd_work(struct work_struct *__work)
1979 {
1980         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1981                                                  struct intel_dp, panel_vdd_work);
1982
1983         pps_lock(intel_dp);
1984         if (!intel_dp->want_panel_vdd)
1985                 edp_panel_vdd_off_sync(intel_dp);
1986         pps_unlock(intel_dp);
1987 }
1988
1989 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp)
1990 {
1991         unsigned long delay;
1992
1993         /*
1994          * Queue the timer to fire a long time from now (relative to the power
1995          * down delay) to keep the panel power up across a sequence of
1996          * operations.
1997          */
1998         delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5);
1999         schedule_delayed_work(&intel_dp->panel_vdd_work, delay);
2000 }
2001
2002 /*
2003  * Must be paired with edp_panel_vdd_on().
2004  * Must hold pps_mutex around the whole on/off sequence.
2005  * Can be nested with intel_edp_panel_vdd_{on,off}() calls.
2006  */
2007 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
2008 {
2009         struct drm_i915_private *dev_priv =
2010                 intel_dp_to_dev(intel_dp)->dev_private;
2011
2012         lockdep_assert_held(&dev_priv->pps_mutex);
2013
2014         if (!is_edp(intel_dp))
2015                 return;
2016
2017         I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on",
2018              port_name(dp_to_dig_port(intel_dp)->port));
2019
2020         intel_dp->want_panel_vdd = false;
2021
2022         if (sync)
2023                 edp_panel_vdd_off_sync(intel_dp);
2024         else
2025                 edp_panel_vdd_schedule_off(intel_dp);
2026 }
2027
2028 static void edp_panel_on(struct intel_dp *intel_dp)
2029 {
2030         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2031         struct drm_i915_private *dev_priv = dev->dev_private;
2032         u32 pp;
2033         i915_reg_t pp_ctrl_reg;
2034
2035         lockdep_assert_held(&dev_priv->pps_mutex);
2036
2037         if (!is_edp(intel_dp))
2038                 return;
2039
2040         DRM_DEBUG_KMS("Turn eDP port %c panel power on\n",
2041                       port_name(dp_to_dig_port(intel_dp)->port));
2042
2043         if (WARN(edp_have_panel_power(intel_dp),
2044                  "eDP port %c panel power already on\n",
2045                  port_name(dp_to_dig_port(intel_dp)->port)))
2046                 return;
2047
2048         wait_panel_power_cycle(intel_dp);
2049
2050         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2051         pp = ironlake_get_pp_control(intel_dp);
2052         if (IS_GEN5(dev)) {
2053                 /* ILK workaround: disable reset around power sequence */
2054                 pp &= ~PANEL_POWER_RESET;
2055                 I915_WRITE(pp_ctrl_reg, pp);
2056                 POSTING_READ(pp_ctrl_reg);
2057         }
2058
2059         pp |= POWER_TARGET_ON;
2060         if (!IS_GEN5(dev))
2061                 pp |= PANEL_POWER_RESET;
2062
2063         I915_WRITE(pp_ctrl_reg, pp);
2064         POSTING_READ(pp_ctrl_reg);
2065
2066         wait_panel_on(intel_dp);
2067         intel_dp->last_power_on = jiffies;
2068
2069         if (IS_GEN5(dev)) {
2070                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
2071                 I915_WRITE(pp_ctrl_reg, pp);
2072                 POSTING_READ(pp_ctrl_reg);
2073         }
2074 }
2075
2076 void intel_edp_panel_on(struct intel_dp *intel_dp)
2077 {
2078         if (!is_edp(intel_dp))
2079                 return;
2080
2081         pps_lock(intel_dp);
2082         edp_panel_on(intel_dp);
2083         pps_unlock(intel_dp);
2084 }
2085
2086
2087 static void edp_panel_off(struct intel_dp *intel_dp)
2088 {
2089         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2090         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2091         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2092         struct drm_i915_private *dev_priv = dev->dev_private;
2093         enum intel_display_power_domain power_domain;
2094         u32 pp;
2095         i915_reg_t pp_ctrl_reg;
2096
2097         lockdep_assert_held(&dev_priv->pps_mutex);
2098
2099         if (!is_edp(intel_dp))
2100                 return;
2101
2102         DRM_DEBUG_KMS("Turn eDP port %c panel power off\n",
2103                       port_name(dp_to_dig_port(intel_dp)->port));
2104
2105         WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n",
2106              port_name(dp_to_dig_port(intel_dp)->port));
2107
2108         pp = ironlake_get_pp_control(intel_dp);
2109         /* We need to switch off panel power _and_ force vdd, for otherwise some
2110          * panels get very unhappy and cease to work. */
2111         pp &= ~(POWER_TARGET_ON | PANEL_POWER_RESET | EDP_FORCE_VDD |
2112                 EDP_BLC_ENABLE);
2113
2114         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2115
2116         intel_dp->want_panel_vdd = false;
2117
2118         I915_WRITE(pp_ctrl_reg, pp);
2119         POSTING_READ(pp_ctrl_reg);
2120
2121         intel_dp->last_power_cycle = jiffies;
2122         wait_panel_off(intel_dp);
2123
2124         /* We got a reference when we enabled the VDD. */
2125         power_domain = intel_display_port_aux_power_domain(intel_encoder);
2126         intel_display_power_put(dev_priv, power_domain);
2127 }
2128
2129 void intel_edp_panel_off(struct intel_dp *intel_dp)
2130 {
2131         if (!is_edp(intel_dp))
2132                 return;
2133
2134         pps_lock(intel_dp);
2135         edp_panel_off(intel_dp);
2136         pps_unlock(intel_dp);
2137 }
2138
2139 /* Enable backlight in the panel power control. */
2140 static void _intel_edp_backlight_on(struct intel_dp *intel_dp)
2141 {
2142         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2143         struct drm_device *dev = intel_dig_port->base.base.dev;
2144         struct drm_i915_private *dev_priv = dev->dev_private;
2145         u32 pp;
2146         i915_reg_t pp_ctrl_reg;
2147
2148         /*
2149          * If we enable the backlight right away following a panel power
2150          * on, we may see slight flicker as the panel syncs with the eDP
2151          * link.  So delay a bit to make sure the image is solid before
2152          * allowing it to appear.
2153          */
2154         wait_backlight_on(intel_dp);
2155
2156         pps_lock(intel_dp);
2157
2158         pp = ironlake_get_pp_control(intel_dp);
2159         pp |= EDP_BLC_ENABLE;
2160
2161         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2162
2163         I915_WRITE(pp_ctrl_reg, pp);
2164         POSTING_READ(pp_ctrl_reg);
2165
2166         pps_unlock(intel_dp);
2167 }
2168
2169 /* Enable backlight PWM and backlight PP control. */
2170 void intel_edp_backlight_on(struct intel_dp *intel_dp)
2171 {
2172         if (!is_edp(intel_dp))
2173                 return;
2174
2175         DRM_DEBUG_KMS("\n");
2176
2177         intel_panel_enable_backlight(intel_dp->attached_connector);
2178         _intel_edp_backlight_on(intel_dp);
2179 }
2180
2181 /* Disable backlight in the panel power control. */
2182 static void _intel_edp_backlight_off(struct intel_dp *intel_dp)
2183 {
2184         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2185         struct drm_i915_private *dev_priv = dev->dev_private;
2186         u32 pp;
2187         i915_reg_t pp_ctrl_reg;
2188
2189         if (!is_edp(intel_dp))
2190                 return;
2191
2192         pps_lock(intel_dp);
2193
2194         pp = ironlake_get_pp_control(intel_dp);
2195         pp &= ~EDP_BLC_ENABLE;
2196
2197         pp_ctrl_reg = _pp_ctrl_reg(intel_dp);
2198
2199         I915_WRITE(pp_ctrl_reg, pp);
2200         POSTING_READ(pp_ctrl_reg);
2201
2202         pps_unlock(intel_dp);
2203
2204         intel_dp->last_backlight_off = jiffies;
2205         edp_wait_backlight_off(intel_dp);
2206 }
2207
2208 /* Disable backlight PP control and backlight PWM. */
2209 void intel_edp_backlight_off(struct intel_dp *intel_dp)
2210 {
2211         if (!is_edp(intel_dp))
2212                 return;
2213
2214         DRM_DEBUG_KMS("\n");
2215
2216         _intel_edp_backlight_off(intel_dp);
2217         intel_panel_disable_backlight(intel_dp->attached_connector);
2218 }
2219
2220 /*
2221  * Hook for controlling the panel power control backlight through the bl_power
2222  * sysfs attribute. Take care to handle multiple calls.
2223  */
2224 static void intel_edp_backlight_power(struct intel_connector *connector,
2225                                       bool enable)
2226 {
2227         struct intel_dp *intel_dp = intel_attached_dp(&connector->base);
2228         bool is_enabled;
2229
2230         pps_lock(intel_dp);
2231         is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE;
2232         pps_unlock(intel_dp);
2233
2234         if (is_enabled == enable)
2235                 return;
2236
2237         DRM_DEBUG_KMS("panel power control backlight %s\n",
2238                       enable ? "enable" : "disable");
2239
2240         if (enable)
2241                 _intel_edp_backlight_on(intel_dp);
2242         else
2243                 _intel_edp_backlight_off(intel_dp);
2244 }
2245
2246 static const char *state_string(bool enabled)
2247 {
2248         return enabled ? "on" : "off";
2249 }
2250
2251 static void assert_dp_port(struct intel_dp *intel_dp, bool state)
2252 {
2253         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
2254         struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev);
2255         bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN;
2256
2257         I915_STATE_WARN(cur_state != state,
2258                         "DP port %c state assertion failure (expected %s, current %s)\n",
2259                         port_name(dig_port->port),
2260                         state_string(state), state_string(cur_state));
2261 }
2262 #define assert_dp_port_disabled(d) assert_dp_port((d), false)
2263
2264 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state)
2265 {
2266         bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE;
2267
2268         I915_STATE_WARN(cur_state != state,
2269                         "eDP PLL state assertion failure (expected %s, current %s)\n",
2270                         state_string(state), state_string(cur_state));
2271 }
2272 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true)
2273 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false)
2274
2275 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
2276 {
2277         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2278         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2279         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2280
2281         assert_pipe_disabled(dev_priv, crtc->pipe);
2282         assert_dp_port_disabled(intel_dp);
2283         assert_edp_pll_disabled(dev_priv);
2284
2285         DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n",
2286                       crtc->config->port_clock);
2287
2288         intel_dp->DP &= ~DP_PLL_FREQ_MASK;
2289
2290         if (crtc->config->port_clock == 162000)
2291                 intel_dp->DP |= DP_PLL_FREQ_162MHZ;
2292         else
2293                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
2294
2295         I915_WRITE(DP_A, intel_dp->DP);
2296         POSTING_READ(DP_A);
2297         udelay(500);
2298
2299         intel_dp->DP |= DP_PLL_ENABLE;
2300
2301         I915_WRITE(DP_A, intel_dp->DP);
2302         POSTING_READ(DP_A);
2303         udelay(200);
2304 }
2305
2306 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
2307 {
2308         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2309         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
2310         struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2311
2312         assert_pipe_disabled(dev_priv, crtc->pipe);
2313         assert_dp_port_disabled(intel_dp);
2314         assert_edp_pll_enabled(dev_priv);
2315
2316         DRM_DEBUG_KMS("disabling eDP PLL\n");
2317
2318         intel_dp->DP &= ~DP_PLL_ENABLE;
2319
2320         I915_WRITE(DP_A, intel_dp->DP);
2321         POSTING_READ(DP_A);
2322         udelay(200);
2323 }
2324
2325 /* If the sink supports it, try to set the power state appropriately */
2326 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
2327 {
2328         int ret, i;
2329
2330         /* Should have a valid DPCD by this point */
2331         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
2332                 return;
2333
2334         if (mode != DRM_MODE_DPMS_ON) {
2335                 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2336                                          DP_SET_POWER_D3);
2337         } else {
2338                 /*
2339                  * When turning on, we need to retry for 1ms to give the sink
2340                  * time to wake up.
2341                  */
2342                 for (i = 0; i < 3; i++) {
2343                         ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
2344                                                  DP_SET_POWER_D0);
2345                         if (ret == 1)
2346                                 break;
2347                         msleep(1);
2348                 }
2349         }
2350
2351         if (ret != 1)
2352                 DRM_DEBUG_KMS("failed to %s sink power state\n",
2353                               mode == DRM_MODE_DPMS_ON ? "enable" : "disable");
2354 }
2355
2356 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
2357                                   enum pipe *pipe)
2358 {
2359         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2360         enum port port = dp_to_dig_port(intel_dp)->port;
2361         struct drm_device *dev = encoder->base.dev;
2362         struct drm_i915_private *dev_priv = dev->dev_private;
2363         enum intel_display_power_domain power_domain;
2364         u32 tmp;
2365
2366         power_domain = intel_display_port_power_domain(encoder);
2367         if (!intel_display_power_is_enabled(dev_priv, power_domain))
2368                 return false;
2369
2370         tmp = I915_READ(intel_dp->output_reg);
2371
2372         if (!(tmp & DP_PORT_EN))
2373                 return false;
2374
2375         if (IS_GEN7(dev) && port == PORT_A) {
2376                 *pipe = PORT_TO_PIPE_CPT(tmp);
2377         } else if (HAS_PCH_CPT(dev) && port != PORT_A) {
2378                 enum pipe p;
2379
2380                 for_each_pipe(dev_priv, p) {
2381                         u32 trans_dp = I915_READ(TRANS_DP_CTL(p));
2382                         if (TRANS_DP_PIPE_TO_PORT(trans_dp) == port) {
2383                                 *pipe = p;
2384                                 return true;
2385                         }
2386                 }
2387
2388                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
2389                               i915_mmio_reg_offset(intel_dp->output_reg));
2390         } else if (IS_CHERRYVIEW(dev)) {
2391                 *pipe = DP_PORT_TO_PIPE_CHV(tmp);
2392         } else {
2393                 *pipe = PORT_TO_PIPE(tmp);
2394         }
2395
2396         return true;
2397 }
2398
2399 static void intel_dp_get_config(struct intel_encoder *encoder,
2400                                 struct intel_crtc_state *pipe_config)
2401 {
2402         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2403         u32 tmp, flags = 0;
2404         struct drm_device *dev = encoder->base.dev;
2405         struct drm_i915_private *dev_priv = dev->dev_private;
2406         enum port port = dp_to_dig_port(intel_dp)->port;
2407         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2408         int dotclock;
2409
2410         tmp = I915_READ(intel_dp->output_reg);
2411
2412         pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A;
2413
2414         if (HAS_PCH_CPT(dev) && port != PORT_A) {
2415                 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe));
2416
2417                 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH)
2418                         flags |= DRM_MODE_FLAG_PHSYNC;
2419                 else
2420                         flags |= DRM_MODE_FLAG_NHSYNC;
2421
2422                 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH)
2423                         flags |= DRM_MODE_FLAG_PVSYNC;
2424                 else
2425                         flags |= DRM_MODE_FLAG_NVSYNC;
2426         } else {
2427                 if (tmp & DP_SYNC_HS_HIGH)
2428                         flags |= DRM_MODE_FLAG_PHSYNC;
2429                 else
2430                         flags |= DRM_MODE_FLAG_NHSYNC;
2431
2432                 if (tmp & DP_SYNC_VS_HIGH)
2433                         flags |= DRM_MODE_FLAG_PVSYNC;
2434                 else
2435                         flags |= DRM_MODE_FLAG_NVSYNC;
2436         }
2437
2438         pipe_config->base.adjusted_mode.flags |= flags;
2439
2440         if (!HAS_PCH_SPLIT(dev) && !IS_VALLEYVIEW(dev) &&
2441             !IS_CHERRYVIEW(dev) && tmp & DP_COLOR_RANGE_16_235)
2442                 pipe_config->limited_color_range = true;
2443
2444         pipe_config->has_dp_encoder = true;
2445
2446         pipe_config->lane_count =
2447                 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1;
2448
2449         intel_dp_get_m_n(crtc, pipe_config);
2450
2451         if (port == PORT_A) {
2452                 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ)
2453                         pipe_config->port_clock = 162000;
2454                 else
2455                         pipe_config->port_clock = 270000;
2456         }
2457
2458         dotclock = intel_dotclock_calculate(pipe_config->port_clock,
2459                                             &pipe_config->dp_m_n);
2460
2461         if (HAS_PCH_SPLIT(dev_priv->dev) && port != PORT_A)
2462                 ironlake_check_encoder_dotclock(pipe_config, dotclock);
2463
2464         pipe_config->base.adjusted_mode.crtc_clock = dotclock;
2465
2466         if (is_edp(intel_dp) && dev_priv->vbt.edp_bpp &&
2467             pipe_config->pipe_bpp > dev_priv->vbt.edp_bpp) {
2468                 /*
2469                  * This is a big fat ugly hack.
2470                  *
2471                  * Some machines in UEFI boot mode provide us a VBT that has 18
2472                  * bpp and 1.62 GHz link bandwidth for eDP, which for reasons
2473                  * unknown we fail to light up. Yet the same BIOS boots up with
2474                  * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as
2475                  * max, not what it tells us to use.
2476                  *
2477                  * Note: This will still be broken if the eDP panel is not lit
2478                  * up by the BIOS, and thus we can't get the mode at module
2479                  * load.
2480                  */
2481                 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n",
2482                               pipe_config->pipe_bpp, dev_priv->vbt.edp_bpp);
2483                 dev_priv->vbt.edp_bpp = pipe_config->pipe_bpp;
2484         }
2485 }
2486
2487 static void intel_disable_dp(struct intel_encoder *encoder)
2488 {
2489         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2490         struct drm_device *dev = encoder->base.dev;
2491         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2492
2493         if (crtc->config->has_audio)
2494                 intel_audio_codec_disable(encoder);
2495
2496         if (HAS_PSR(dev) && !HAS_DDI(dev))
2497                 intel_psr_disable(intel_dp);
2498
2499         /* Make sure the panel is off before trying to change the mode. But also
2500          * ensure that we have vdd while we switch off the panel. */
2501         intel_edp_panel_vdd_on(intel_dp);
2502         intel_edp_backlight_off(intel_dp);
2503         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF);
2504         intel_edp_panel_off(intel_dp);
2505
2506         /* disable the port before the pipe on g4x */
2507         if (INTEL_INFO(dev)->gen < 5)
2508                 intel_dp_link_down(intel_dp);
2509 }
2510
2511 static void ilk_post_disable_dp(struct intel_encoder *encoder)
2512 {
2513         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2514         enum port port = dp_to_dig_port(intel_dp)->port;
2515
2516         intel_dp_link_down(intel_dp);
2517
2518         /* Only ilk+ has port A */
2519         if (port == PORT_A)
2520                 ironlake_edp_pll_off(intel_dp);
2521 }
2522
2523 static void vlv_post_disable_dp(struct intel_encoder *encoder)
2524 {
2525         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2526
2527         intel_dp_link_down(intel_dp);
2528 }
2529
2530 static void chv_data_lane_soft_reset(struct intel_encoder *encoder,
2531                                      bool reset)
2532 {
2533         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2534         enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
2535         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2536         enum pipe pipe = crtc->pipe;
2537         uint32_t val;
2538
2539         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
2540         if (reset)
2541                 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2542         else
2543                 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
2544         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
2545
2546         if (crtc->config->lane_count > 2) {
2547                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
2548                 if (reset)
2549                         val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
2550                 else
2551                         val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
2552                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
2553         }
2554
2555         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
2556         val |= CHV_PCS_REQ_SOFTRESET_EN;
2557         if (reset)
2558                 val &= ~DPIO_PCS_CLK_SOFT_RESET;
2559         else
2560                 val |= DPIO_PCS_CLK_SOFT_RESET;
2561         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
2562
2563         if (crtc->config->lane_count > 2) {
2564                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
2565                 val |= CHV_PCS_REQ_SOFTRESET_EN;
2566                 if (reset)
2567                         val &= ~DPIO_PCS_CLK_SOFT_RESET;
2568                 else
2569                         val |= DPIO_PCS_CLK_SOFT_RESET;
2570                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
2571         }
2572 }
2573
2574 static void chv_post_disable_dp(struct intel_encoder *encoder)
2575 {
2576         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2577         struct drm_device *dev = encoder->base.dev;
2578         struct drm_i915_private *dev_priv = dev->dev_private;
2579
2580         intel_dp_link_down(intel_dp);
2581
2582         mutex_lock(&dev_priv->sb_lock);
2583
2584         /* Assert data lane reset */
2585         chv_data_lane_soft_reset(encoder, true);
2586
2587         mutex_unlock(&dev_priv->sb_lock);
2588 }
2589
2590 static void
2591 _intel_dp_set_link_train(struct intel_dp *intel_dp,
2592                          uint32_t *DP,
2593                          uint8_t dp_train_pat)
2594 {
2595         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2596         struct drm_device *dev = intel_dig_port->base.base.dev;
2597         struct drm_i915_private *dev_priv = dev->dev_private;
2598         enum port port = intel_dig_port->port;
2599
2600         if (HAS_DDI(dev)) {
2601                 uint32_t temp = I915_READ(DP_TP_CTL(port));
2602
2603                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
2604                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
2605                 else
2606                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
2607
2608                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
2609                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2610                 case DP_TRAINING_PATTERN_DISABLE:
2611                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
2612
2613                         break;
2614                 case DP_TRAINING_PATTERN_1:
2615                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
2616                         break;
2617                 case DP_TRAINING_PATTERN_2:
2618                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
2619                         break;
2620                 case DP_TRAINING_PATTERN_3:
2621                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
2622                         break;
2623                 }
2624                 I915_WRITE(DP_TP_CTL(port), temp);
2625
2626         } else if ((IS_GEN7(dev) && port == PORT_A) ||
2627                    (HAS_PCH_CPT(dev) && port != PORT_A)) {
2628                 *DP &= ~DP_LINK_TRAIN_MASK_CPT;
2629
2630                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2631                 case DP_TRAINING_PATTERN_DISABLE:
2632                         *DP |= DP_LINK_TRAIN_OFF_CPT;
2633                         break;
2634                 case DP_TRAINING_PATTERN_1:
2635                         *DP |= DP_LINK_TRAIN_PAT_1_CPT;
2636                         break;
2637                 case DP_TRAINING_PATTERN_2:
2638                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2639                         break;
2640                 case DP_TRAINING_PATTERN_3:
2641                         DRM_ERROR("DP training pattern 3 not supported\n");
2642                         *DP |= DP_LINK_TRAIN_PAT_2_CPT;
2643                         break;
2644                 }
2645
2646         } else {
2647                 if (IS_CHERRYVIEW(dev))
2648                         *DP &= ~DP_LINK_TRAIN_MASK_CHV;
2649                 else
2650                         *DP &= ~DP_LINK_TRAIN_MASK;
2651
2652                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
2653                 case DP_TRAINING_PATTERN_DISABLE:
2654                         *DP |= DP_LINK_TRAIN_OFF;
2655                         break;
2656                 case DP_TRAINING_PATTERN_1:
2657                         *DP |= DP_LINK_TRAIN_PAT_1;
2658                         break;
2659                 case DP_TRAINING_PATTERN_2:
2660                         *DP |= DP_LINK_TRAIN_PAT_2;
2661                         break;
2662                 case DP_TRAINING_PATTERN_3:
2663                         if (IS_CHERRYVIEW(dev)) {
2664                                 *DP |= DP_LINK_TRAIN_PAT_3_CHV;
2665                         } else {
2666                                 DRM_ERROR("DP training pattern 3 not supported\n");
2667                                 *DP |= DP_LINK_TRAIN_PAT_2;
2668                         }
2669                         break;
2670                 }
2671         }
2672 }
2673
2674 static void intel_dp_enable_port(struct intel_dp *intel_dp)
2675 {
2676         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2677         struct drm_i915_private *dev_priv = dev->dev_private;
2678         struct intel_crtc *crtc =
2679                 to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc);
2680
2681         /* enable with pattern 1 (as per spec) */
2682         _intel_dp_set_link_train(intel_dp, &intel_dp->DP,
2683                                  DP_TRAINING_PATTERN_1);
2684
2685         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2686         POSTING_READ(intel_dp->output_reg);
2687
2688         /*
2689          * Magic for VLV/CHV. We _must_ first set up the register
2690          * without actually enabling the port, and then do another
2691          * write to enable the port. Otherwise link training will
2692          * fail when the power sequencer is freshly used for this port.
2693          */
2694         intel_dp->DP |= DP_PORT_EN;
2695         if (crtc->config->has_audio)
2696                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
2697
2698         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
2699         POSTING_READ(intel_dp->output_reg);
2700 }
2701
2702 static void intel_enable_dp(struct intel_encoder *encoder)
2703 {
2704         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2705         struct drm_device *dev = encoder->base.dev;
2706         struct drm_i915_private *dev_priv = dev->dev_private;
2707         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2708         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
2709         enum port port = dp_to_dig_port(intel_dp)->port;
2710         enum pipe pipe = crtc->pipe;
2711
2712         if (WARN_ON(dp_reg & DP_PORT_EN))
2713                 return;
2714
2715         pps_lock(intel_dp);
2716
2717         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
2718                 vlv_init_panel_power_sequencer(intel_dp);
2719
2720         /*
2721          * We get an occasional spurious underrun between the port
2722          * enable and vdd enable, when enabling port A eDP.
2723          *
2724          * FIXME: Not sure if this applies to (PCH) port D eDP as well
2725          */
2726         if (port == PORT_A)
2727                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, false);
2728
2729         intel_dp_enable_port(intel_dp);
2730
2731         if (port == PORT_A && IS_GEN5(dev_priv)) {
2732                 /*
2733                  * Underrun reporting for the other pipe was disabled in
2734                  * g4x_pre_enable_dp(). The eDP PLL and port have now been
2735                  * enabled, so it's now safe to re-enable underrun reporting.
2736                  */
2737                 intel_wait_for_vblank_if_active(dev_priv->dev, !pipe);
2738                 intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, true);
2739                 intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, true);
2740         }
2741
2742         edp_panel_vdd_on(intel_dp);
2743         edp_panel_on(intel_dp);
2744         edp_panel_vdd_off(intel_dp, true);
2745
2746         if (port == PORT_A)
2747                 intel_set_cpu_fifo_underrun_reporting(dev_priv, pipe, true);
2748
2749         pps_unlock(intel_dp);
2750
2751         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
2752                 unsigned int lane_mask = 0x0;
2753
2754                 if (IS_CHERRYVIEW(dev))
2755                         lane_mask = intel_dp_unused_lane_mask(crtc->config->lane_count);
2756
2757                 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp),
2758                                     lane_mask);
2759         }
2760
2761         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
2762         intel_dp_start_link_train(intel_dp);
2763         intel_dp_stop_link_train(intel_dp);
2764
2765         if (crtc->config->has_audio) {
2766                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
2767                                  pipe_name(pipe));
2768                 intel_audio_codec_enable(encoder);
2769         }
2770 }
2771
2772 static void g4x_enable_dp(struct intel_encoder *encoder)
2773 {
2774         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2775
2776         intel_enable_dp(encoder);
2777         intel_edp_backlight_on(intel_dp);
2778 }
2779
2780 static void vlv_enable_dp(struct intel_encoder *encoder)
2781 {
2782         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2783
2784         intel_edp_backlight_on(intel_dp);
2785         intel_psr_enable(intel_dp);
2786 }
2787
2788 static void g4x_pre_enable_dp(struct intel_encoder *encoder)
2789 {
2790         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
2791         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2792         enum port port = dp_to_dig_port(intel_dp)->port;
2793         enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
2794
2795         intel_dp_prepare(encoder);
2796
2797         if (port == PORT_A && IS_GEN5(dev_priv)) {
2798                 /*
2799                  * We get FIFO underruns on the other pipe when
2800                  * enabling the CPU eDP PLL, and when enabling CPU
2801                  * eDP port. We could potentially avoid the PLL
2802                  * underrun with a vblank wait just prior to enabling
2803                  * the PLL, but that doesn't appear to help the port
2804                  * enable case. Just sweep it all under the rug.
2805                  */
2806                 intel_set_cpu_fifo_underrun_reporting(dev_priv, !pipe, false);
2807                 intel_set_pch_fifo_underrun_reporting(dev_priv, !pipe, false);
2808         }
2809
2810         /* Only ilk+ has port A */
2811         if (port == PORT_A)
2812                 ironlake_edp_pll_on(intel_dp);
2813 }
2814
2815 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp)
2816 {
2817         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2818         struct drm_i915_private *dev_priv = intel_dig_port->base.base.dev->dev_private;
2819         enum pipe pipe = intel_dp->pps_pipe;
2820         i915_reg_t pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
2821
2822         edp_panel_vdd_off_sync(intel_dp);
2823
2824         /*
2825          * VLV seems to get confused when multiple power seqeuencers
2826          * have the same port selected (even if only one has power/vdd
2827          * enabled). The failure manifests as vlv_wait_port_ready() failing
2828          * CHV on the other hand doesn't seem to mind having the same port
2829          * selected in multiple power seqeuencers, but let's clear the
2830          * port select always when logically disconnecting a power sequencer
2831          * from a port.
2832          */
2833         DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n",
2834                       pipe_name(pipe), port_name(intel_dig_port->port));
2835         I915_WRITE(pp_on_reg, 0);
2836         POSTING_READ(pp_on_reg);
2837
2838         intel_dp->pps_pipe = INVALID_PIPE;
2839 }
2840
2841 static void vlv_steal_power_sequencer(struct drm_device *dev,
2842                                       enum pipe pipe)
2843 {
2844         struct drm_i915_private *dev_priv = dev->dev_private;
2845         struct intel_encoder *encoder;
2846
2847         lockdep_assert_held(&dev_priv->pps_mutex);
2848
2849         if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
2850                 return;
2851
2852         for_each_intel_encoder(dev, encoder) {
2853                 struct intel_dp *intel_dp;
2854                 enum port port;
2855
2856                 if (encoder->type != INTEL_OUTPUT_EDP)
2857                         continue;
2858
2859                 intel_dp = enc_to_intel_dp(&encoder->base);
2860                 port = dp_to_dig_port(intel_dp)->port;
2861
2862                 if (intel_dp->pps_pipe != pipe)
2863                         continue;
2864
2865                 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n",
2866                               pipe_name(pipe), port_name(port));
2867
2868                 WARN(encoder->base.crtc,
2869                      "stealing pipe %c power sequencer from active eDP port %c\n",
2870                      pipe_name(pipe), port_name(port));
2871
2872                 /* make sure vdd is off before we steal it */
2873                 vlv_detach_power_sequencer(intel_dp);
2874         }
2875 }
2876
2877 static void vlv_init_panel_power_sequencer(struct intel_dp *intel_dp)
2878 {
2879         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2880         struct intel_encoder *encoder = &intel_dig_port->base;
2881         struct drm_device *dev = encoder->base.dev;
2882         struct drm_i915_private *dev_priv = dev->dev_private;
2883         struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
2884
2885         lockdep_assert_held(&dev_priv->pps_mutex);
2886
2887         if (!is_edp(intel_dp))
2888                 return;
2889
2890         if (intel_dp->pps_pipe == crtc->pipe)
2891                 return;
2892
2893         /*
2894          * If another power sequencer was being used on this
2895          * port previously make sure to turn off vdd there while
2896          * we still have control of it.
2897          */
2898         if (intel_dp->pps_pipe != INVALID_PIPE)
2899                 vlv_detach_power_sequencer(intel_dp);
2900
2901         /*
2902          * We may be stealing the power
2903          * sequencer from another port.
2904          */
2905         vlv_steal_power_sequencer(dev, crtc->pipe);
2906
2907         /* now it's all ours */
2908         intel_dp->pps_pipe = crtc->pipe;
2909
2910         DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n",
2911                       pipe_name(intel_dp->pps_pipe), port_name(intel_dig_port->port));
2912
2913         /* init power sequencer on this pipe and port */
2914         intel_dp_init_panel_power_sequencer(dev, intel_dp);
2915         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
2916 }
2917
2918 static void vlv_pre_enable_dp(struct intel_encoder *encoder)
2919 {
2920         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2921         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2922         struct drm_device *dev = encoder->base.dev;
2923         struct drm_i915_private *dev_priv = dev->dev_private;
2924         struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
2925         enum dpio_channel port = vlv_dport_to_channel(dport);
2926         int pipe = intel_crtc->pipe;
2927         u32 val;
2928
2929         mutex_lock(&dev_priv->sb_lock);
2930
2931         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
2932         val = 0;
2933         if (pipe)
2934                 val |= (1<<21);
2935         else
2936                 val &= ~(1<<21);
2937         val |= 0x001000c4;
2938         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
2939         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
2940         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
2941
2942         mutex_unlock(&dev_priv->sb_lock);
2943
2944         intel_enable_dp(encoder);
2945 }
2946
2947 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder)
2948 {
2949         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
2950         struct drm_device *dev = encoder->base.dev;
2951         struct drm_i915_private *dev_priv = dev->dev_private;
2952         struct intel_crtc *intel_crtc =
2953                 to_intel_crtc(encoder->base.crtc);
2954         enum dpio_channel port = vlv_dport_to_channel(dport);
2955         int pipe = intel_crtc->pipe;
2956
2957         intel_dp_prepare(encoder);
2958
2959         /* Program Tx lane resets to default */
2960         mutex_lock(&dev_priv->sb_lock);
2961         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
2962                          DPIO_PCS_TX_LANE2_RESET |
2963                          DPIO_PCS_TX_LANE1_RESET);
2964         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
2965                          DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
2966                          DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
2967                          (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
2968                                  DPIO_PCS_CLK_SOFT_RESET);
2969
2970         /* Fix up inter-pair skew failure */
2971         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
2972         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
2973         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
2974         mutex_unlock(&dev_priv->sb_lock);
2975 }
2976
2977 static void chv_pre_enable_dp(struct intel_encoder *encoder)
2978 {
2979         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
2980         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
2981         struct drm_device *dev = encoder->base.dev;
2982         struct drm_i915_private *dev_priv = dev->dev_private;
2983         struct intel_crtc *intel_crtc =
2984                 to_intel_crtc(encoder->base.crtc);
2985         enum dpio_channel ch = vlv_dport_to_channel(dport);
2986         int pipe = intel_crtc->pipe;
2987         int data, i, stagger;
2988         u32 val;
2989
2990         mutex_lock(&dev_priv->sb_lock);
2991
2992         /* allow hardware to manage TX FIFO reset source */
2993         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
2994         val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
2995         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
2996
2997         if (intel_crtc->config->lane_count > 2) {
2998                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
2999                 val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
3000                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
3001         }
3002
3003         /* Program Tx lane latency optimal setting*/
3004         for (i = 0; i < intel_crtc->config->lane_count; i++) {
3005                 /* Set the upar bit */
3006                 if (intel_crtc->config->lane_count == 1)
3007                         data = 0x0;
3008                 else
3009                         data = (i == 1) ? 0x0 : 0x1;
3010                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
3011                                 data << DPIO_UPAR_SHIFT);
3012         }
3013
3014         /* Data lane stagger programming */
3015         if (intel_crtc->config->port_clock > 270000)
3016                 stagger = 0x18;
3017         else if (intel_crtc->config->port_clock > 135000)
3018                 stagger = 0xd;
3019         else if (intel_crtc->config->port_clock > 67500)
3020                 stagger = 0x7;
3021         else if (intel_crtc->config->port_clock > 33750)
3022                 stagger = 0x4;
3023         else
3024                 stagger = 0x2;
3025
3026         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
3027         val |= DPIO_TX2_STAGGER_MASK(0x1f);
3028         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
3029
3030         if (intel_crtc->config->lane_count > 2) {
3031                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
3032                 val |= DPIO_TX2_STAGGER_MASK(0x1f);
3033                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
3034         }
3035
3036         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
3037                        DPIO_LANESTAGGER_STRAP(stagger) |
3038                        DPIO_LANESTAGGER_STRAP_OVRD |
3039                        DPIO_TX1_STAGGER_MASK(0x1f) |
3040                        DPIO_TX1_STAGGER_MULT(6) |
3041                        DPIO_TX2_STAGGER_MULT(0));
3042
3043         if (intel_crtc->config->lane_count > 2) {
3044                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
3045                                DPIO_LANESTAGGER_STRAP(stagger) |
3046                                DPIO_LANESTAGGER_STRAP_OVRD |
3047                                DPIO_TX1_STAGGER_MASK(0x1f) |
3048                                DPIO_TX1_STAGGER_MULT(7) |
3049                                DPIO_TX2_STAGGER_MULT(5));
3050         }
3051
3052         /* Deassert data lane reset */
3053         chv_data_lane_soft_reset(encoder, false);
3054
3055         mutex_unlock(&dev_priv->sb_lock);
3056
3057         intel_enable_dp(encoder);
3058
3059         /* Second common lane will stay alive on its own now */
3060         if (dport->release_cl2_override) {
3061                 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
3062                 dport->release_cl2_override = false;
3063         }
3064 }
3065
3066 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder)
3067 {
3068         struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
3069         struct drm_device *dev = encoder->base.dev;
3070         struct drm_i915_private *dev_priv = dev->dev_private;
3071         struct intel_crtc *intel_crtc =
3072                 to_intel_crtc(encoder->base.crtc);
3073         enum dpio_channel ch = vlv_dport_to_channel(dport);
3074         enum pipe pipe = intel_crtc->pipe;
3075         unsigned int lane_mask =
3076                 intel_dp_unused_lane_mask(intel_crtc->config->lane_count);
3077         u32 val;
3078
3079         intel_dp_prepare(encoder);
3080
3081         /*
3082          * Must trick the second common lane into life.
3083          * Otherwise we can't even access the PLL.
3084          */
3085         if (ch == DPIO_CH0 && pipe == PIPE_B)
3086                 dport->release_cl2_override =
3087                         !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
3088
3089         chv_phy_powergate_lanes(encoder, true, lane_mask);
3090
3091         mutex_lock(&dev_priv->sb_lock);
3092
3093         /* Assert data lane reset */
3094         chv_data_lane_soft_reset(encoder, true);
3095
3096         /* program left/right clock distribution */
3097         if (pipe != PIPE_B) {
3098                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
3099                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
3100                 if (ch == DPIO_CH0)
3101                         val |= CHV_BUFLEFTENA1_FORCE;
3102                 if (ch == DPIO_CH1)
3103                         val |= CHV_BUFRIGHTENA1_FORCE;
3104                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
3105         } else {
3106                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
3107                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
3108                 if (ch == DPIO_CH0)
3109                         val |= CHV_BUFLEFTENA2_FORCE;
3110                 if (ch == DPIO_CH1)
3111                         val |= CHV_BUFRIGHTENA2_FORCE;
3112                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
3113         }
3114
3115         /* program clock channel usage */
3116         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
3117         val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
3118         if (pipe != PIPE_B)
3119                 val &= ~CHV_PCS_USEDCLKCHANNEL;
3120         else
3121                 val |= CHV_PCS_USEDCLKCHANNEL;
3122         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
3123
3124         if (intel_crtc->config->lane_count > 2) {
3125                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
3126                 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
3127                 if (pipe != PIPE_B)
3128                         val &= ~CHV_PCS_USEDCLKCHANNEL;
3129                 else
3130                         val |= CHV_PCS_USEDCLKCHANNEL;
3131                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
3132         }
3133
3134         /*
3135          * This a a bit weird since generally CL
3136          * matches the pipe, but here we need to
3137          * pick the CL based on the port.
3138          */
3139         val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
3140         if (pipe != PIPE_B)
3141                 val &= ~CHV_CMN_USEDCLKCHANNEL;
3142         else
3143                 val |= CHV_CMN_USEDCLKCHANNEL;
3144         vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
3145
3146         mutex_unlock(&dev_priv->sb_lock);
3147 }
3148
3149 static void chv_dp_post_pll_disable(struct intel_encoder *encoder)
3150 {
3151         struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
3152         enum pipe pipe = to_intel_crtc(encoder->base.crtc)->pipe;
3153         u32 val;
3154
3155         mutex_lock(&dev_priv->sb_lock);
3156
3157         /* disable left/right clock distribution */
3158         if (pipe != PIPE_B) {
3159                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
3160                 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
3161                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
3162         } else {
3163                 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
3164                 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
3165                 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
3166         }
3167
3168         mutex_unlock(&dev_priv->sb_lock);
3169
3170         /*
3171          * Leave the power down bit cleared for at least one
3172          * lane so that chv_powergate_phy_ch() will power
3173          * on something when the channel is otherwise unused.
3174          * When the port is off and the override is removed
3175          * the lanes power down anyway, so otherwise it doesn't
3176          * really matter what the state of power down bits is
3177          * after this.
3178          */
3179         chv_phy_powergate_lanes(encoder, false, 0x0);
3180 }
3181
3182 /*
3183  * Native read with retry for link status and receiver capability reads for
3184  * cases where the sink may still be asleep.
3185  *
3186  * Sinks are *supposed* to come up within 1ms from an off state, but we're also
3187  * supposed to retry 3 times per the spec.
3188  */
3189 static ssize_t
3190 intel_dp_dpcd_read_wake(struct drm_dp_aux *aux, unsigned int offset,
3191                         void *buffer, size_t size)
3192 {
3193         ssize_t ret;
3194         int i;
3195
3196         /*
3197          * Sometime we just get the same incorrect byte repeated
3198          * over the entire buffer. Doing just one throw away read
3199          * initially seems to "solve" it.
3200          */
3201         drm_dp_dpcd_read(aux, DP_DPCD_REV, buffer, 1);
3202
3203         for (i = 0; i < 3; i++) {
3204                 ret = drm_dp_dpcd_read(aux, offset, buffer, size);
3205                 if (ret == size)
3206                         return ret;
3207                 msleep(1);
3208         }
3209
3210         return ret;
3211 }
3212
3213 /*
3214  * Fetch AUX CH registers 0x202 - 0x207 which contain
3215  * link status information
3216  */
3217 bool
3218 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
3219 {
3220         return intel_dp_dpcd_read_wake(&intel_dp->aux,
3221                                        DP_LANE0_1_STATUS,
3222                                        link_status,
3223                                        DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE;
3224 }
3225
3226 /* These are source-specific values. */
3227 uint8_t
3228 intel_dp_voltage_max(struct intel_dp *intel_dp)
3229 {
3230         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3231         struct drm_i915_private *dev_priv = dev->dev_private;
3232         enum port port = dp_to_dig_port(intel_dp)->port;
3233
3234         if (IS_BROXTON(dev))
3235                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3236         else if (INTEL_INFO(dev)->gen >= 9) {
3237                 if (dev_priv->edp_low_vswing && port == PORT_A)
3238                         return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3239                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3240         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
3241                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3242         else if (IS_GEN7(dev) && port == PORT_A)
3243                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3244         else if (HAS_PCH_CPT(dev) && port != PORT_A)
3245                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3246         else
3247                 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
3248 }
3249
3250 uint8_t
3251 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
3252 {
3253         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3254         enum port port = dp_to_dig_port(intel_dp)->port;
3255
3256         if (INTEL_INFO(dev)->gen >= 9) {
3257                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3258                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3259                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3260                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3261                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3262                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3263                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3264                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3265                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3266                 default:
3267                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3268                 }
3269         } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
3270                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3271                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3272                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3273                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3274                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3275                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3276                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3277                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3278                 default:
3279                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3280                 }
3281         } else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
3282                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3283                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3284                         return DP_TRAIN_PRE_EMPH_LEVEL_3;
3285                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3286                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3287                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3288                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3289                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3290                 default:
3291                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3292                 }
3293         } else if (IS_GEN7(dev) && port == PORT_A) {
3294                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3295                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3296                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3297                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3298                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3299                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3300                 default:
3301                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3302                 }
3303         } else {
3304                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
3305                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3306                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3307                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3308                         return DP_TRAIN_PRE_EMPH_LEVEL_2;
3309                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3310                         return DP_TRAIN_PRE_EMPH_LEVEL_1;
3311                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3312                 default:
3313                         return DP_TRAIN_PRE_EMPH_LEVEL_0;
3314                 }
3315         }
3316 }
3317
3318 static uint32_t vlv_signal_levels(struct intel_dp *intel_dp)
3319 {
3320         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3321         struct drm_i915_private *dev_priv = dev->dev_private;
3322         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3323         struct intel_crtc *intel_crtc =
3324                 to_intel_crtc(dport->base.base.crtc);
3325         unsigned long demph_reg_value, preemph_reg_value,
3326                 uniqtranscale_reg_value;
3327         uint8_t train_set = intel_dp->train_set[0];
3328         enum dpio_channel port = vlv_dport_to_channel(dport);
3329         int pipe = intel_crtc->pipe;
3330
3331         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3332         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3333                 preemph_reg_value = 0x0004000;
3334                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3335                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3336                         demph_reg_value = 0x2B405555;
3337                         uniqtranscale_reg_value = 0x552AB83A;
3338                         break;
3339                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3340                         demph_reg_value = 0x2B404040;
3341                         uniqtranscale_reg_value = 0x5548B83A;
3342                         break;
3343                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3344                         demph_reg_value = 0x2B245555;
3345                         uniqtranscale_reg_value = 0x5560B83A;
3346                         break;
3347                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3348                         demph_reg_value = 0x2B405555;
3349                         uniqtranscale_reg_value = 0x5598DA3A;
3350                         break;
3351                 default:
3352                         return 0;
3353                 }
3354                 break;
3355         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3356                 preemph_reg_value = 0x0002000;
3357                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3358                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3359                         demph_reg_value = 0x2B404040;
3360                         uniqtranscale_reg_value = 0x5552B83A;
3361                         break;
3362                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3363                         demph_reg_value = 0x2B404848;
3364                         uniqtranscale_reg_value = 0x5580B83A;
3365                         break;
3366                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3367                         demph_reg_value = 0x2B404040;
3368                         uniqtranscale_reg_value = 0x55ADDA3A;
3369                         break;
3370                 default:
3371                         return 0;
3372                 }
3373                 break;
3374         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3375                 preemph_reg_value = 0x0000000;
3376                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3377                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3378                         demph_reg_value = 0x2B305555;
3379                         uniqtranscale_reg_value = 0x5570B83A;
3380                         break;
3381                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3382                         demph_reg_value = 0x2B2B4040;
3383                         uniqtranscale_reg_value = 0x55ADDA3A;
3384                         break;
3385                 default:
3386                         return 0;
3387                 }
3388                 break;
3389         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3390                 preemph_reg_value = 0x0006000;
3391                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3392                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3393                         demph_reg_value = 0x1B405555;
3394                         uniqtranscale_reg_value = 0x55ADDA3A;
3395                         break;
3396                 default:
3397                         return 0;
3398                 }
3399                 break;
3400         default:
3401                 return 0;
3402         }
3403
3404         mutex_lock(&dev_priv->sb_lock);
3405         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
3406         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
3407         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
3408                          uniqtranscale_reg_value);
3409         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
3410         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
3411         vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
3412         vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x80000000);
3413         mutex_unlock(&dev_priv->sb_lock);
3414
3415         return 0;
3416 }
3417
3418 static bool chv_need_uniq_trans_scale(uint8_t train_set)
3419 {
3420         return (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) == DP_TRAIN_PRE_EMPH_LEVEL_0 &&
3421                 (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) == DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
3422 }
3423
3424 static uint32_t chv_signal_levels(struct intel_dp *intel_dp)
3425 {
3426         struct drm_device *dev = intel_dp_to_dev(intel_dp);
3427         struct drm_i915_private *dev_priv = dev->dev_private;
3428         struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
3429         struct intel_crtc *intel_crtc = to_intel_crtc(dport->base.base.crtc);
3430         u32 deemph_reg_value, margin_reg_value, val;
3431         uint8_t train_set = intel_dp->train_set[0];
3432         enum dpio_channel ch = vlv_dport_to_channel(dport);
3433         enum pipe pipe = intel_crtc->pipe;
3434         int i;
3435
3436         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3437         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3438                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3439                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3440                         deemph_reg_value = 128;
3441                         margin_reg_value = 52;
3442                         break;
3443                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3444                         deemph_reg_value = 128;
3445                         margin_reg_value = 77;
3446                         break;
3447                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3448                         deemph_reg_value = 128;
3449                         margin_reg_value = 102;
3450                         break;
3451                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3452                         deemph_reg_value = 128;
3453                         margin_reg_value = 154;
3454                         /* FIXME extra to set for 1200 */
3455                         break;
3456                 default:
3457                         return 0;
3458                 }
3459                 break;
3460         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3461                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3462                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3463                         deemph_reg_value = 85;
3464                         margin_reg_value = 78;
3465                         break;
3466                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3467                         deemph_reg_value = 85;
3468                         margin_reg_value = 116;
3469                         break;
3470                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3471                         deemph_reg_value = 85;
3472                         margin_reg_value = 154;
3473                         break;
3474                 default:
3475                         return 0;
3476                 }
3477                 break;
3478         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3479                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3480                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3481                         deemph_reg_value = 64;
3482                         margin_reg_value = 104;
3483                         break;
3484                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3485                         deemph_reg_value = 64;
3486                         margin_reg_value = 154;
3487                         break;
3488                 default:
3489                         return 0;
3490                 }
3491                 break;
3492         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3493                 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3494                 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3495                         deemph_reg_value = 43;
3496                         margin_reg_value = 154;
3497                         break;
3498                 default:
3499                         return 0;
3500                 }
3501                 break;
3502         default:
3503                 return 0;
3504         }
3505
3506         mutex_lock(&dev_priv->sb_lock);
3507
3508         /* Clear calc init */
3509         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3510         val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3511         val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3512         val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3513         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3514
3515         if (intel_crtc->config->lane_count > 2) {
3516                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3517                 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
3518                 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
3519                 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
3520                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3521         }
3522
3523         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
3524         val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3525         val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3526         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
3527
3528         if (intel_crtc->config->lane_count > 2) {
3529                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
3530                 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
3531                 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
3532                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
3533         }
3534
3535         /* Program swing deemph */
3536         for (i = 0; i < intel_crtc->config->lane_count; i++) {
3537                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
3538                 val &= ~DPIO_SWING_DEEMPH9P5_MASK;
3539                 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
3540                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
3541         }
3542
3543         /* Program swing margin */
3544         for (i = 0; i < intel_crtc->config->lane_count; i++) {
3545                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
3546
3547                 val &= ~DPIO_SWING_MARGIN000_MASK;
3548                 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
3549
3550                 /*
3551                  * Supposedly this value shouldn't matter when unique transition
3552                  * scale is disabled, but in fact it does matter. Let's just
3553                  * always program the same value and hope it's OK.
3554                  */
3555                 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
3556                 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
3557
3558                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
3559         }
3560
3561         /*
3562          * The document said it needs to set bit 27 for ch0 and bit 26
3563          * for ch1. Might be a typo in the doc.
3564          * For now, for this unique transition scale selection, set bit
3565          * 27 for ch0 and ch1.
3566          */
3567         for (i = 0; i < intel_crtc->config->lane_count; i++) {
3568                 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
3569                 if (chv_need_uniq_trans_scale(train_set))
3570                         val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
3571                 else
3572                         val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
3573                 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
3574         }
3575
3576         /* Start swing calculation */
3577         val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
3578         val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3579         vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
3580
3581         if (intel_crtc->config->lane_count > 2) {
3582                 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
3583                 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
3584                 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
3585         }
3586
3587         mutex_unlock(&dev_priv->sb_lock);
3588
3589         return 0;
3590 }
3591
3592 static uint32_t
3593 gen4_signal_levels(uint8_t train_set)
3594 {
3595         uint32_t        signal_levels = 0;
3596
3597         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
3598         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0:
3599         default:
3600                 signal_levels |= DP_VOLTAGE_0_4;
3601                 break;
3602         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1:
3603                 signal_levels |= DP_VOLTAGE_0_6;
3604                 break;
3605         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2:
3606                 signal_levels |= DP_VOLTAGE_0_8;
3607                 break;
3608         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3:
3609                 signal_levels |= DP_VOLTAGE_1_2;
3610                 break;
3611         }
3612         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
3613         case DP_TRAIN_PRE_EMPH_LEVEL_0:
3614         default:
3615                 signal_levels |= DP_PRE_EMPHASIS_0;
3616                 break;
3617         case DP_TRAIN_PRE_EMPH_LEVEL_1:
3618                 signal_levels |= DP_PRE_EMPHASIS_3_5;
3619                 break;
3620         case DP_TRAIN_PRE_EMPH_LEVEL_2:
3621                 signal_levels |= DP_PRE_EMPHASIS_6;
3622                 break;
3623         case DP_TRAIN_PRE_EMPH_LEVEL_3:
3624                 signal_levels |= DP_PRE_EMPHASIS_9_5;
3625                 break;
3626         }
3627         return signal_levels;
3628 }
3629
3630 /* Gen6's DP voltage swing and pre-emphasis control */
3631 static uint32_t
3632 gen6_edp_signal_levels(uint8_t train_set)
3633 {
3634         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3635                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3636         switch (signal_levels) {
3637         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3638         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3639                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3640         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3641                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
3642         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3643         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3644                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
3645         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3646         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3647                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
3648         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3649         case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3650                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
3651         default:
3652                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3653                               "0x%x\n", signal_levels);
3654                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
3655         }
3656 }
3657
3658 /* Gen7's DP voltage swing and pre-emphasis control */
3659 static uint32_t
3660 gen7_edp_signal_levels(uint8_t train_set)
3661 {
3662         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
3663                                          DP_TRAIN_PRE_EMPHASIS_MASK);
3664         switch (signal_levels) {
3665         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3666                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
3667         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3668                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
3669         case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2:
3670                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
3671
3672         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3673                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
3674         case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3675                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
3676
3677         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0:
3678                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
3679         case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1:
3680                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
3681
3682         default:
3683                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
3684                               "0x%x\n", signal_levels);
3685                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
3686         }
3687 }
3688
3689 void
3690 intel_dp_set_signal_levels(struct intel_dp *intel_dp)
3691 {
3692         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3693         enum port port = intel_dig_port->port;
3694         struct drm_device *dev = intel_dig_port->base.base.dev;
3695         struct drm_i915_private *dev_priv = to_i915(dev);
3696         uint32_t signal_levels, mask = 0;
3697         uint8_t train_set = intel_dp->train_set[0];
3698
3699         if (HAS_DDI(dev)) {
3700                 signal_levels = ddi_signal_levels(intel_dp);
3701
3702                 if (IS_BROXTON(dev))
3703                         signal_levels = 0;
3704                 else
3705                         mask = DDI_BUF_EMP_MASK;
3706         } else if (IS_CHERRYVIEW(dev)) {
3707                 signal_levels = chv_signal_levels(intel_dp);
3708         } else if (IS_VALLEYVIEW(dev)) {
3709                 signal_levels = vlv_signal_levels(intel_dp);
3710         } else if (IS_GEN7(dev) && port == PORT_A) {
3711                 signal_levels = gen7_edp_signal_levels(train_set);
3712                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
3713         } else if (IS_GEN6(dev) && port == PORT_A) {
3714                 signal_levels = gen6_edp_signal_levels(train_set);
3715                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
3716         } else {
3717                 signal_levels = gen4_signal_levels(train_set);
3718                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
3719         }
3720
3721         if (mask)
3722                 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
3723
3724         DRM_DEBUG_KMS("Using vswing level %d\n",
3725                 train_set & DP_TRAIN_VOLTAGE_SWING_MASK);
3726         DRM_DEBUG_KMS("Using pre-emphasis level %d\n",
3727                 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
3728                         DP_TRAIN_PRE_EMPHASIS_SHIFT);
3729
3730         intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels;
3731
3732         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3733         POSTING_READ(intel_dp->output_reg);
3734 }
3735
3736 void
3737 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
3738                                        uint8_t dp_train_pat)
3739 {
3740         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3741         struct drm_i915_private *dev_priv =
3742                 to_i915(intel_dig_port->base.base.dev);
3743
3744         _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat);
3745
3746         I915_WRITE(intel_dp->output_reg, intel_dp->DP);
3747         POSTING_READ(intel_dp->output_reg);
3748 }
3749
3750 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp)
3751 {
3752         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3753         struct drm_device *dev = intel_dig_port->base.base.dev;
3754         struct drm_i915_private *dev_priv = dev->dev_private;
3755         enum port port = intel_dig_port->port;
3756         uint32_t val;
3757
3758         if (!HAS_DDI(dev))
3759                 return;
3760
3761         val = I915_READ(DP_TP_CTL(port));
3762         val &= ~DP_TP_CTL_LINK_TRAIN_MASK;
3763         val |= DP_TP_CTL_LINK_TRAIN_IDLE;
3764         I915_WRITE(DP_TP_CTL(port), val);
3765
3766         /*
3767          * On PORT_A we can have only eDP in SST mode. There the only reason
3768          * we need to set idle transmission mode is to work around a HW issue
3769          * where we enable the pipe while not in idle link-training mode.
3770          * In this case there is requirement to wait for a minimum number of
3771          * idle patterns to be sent.
3772          */
3773         if (port == PORT_A)
3774                 return;
3775
3776         if (wait_for((I915_READ(DP_TP_STATUS(port)) & DP_TP_STATUS_IDLE_DONE),
3777                      1))
3778                 DRM_ERROR("Timed out waiting for DP idle patterns\n");
3779 }
3780
3781 static void
3782 intel_dp_link_down(struct intel_dp *intel_dp)
3783 {
3784         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
3785         struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
3786         enum port port = intel_dig_port->port;
3787         struct drm_device *dev = intel_dig_port->base.base.dev;
3788         struct drm_i915_private *dev_priv = dev->dev_private;
3789         uint32_t DP = intel_dp->DP;
3790
3791         if (WARN_ON(HAS_DDI(dev)))
3792                 return;
3793
3794         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
3795                 return;
3796
3797         DRM_DEBUG_KMS("\n");
3798
3799         if ((IS_GEN7(dev) && port == PORT_A) ||
3800             (HAS_PCH_CPT(dev) && port != PORT_A)) {
3801                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
3802                 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT;
3803         } else {
3804                 if (IS_CHERRYVIEW(dev))
3805                         DP &= ~DP_LINK_TRAIN_MASK_CHV;
3806                 else
3807                         DP &= ~DP_LINK_TRAIN_MASK;
3808                 DP |= DP_LINK_TRAIN_PAT_IDLE;
3809         }
3810         I915_WRITE(intel_dp->output_reg, DP);
3811         POSTING_READ(intel_dp->output_reg);
3812
3813         DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
3814         I915_WRITE(intel_dp->output_reg, DP);
3815         POSTING_READ(intel_dp->output_reg);
3816
3817         /*
3818          * HW workaround for IBX, we need to move the port
3819          * to transcoder A after disabling it to allow the
3820          * matching HDMI port to be enabled on transcoder A.
3821          */
3822         if (HAS_PCH_IBX(dev) && crtc->pipe == PIPE_B && port != PORT_A) {
3823                 /*
3824                  * We get CPU/PCH FIFO underruns on the other pipe when
3825                  * doing the workaround. Sweep them under the rug.
3826                  */
3827                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3828                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false);
3829
3830                 /* always enable with pattern 1 (as per spec) */
3831                 DP &= ~(DP_PIPEB_SELECT | DP_LINK_TRAIN_MASK);
3832                 DP |= DP_PORT_EN | DP_LINK_TRAIN_PAT_1;
3833                 I915_WRITE(intel_dp->output_reg, DP);
3834                 POSTING_READ(intel_dp->output_reg);
3835
3836                 DP &= ~DP_PORT_EN;
3837                 I915_WRITE(intel_dp->output_reg, DP);
3838                 POSTING_READ(intel_dp->output_reg);
3839
3840                 intel_wait_for_vblank_if_active(dev_priv->dev, PIPE_A);
3841                 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3842                 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true);
3843         }
3844
3845         msleep(intel_dp->panel_power_down_delay);
3846
3847         intel_dp->DP = DP;
3848 }
3849
3850 static bool
3851 intel_dp_get_dpcd(struct intel_dp *intel_dp)
3852 {
3853         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3854         struct drm_device *dev = dig_port->base.base.dev;
3855         struct drm_i915_private *dev_priv = dev->dev_private;
3856         uint8_t rev;
3857
3858         if (intel_dp_dpcd_read_wake(&intel_dp->aux, 0x000, intel_dp->dpcd,
3859                                     sizeof(intel_dp->dpcd)) < 0)
3860                 return false; /* aux transfer failed */
3861
3862         DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd);
3863
3864         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
3865                 return false; /* DPCD not present */
3866
3867         /* Check if the panel supports PSR */
3868         memset(intel_dp->psr_dpcd, 0, sizeof(intel_dp->psr_dpcd));
3869         if (is_edp(intel_dp)) {
3870                 intel_dp_dpcd_read_wake(&intel_dp->aux, DP_PSR_SUPPORT,
3871                                         intel_dp->psr_dpcd,
3872                                         sizeof(intel_dp->psr_dpcd));
3873                 if (intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED) {
3874                         dev_priv->psr.sink_support = true;
3875                         DRM_DEBUG_KMS("Detected EDP PSR Panel.\n");
3876                 }
3877
3878                 if (INTEL_INFO(dev)->gen >= 9 &&
3879                         (intel_dp->psr_dpcd[0] & DP_PSR2_IS_SUPPORTED)) {
3880                         uint8_t frame_sync_cap;
3881
3882                         dev_priv->psr.sink_support = true;
3883                         intel_dp_dpcd_read_wake(&intel_dp->aux,
3884                                         DP_SINK_DEVICE_AUX_FRAME_SYNC_CAP,
3885                                         &frame_sync_cap, 1);
3886                         dev_priv->psr.aux_frame_sync = frame_sync_cap ? true : false;
3887                         /* PSR2 needs frame sync as well */
3888                         dev_priv->psr.psr2_support = dev_priv->psr.aux_frame_sync;
3889                         DRM_DEBUG_KMS("PSR2 %s on sink",
3890                                 dev_priv->psr.psr2_support ? "supported" : "not supported");
3891                 }
3892         }
3893
3894         DRM_DEBUG_KMS("Display Port TPS3 support: source %s, sink %s\n",
3895                       yesno(intel_dp_source_supports_hbr2(intel_dp)),
3896                       yesno(drm_dp_tps3_supported(intel_dp->dpcd)));
3897
3898         /* Intermediate frequency support */
3899         if (is_edp(intel_dp) &&
3900             (intel_dp->dpcd[DP_EDP_CONFIGURATION_CAP] & DP_DPCD_DISPLAY_CONTROL_CAPABLE) &&
3901             (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_EDP_DPCD_REV, &rev, 1) == 1) &&
3902             (rev >= 0x03)) { /* eDp v1.4 or higher */
3903                 __le16 sink_rates[DP_MAX_SUPPORTED_RATES];
3904                 int i;
3905
3906                 intel_dp_dpcd_read_wake(&intel_dp->aux,
3907                                 DP_SUPPORTED_LINK_RATES,
3908                                 sink_rates,
3909                                 sizeof(sink_rates));
3910
3911                 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) {
3912                         int val = le16_to_cpu(sink_rates[i]);
3913
3914                         if (val == 0)
3915                                 break;
3916
3917                         /* Value read is in kHz while drm clock is saved in deca-kHz */
3918                         intel_dp->sink_rates[i] = (val * 200) / 10;
3919                 }
3920                 intel_dp->num_sink_rates = i;
3921         }
3922
3923         intel_dp_print_rates(intel_dp);
3924
3925         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
3926               DP_DWN_STRM_PORT_PRESENT))
3927                 return true; /* native DP sink */
3928
3929         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
3930                 return true; /* no per-port downstream info */
3931
3932         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_DOWNSTREAM_PORT_0,
3933                                     intel_dp->downstream_ports,
3934                                     DP_MAX_DOWNSTREAM_PORTS) < 0)
3935                 return false; /* downstream port status fetch failed */
3936
3937         return true;
3938 }
3939
3940 static void
3941 intel_dp_probe_oui(struct intel_dp *intel_dp)
3942 {
3943         u8 buf[3];
3944
3945         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
3946                 return;
3947
3948         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_OUI, buf, 3) == 3)
3949                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
3950                               buf[0], buf[1], buf[2]);
3951
3952         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_BRANCH_OUI, buf, 3) == 3)
3953                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
3954                               buf[0], buf[1], buf[2]);
3955 }
3956
3957 static bool
3958 intel_dp_probe_mst(struct intel_dp *intel_dp)
3959 {
3960         u8 buf[1];
3961
3962         if (!intel_dp->can_mst)
3963                 return false;
3964
3965         if (intel_dp->dpcd[DP_DPCD_REV] < 0x12)
3966                 return false;
3967
3968         if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_MSTM_CAP, buf, 1)) {
3969                 if (buf[0] & DP_MST_CAP) {
3970                         DRM_DEBUG_KMS("Sink is MST capable\n");
3971                         intel_dp->is_mst = true;
3972                 } else {
3973                         DRM_DEBUG_KMS("Sink is not MST capable\n");
3974                         intel_dp->is_mst = false;
3975                 }
3976         }
3977
3978         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
3979         return intel_dp->is_mst;
3980 }
3981
3982 static int intel_dp_sink_crc_stop(struct intel_dp *intel_dp)
3983 {
3984         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
3985         struct drm_device *dev = dig_port->base.base.dev;
3986         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
3987         u8 buf;
3988         int ret = 0;
3989         int count = 0;
3990         int attempts = 10;
3991
3992         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0) {
3993                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
3994                 ret = -EIO;
3995                 goto out;
3996         }
3997
3998         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
3999                                buf & ~DP_TEST_SINK_START) < 0) {
4000                 DRM_DEBUG_KMS("Sink CRC couldn't be stopped properly\n");
4001                 ret = -EIO;
4002                 goto out;
4003         }
4004
4005         do {
4006                 intel_wait_for_vblank(dev, intel_crtc->pipe);
4007
4008                 if (drm_dp_dpcd_readb(&intel_dp->aux,
4009                                       DP_TEST_SINK_MISC, &buf) < 0) {
4010                         ret = -EIO;
4011                         goto out;
4012                 }
4013                 count = buf & DP_TEST_COUNT_MASK;
4014         } while (--attempts && count);
4015
4016         if (attempts == 0) {
4017                 DRM_ERROR("TIMEOUT: Sink CRC counter is not zeroed\n");
4018                 ret = -ETIMEDOUT;
4019         }
4020
4021  out:
4022         hsw_enable_ips(intel_crtc);
4023         return ret;
4024 }
4025
4026 static int intel_dp_sink_crc_start(struct intel_dp *intel_dp)
4027 {
4028         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4029         struct drm_device *dev = dig_port->base.base.dev;
4030         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
4031         u8 buf;
4032         int ret;
4033
4034         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK_MISC, &buf) < 0)
4035                 return -EIO;
4036
4037         if (!(buf & DP_TEST_CRC_SUPPORTED))
4038                 return -ENOTTY;
4039
4040         if (drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_SINK, &buf) < 0)
4041                 return -EIO;
4042
4043         if (buf & DP_TEST_SINK_START) {
4044                 ret = intel_dp_sink_crc_stop(intel_dp);
4045                 if (ret)
4046                         return ret;
4047         }
4048
4049         hsw_disable_ips(intel_crtc);
4050
4051         if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_SINK,
4052                                buf | DP_TEST_SINK_START) < 0) {
4053                 hsw_enable_ips(intel_crtc);
4054                 return -EIO;
4055         }
4056
4057         intel_wait_for_vblank(dev, intel_crtc->pipe);
4058         return 0;
4059 }
4060
4061 int intel_dp_sink_crc(struct intel_dp *intel_dp, u8 *crc)
4062 {
4063         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
4064         struct drm_device *dev = dig_port->base.base.dev;
4065         struct intel_crtc *intel_crtc = to_intel_crtc(dig_port->base.base.crtc);
4066         u8 buf;
4067         int count, ret;
4068         int attempts = 6;
4069
4070         ret = intel_dp_sink_crc_start(intel_dp);
4071         if (ret)
4072                 return ret;
4073
4074         do {
4075                 intel_wait_for_vblank(dev, intel_crtc->pipe);
4076
4077                 if (drm_dp_dpcd_readb(&intel_dp->aux,
4078                                       DP_TEST_SINK_MISC, &buf) < 0) {
4079                         ret = -EIO;
4080                         goto stop;
4081                 }
4082                 count = buf & DP_TEST_COUNT_MASK;
4083
4084         } while (--attempts && count == 0);
4085
4086         if (attempts == 0) {
4087                 DRM_ERROR("Panel is unable to calculate any CRC after 6 vblanks\n");
4088                 ret = -ETIMEDOUT;
4089                 goto stop;
4090         }
4091
4092         if (drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_CRC_R_CR, crc, 6) < 0) {
4093                 ret = -EIO;
4094                 goto stop;
4095         }
4096
4097 stop:
4098         intel_dp_sink_crc_stop(intel_dp);
4099         return ret;
4100 }
4101
4102 static bool
4103 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4104 {
4105         return intel_dp_dpcd_read_wake(&intel_dp->aux,
4106                                        DP_DEVICE_SERVICE_IRQ_VECTOR,
4107                                        sink_irq_vector, 1) == 1;
4108 }
4109
4110 static bool
4111 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector)
4112 {
4113         int ret;
4114
4115         ret = intel_dp_dpcd_read_wake(&intel_dp->aux,
4116                                              DP_SINK_COUNT_ESI,
4117                                              sink_irq_vector, 14);
4118         if (ret != 14)
4119                 return false;
4120
4121         return true;
4122 }
4123
4124 static uint8_t intel_dp_autotest_link_training(struct intel_dp *intel_dp)
4125 {
4126         uint8_t test_result = DP_TEST_ACK;
4127         return test_result;
4128 }
4129
4130 static uint8_t intel_dp_autotest_video_pattern(struct intel_dp *intel_dp)
4131 {
4132         uint8_t test_result = DP_TEST_NAK;
4133         return test_result;
4134 }
4135
4136 static uint8_t intel_dp_autotest_edid(struct intel_dp *intel_dp)
4137 {
4138         uint8_t test_result = DP_TEST_NAK;
4139         struct intel_connector *intel_connector = intel_dp->attached_connector;
4140         struct drm_connector *connector = &intel_connector->base;
4141
4142         if (intel_connector->detect_edid == NULL ||
4143             connector->edid_corrupt ||
4144             intel_dp->aux.i2c_defer_count > 6) {
4145                 /* Check EDID read for NACKs, DEFERs and corruption
4146                  * (DP CTS 1.2 Core r1.1)
4147                  *    4.2.2.4 : Failed EDID read, I2C_NAK
4148                  *    4.2.2.5 : Failed EDID read, I2C_DEFER
4149                  *    4.2.2.6 : EDID corruption detected
4150                  * Use failsafe mode for all cases
4151                  */
4152                 if (intel_dp->aux.i2c_nack_count > 0 ||
4153                         intel_dp->aux.i2c_defer_count > 0)
4154                         DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n",
4155                                       intel_dp->aux.i2c_nack_count,
4156                                       intel_dp->aux.i2c_defer_count);
4157                 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_FAILSAFE;
4158         } else {
4159                 struct edid *block = intel_connector->detect_edid;
4160
4161                 /* We have to write the checksum
4162                  * of the last block read
4163                  */
4164                 block += intel_connector->detect_edid->extensions;
4165
4166                 if (!drm_dp_dpcd_write(&intel_dp->aux,
4167                                         DP_TEST_EDID_CHECKSUM,
4168                                         &block->checksum,
4169                                         1))
4170                         DRM_DEBUG_KMS("Failed to write EDID checksum\n");
4171
4172                 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE;
4173                 intel_dp->compliance_test_data = INTEL_DP_RESOLUTION_STANDARD;
4174         }
4175
4176         /* Set test active flag here so userspace doesn't interrupt things */
4177         intel_dp->compliance_test_active = 1;
4178
4179         return test_result;
4180 }
4181
4182 static uint8_t intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp)
4183 {
4184         uint8_t test_result = DP_TEST_NAK;
4185         return test_result;
4186 }
4187
4188 static void intel_dp_handle_test_request(struct intel_dp *intel_dp)
4189 {
4190         uint8_t response = DP_TEST_NAK;
4191         uint8_t rxdata = 0;
4192         int status = 0;
4193
4194         status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_REQUEST, &rxdata, 1);
4195         if (status <= 0) {
4196                 DRM_DEBUG_KMS("Could not read test request from sink\n");
4197                 goto update_status;
4198         }
4199
4200         switch (rxdata) {
4201         case DP_TEST_LINK_TRAINING:
4202                 DRM_DEBUG_KMS("LINK_TRAINING test requested\n");
4203                 intel_dp->compliance_test_type = DP_TEST_LINK_TRAINING;
4204                 response = intel_dp_autotest_link_training(intel_dp);
4205                 break;
4206         case DP_TEST_LINK_VIDEO_PATTERN:
4207                 DRM_DEBUG_KMS("TEST_PATTERN test requested\n");
4208                 intel_dp->compliance_test_type = DP_TEST_LINK_VIDEO_PATTERN;
4209                 response = intel_dp_autotest_video_pattern(intel_dp);
4210                 break;
4211         case DP_TEST_LINK_EDID_READ:
4212                 DRM_DEBUG_KMS("EDID test requested\n");
4213                 intel_dp->compliance_test_type = DP_TEST_LINK_EDID_READ;
4214                 response = intel_dp_autotest_edid(intel_dp);
4215                 break;
4216         case DP_TEST_LINK_PHY_TEST_PATTERN:
4217                 DRM_DEBUG_KMS("PHY_PATTERN test requested\n");
4218                 intel_dp->compliance_test_type = DP_TEST_LINK_PHY_TEST_PATTERN;
4219                 response = intel_dp_autotest_phy_pattern(intel_dp);
4220                 break;
4221         default:
4222                 DRM_DEBUG_KMS("Invalid test request '%02x'\n", rxdata);
4223                 break;
4224         }
4225
4226 update_status:
4227         status = drm_dp_dpcd_write(&intel_dp->aux,
4228                                    DP_TEST_RESPONSE,
4229                                    &response, 1);
4230         if (status <= 0)
4231                 DRM_DEBUG_KMS("Could not write test response to sink\n");
4232 }
4233
4234 static int
4235 intel_dp_check_mst_status(struct intel_dp *intel_dp)
4236 {
4237         bool bret;
4238
4239         if (intel_dp->is_mst) {
4240                 u8 esi[16] = { 0 };
4241                 int ret = 0;
4242                 int retry;
4243                 bool handled;
4244                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4245 go_again:
4246                 if (bret == true) {
4247
4248                         /* check link status - esi[10] = 0x200c */
4249                         if (intel_dp->active_mst_links &&
4250                             !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) {
4251                                 DRM_DEBUG_KMS("channel EQ not ok, retraining\n");
4252                                 intel_dp_start_link_train(intel_dp);
4253                                 intel_dp_stop_link_train(intel_dp);
4254                         }
4255
4256                         DRM_DEBUG_KMS("got esi %3ph\n", esi);
4257                         ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled);
4258
4259                         if (handled) {
4260                                 for (retry = 0; retry < 3; retry++) {
4261                                         int wret;
4262                                         wret = drm_dp_dpcd_write(&intel_dp->aux,
4263                                                                  DP_SINK_COUNT_ESI+1,
4264                                                                  &esi[1], 3);
4265                                         if (wret == 3) {
4266                                                 break;
4267                                         }
4268                                 }
4269
4270                                 bret = intel_dp_get_sink_irq_esi(intel_dp, esi);
4271                                 if (bret == true) {
4272                                         DRM_DEBUG_KMS("got esi2 %3ph\n", esi);
4273                                         goto go_again;
4274                                 }
4275                         } else
4276                                 ret = 0;
4277
4278                         return ret;
4279                 } else {
4280                         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4281                         DRM_DEBUG_KMS("failed to get ESI - device may have failed\n");
4282                         intel_dp->is_mst = false;
4283                         drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
4284                         /* send a hotplug event */
4285                         drm_kms_helper_hotplug_event(intel_dig_port->base.base.dev);
4286                 }
4287         }
4288         return -EINVAL;
4289 }
4290
4291 /*
4292  * According to DP spec
4293  * 5.1.2:
4294  *  1. Read DPCD
4295  *  2. Configure link according to Receiver Capabilities
4296  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
4297  *  4. Check link status on receipt of hot-plug interrupt
4298  */
4299 static void
4300 intel_dp_check_link_status(struct intel_dp *intel_dp)
4301 {
4302         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4303         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4304         u8 sink_irq_vector;
4305         u8 link_status[DP_LINK_STATUS_SIZE];
4306
4307         WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
4308
4309         /*
4310          * Clearing compliance test variables to allow capturing
4311          * of values for next automated test request.
4312          */
4313         intel_dp->compliance_test_active = 0;
4314         intel_dp->compliance_test_type = 0;
4315         intel_dp->compliance_test_data = 0;
4316
4317         if (!intel_encoder->base.crtc)
4318                 return;
4319
4320         if (!to_intel_crtc(intel_encoder->base.crtc)->active)
4321                 return;
4322
4323         /* Try to read receiver status if the link appears to be up */
4324         if (!intel_dp_get_link_status(intel_dp, link_status)) {
4325                 return;
4326         }
4327
4328         /* Now read the DPCD to see if it's actually running */
4329         if (!intel_dp_get_dpcd(intel_dp)) {
4330                 return;
4331         }
4332
4333         /* Try to read the source of the interrupt */
4334         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4335             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4336                 /* Clear interrupt source */
4337                 drm_dp_dpcd_writeb(&intel_dp->aux,
4338                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4339                                    sink_irq_vector);
4340
4341                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4342                         DRM_DEBUG_DRIVER("Test request in short pulse not handled\n");
4343                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4344                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4345         }
4346
4347         /* if link training is requested we should perform it always */
4348         if ((intel_dp->compliance_test_type == DP_TEST_LINK_TRAINING) ||
4349                 (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count))) {
4350                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
4351                               intel_encoder->base.name);
4352                 intel_dp_start_link_train(intel_dp);
4353                 intel_dp_stop_link_train(intel_dp);
4354         }
4355 }
4356
4357 /* XXX this is probably wrong for multiple downstream ports */
4358 static enum drm_connector_status
4359 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
4360 {
4361         uint8_t *dpcd = intel_dp->dpcd;
4362         uint8_t type;
4363
4364         if (!intel_dp_get_dpcd(intel_dp))
4365                 return connector_status_disconnected;
4366
4367         /* if there's no downstream port, we're done */
4368         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
4369                 return connector_status_connected;
4370
4371         /* If we're HPD-aware, SINK_COUNT changes dynamically */
4372         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4373             intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) {
4374                 uint8_t reg;
4375
4376                 if (intel_dp_dpcd_read_wake(&intel_dp->aux, DP_SINK_COUNT,
4377                                             &reg, 1) < 0)
4378                         return connector_status_unknown;
4379
4380                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
4381                                               : connector_status_disconnected;
4382         }
4383
4384         /* If no HPD, poke DDC gently */
4385         if (drm_probe_ddc(&intel_dp->aux.ddc))
4386                 return connector_status_connected;
4387
4388         /* Well we tried, say unknown for unreliable port types */
4389         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) {
4390                 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
4391                 if (type == DP_DS_PORT_TYPE_VGA ||
4392                     type == DP_DS_PORT_TYPE_NON_EDID)
4393                         return connector_status_unknown;
4394         } else {
4395                 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
4396                         DP_DWN_STRM_PORT_TYPE_MASK;
4397                 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG ||
4398                     type == DP_DWN_STRM_PORT_TYPE_OTHER)
4399                         return connector_status_unknown;
4400         }
4401
4402         /* Anything else is out of spec, warn and ignore */
4403         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
4404         return connector_status_disconnected;
4405 }
4406
4407 static enum drm_connector_status
4408 edp_detect(struct intel_dp *intel_dp)
4409 {
4410         struct drm_device *dev = intel_dp_to_dev(intel_dp);
4411         enum drm_connector_status status;
4412
4413         status = intel_panel_detect(dev);
4414         if (status == connector_status_unknown)
4415                 status = connector_status_connected;
4416
4417         return status;
4418 }
4419
4420 static bool ibx_digital_port_connected(struct drm_i915_private *dev_priv,
4421                                        struct intel_digital_port *port)
4422 {
4423         u32 bit;
4424
4425         switch (port->port) {
4426         case PORT_A:
4427                 return true;
4428         case PORT_B:
4429                 bit = SDE_PORTB_HOTPLUG;
4430                 break;
4431         case PORT_C:
4432                 bit = SDE_PORTC_HOTPLUG;
4433                 break;
4434         case PORT_D:
4435                 bit = SDE_PORTD_HOTPLUG;
4436                 break;
4437         default:
4438                 MISSING_CASE(port->port);
4439                 return false;
4440         }
4441
4442         return I915_READ(SDEISR) & bit;
4443 }
4444
4445 static bool cpt_digital_port_connected(struct drm_i915_private *dev_priv,
4446                                        struct intel_digital_port *port)
4447 {
4448         u32 bit;
4449
4450         switch (port->port) {
4451         case PORT_A:
4452                 return true;
4453         case PORT_B:
4454                 bit = SDE_PORTB_HOTPLUG_CPT;
4455                 break;
4456         case PORT_C:
4457                 bit = SDE_PORTC_HOTPLUG_CPT;
4458                 break;
4459         case PORT_D:
4460                 bit = SDE_PORTD_HOTPLUG_CPT;
4461                 break;
4462         case PORT_E:
4463                 bit = SDE_PORTE_HOTPLUG_SPT;
4464                 break;
4465         default:
4466                 MISSING_CASE(port->port);
4467                 return false;
4468         }
4469
4470         return I915_READ(SDEISR) & bit;
4471 }
4472
4473 static bool g4x_digital_port_connected(struct drm_i915_private *dev_priv,
4474                                        struct intel_digital_port *port)
4475 {
4476         u32 bit;
4477
4478         switch (port->port) {
4479         case PORT_B:
4480                 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X;
4481                 break;
4482         case PORT_C:
4483                 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X;
4484                 break;
4485         case PORT_D:
4486                 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X;
4487                 break;
4488         default:
4489                 MISSING_CASE(port->port);
4490                 return false;
4491         }
4492
4493         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4494 }
4495
4496 static bool vlv_digital_port_connected(struct drm_i915_private *dev_priv,
4497                                        struct intel_digital_port *port)
4498 {
4499         u32 bit;
4500
4501         switch (port->port) {
4502         case PORT_B:
4503                 bit = PORTB_HOTPLUG_LIVE_STATUS_VLV;
4504                 break;
4505         case PORT_C:
4506                 bit = PORTC_HOTPLUG_LIVE_STATUS_VLV;
4507                 break;
4508         case PORT_D:
4509                 bit = PORTD_HOTPLUG_LIVE_STATUS_VLV;
4510                 break;
4511         default:
4512                 MISSING_CASE(port->port);
4513                 return false;
4514         }
4515
4516         return I915_READ(PORT_HOTPLUG_STAT) & bit;
4517 }
4518
4519 static bool bxt_digital_port_connected(struct drm_i915_private *dev_priv,
4520                                        struct intel_digital_port *intel_dig_port)
4521 {
4522         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4523         enum port port;
4524         u32 bit;
4525
4526         intel_hpd_pin_to_port(intel_encoder->hpd_pin, &port);
4527         switch (port) {
4528         case PORT_A:
4529                 bit = BXT_DE_PORT_HP_DDIA;
4530                 break;
4531         case PORT_B:
4532                 bit = BXT_DE_PORT_HP_DDIB;
4533                 break;
4534         case PORT_C:
4535                 bit = BXT_DE_PORT_HP_DDIC;
4536                 break;
4537         default:
4538                 MISSING_CASE(port);
4539                 return false;
4540         }
4541
4542         return I915_READ(GEN8_DE_PORT_ISR) & bit;
4543 }
4544
4545 /*
4546  * intel_digital_port_connected - is the specified port connected?
4547  * @dev_priv: i915 private structure
4548  * @port: the port to test
4549  *
4550  * Return %true if @port is connected, %false otherwise.
4551  */
4552 bool intel_digital_port_connected(struct drm_i915_private *dev_priv,
4553                                          struct intel_digital_port *port)
4554 {
4555         if (HAS_PCH_IBX(dev_priv))
4556                 return ibx_digital_port_connected(dev_priv, port);
4557         if (HAS_PCH_SPLIT(dev_priv))
4558                 return cpt_digital_port_connected(dev_priv, port);
4559         else if (IS_BROXTON(dev_priv))
4560                 return bxt_digital_port_connected(dev_priv, port);
4561         else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
4562                 return vlv_digital_port_connected(dev_priv, port);
4563         else
4564                 return g4x_digital_port_connected(dev_priv, port);
4565 }
4566
4567 static struct edid *
4568 intel_dp_get_edid(struct intel_dp *intel_dp)
4569 {
4570         struct intel_connector *intel_connector = intel_dp->attached_connector;
4571
4572         /* use cached edid if we have one */
4573         if (intel_connector->edid) {
4574                 /* invalid edid */
4575                 if (IS_ERR(intel_connector->edid))
4576                         return NULL;
4577
4578                 return drm_edid_duplicate(intel_connector->edid);
4579         } else
4580                 return drm_get_edid(&intel_connector->base,
4581                                     &intel_dp->aux.ddc);
4582 }
4583
4584 static void
4585 intel_dp_set_edid(struct intel_dp *intel_dp)
4586 {
4587         struct intel_connector *intel_connector = intel_dp->attached_connector;
4588         struct edid *edid;
4589
4590         edid = intel_dp_get_edid(intel_dp);
4591         intel_connector->detect_edid = edid;
4592
4593         if (intel_dp->force_audio != HDMI_AUDIO_AUTO)
4594                 intel_dp->has_audio = intel_dp->force_audio == HDMI_AUDIO_ON;
4595         else
4596                 intel_dp->has_audio = drm_detect_monitor_audio(edid);
4597 }
4598
4599 static void
4600 intel_dp_unset_edid(struct intel_dp *intel_dp)
4601 {
4602         struct intel_connector *intel_connector = intel_dp->attached_connector;
4603
4604         kfree(intel_connector->detect_edid);
4605         intel_connector->detect_edid = NULL;
4606
4607         intel_dp->has_audio = false;
4608 }
4609
4610 static enum drm_connector_status
4611 intel_dp_detect(struct drm_connector *connector, bool force)
4612 {
4613         struct intel_dp *intel_dp = intel_attached_dp(connector);
4614         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4615         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4616         struct drm_device *dev = connector->dev;
4617         enum drm_connector_status status;
4618         enum intel_display_power_domain power_domain;
4619         bool ret;
4620         u8 sink_irq_vector;
4621
4622         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4623                       connector->base.id, connector->name);
4624         intel_dp_unset_edid(intel_dp);
4625
4626         if (intel_dp->is_mst) {
4627                 /* MST devices are disconnected from a monitor POV */
4628                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4629                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4630                 return connector_status_disconnected;
4631         }
4632
4633         power_domain = intel_display_port_aux_power_domain(intel_encoder);
4634         intel_display_power_get(to_i915(dev), power_domain);
4635
4636         /* Can't disconnect eDP, but you can close the lid... */
4637         if (is_edp(intel_dp))
4638                 status = edp_detect(intel_dp);
4639         else if (intel_digital_port_connected(to_i915(dev),
4640                                               dp_to_dig_port(intel_dp)))
4641                 status = intel_dp_detect_dpcd(intel_dp);
4642         else
4643                 status = connector_status_disconnected;
4644
4645         if (status != connector_status_connected) {
4646                 intel_dp->compliance_test_active = 0;
4647                 intel_dp->compliance_test_type = 0;
4648                 intel_dp->compliance_test_data = 0;
4649
4650                 goto out;
4651         }
4652
4653         intel_dp_probe_oui(intel_dp);
4654
4655         ret = intel_dp_probe_mst(intel_dp);
4656         if (ret) {
4657                 /* if we are in MST mode then this connector
4658                    won't appear connected or have anything with EDID on it */
4659                 if (intel_encoder->type != INTEL_OUTPUT_EDP)
4660                         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4661                 status = connector_status_disconnected;
4662                 goto out;
4663         }
4664
4665         /*
4666          * Clearing NACK and defer counts to get their exact values
4667          * while reading EDID which are required by Compliance tests
4668          * 4.2.2.4 and 4.2.2.5
4669          */
4670         intel_dp->aux.i2c_nack_count = 0;
4671         intel_dp->aux.i2c_defer_count = 0;
4672
4673         intel_dp_set_edid(intel_dp);
4674
4675         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4676                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4677         status = connector_status_connected;
4678
4679         /* Try to read the source of the interrupt */
4680         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
4681             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
4682                 /* Clear interrupt source */
4683                 drm_dp_dpcd_writeb(&intel_dp->aux,
4684                                    DP_DEVICE_SERVICE_IRQ_VECTOR,
4685                                    sink_irq_vector);
4686
4687                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
4688                         intel_dp_handle_test_request(intel_dp);
4689                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
4690                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
4691         }
4692
4693 out:
4694         intel_display_power_put(to_i915(dev), power_domain);
4695         return status;
4696 }
4697
4698 static void
4699 intel_dp_force(struct drm_connector *connector)
4700 {
4701         struct intel_dp *intel_dp = intel_attached_dp(connector);
4702         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
4703         struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev);
4704         enum intel_display_power_domain power_domain;
4705
4706         DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
4707                       connector->base.id, connector->name);
4708         intel_dp_unset_edid(intel_dp);
4709
4710         if (connector->status != connector_status_connected)
4711                 return;
4712
4713         power_domain = intel_display_port_aux_power_domain(intel_encoder);
4714         intel_display_power_get(dev_priv, power_domain);
4715
4716         intel_dp_set_edid(intel_dp);
4717
4718         intel_display_power_put(dev_priv, power_domain);
4719
4720         if (intel_encoder->type != INTEL_OUTPUT_EDP)
4721                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
4722 }
4723
4724 static int intel_dp_get_modes(struct drm_connector *connector)
4725 {
4726         struct intel_connector *intel_connector = to_intel_connector(connector);
4727         struct edid *edid;
4728
4729         edid = intel_connector->detect_edid;
4730         if (edid) {
4731                 int ret = intel_connector_update_modes(connector, edid);
4732                 if (ret)
4733                         return ret;
4734         }
4735
4736         /* if eDP has no EDID, fall back to fixed mode */
4737         if (is_edp(intel_attached_dp(connector)) &&
4738             intel_connector->panel.fixed_mode) {
4739                 struct drm_display_mode *mode;
4740
4741                 mode = drm_mode_duplicate(connector->dev,
4742                                           intel_connector->panel.fixed_mode);
4743                 if (mode) {
4744                         drm_mode_probed_add(connector, mode);
4745                         return 1;
4746                 }
4747         }
4748
4749         return 0;
4750 }
4751
4752 static bool
4753 intel_dp_detect_audio(struct drm_connector *connector)
4754 {
4755         bool has_audio = false;
4756         struct edid *edid;
4757
4758         edid = to_intel_connector(connector)->detect_edid;
4759         if (edid)
4760                 has_audio = drm_detect_monitor_audio(edid);
4761
4762         return has_audio;
4763 }
4764
4765 static int
4766 intel_dp_set_property(struct drm_connector *connector,
4767                       struct drm_property *property,
4768                       uint64_t val)
4769 {
4770         struct drm_i915_private *dev_priv = connector->dev->dev_private;
4771         struct intel_connector *intel_connector = to_intel_connector(connector);
4772         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
4773         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4774         int ret;
4775
4776         ret = drm_object_property_set_value(&connector->base, property, val);
4777         if (ret)
4778                 return ret;
4779
4780         if (property == dev_priv->force_audio_property) {
4781                 int i = val;
4782                 bool has_audio;
4783
4784                 if (i == intel_dp->force_audio)
4785                         return 0;
4786
4787                 intel_dp->force_audio = i;
4788
4789                 if (i == HDMI_AUDIO_AUTO)
4790                         has_audio = intel_dp_detect_audio(connector);
4791                 else
4792                         has_audio = (i == HDMI_AUDIO_ON);
4793
4794                 if (has_audio == intel_dp->has_audio)
4795                         return 0;
4796
4797                 intel_dp->has_audio = has_audio;
4798                 goto done;
4799         }
4800
4801         if (property == dev_priv->broadcast_rgb_property) {
4802                 bool old_auto = intel_dp->color_range_auto;
4803                 bool old_range = intel_dp->limited_color_range;
4804
4805                 switch (val) {
4806                 case INTEL_BROADCAST_RGB_AUTO:
4807                         intel_dp->color_range_auto = true;
4808                         break;
4809                 case INTEL_BROADCAST_RGB_FULL:
4810                         intel_dp->color_range_auto = false;
4811                         intel_dp->limited_color_range = false;
4812                         break;
4813                 case INTEL_BROADCAST_RGB_LIMITED:
4814                         intel_dp->color_range_auto = false;
4815                         intel_dp->limited_color_range = true;
4816                         break;
4817                 default:
4818                         return -EINVAL;
4819                 }
4820
4821                 if (old_auto == intel_dp->color_range_auto &&
4822                     old_range == intel_dp->limited_color_range)
4823                         return 0;
4824
4825                 goto done;
4826         }
4827
4828         if (is_edp(intel_dp) &&
4829             property == connector->dev->mode_config.scaling_mode_property) {
4830                 if (val == DRM_MODE_SCALE_NONE) {
4831                         DRM_DEBUG_KMS("no scaling not supported\n");
4832                         return -EINVAL;
4833                 }
4834
4835                 if (intel_connector->panel.fitting_mode == val) {
4836                         /* the eDP scaling property is not changed */
4837                         return 0;
4838                 }
4839                 intel_connector->panel.fitting_mode = val;
4840
4841                 goto done;
4842         }
4843
4844         return -EINVAL;
4845
4846 done:
4847         if (intel_encoder->base.crtc)
4848                 intel_crtc_restore_mode(intel_encoder->base.crtc);
4849
4850         return 0;
4851 }
4852
4853 static void
4854 intel_dp_connector_destroy(struct drm_connector *connector)
4855 {
4856         struct intel_connector *intel_connector = to_intel_connector(connector);
4857
4858         kfree(intel_connector->detect_edid);
4859
4860         if (!IS_ERR_OR_NULL(intel_connector->edid))
4861                 kfree(intel_connector->edid);
4862
4863         /* Can't call is_edp() since the encoder may have been destroyed
4864          * already. */
4865         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
4866                 intel_panel_fini(&intel_connector->panel);
4867
4868         drm_connector_cleanup(connector);
4869         kfree(connector);
4870 }
4871
4872 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
4873 {
4874         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
4875         struct intel_dp *intel_dp = &intel_dig_port->dp;
4876
4877         intel_dp_aux_fini(intel_dp);
4878         intel_dp_mst_encoder_cleanup(intel_dig_port);
4879         if (is_edp(intel_dp)) {
4880                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4881                 /*
4882                  * vdd might still be enabled do to the delayed vdd off.
4883                  * Make sure vdd is actually turned off here.
4884                  */
4885                 pps_lock(intel_dp);
4886                 edp_panel_vdd_off_sync(intel_dp);
4887                 pps_unlock(intel_dp);
4888
4889                 if (intel_dp->edp_notifier.notifier_call) {
4890                         unregister_reboot_notifier(&intel_dp->edp_notifier);
4891                         intel_dp->edp_notifier.notifier_call = NULL;
4892                 }
4893         }
4894         drm_encoder_cleanup(encoder);
4895         kfree(intel_dig_port);
4896 }
4897
4898 static void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder)
4899 {
4900         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
4901
4902         if (!is_edp(intel_dp))
4903                 return;
4904
4905         /*
4906          * vdd might still be enabled do to the delayed vdd off.
4907          * Make sure vdd is actually turned off here.
4908          */
4909         cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
4910         pps_lock(intel_dp);
4911         edp_panel_vdd_off_sync(intel_dp);
4912         pps_unlock(intel_dp);
4913 }
4914
4915 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp)
4916 {
4917         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
4918         struct drm_device *dev = intel_dig_port->base.base.dev;
4919         struct drm_i915_private *dev_priv = dev->dev_private;
4920         enum intel_display_power_domain power_domain;
4921
4922         lockdep_assert_held(&dev_priv->pps_mutex);
4923
4924         if (!edp_have_panel_vdd(intel_dp))
4925                 return;
4926
4927         /*
4928          * The VDD bit needs a power domain reference, so if the bit is
4929          * already enabled when we boot or resume, grab this reference and
4930          * schedule a vdd off, so we don't hold on to the reference
4931          * indefinitely.
4932          */
4933         DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n");
4934         power_domain = intel_display_port_aux_power_domain(&intel_dig_port->base);
4935         intel_display_power_get(dev_priv, power_domain);
4936
4937         edp_panel_vdd_schedule_off(intel_dp);
4938 }
4939
4940 static void intel_dp_encoder_reset(struct drm_encoder *encoder)
4941 {
4942         struct intel_dp *intel_dp;
4943
4944         if (to_intel_encoder(encoder)->type != INTEL_OUTPUT_EDP)
4945                 return;
4946
4947         intel_dp = enc_to_intel_dp(encoder);
4948
4949         pps_lock(intel_dp);
4950
4951         /*
4952          * Read out the current power sequencer assignment,
4953          * in case the BIOS did something with it.
4954          */
4955         if (IS_VALLEYVIEW(encoder->dev) || IS_CHERRYVIEW(encoder->dev))
4956                 vlv_initial_power_sequencer_setup(intel_dp);
4957
4958         intel_edp_panel_vdd_sanitize(intel_dp);
4959
4960         pps_unlock(intel_dp);
4961 }
4962
4963 static const struct drm_connector_funcs intel_dp_connector_funcs = {
4964         .dpms = drm_atomic_helper_connector_dpms,
4965         .detect = intel_dp_detect,
4966         .force = intel_dp_force,
4967         .fill_modes = drm_helper_probe_single_connector_modes,
4968         .set_property = intel_dp_set_property,
4969         .atomic_get_property = intel_connector_atomic_get_property,
4970         .destroy = intel_dp_connector_destroy,
4971         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
4972         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
4973 };
4974
4975 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
4976         .get_modes = intel_dp_get_modes,
4977         .mode_valid = intel_dp_mode_valid,
4978         .best_encoder = intel_best_encoder,
4979 };
4980
4981 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
4982         .reset = intel_dp_encoder_reset,
4983         .destroy = intel_dp_encoder_destroy,
4984 };
4985
4986 enum irqreturn
4987 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd)
4988 {
4989         struct intel_dp *intel_dp = &intel_dig_port->dp;
4990         struct intel_encoder *intel_encoder = &intel_dig_port->base;
4991         struct drm_device *dev = intel_dig_port->base.base.dev;
4992         struct drm_i915_private *dev_priv = dev->dev_private;
4993         enum intel_display_power_domain power_domain;
4994         enum irqreturn ret = IRQ_NONE;
4995
4996         if (intel_dig_port->base.type != INTEL_OUTPUT_EDP &&
4997             intel_dig_port->base.type != INTEL_OUTPUT_HDMI)
4998                 intel_dig_port->base.type = INTEL_OUTPUT_DISPLAYPORT;
4999
5000         if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) {
5001                 /*
5002                  * vdd off can generate a long pulse on eDP which
5003                  * would require vdd on to handle it, and thus we
5004                  * would end up in an endless cycle of
5005                  * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..."
5006                  */
5007                 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n",
5008                               port_name(intel_dig_port->port));
5009                 return IRQ_HANDLED;
5010         }
5011
5012         DRM_DEBUG_KMS("got hpd irq on port %c - %s\n",
5013                       port_name(intel_dig_port->port),
5014                       long_hpd ? "long" : "short");
5015
5016         power_domain = intel_display_port_aux_power_domain(intel_encoder);
5017         intel_display_power_get(dev_priv, power_domain);
5018
5019         if (long_hpd) {
5020                 /* indicate that we need to restart link training */
5021                 intel_dp->train_set_valid = false;
5022
5023                 if (!intel_digital_port_connected(dev_priv, intel_dig_port))
5024                         goto mst_fail;
5025
5026                 if (!intel_dp_get_dpcd(intel_dp)) {
5027                         goto mst_fail;
5028                 }
5029
5030                 intel_dp_probe_oui(intel_dp);
5031
5032                 if (!intel_dp_probe_mst(intel_dp)) {
5033                         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
5034                         intel_dp_check_link_status(intel_dp);
5035                         drm_modeset_unlock(&dev->mode_config.connection_mutex);
5036                         goto mst_fail;
5037                 }
5038         } else {
5039                 if (intel_dp->is_mst) {
5040                         if (intel_dp_check_mst_status(intel_dp) == -EINVAL)
5041                                 goto mst_fail;
5042                 }
5043
5044                 if (!intel_dp->is_mst) {
5045                         drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
5046                         intel_dp_check_link_status(intel_dp);
5047                         drm_modeset_unlock(&dev->mode_config.connection_mutex);
5048                 }
5049         }
5050
5051         ret = IRQ_HANDLED;
5052
5053         goto put_power;
5054 mst_fail:
5055         /* if we were in MST mode, and device is not there get out of MST mode */
5056         if (intel_dp->is_mst) {
5057                 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", intel_dp->is_mst, intel_dp->mst_mgr.mst_state);
5058                 intel_dp->is_mst = false;
5059                 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, intel_dp->is_mst);
5060         }
5061 put_power:
5062         intel_display_power_put(dev_priv, power_domain);
5063
5064         return ret;
5065 }
5066
5067 /* check the VBT to see whether the eDP is on another port */
5068 bool intel_dp_is_edp(struct drm_device *dev, enum port port)
5069 {
5070         struct drm_i915_private *dev_priv = dev->dev_private;
5071         union child_device_config *p_child;
5072         int i;
5073         static const short port_mapping[] = {
5074                 [PORT_B] = DVO_PORT_DPB,
5075                 [PORT_C] = DVO_PORT_DPC,
5076                 [PORT_D] = DVO_PORT_DPD,
5077                 [PORT_E] = DVO_PORT_DPE,
5078         };
5079
5080         /*
5081          * eDP not supported on g4x. so bail out early just
5082          * for a bit extra safety in case the VBT is bonkers.
5083          */
5084         if (INTEL_INFO(dev)->gen < 5)
5085                 return false;
5086
5087         if (port == PORT_A)
5088                 return true;
5089
5090         if (!dev_priv->vbt.child_dev_num)
5091                 return false;
5092
5093         for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
5094                 p_child = dev_priv->vbt.child_dev + i;
5095
5096                 if (p_child->common.dvo_port == port_mapping[port] &&
5097                     (p_child->common.device_type & DEVICE_TYPE_eDP_BITS) ==
5098                     (DEVICE_TYPE_eDP & DEVICE_TYPE_eDP_BITS))
5099                         return true;
5100         }
5101         return false;
5102 }
5103
5104 void
5105 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
5106 {
5107         struct intel_connector *intel_connector = to_intel_connector(connector);
5108
5109         intel_attach_force_audio_property(connector);
5110         intel_attach_broadcast_rgb_property(connector);
5111         intel_dp->color_range_auto = true;
5112
5113         if (is_edp(intel_dp)) {
5114                 drm_mode_create_scaling_mode_property(connector->dev);
5115                 drm_object_attach_property(
5116                         &connector->base,
5117                         connector->dev->mode_config.scaling_mode_property,
5118                         DRM_MODE_SCALE_ASPECT);
5119                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
5120         }
5121 }
5122
5123 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp)
5124 {
5125         intel_dp->last_power_cycle = jiffies;
5126         intel_dp->last_power_on = jiffies;
5127         intel_dp->last_backlight_off = jiffies;
5128 }
5129
5130 static void
5131 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
5132                                     struct intel_dp *intel_dp)
5133 {
5134         struct drm_i915_private *dev_priv = dev->dev_private;
5135         struct edp_power_seq cur, vbt, spec,
5136                 *final = &intel_dp->pps_delays;
5137         u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
5138         i915_reg_t pp_ctrl_reg, pp_on_reg, pp_off_reg, pp_div_reg;
5139
5140         lockdep_assert_held(&dev_priv->pps_mutex);
5141
5142         /* already initialized? */
5143         if (final->t11_t12 != 0)
5144                 return;
5145
5146         if (IS_BROXTON(dev)) {
5147                 /*
5148                  * TODO: BXT has 2 sets of PPS registers.
5149                  * Correct Register for Broxton need to be identified
5150                  * using VBT. hardcoding for now
5151                  */
5152                 pp_ctrl_reg = BXT_PP_CONTROL(0);
5153                 pp_on_reg = BXT_PP_ON_DELAYS(0);
5154                 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5155         } else if (HAS_PCH_SPLIT(dev)) {
5156                 pp_ctrl_reg = PCH_PP_CONTROL;
5157                 pp_on_reg = PCH_PP_ON_DELAYS;
5158                 pp_off_reg = PCH_PP_OFF_DELAYS;
5159                 pp_div_reg = PCH_PP_DIVISOR;
5160         } else {
5161                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5162
5163                 pp_ctrl_reg = VLV_PIPE_PP_CONTROL(pipe);
5164                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5165                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5166                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
5167         }
5168
5169         /* Workaround: Need to write PP_CONTROL with the unlock key as
5170          * the very first thing. */
5171         pp_ctl = ironlake_get_pp_control(intel_dp);
5172
5173         pp_on = I915_READ(pp_on_reg);
5174         pp_off = I915_READ(pp_off_reg);
5175         if (!IS_BROXTON(dev)) {
5176                 I915_WRITE(pp_ctrl_reg, pp_ctl);
5177                 pp_div = I915_READ(pp_div_reg);
5178         }
5179
5180         /* Pull timing values out of registers */
5181         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
5182                 PANEL_POWER_UP_DELAY_SHIFT;
5183
5184         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
5185                 PANEL_LIGHT_ON_DELAY_SHIFT;
5186
5187         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
5188                 PANEL_LIGHT_OFF_DELAY_SHIFT;
5189
5190         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
5191                 PANEL_POWER_DOWN_DELAY_SHIFT;
5192
5193         if (IS_BROXTON(dev)) {
5194                 u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >>
5195                         BXT_POWER_CYCLE_DELAY_SHIFT;
5196                 if (tmp > 0)
5197                         cur.t11_t12 = (tmp - 1) * 1000;
5198                 else
5199                         cur.t11_t12 = 0;
5200         } else {
5201                 cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
5202                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
5203         }
5204
5205         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5206                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
5207
5208         vbt = dev_priv->vbt.edp_pps;
5209
5210         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
5211          * our hw here, which are all in 100usec. */
5212         spec.t1_t3 = 210 * 10;
5213         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
5214         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
5215         spec.t10 = 500 * 10;
5216         /* This one is special and actually in units of 100ms, but zero
5217          * based in the hw (so we need to add 100 ms). But the sw vbt
5218          * table multiplies it with 1000 to make it in units of 100usec,
5219          * too. */
5220         spec.t11_t12 = (510 + 100) * 10;
5221
5222         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
5223                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
5224
5225         /* Use the max of the register settings and vbt. If both are
5226          * unset, fall back to the spec limits. */
5227 #define assign_final(field)     final->field = (max(cur.field, vbt.field) == 0 ? \
5228                                        spec.field : \
5229                                        max(cur.field, vbt.field))
5230         assign_final(t1_t3);
5231         assign_final(t8);
5232         assign_final(t9);
5233         assign_final(t10);
5234         assign_final(t11_t12);
5235 #undef assign_final
5236
5237 #define get_delay(field)        (DIV_ROUND_UP(final->field, 10))
5238         intel_dp->panel_power_up_delay = get_delay(t1_t3);
5239         intel_dp->backlight_on_delay = get_delay(t8);
5240         intel_dp->backlight_off_delay = get_delay(t9);
5241         intel_dp->panel_power_down_delay = get_delay(t10);
5242         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
5243 #undef get_delay
5244
5245         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
5246                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
5247                       intel_dp->panel_power_cycle_delay);
5248
5249         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
5250                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
5251 }
5252
5253 static void
5254 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
5255                                               struct intel_dp *intel_dp)
5256 {
5257         struct drm_i915_private *dev_priv = dev->dev_private;
5258         u32 pp_on, pp_off, pp_div, port_sel = 0;
5259         int div = HAS_PCH_SPLIT(dev) ? intel_pch_rawclk(dev) : intel_hrawclk(dev);
5260         i915_reg_t pp_on_reg, pp_off_reg, pp_div_reg, pp_ctrl_reg;
5261         enum port port = dp_to_dig_port(intel_dp)->port;
5262         const struct edp_power_seq *seq = &intel_dp->pps_delays;
5263
5264         lockdep_assert_held(&dev_priv->pps_mutex);
5265
5266         if (IS_BROXTON(dev)) {
5267                 /*
5268                  * TODO: BXT has 2 sets of PPS registers.
5269                  * Correct Register for Broxton need to be identified
5270                  * using VBT. hardcoding for now
5271                  */
5272                 pp_ctrl_reg = BXT_PP_CONTROL(0);
5273                 pp_on_reg = BXT_PP_ON_DELAYS(0);
5274                 pp_off_reg = BXT_PP_OFF_DELAYS(0);
5275
5276         } else if (HAS_PCH_SPLIT(dev)) {
5277                 pp_on_reg = PCH_PP_ON_DELAYS;
5278                 pp_off_reg = PCH_PP_OFF_DELAYS;
5279                 pp_div_reg = PCH_PP_DIVISOR;
5280         } else {
5281                 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp);
5282
5283                 pp_on_reg = VLV_PIPE_PP_ON_DELAYS(pipe);
5284                 pp_off_reg = VLV_PIPE_PP_OFF_DELAYS(pipe);
5285                 pp_div_reg = VLV_PIPE_PP_DIVISOR(pipe);
5286         }
5287
5288         /*
5289          * And finally store the new values in the power sequencer. The
5290          * backlight delays are set to 1 because we do manual waits on them. For
5291          * T8, even BSpec recommends doing it. For T9, if we don't do this,
5292          * we'll end up waiting for the backlight off delay twice: once when we
5293          * do the manual sleep, and once when we disable the panel and wait for
5294          * the PP_STATUS bit to become zero.
5295          */
5296         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
5297                 (1 << PANEL_LIGHT_ON_DELAY_SHIFT);
5298         pp_off = (1 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
5299                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
5300         /* Compute the divisor for the pp clock, simply match the Bspec
5301          * formula. */
5302         if (IS_BROXTON(dev)) {
5303                 pp_div = I915_READ(pp_ctrl_reg);
5304                 pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
5305                 pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000)
5306                                 << BXT_POWER_CYCLE_DELAY_SHIFT);
5307         } else {
5308                 pp_div = ((100 * div)/2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
5309                 pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
5310                                 << PANEL_POWER_CYCLE_DELAY_SHIFT);
5311         }
5312
5313         /* Haswell doesn't have any port selection bits for the panel
5314          * power sequencer any more. */
5315         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5316                 port_sel = PANEL_PORT_SELECT_VLV(port);
5317         } else if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5318                 if (port == PORT_A)
5319                         port_sel = PANEL_PORT_SELECT_DPA;
5320                 else
5321                         port_sel = PANEL_PORT_SELECT_DPD;
5322         }
5323
5324         pp_on |= port_sel;
5325
5326         I915_WRITE(pp_on_reg, pp_on);
5327         I915_WRITE(pp_off_reg, pp_off);
5328         if (IS_BROXTON(dev))
5329                 I915_WRITE(pp_ctrl_reg, pp_div);
5330         else
5331                 I915_WRITE(pp_div_reg, pp_div);
5332
5333         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
5334                       I915_READ(pp_on_reg),
5335                       I915_READ(pp_off_reg),
5336                       IS_BROXTON(dev) ?
5337                       (I915_READ(pp_ctrl_reg) & BXT_POWER_CYCLE_DELAY_MASK) :
5338                       I915_READ(pp_div_reg));
5339 }
5340
5341 /**
5342  * intel_dp_set_drrs_state - program registers for RR switch to take effect
5343  * @dev: DRM device
5344  * @refresh_rate: RR to be programmed
5345  *
5346  * This function gets called when refresh rate (RR) has to be changed from
5347  * one frequency to another. Switches can be between high and low RR
5348  * supported by the panel or to any other RR based on media playback (in
5349  * this case, RR value needs to be passed from user space).
5350  *
5351  * The caller of this function needs to take a lock on dev_priv->drrs.
5352  */
5353 static void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate)
5354 {
5355         struct drm_i915_private *dev_priv = dev->dev_private;
5356         struct intel_encoder *encoder;
5357         struct intel_digital_port *dig_port = NULL;
5358         struct intel_dp *intel_dp = dev_priv->drrs.dp;
5359         struct intel_crtc_state *config = NULL;
5360         struct intel_crtc *intel_crtc = NULL;
5361         enum drrs_refresh_rate_type index = DRRS_HIGH_RR;
5362
5363         if (refresh_rate <= 0) {
5364                 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n");
5365                 return;
5366         }
5367
5368         if (intel_dp == NULL) {
5369                 DRM_DEBUG_KMS("DRRS not supported.\n");
5370                 return;
5371         }
5372
5373         /*
5374          * FIXME: This needs proper synchronization with psr state for some
5375          * platforms that cannot have PSR and DRRS enabled at the same time.
5376          */
5377
5378         dig_port = dp_to_dig_port(intel_dp);
5379         encoder = &dig_port->base;
5380         intel_crtc = to_intel_crtc(encoder->base.crtc);
5381
5382         if (!intel_crtc) {
5383                 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n");
5384                 return;
5385         }
5386
5387         config = intel_crtc->config;
5388
5389         if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) {
5390                 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n");
5391                 return;
5392         }
5393
5394         if (intel_dp->attached_connector->panel.downclock_mode->vrefresh ==
5395                         refresh_rate)
5396                 index = DRRS_LOW_RR;
5397
5398         if (index == dev_priv->drrs.refresh_rate_type) {
5399                 DRM_DEBUG_KMS(
5400                         "DRRS requested for previously set RR...ignoring\n");
5401                 return;
5402         }
5403
5404         if (!intel_crtc->active) {
5405                 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n");
5406                 return;
5407         }
5408
5409         if (INTEL_INFO(dev)->gen >= 8 && !IS_CHERRYVIEW(dev)) {
5410                 switch (index) {
5411                 case DRRS_HIGH_RR:
5412                         intel_dp_set_m_n(intel_crtc, M1_N1);
5413                         break;
5414                 case DRRS_LOW_RR:
5415                         intel_dp_set_m_n(intel_crtc, M2_N2);
5416                         break;
5417                 case DRRS_MAX_RR:
5418                 default:
5419                         DRM_ERROR("Unsupported refreshrate type\n");
5420                 }
5421         } else if (INTEL_INFO(dev)->gen > 6) {
5422                 i915_reg_t reg = PIPECONF(intel_crtc->config->cpu_transcoder);
5423                 u32 val;
5424
5425                 val = I915_READ(reg);
5426                 if (index > DRRS_HIGH_RR) {
5427                         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
5428                                 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5429                         else
5430                                 val |= PIPECONF_EDP_RR_MODE_SWITCH;
5431                 } else {
5432                         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
5433                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV;
5434                         else
5435                                 val &= ~PIPECONF_EDP_RR_MODE_SWITCH;
5436                 }
5437                 I915_WRITE(reg, val);
5438         }
5439
5440         dev_priv->drrs.refresh_rate_type = index;
5441
5442         DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate);
5443 }
5444
5445 /**
5446  * intel_edp_drrs_enable - init drrs struct if supported
5447  * @intel_dp: DP struct
5448  *
5449  * Initializes frontbuffer_bits and drrs.dp
5450  */
5451 void intel_edp_drrs_enable(struct intel_dp *intel_dp)
5452 {
5453         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5454         struct drm_i915_private *dev_priv = dev->dev_private;
5455         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5456         struct drm_crtc *crtc = dig_port->base.base.crtc;
5457         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5458
5459         if (!intel_crtc->config->has_drrs) {
5460                 DRM_DEBUG_KMS("Panel doesn't support DRRS\n");
5461                 return;
5462         }
5463
5464         mutex_lock(&dev_priv->drrs.mutex);
5465         if (WARN_ON(dev_priv->drrs.dp)) {
5466                 DRM_ERROR("DRRS already enabled\n");
5467                 goto unlock;
5468         }
5469
5470         dev_priv->drrs.busy_frontbuffer_bits = 0;
5471
5472         dev_priv->drrs.dp = intel_dp;
5473
5474 unlock:
5475         mutex_unlock(&dev_priv->drrs.mutex);
5476 }
5477
5478 /**
5479  * intel_edp_drrs_disable - Disable DRRS
5480  * @intel_dp: DP struct
5481  *
5482  */
5483 void intel_edp_drrs_disable(struct intel_dp *intel_dp)
5484 {
5485         struct drm_device *dev = intel_dp_to_dev(intel_dp);
5486         struct drm_i915_private *dev_priv = dev->dev_private;
5487         struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
5488         struct drm_crtc *crtc = dig_port->base.base.crtc;
5489         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5490
5491         if (!intel_crtc->config->has_drrs)
5492                 return;
5493
5494         mutex_lock(&dev_priv->drrs.mutex);
5495         if (!dev_priv->drrs.dp) {
5496                 mutex_unlock(&dev_priv->drrs.mutex);
5497                 return;
5498         }
5499
5500         if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5501                 intel_dp_set_drrs_state(dev_priv->dev,
5502                         intel_dp->attached_connector->panel.
5503                         fixed_mode->vrefresh);
5504
5505         dev_priv->drrs.dp = NULL;
5506         mutex_unlock(&dev_priv->drrs.mutex);
5507
5508         cancel_delayed_work_sync(&dev_priv->drrs.work);
5509 }
5510
5511 static void intel_edp_drrs_downclock_work(struct work_struct *work)
5512 {
5513         struct drm_i915_private *dev_priv =
5514                 container_of(work, typeof(*dev_priv), drrs.work.work);
5515         struct intel_dp *intel_dp;
5516
5517         mutex_lock(&dev_priv->drrs.mutex);
5518
5519         intel_dp = dev_priv->drrs.dp;
5520
5521         if (!intel_dp)
5522                 goto unlock;
5523
5524         /*
5525          * The delayed work can race with an invalidate hence we need to
5526          * recheck.
5527          */
5528
5529         if (dev_priv->drrs.busy_frontbuffer_bits)
5530                 goto unlock;
5531
5532         if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR)
5533                 intel_dp_set_drrs_state(dev_priv->dev,
5534                         intel_dp->attached_connector->panel.
5535                         downclock_mode->vrefresh);
5536
5537 unlock:
5538         mutex_unlock(&dev_priv->drrs.mutex);
5539 }
5540
5541 /**
5542  * intel_edp_drrs_invalidate - Disable Idleness DRRS
5543  * @dev: DRM device
5544  * @frontbuffer_bits: frontbuffer plane tracking bits
5545  *
5546  * This function gets called everytime rendering on the given planes start.
5547  * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR).
5548  *
5549  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5550  */
5551 void intel_edp_drrs_invalidate(struct drm_device *dev,
5552                 unsigned frontbuffer_bits)
5553 {
5554         struct drm_i915_private *dev_priv = dev->dev_private;
5555         struct drm_crtc *crtc;
5556         enum pipe pipe;
5557
5558         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5559                 return;
5560
5561         cancel_delayed_work(&dev_priv->drrs.work);
5562
5563         mutex_lock(&dev_priv->drrs.mutex);
5564         if (!dev_priv->drrs.dp) {
5565                 mutex_unlock(&dev_priv->drrs.mutex);
5566                 return;
5567         }
5568
5569         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5570         pipe = to_intel_crtc(crtc)->pipe;
5571
5572         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5573         dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits;
5574
5575         /* invalidate means busy screen hence upclock */
5576         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5577                 intel_dp_set_drrs_state(dev_priv->dev,
5578                                 dev_priv->drrs.dp->attached_connector->panel.
5579                                 fixed_mode->vrefresh);
5580
5581         mutex_unlock(&dev_priv->drrs.mutex);
5582 }
5583
5584 /**
5585  * intel_edp_drrs_flush - Restart Idleness DRRS
5586  * @dev: DRM device
5587  * @frontbuffer_bits: frontbuffer plane tracking bits
5588  *
5589  * This function gets called every time rendering on the given planes has
5590  * completed or flip on a crtc is completed. So DRRS should be upclocked
5591  * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again,
5592  * if no other planes are dirty.
5593  *
5594  * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits.
5595  */
5596 void intel_edp_drrs_flush(struct drm_device *dev,
5597                 unsigned frontbuffer_bits)
5598 {
5599         struct drm_i915_private *dev_priv = dev->dev_private;
5600         struct drm_crtc *crtc;
5601         enum pipe pipe;
5602
5603         if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED)
5604                 return;
5605
5606         cancel_delayed_work(&dev_priv->drrs.work);
5607
5608         mutex_lock(&dev_priv->drrs.mutex);
5609         if (!dev_priv->drrs.dp) {
5610                 mutex_unlock(&dev_priv->drrs.mutex);
5611                 return;
5612         }
5613
5614         crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc;
5615         pipe = to_intel_crtc(crtc)->pipe;
5616
5617         frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
5618         dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits;
5619
5620         /* flush means busy screen hence upclock */
5621         if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR)
5622                 intel_dp_set_drrs_state(dev_priv->dev,
5623                                 dev_priv->drrs.dp->attached_connector->panel.
5624                                 fixed_mode->vrefresh);
5625
5626         /*
5627          * flush also means no more activity hence schedule downclock, if all
5628          * other fbs are quiescent too
5629          */
5630         if (!dev_priv->drrs.busy_frontbuffer_bits)
5631                 schedule_delayed_work(&dev_priv->drrs.work,
5632                                 msecs_to_jiffies(1000));
5633         mutex_unlock(&dev_priv->drrs.mutex);
5634 }
5635
5636 /**
5637  * DOC: Display Refresh Rate Switching (DRRS)
5638  *
5639  * Display Refresh Rate Switching (DRRS) is a power conservation feature
5640  * which enables swtching between low and high refresh rates,
5641  * dynamically, based on the usage scenario. This feature is applicable
5642  * for internal panels.
5643  *
5644  * Indication that the panel supports DRRS is given by the panel EDID, which
5645  * would list multiple refresh rates for one resolution.
5646  *
5647  * DRRS is of 2 types - static and seamless.
5648  * Static DRRS involves changing refresh rate (RR) by doing a full modeset
5649  * (may appear as a blink on screen) and is used in dock-undock scenario.
5650  * Seamless DRRS involves changing RR without any visual effect to the user
5651  * and can be used during normal system usage. This is done by programming
5652  * certain registers.
5653  *
5654  * Support for static/seamless DRRS may be indicated in the VBT based on
5655  * inputs from the panel spec.
5656  *
5657  * DRRS saves power by switching to low RR based on usage scenarios.
5658  *
5659  * eDP DRRS:-
5660  *        The implementation is based on frontbuffer tracking implementation.
5661  * When there is a disturbance on the screen triggered by user activity or a
5662  * periodic system activity, DRRS is disabled (RR is changed to high RR).
5663  * When there is no movement on screen, after a timeout of 1 second, a switch
5664  * to low RR is made.
5665  *        For integration with frontbuffer tracking code,
5666  * intel_edp_drrs_invalidate() and intel_edp_drrs_flush() are called.
5667  *
5668  * DRRS can be further extended to support other internal panels and also
5669  * the scenario of video playback wherein RR is set based on the rate
5670  * requested by userspace.
5671  */
5672
5673 /**
5674  * intel_dp_drrs_init - Init basic DRRS work and mutex.
5675  * @intel_connector: eDP connector
5676  * @fixed_mode: preferred mode of panel
5677  *
5678  * This function is  called only once at driver load to initialize basic
5679  * DRRS stuff.
5680  *
5681  * Returns:
5682  * Downclock mode if panel supports it, else return NULL.
5683  * DRRS support is determined by the presence of downclock mode (apart
5684  * from VBT setting).
5685  */
5686 static struct drm_display_mode *
5687 intel_dp_drrs_init(struct intel_connector *intel_connector,
5688                 struct drm_display_mode *fixed_mode)
5689 {
5690         struct drm_connector *connector = &intel_connector->base;
5691         struct drm_device *dev = connector->dev;
5692         struct drm_i915_private *dev_priv = dev->dev_private;
5693         struct drm_display_mode *downclock_mode = NULL;
5694
5695         INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work);
5696         mutex_init(&dev_priv->drrs.mutex);
5697
5698         if (INTEL_INFO(dev)->gen <= 6) {
5699                 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n");
5700                 return NULL;
5701         }
5702
5703         if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) {
5704                 DRM_DEBUG_KMS("VBT doesn't support DRRS\n");
5705                 return NULL;
5706         }
5707
5708         downclock_mode = intel_find_panel_downclock
5709                                         (dev, fixed_mode, connector);
5710
5711         if (!downclock_mode) {
5712                 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n");
5713                 return NULL;
5714         }
5715
5716         dev_priv->drrs.type = dev_priv->vbt.drrs_type;
5717
5718         dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR;
5719         DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n");
5720         return downclock_mode;
5721 }
5722
5723 static bool intel_edp_init_connector(struct intel_dp *intel_dp,
5724                                      struct intel_connector *intel_connector)
5725 {
5726         struct drm_connector *connector = &intel_connector->base;
5727         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
5728         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5729         struct drm_device *dev = intel_encoder->base.dev;
5730         struct drm_i915_private *dev_priv = dev->dev_private;
5731         struct drm_display_mode *fixed_mode = NULL;
5732         struct drm_display_mode *downclock_mode = NULL;
5733         bool has_dpcd;
5734         struct drm_display_mode *scan;
5735         struct edid *edid;
5736         enum pipe pipe = INVALID_PIPE;
5737
5738         if (!is_edp(intel_dp))
5739                 return true;
5740
5741         pps_lock(intel_dp);
5742         intel_edp_panel_vdd_sanitize(intel_dp);
5743         pps_unlock(intel_dp);
5744
5745         /* Cache DPCD and EDID for edp. */
5746         has_dpcd = intel_dp_get_dpcd(intel_dp);
5747
5748         if (has_dpcd) {
5749                 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
5750                         dev_priv->no_aux_handshake =
5751                                 intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
5752                                 DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
5753         } else {
5754                 /* if this fails, presume the device is a ghost */
5755                 DRM_INFO("failed to retrieve link info, disabling eDP\n");
5756                 return false;
5757         }
5758
5759         /* We now know it's not a ghost, init power sequence regs. */
5760         pps_lock(intel_dp);
5761         intel_dp_init_panel_power_sequencer_registers(dev, intel_dp);
5762         pps_unlock(intel_dp);
5763
5764         mutex_lock(&dev->mode_config.mutex);
5765         edid = drm_get_edid(connector, &intel_dp->aux.ddc);
5766         if (edid) {
5767                 if (drm_add_edid_modes(connector, edid)) {
5768                         drm_mode_connector_update_edid_property(connector,
5769                                                                 edid);
5770                         drm_edid_to_eld(connector, edid);
5771                 } else {
5772                         kfree(edid);
5773                         edid = ERR_PTR(-EINVAL);
5774                 }
5775         } else {
5776                 edid = ERR_PTR(-ENOENT);
5777         }
5778         intel_connector->edid = edid;
5779
5780         /* prefer fixed mode from EDID if available */
5781         list_for_each_entry(scan, &connector->probed_modes, head) {
5782                 if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
5783                         fixed_mode = drm_mode_duplicate(dev, scan);
5784                         downclock_mode = intel_dp_drrs_init(
5785                                                 intel_connector, fixed_mode);
5786                         break;
5787                 }
5788         }
5789
5790         /* fallback to VBT if available for eDP */
5791         if (!fixed_mode && dev_priv->vbt.lfp_lvds_vbt_mode) {
5792                 fixed_mode = drm_mode_duplicate(dev,
5793                                         dev_priv->vbt.lfp_lvds_vbt_mode);
5794                 if (fixed_mode)
5795                         fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
5796         }
5797         mutex_unlock(&dev->mode_config.mutex);
5798
5799         if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5800                 intel_dp->edp_notifier.notifier_call = edp_notify_handler;
5801                 register_reboot_notifier(&intel_dp->edp_notifier);
5802
5803                 /*
5804                  * Figure out the current pipe for the initial backlight setup.
5805                  * If the current pipe isn't valid, try the PPS pipe, and if that
5806                  * fails just assume pipe A.
5807                  */
5808                 if (IS_CHERRYVIEW(dev))
5809                         pipe = DP_PORT_TO_PIPE_CHV(intel_dp->DP);
5810                 else
5811                         pipe = PORT_TO_PIPE(intel_dp->DP);
5812
5813                 if (pipe != PIPE_A && pipe != PIPE_B)
5814                         pipe = intel_dp->pps_pipe;
5815
5816                 if (pipe != PIPE_A && pipe != PIPE_B)
5817                         pipe = PIPE_A;
5818
5819                 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n",
5820                               pipe_name(pipe));
5821         }
5822
5823         intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
5824         intel_connector->panel.backlight.power = intel_edp_backlight_power;
5825         intel_panel_setup_backlight(connector, pipe);
5826
5827         return true;
5828 }
5829
5830 bool
5831 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
5832                         struct intel_connector *intel_connector)
5833 {
5834         struct drm_connector *connector = &intel_connector->base;
5835         struct intel_dp *intel_dp = &intel_dig_port->dp;
5836         struct intel_encoder *intel_encoder = &intel_dig_port->base;
5837         struct drm_device *dev = intel_encoder->base.dev;
5838         struct drm_i915_private *dev_priv = dev->dev_private;
5839         enum port port = intel_dig_port->port;
5840         int type, ret;
5841
5842         intel_dp->pps_pipe = INVALID_PIPE;
5843
5844         /* intel_dp vfuncs */
5845         if (INTEL_INFO(dev)->gen >= 9)
5846                 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider;
5847         else if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
5848                 intel_dp->get_aux_clock_divider = vlv_get_aux_clock_divider;
5849         else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
5850                 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider;
5851         else if (HAS_PCH_SPLIT(dev))
5852                 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider;
5853         else
5854                 intel_dp->get_aux_clock_divider = i9xx_get_aux_clock_divider;
5855
5856         if (INTEL_INFO(dev)->gen >= 9)
5857                 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl;
5858         else
5859                 intel_dp->get_aux_send_ctl = i9xx_get_aux_send_ctl;
5860
5861         if (HAS_DDI(dev))
5862                 intel_dp->prepare_link_retrain = intel_ddi_prepare_link_retrain;
5863
5864         /* Preserve the current hw state. */
5865         intel_dp->DP = I915_READ(intel_dp->output_reg);
5866         intel_dp->attached_connector = intel_connector;
5867
5868         if (intel_dp_is_edp(dev, port))
5869                 type = DRM_MODE_CONNECTOR_eDP;
5870         else
5871                 type = DRM_MODE_CONNECTOR_DisplayPort;
5872
5873         /*
5874          * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but
5875          * for DP the encoder type can be set by the caller to
5876          * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it.
5877          */
5878         if (type == DRM_MODE_CONNECTOR_eDP)
5879                 intel_encoder->type = INTEL_OUTPUT_EDP;
5880
5881         /* eDP only on port B and/or C on vlv/chv */
5882         if (WARN_ON((IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) &&
5883                     is_edp(intel_dp) && port != PORT_B && port != PORT_C))
5884                 return false;
5885
5886         DRM_DEBUG_KMS("Adding %s connector on port %c\n",
5887                         type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP",
5888                         port_name(port));
5889
5890         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
5891         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
5892
5893         connector->interlace_allowed = true;
5894         connector->doublescan_allowed = 0;
5895
5896         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
5897                           edp_panel_vdd_work);
5898
5899         intel_connector_attach_encoder(intel_connector, intel_encoder);
5900         drm_connector_register(connector);
5901
5902         if (HAS_DDI(dev))
5903                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
5904         else
5905                 intel_connector->get_hw_state = intel_connector_get_hw_state;
5906         intel_connector->unregister = intel_dp_connector_unregister;
5907
5908         /* Set up the hotplug pin. */
5909         switch (port) {
5910         case PORT_A:
5911                 intel_encoder->hpd_pin = HPD_PORT_A;
5912                 break;
5913         case PORT_B:
5914                 intel_encoder->hpd_pin = HPD_PORT_B;
5915                 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
5916                         intel_encoder->hpd_pin = HPD_PORT_A;
5917                 break;
5918         case PORT_C:
5919                 intel_encoder->hpd_pin = HPD_PORT_C;
5920                 break;
5921         case PORT_D:
5922                 intel_encoder->hpd_pin = HPD_PORT_D;
5923                 break;
5924         case PORT_E:
5925                 intel_encoder->hpd_pin = HPD_PORT_E;
5926                 break;
5927         default:
5928                 BUG();
5929         }
5930
5931         if (is_edp(intel_dp)) {
5932                 pps_lock(intel_dp);
5933                 intel_dp_init_panel_power_timestamps(intel_dp);
5934                 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
5935                         vlv_initial_power_sequencer_setup(intel_dp);
5936                 else
5937                         intel_dp_init_panel_power_sequencer(dev, intel_dp);
5938                 pps_unlock(intel_dp);
5939         }
5940
5941         ret = intel_dp_aux_init(intel_dp, intel_connector);
5942         if (ret)
5943                 goto fail;
5944
5945         /* init MST on ports that can support it */
5946         if (HAS_DP_MST(dev) &&
5947             (port == PORT_B || port == PORT_C || port == PORT_D))
5948                 intel_dp_mst_encoder_init(intel_dig_port,
5949                                           intel_connector->base.base.id);
5950
5951         if (!intel_edp_init_connector(intel_dp, intel_connector)) {
5952                 intel_dp_aux_fini(intel_dp);
5953                 intel_dp_mst_encoder_cleanup(intel_dig_port);
5954                 goto fail;
5955         }
5956
5957         intel_dp_add_properties(intel_dp, connector);
5958
5959         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
5960          * 0xd.  Failure to do so will result in spurious interrupts being
5961          * generated on the port when a cable is not attached.
5962          */
5963         if (IS_G4X(dev) && !IS_GM45(dev)) {
5964                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
5965                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
5966         }
5967
5968         i915_debugfs_connector_add(connector);
5969
5970         return true;
5971
5972 fail:
5973         if (is_edp(intel_dp)) {
5974                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
5975                 /*
5976                  * vdd might still be enabled do to the delayed vdd off.
5977                  * Make sure vdd is actually turned off here.
5978                  */
5979                 pps_lock(intel_dp);
5980                 edp_panel_vdd_off_sync(intel_dp);
5981                 pps_unlock(intel_dp);
5982         }
5983         drm_connector_unregister(connector);
5984         drm_connector_cleanup(connector);
5985
5986         return false;
5987 }
5988
5989 void
5990 intel_dp_init(struct drm_device *dev,
5991               i915_reg_t output_reg, enum port port)
5992 {
5993         struct drm_i915_private *dev_priv = dev->dev_private;
5994         struct intel_digital_port *intel_dig_port;
5995         struct intel_encoder *intel_encoder;
5996         struct drm_encoder *encoder;
5997         struct intel_connector *intel_connector;
5998
5999         intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL);
6000         if (!intel_dig_port)
6001                 return;
6002
6003         intel_connector = intel_connector_alloc();
6004         if (!intel_connector)
6005                 goto err_connector_alloc;
6006
6007         intel_encoder = &intel_dig_port->base;
6008         encoder = &intel_encoder->base;
6009
6010         if (drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
6011                              DRM_MODE_ENCODER_TMDS, NULL))
6012                 goto err_encoder_init;
6013
6014         intel_encoder->compute_config = intel_dp_compute_config;
6015         intel_encoder->disable = intel_disable_dp;
6016         intel_encoder->get_hw_state = intel_dp_get_hw_state;
6017         intel_encoder->get_config = intel_dp_get_config;
6018         intel_encoder->suspend = intel_dp_encoder_suspend;
6019         if (IS_CHERRYVIEW(dev)) {
6020                 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable;
6021                 intel_encoder->pre_enable = chv_pre_enable_dp;
6022                 intel_encoder->enable = vlv_enable_dp;
6023                 intel_encoder->post_disable = chv_post_disable_dp;
6024                 intel_encoder->post_pll_disable = chv_dp_post_pll_disable;
6025         } else if (IS_VALLEYVIEW(dev)) {
6026                 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable;
6027                 intel_encoder->pre_enable = vlv_pre_enable_dp;
6028                 intel_encoder->enable = vlv_enable_dp;
6029                 intel_encoder->post_disable = vlv_post_disable_dp;
6030         } else {
6031                 intel_encoder->pre_enable = g4x_pre_enable_dp;
6032                 intel_encoder->enable = g4x_enable_dp;
6033                 if (INTEL_INFO(dev)->gen >= 5)
6034                         intel_encoder->post_disable = ilk_post_disable_dp;
6035         }
6036
6037         intel_dig_port->port = port;
6038         dev_priv->dig_port_map[port] = intel_encoder;
6039         intel_dig_port->dp.output_reg = output_reg;
6040
6041         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
6042         if (IS_CHERRYVIEW(dev)) {
6043                 if (port == PORT_D)
6044                         intel_encoder->crtc_mask = 1 << 2;
6045                 else
6046                         intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
6047         } else {
6048                 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
6049         }
6050         intel_encoder->cloneable = 0;
6051
6052         intel_dig_port->hpd_pulse = intel_dp_hpd_pulse;
6053         dev_priv->hotplug.irq_port[port] = intel_dig_port;
6054
6055         if (!intel_dp_init_connector(intel_dig_port, intel_connector))
6056                 goto err_init_connector;
6057
6058         return;
6059
6060 err_init_connector:
6061         drm_encoder_cleanup(encoder);
6062 err_encoder_init:
6063         kfree(intel_connector);
6064 err_connector_alloc:
6065         kfree(intel_dig_port);
6066
6067         return;
6068 }
6069
6070 void intel_dp_mst_suspend(struct drm_device *dev)
6071 {
6072         struct drm_i915_private *dev_priv = dev->dev_private;
6073         int i;
6074
6075         /* disable MST */
6076         for (i = 0; i < I915_MAX_PORTS; i++) {
6077                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6078                 if (!intel_dig_port)
6079                         continue;
6080
6081                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
6082                         if (!intel_dig_port->dp.can_mst)
6083                                 continue;
6084                         if (intel_dig_port->dp.is_mst)
6085                                 drm_dp_mst_topology_mgr_suspend(&intel_dig_port->dp.mst_mgr);
6086                 }
6087         }
6088 }
6089
6090 void intel_dp_mst_resume(struct drm_device *dev)
6091 {
6092         struct drm_i915_private *dev_priv = dev->dev_private;
6093         int i;
6094
6095         for (i = 0; i < I915_MAX_PORTS; i++) {
6096                 struct intel_digital_port *intel_dig_port = dev_priv->hotplug.irq_port[i];
6097                 if (!intel_dig_port)
6098                         continue;
6099                 if (intel_dig_port->base.type == INTEL_OUTPUT_DISPLAYPORT) {
6100                         int ret;
6101
6102                         if (!intel_dig_port->dp.can_mst)
6103                                 continue;
6104
6105                         ret = drm_dp_mst_topology_mgr_resume(&intel_dig_port->dp.mst_mgr);
6106                         if (ret != 0) {
6107                                 intel_dp_check_mst_status(&intel_dig_port->dp);
6108                         }
6109                 }
6110         }
6111 }