1 // SPDX-License-Identifier: GPL-2.0
3 * xhci-dbgcap.c - xHCI debug capability support
5 * Copyright (C) 2017 Intel Corporation
9 #include <linux/dma-mapping.h>
10 #include <linux/slab.h>
11 #include <linux/nls.h>
14 #include "xhci-trace.h"
15 #include "xhci-dbgcap.h"
17 static void dbc_free_ctx(struct device *dev, struct xhci_container_ctx *ctx)
21 dma_free_coherent(dev, ctx->size, ctx->bytes, ctx->dma);
25 /* we use only one segment for DbC rings */
26 static void dbc_ring_free(struct device *dev, struct xhci_ring *ring)
31 if (ring->first_seg && ring->first_seg->trbs) {
32 dma_free_coherent(dev, TRB_SEGMENT_SIZE,
33 ring->first_seg->trbs,
34 ring->first_seg->dma);
35 kfree(ring->first_seg);
40 static u32 xhci_dbc_populate_strings(struct dbc_str_descs *strings)
42 struct usb_string_descriptor *s_desc;
46 s_desc = (struct usb_string_descriptor *)strings->serial;
47 utf8s_to_utf16s(DBC_STRING_SERIAL, strlen(DBC_STRING_SERIAL),
48 UTF16_LITTLE_ENDIAN, (wchar_t *)s_desc->wData,
49 DBC_MAX_STRING_LENGTH);
51 s_desc->bLength = (strlen(DBC_STRING_SERIAL) + 1) * 2;
52 s_desc->bDescriptorType = USB_DT_STRING;
53 string_length = s_desc->bLength;
57 s_desc = (struct usb_string_descriptor *)strings->product;
58 utf8s_to_utf16s(DBC_STRING_PRODUCT, strlen(DBC_STRING_PRODUCT),
59 UTF16_LITTLE_ENDIAN, (wchar_t *)s_desc->wData,
60 DBC_MAX_STRING_LENGTH);
62 s_desc->bLength = (strlen(DBC_STRING_PRODUCT) + 1) * 2;
63 s_desc->bDescriptorType = USB_DT_STRING;
64 string_length += s_desc->bLength;
67 /* Manufacture string: */
68 s_desc = (struct usb_string_descriptor *)strings->manufacturer;
69 utf8s_to_utf16s(DBC_STRING_MANUFACTURER,
70 strlen(DBC_STRING_MANUFACTURER),
71 UTF16_LITTLE_ENDIAN, (wchar_t *)s_desc->wData,
72 DBC_MAX_STRING_LENGTH);
74 s_desc->bLength = (strlen(DBC_STRING_MANUFACTURER) + 1) * 2;
75 s_desc->bDescriptorType = USB_DT_STRING;
76 string_length += s_desc->bLength;
80 strings->string0[0] = 4;
81 strings->string0[1] = USB_DT_STRING;
82 strings->string0[2] = 0x09;
83 strings->string0[3] = 0x04;
89 static void xhci_dbc_init_contexts(struct xhci_dbc *dbc, u32 string_length)
91 struct dbc_info_context *info;
92 struct xhci_ep_ctx *ep_ctx;
95 unsigned int max_burst;
100 /* Populate info Context: */
101 info = (struct dbc_info_context *)dbc->ctx->bytes;
102 dma = dbc->string_dma;
103 info->string0 = cpu_to_le64(dma);
104 info->manufacturer = cpu_to_le64(dma + DBC_MAX_STRING_LENGTH);
105 info->product = cpu_to_le64(dma + DBC_MAX_STRING_LENGTH * 2);
106 info->serial = cpu_to_le64(dma + DBC_MAX_STRING_LENGTH * 3);
107 info->length = cpu_to_le32(string_length);
109 /* Populate bulk out endpoint context: */
110 ep_ctx = dbc_bulkout_ctx(dbc);
111 max_burst = DBC_CTRL_MAXBURST(readl(&dbc->regs->control));
112 deq = dbc_bulkout_enq(dbc);
114 ep_ctx->ep_info2 = dbc_epctx_info2(BULK_OUT_EP, 1024, max_burst);
115 ep_ctx->deq = cpu_to_le64(deq | dbc->ring_out->cycle_state);
117 /* Populate bulk in endpoint context: */
118 ep_ctx = dbc_bulkin_ctx(dbc);
119 deq = dbc_bulkin_enq(dbc);
121 ep_ctx->ep_info2 = dbc_epctx_info2(BULK_IN_EP, 1024, max_burst);
122 ep_ctx->deq = cpu_to_le64(deq | dbc->ring_in->cycle_state);
124 /* Set DbC context and info registers: */
125 lo_hi_writeq(dbc->ctx->dma, &dbc->regs->dccp);
127 dev_info = cpu_to_le32((DBC_VENDOR_ID << 16) | DBC_PROTOCOL);
128 writel(dev_info, &dbc->regs->devinfo1);
130 dev_info = cpu_to_le32((DBC_DEVICE_REV << 16) | DBC_PRODUCT_ID);
131 writel(dev_info, &dbc->regs->devinfo2);
134 static void xhci_dbc_giveback(struct dbc_request *req, int status)
135 __releases(&dbc->lock)
136 __acquires(&dbc->lock)
138 struct xhci_dbc *dbc = req->dbc;
139 struct device *dev = dbc->dev;
141 list_del_init(&req->list_pending);
145 if (req->status == -EINPROGRESS)
146 req->status = status;
148 trace_xhci_dbc_giveback_request(req);
150 dma_unmap_single(dev,
153 dbc_ep_dma_direction(req));
155 /* Give back the transfer request: */
156 spin_unlock(&dbc->lock);
157 req->complete(dbc, req);
158 spin_lock(&dbc->lock);
161 static void xhci_dbc_flush_single_request(struct dbc_request *req)
163 union xhci_trb *trb = req->trb;
165 trb->generic.field[0] = 0;
166 trb->generic.field[1] = 0;
167 trb->generic.field[2] = 0;
168 trb->generic.field[3] &= cpu_to_le32(TRB_CYCLE);
169 trb->generic.field[3] |= cpu_to_le32(TRB_TYPE(TRB_TR_NOOP));
171 xhci_dbc_giveback(req, -ESHUTDOWN);
174 static void xhci_dbc_flush_endpoint_requests(struct dbc_ep *dep)
176 struct dbc_request *req, *tmp;
178 list_for_each_entry_safe(req, tmp, &dep->list_pending, list_pending)
179 xhci_dbc_flush_single_request(req);
182 static void xhci_dbc_flush_requests(struct xhci_dbc *dbc)
184 xhci_dbc_flush_endpoint_requests(&dbc->eps[BULK_OUT]);
185 xhci_dbc_flush_endpoint_requests(&dbc->eps[BULK_IN]);
189 dbc_alloc_request(struct xhci_dbc *dbc, unsigned int direction, gfp_t flags)
191 struct dbc_request *req;
193 if (direction != BULK_IN &&
194 direction != BULK_OUT)
200 req = kzalloc(sizeof(*req), flags);
205 INIT_LIST_HEAD(&req->list_pending);
206 INIT_LIST_HEAD(&req->list_pool);
207 req->direction = direction;
209 trace_xhci_dbc_alloc_request(req);
215 dbc_free_request(struct dbc_request *req)
217 trace_xhci_dbc_free_request(req);
223 xhci_dbc_queue_trb(struct xhci_ring *ring, u32 field1,
224 u32 field2, u32 field3, u32 field4)
226 union xhci_trb *trb, *next;
229 trb->generic.field[0] = cpu_to_le32(field1);
230 trb->generic.field[1] = cpu_to_le32(field2);
231 trb->generic.field[2] = cpu_to_le32(field3);
232 trb->generic.field[3] = cpu_to_le32(field4);
234 trace_xhci_dbc_gadget_ep_queue(ring, &trb->generic);
236 ring->num_trbs_free--;
237 next = ++(ring->enqueue);
238 if (TRB_TYPE_LINK_LE32(next->link.control)) {
239 next->link.control ^= cpu_to_le32(TRB_CYCLE);
240 ring->enqueue = ring->enq_seg->trbs;
241 ring->cycle_state ^= 1;
245 static int xhci_dbc_queue_bulk_tx(struct dbc_ep *dep,
246 struct dbc_request *req)
250 unsigned int num_trbs;
251 struct xhci_dbc *dbc = req->dbc;
252 struct xhci_ring *ring = dep->ring;
253 u32 length, control, cycle;
255 num_trbs = count_trbs(req->dma, req->length);
256 WARN_ON(num_trbs != 1);
257 if (ring->num_trbs_free < num_trbs)
262 cycle = ring->cycle_state;
263 length = TRB_LEN(req->length);
264 control = TRB_TYPE(TRB_NORMAL) | TRB_IOC;
267 control &= cpu_to_le32(~TRB_CYCLE);
269 control |= cpu_to_le32(TRB_CYCLE);
271 req->trb = ring->enqueue;
272 req->trb_dma = xhci_trb_virt_to_dma(ring->enq_seg, ring->enqueue);
273 xhci_dbc_queue_trb(ring,
279 * Add a barrier between writes of trb fields and flipping
285 trb->generic.field[3] |= cpu_to_le32(TRB_CYCLE);
287 trb->generic.field[3] &= cpu_to_le32(~TRB_CYCLE);
289 writel(DBC_DOOR_BELL_TARGET(dep->direction), &dbc->regs->doorbell);
295 dbc_ep_do_queue(struct dbc_request *req)
298 struct xhci_dbc *dbc = req->dbc;
299 struct device *dev = dbc->dev;
300 struct dbc_ep *dep = &dbc->eps[req->direction];
302 if (!req->length || !req->buf)
306 req->status = -EINPROGRESS;
308 req->dma = dma_map_single(dev,
311 dbc_ep_dma_direction(dep));
312 if (dma_mapping_error(dev, req->dma)) {
313 dev_err(dbc->dev, "failed to map buffer\n");
317 ret = xhci_dbc_queue_bulk_tx(dep, req);
319 dev_err(dbc->dev, "failed to queue trbs\n");
320 dma_unmap_single(dev,
323 dbc_ep_dma_direction(dep));
327 list_add_tail(&req->list_pending, &dep->list_pending);
332 int dbc_ep_queue(struct dbc_request *req)
335 struct xhci_dbc *dbc = req->dbc;
336 int ret = -ESHUTDOWN;
341 if (req->direction != BULK_IN &&
342 req->direction != BULK_OUT)
345 spin_lock_irqsave(&dbc->lock, flags);
346 if (dbc->state == DS_CONFIGURED)
347 ret = dbc_ep_do_queue(req);
348 spin_unlock_irqrestore(&dbc->lock, flags);
350 mod_delayed_work(system_wq, &dbc->event_work, 0);
352 trace_xhci_dbc_queue_request(req);
357 static inline void xhci_dbc_do_eps_init(struct xhci_dbc *dbc, bool direction)
361 dep = &dbc->eps[direction];
363 dep->direction = direction;
364 dep->ring = direction ? dbc->ring_in : dbc->ring_out;
366 INIT_LIST_HEAD(&dep->list_pending);
369 static void xhci_dbc_eps_init(struct xhci_dbc *dbc)
371 xhci_dbc_do_eps_init(dbc, BULK_OUT);
372 xhci_dbc_do_eps_init(dbc, BULK_IN);
375 static void xhci_dbc_eps_exit(struct xhci_dbc *dbc)
377 memset(dbc->eps, 0, sizeof(struct dbc_ep) * ARRAY_SIZE(dbc->eps));
380 static int dbc_erst_alloc(struct device *dev, struct xhci_ring *evt_ring,
381 struct xhci_erst *erst, gfp_t flags)
383 erst->entries = dma_alloc_coherent(dev, sizeof(struct xhci_erst_entry),
384 &erst->erst_dma_addr, flags);
388 erst->num_entries = 1;
389 erst->entries[0].seg_addr = cpu_to_le64(evt_ring->first_seg->dma);
390 erst->entries[0].seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
391 erst->entries[0].rsvd = 0;
395 static void dbc_erst_free(struct device *dev, struct xhci_erst *erst)
398 dma_free_coherent(dev, sizeof(struct xhci_erst_entry),
399 erst->entries, erst->erst_dma_addr);
400 erst->entries = NULL;
403 static struct xhci_container_ctx *
404 dbc_alloc_ctx(struct device *dev, gfp_t flags)
406 struct xhci_container_ctx *ctx;
408 ctx = kzalloc(sizeof(*ctx), flags);
412 /* xhci 7.6.9, all three contexts; info, ep-out and ep-in. Each 64 bytes*/
413 ctx->size = 3 * DBC_CONTEXT_SIZE;
414 ctx->bytes = dma_alloc_coherent(dev, ctx->size, &ctx->dma, flags);
422 static struct xhci_ring *
423 xhci_dbc_ring_alloc(struct device *dev, enum xhci_ring_type type, gfp_t flags)
425 struct xhci_ring *ring;
426 struct xhci_segment *seg;
429 ring = kzalloc(sizeof(*ring), flags);
436 seg = kzalloc(sizeof(*seg), flags);
440 ring->first_seg = seg;
441 ring->last_seg = seg;
444 seg->trbs = dma_alloc_coherent(dev, TRB_SEGMENT_SIZE, &dma, flags);
450 /* Only event ring does not use link TRB */
451 if (type != TYPE_EVENT) {
452 union xhci_trb *trb = &seg->trbs[TRBS_PER_SEGMENT - 1];
454 trb->link.segment_ptr = cpu_to_le64(dma);
455 trb->link.control = cpu_to_le32(LINK_TOGGLE | TRB_TYPE(TRB_LINK));
457 INIT_LIST_HEAD(&ring->td_list);
458 xhci_initialize_ring_info(ring, 1);
467 static int xhci_dbc_mem_init(struct xhci_dbc *dbc, gfp_t flags)
472 struct device *dev = dbc->dev;
474 /* Allocate various rings for events and transfers: */
475 dbc->ring_evt = xhci_dbc_ring_alloc(dev, TYPE_EVENT, flags);
479 dbc->ring_in = xhci_dbc_ring_alloc(dev, TYPE_BULK, flags);
483 dbc->ring_out = xhci_dbc_ring_alloc(dev, TYPE_BULK, flags);
487 /* Allocate and populate ERST: */
488 ret = dbc_erst_alloc(dev, dbc->ring_evt, &dbc->erst, flags);
492 /* Allocate context data structure: */
493 dbc->ctx = dbc_alloc_ctx(dev, flags); /* was sysdev, and is still */
497 /* Allocate the string table: */
498 dbc->string_size = sizeof(struct dbc_str_descs);
499 dbc->string = dma_alloc_coherent(dev, dbc->string_size,
500 &dbc->string_dma, flags);
504 /* Setup ERST register: */
505 writel(dbc->erst.erst_size, &dbc->regs->ersts);
507 lo_hi_writeq(dbc->erst.erst_dma_addr, &dbc->regs->erstba);
508 deq = xhci_trb_virt_to_dma(dbc->ring_evt->deq_seg,
509 dbc->ring_evt->dequeue);
510 lo_hi_writeq(deq, &dbc->regs->erdp);
512 /* Setup strings and contexts: */
513 string_length = xhci_dbc_populate_strings(dbc->string);
514 xhci_dbc_init_contexts(dbc, string_length);
516 xhci_dbc_eps_init(dbc);
517 dbc->state = DS_INITIALIZED;
522 dbc_free_ctx(dev, dbc->ctx);
525 dbc_erst_free(dev, &dbc->erst);
527 dbc_ring_free(dev, dbc->ring_out);
528 dbc->ring_out = NULL;
530 dbc_ring_free(dev, dbc->ring_in);
533 dbc_ring_free(dev, dbc->ring_evt);
534 dbc->ring_evt = NULL;
539 static void xhci_dbc_mem_cleanup(struct xhci_dbc *dbc)
544 xhci_dbc_eps_exit(dbc);
547 dma_free_coherent(dbc->dev, dbc->string_size,
548 dbc->string, dbc->string_dma);
552 dbc_free_ctx(dbc->dev, dbc->ctx);
555 dbc_erst_free(dbc->dev, &dbc->erst);
556 dbc_ring_free(dbc->dev, dbc->ring_out);
557 dbc_ring_free(dbc->dev, dbc->ring_in);
558 dbc_ring_free(dbc->dev, dbc->ring_evt);
560 dbc->ring_out = NULL;
561 dbc->ring_evt = NULL;
564 static int xhci_do_dbc_start(struct xhci_dbc *dbc)
569 if (dbc->state != DS_DISABLED)
572 writel(0, &dbc->regs->control);
573 ret = xhci_handshake(&dbc->regs->control,
579 ret = xhci_dbc_mem_init(dbc, GFP_ATOMIC);
583 ctrl = readl(&dbc->regs->control);
584 writel(ctrl | DBC_CTRL_DBC_ENABLE | DBC_CTRL_PORT_ENABLE,
585 &dbc->regs->control);
586 ret = xhci_handshake(&dbc->regs->control,
588 DBC_CTRL_DBC_ENABLE, 1000);
592 dbc->state = DS_ENABLED;
597 static int xhci_do_dbc_stop(struct xhci_dbc *dbc)
599 if (dbc->state == DS_DISABLED)
602 writel(0, &dbc->regs->control);
603 dbc->state = DS_DISABLED;
608 static int xhci_dbc_start(struct xhci_dbc *dbc)
615 pm_runtime_get_sync(dbc->dev); /* note this was self.controller */
617 spin_lock_irqsave(&dbc->lock, flags);
618 ret = xhci_do_dbc_start(dbc);
619 spin_unlock_irqrestore(&dbc->lock, flags);
622 pm_runtime_put(dbc->dev); /* note this was self.controller */
626 return mod_delayed_work(system_wq, &dbc->event_work, 1);
629 static void xhci_dbc_stop(struct xhci_dbc *dbc)
636 switch (dbc->state) {
641 if (dbc->driver->disconnect)
642 dbc->driver->disconnect(dbc);
648 cancel_delayed_work_sync(&dbc->event_work);
650 spin_lock_irqsave(&dbc->lock, flags);
651 ret = xhci_do_dbc_stop(dbc);
652 spin_unlock_irqrestore(&dbc->lock, flags);
655 xhci_dbc_mem_cleanup(dbc);
656 pm_runtime_put_sync(dbc->dev); /* note, was self.controller */
661 dbc_handle_port_status(struct xhci_dbc *dbc, union xhci_trb *event)
665 portsc = readl(&dbc->regs->portsc);
666 if (portsc & DBC_PORTSC_CONN_CHANGE)
667 dev_info(dbc->dev, "DbC port connect change\n");
669 if (portsc & DBC_PORTSC_RESET_CHANGE)
670 dev_info(dbc->dev, "DbC port reset change\n");
672 if (portsc & DBC_PORTSC_LINK_CHANGE)
673 dev_info(dbc->dev, "DbC port link status change\n");
675 if (portsc & DBC_PORTSC_CONFIG_CHANGE)
676 dev_info(dbc->dev, "DbC config error change\n");
678 /* Port reset change bit will be cleared in other place: */
679 writel(portsc & ~DBC_PORTSC_RESET_CHANGE, &dbc->regs->portsc);
682 static void dbc_handle_xfer_event(struct xhci_dbc *dbc, union xhci_trb *event)
685 struct xhci_ring *ring;
689 size_t remain_length;
690 struct dbc_request *req = NULL, *r;
692 comp_code = GET_COMP_CODE(le32_to_cpu(event->generic.field[2]));
693 remain_length = EVENT_TRB_LEN(le32_to_cpu(event->generic.field[2]));
694 ep_id = TRB_TO_EP_ID(le32_to_cpu(event->generic.field[3]));
695 dep = (ep_id == EPID_OUT) ?
696 get_out_ep(dbc) : get_in_ep(dbc);
703 case COMP_SHORT_PACKET:
707 case COMP_BABBLE_DETECTED_ERROR:
708 case COMP_USB_TRANSACTION_ERROR:
709 case COMP_STALL_ERROR:
710 dev_warn(dbc->dev, "tx error %d detected\n", comp_code);
714 dev_err(dbc->dev, "unknown tx error %d\n", comp_code);
719 /* Match the pending request: */
720 list_for_each_entry(r, &dep->list_pending, list_pending) {
721 if (r->trb_dma == event->trans_event.buffer) {
728 dev_warn(dbc->dev, "no matched request\n");
732 trace_xhci_dbc_handle_transfer(ring, &req->trb->generic);
734 ring->num_trbs_free++;
735 req->actual = req->length - remain_length;
736 xhci_dbc_giveback(req, status);
739 static void inc_evt_deq(struct xhci_ring *ring)
741 /* If on the last TRB of the segment go back to the beginning */
742 if (ring->dequeue == &ring->deq_seg->trbs[TRBS_PER_SEGMENT - 1]) {
743 ring->cycle_state ^= 1;
744 ring->dequeue = ring->deq_seg->trbs;
750 static enum evtreturn xhci_dbc_do_handle_events(struct xhci_dbc *dbc)
756 bool update_erdp = false;
758 /* DbC state machine: */
759 switch (dbc->state) {
765 portsc = readl(&dbc->regs->portsc);
766 if (portsc & DBC_PORTSC_CONN_STATUS) {
767 dbc->state = DS_CONNECTED;
768 dev_info(dbc->dev, "DbC connected\n");
773 ctrl = readl(&dbc->regs->control);
774 if (ctrl & DBC_CTRL_DBC_RUN) {
775 dbc->state = DS_CONFIGURED;
776 dev_info(dbc->dev, "DbC configured\n");
777 portsc = readl(&dbc->regs->portsc);
778 writel(portsc, &dbc->regs->portsc);
784 /* Handle cable unplug event: */
785 portsc = readl(&dbc->regs->portsc);
786 if (!(portsc & DBC_PORTSC_PORT_ENABLED) &&
787 !(portsc & DBC_PORTSC_CONN_STATUS)) {
788 dev_info(dbc->dev, "DbC cable unplugged\n");
789 dbc->state = DS_ENABLED;
790 xhci_dbc_flush_requests(dbc);
795 /* Handle debug port reset event: */
796 if (portsc & DBC_PORTSC_RESET_CHANGE) {
797 dev_info(dbc->dev, "DbC port reset\n");
798 writel(portsc, &dbc->regs->portsc);
799 dbc->state = DS_ENABLED;
800 xhci_dbc_flush_requests(dbc);
805 /* Handle endpoint stall event: */
806 ctrl = readl(&dbc->regs->control);
807 if ((ctrl & DBC_CTRL_HALT_IN_TR) ||
808 (ctrl & DBC_CTRL_HALT_OUT_TR)) {
809 dev_info(dbc->dev, "DbC Endpoint stall\n");
810 dbc->state = DS_STALLED;
812 if (ctrl & DBC_CTRL_HALT_IN_TR) {
813 dep = get_in_ep(dbc);
814 xhci_dbc_flush_endpoint_requests(dep);
817 if (ctrl & DBC_CTRL_HALT_OUT_TR) {
818 dep = get_out_ep(dbc);
819 xhci_dbc_flush_endpoint_requests(dep);
825 /* Clear DbC run change bit: */
826 if (ctrl & DBC_CTRL_DBC_RUN_CHANGE) {
827 writel(ctrl, &dbc->regs->control);
828 ctrl = readl(&dbc->regs->control);
833 ctrl = readl(&dbc->regs->control);
834 if (!(ctrl & DBC_CTRL_HALT_IN_TR) &&
835 !(ctrl & DBC_CTRL_HALT_OUT_TR) &&
836 (ctrl & DBC_CTRL_DBC_RUN)) {
837 dbc->state = DS_CONFIGURED;
843 dev_err(dbc->dev, "Unknown DbC state %d\n", dbc->state);
847 /* Handle the events in the event ring: */
848 evt = dbc->ring_evt->dequeue;
849 while ((le32_to_cpu(evt->event_cmd.flags) & TRB_CYCLE) ==
850 dbc->ring_evt->cycle_state) {
852 * Add a barrier between reading the cycle flag and any
853 * reads of the event's flags/data below:
857 trace_xhci_dbc_handle_event(dbc->ring_evt, &evt->generic);
859 switch (le32_to_cpu(evt->event_cmd.flags) & TRB_TYPE_BITMASK) {
860 case TRB_TYPE(TRB_PORT_STATUS):
861 dbc_handle_port_status(dbc, evt);
863 case TRB_TYPE(TRB_TRANSFER):
864 dbc_handle_xfer_event(dbc, evt);
870 inc_evt_deq(dbc->ring_evt);
872 evt = dbc->ring_evt->dequeue;
876 /* Update event ring dequeue pointer: */
878 deq = xhci_trb_virt_to_dma(dbc->ring_evt->deq_seg,
879 dbc->ring_evt->dequeue);
880 lo_hi_writeq(deq, &dbc->regs->erdp);
886 static void xhci_dbc_handle_events(struct work_struct *work)
889 struct xhci_dbc *dbc;
892 dbc = container_of(to_delayed_work(work), struct xhci_dbc, event_work);
894 spin_lock_irqsave(&dbc->lock, flags);
895 evtr = xhci_dbc_do_handle_events(dbc);
896 spin_unlock_irqrestore(&dbc->lock, flags);
900 if (dbc->driver->configure)
901 dbc->driver->configure(dbc);
904 if (dbc->driver->disconnect)
905 dbc->driver->disconnect(dbc);
910 dev_info(dbc->dev, "stop handling dbc events\n");
914 mod_delayed_work(system_wq, &dbc->event_work, 1);
917 static void xhci_do_dbc_exit(struct xhci_hcd *xhci)
921 spin_lock_irqsave(&xhci->lock, flags);
924 spin_unlock_irqrestore(&xhci->lock, flags);
927 static int xhci_do_dbc_init(struct xhci_hcd *xhci)
930 struct xhci_dbc *dbc;
935 base = &xhci->cap_regs->hc_capbase;
936 dbc_cap_offs = xhci_find_next_ext_cap(base, 0, XHCI_EXT_CAPS_DEBUG);
940 dbc = kzalloc(sizeof(*dbc), GFP_KERNEL);
944 dbc->regs = base + dbc_cap_offs;
946 /* We will avoid using DbC in xhci driver if it's in use. */
947 reg = readl(&dbc->regs->control);
948 if (reg & DBC_CTRL_DBC_ENABLE) {
953 spin_lock_irqsave(&xhci->lock, flags);
955 spin_unlock_irqrestore(&xhci->lock, flags);
960 spin_unlock_irqrestore(&xhci->lock, flags);
963 dbc->dev = xhci_to_hcd(xhci)->self.sysdev;
964 INIT_DELAYED_WORK(&dbc->event_work, xhci_dbc_handle_events);
965 spin_lock_init(&dbc->lock);
970 static ssize_t dbc_show(struct device *dev,
971 struct device_attribute *attr,
975 struct xhci_dbc *dbc;
976 struct xhci_hcd *xhci;
978 xhci = hcd_to_xhci(dev_get_drvdata(dev));
981 switch (dbc->state) {
1004 return sprintf(buf, "%s\n", p);
1007 static ssize_t dbc_store(struct device *dev,
1008 struct device_attribute *attr,
1009 const char *buf, size_t count)
1011 struct xhci_hcd *xhci;
1012 struct xhci_dbc *dbc;
1014 xhci = hcd_to_xhci(dev_get_drvdata(dev));
1017 if (!strncmp(buf, "enable", 6))
1018 xhci_dbc_start(dbc);
1019 else if (!strncmp(buf, "disable", 7))
1027 static DEVICE_ATTR_RW(dbc);
1029 int xhci_dbc_init(struct xhci_hcd *xhci)
1032 struct device *dev = xhci_to_hcd(xhci)->self.controller;
1034 ret = xhci_do_dbc_init(xhci);
1038 ret = xhci_dbc_tty_probe(xhci);
1042 ret = device_create_file(dev, &dev_attr_dbc);
1049 xhci_dbc_tty_remove(xhci->dbc);
1051 xhci_do_dbc_exit(xhci);
1056 void xhci_dbc_exit(struct xhci_hcd *xhci)
1058 struct device *dev = xhci_to_hcd(xhci)->self.controller;
1063 device_remove_file(dev, &dev_attr_dbc);
1064 xhci_dbc_tty_remove(xhci->dbc);
1065 xhci_dbc_stop(xhci->dbc);
1066 xhci_do_dbc_exit(xhci);
1070 int xhci_dbc_suspend(struct xhci_hcd *xhci)
1072 struct xhci_dbc *dbc = xhci->dbc;
1077 if (dbc->state == DS_CONFIGURED)
1078 dbc->resume_required = 1;
1085 int xhci_dbc_resume(struct xhci_hcd *xhci)
1088 struct xhci_dbc *dbc = xhci->dbc;
1093 if (dbc->resume_required) {
1094 dbc->resume_required = 0;
1095 xhci_dbc_start(dbc);
1100 #endif /* CONFIG_PM */