drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c

   1 /*
   2  * Copyright 2008 Jerome Glisse.
   3  * All Rights Reserved.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice (including the next
  13  * paragraph) shall be included in all copies or substantial portions of the
  14  * Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * PRECISION INSIGHT AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  22  * DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors:
  25  *    Jerome Glisse <[email protected]>
  26  */
  27 #include <linux/list_sort.h>
  28 #include <drm/drmP.h>
  29 #include <drm/amdgpu_drm.h>
  30 #include "amdgpu.h"
  31 #include "amdgpu_trace.h"
  32
  33 #define AMDGPU_CS_MAX_PRIORITY          32u
  34 #define AMDGPU_CS_NUM_BUCKETS           (AMDGPU_CS_MAX_PRIORITY + 1)
  35
  36 /* This is based on the bucket sort with O(n) time complexity.
  37  * An item with priority "i" is added to bucket[i]. The lists are then
  38  * concatenated in descending order.
  39  */
  40 struct amdgpu_cs_buckets {
  41         struct list_head bucket[AMDGPU_CS_NUM_BUCKETS];
  42 };
  43
  44 static void amdgpu_cs_buckets_init(struct amdgpu_cs_buckets *b)
  45 {
  46         unsigned i;
  47
  48         for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++)
  49                 INIT_LIST_HEAD(&b->bucket[i]);
  50 }
  51
  52 static void amdgpu_cs_buckets_add(struct amdgpu_cs_buckets *b,
  53                                   struct list_head *item, unsigned priority)
  54 {
  55         /* Since buffers which appear sooner in the relocation list are
  56          * likely to be used more often than buffers which appear later
  57          * in the list, the sort mustn't change the ordering of buffers
  58          * with the same priority, i.e. it must be stable.
  59          */
  60         list_add_tail(item, &b->bucket[min(priority, AMDGPU_CS_MAX_PRIORITY)]);
  61 }
  62
  63 static void amdgpu_cs_buckets_get_list(struct amdgpu_cs_buckets *b,
  64                                        struct list_head *out_list)
  65 {
  66         unsigned i;
  67
  68         /* Connect the sorted buckets in the output list. */
  69         for (i = 0; i < AMDGPU_CS_NUM_BUCKETS; i++) {
  70                 list_splice(&b->bucket[i], out_list);
  71         }
  72 }
  73
  74 int amdgpu_cs_get_ring(struct amdgpu_device *adev, u32 ip_type,
  75                        u32 ip_instance, u32 ring,
  76                        struct amdgpu_ring **out_ring)
  77 {
  78         /* Right now all IPs have only one instance - multiple rings. */
  79         if (ip_instance != 0) {
  80                 DRM_ERROR("invalid ip instance: %d\n", ip_instance);
  81                 return -EINVAL;
  82         }
  83
  84         switch (ip_type) {
  85         default:
  86                 DRM_ERROR("unknown ip type: %d\n", ip_type);
  87                 return -EINVAL;
  88         case AMDGPU_HW_IP_GFX:
  89                 if (ring < adev->gfx.num_gfx_rings) {
  90                         *out_ring = &adev->gfx.gfx_ring[ring];
  91                 } else {
  92                         DRM_ERROR("only %d gfx rings are supported now\n",
  93                                   adev->gfx.num_gfx_rings);
  94                         return -EINVAL;
  95                 }
  96                 break;
  97         case AMDGPU_HW_IP_COMPUTE:
  98                 if (ring < adev->gfx.num_compute_rings) {
  99                         *out_ring = &adev->gfx.compute_ring[ring];
 100                 } else {
 101                         DRM_ERROR("only %d compute rings are supported now\n",
 102                                   adev->gfx.num_compute_rings);
 103                         return -EINVAL;
 104                 }
 105                 break;
 106         case AMDGPU_HW_IP_DMA:
 107                 if (ring < 2) {
 108                         *out_ring = &adev->sdma[ring].ring;
 109                 } else {
 110                         DRM_ERROR("only two SDMA rings are supported\n");
 111                         return -EINVAL;
 112                 }
 113                 break;
 114         case AMDGPU_HW_IP_UVD:
 115                 *out_ring = &adev->uvd.ring;
 116                 break;
 117         case AMDGPU_HW_IP_VCE:
 118                 if (ring < 2){
 119                         *out_ring = &adev->vce.ring[ring];
 120                 } else {
 121                         DRM_ERROR("only two VCE rings are supported\n");
 122                         return -EINVAL;
 123                 }
 124                 break;
 125         }
 126         return 0;
 127 }
 128
 129 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
 130 {
 131         union drm_amdgpu_cs *cs = data;
 132         uint64_t *chunk_array_user;
 133         uint64_t *chunk_array = NULL;
 134         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 135         unsigned size, i;
 136         int r = 0;
 137
 138         if (!cs->in.num_chunks)
 139                 goto out;
 140
 141         p->ctx = amdgpu_ctx_get(fpriv, cs->in.ctx_id);
 142         if (!p->ctx) {
 143                 r = -EINVAL;
 144                 goto out;
 145         }
 146         p->bo_list = amdgpu_bo_list_get(fpriv, cs->in.bo_list_handle);
 147
 148         /* get chunks */
 149         INIT_LIST_HEAD(&p->validated);
 150         chunk_array = kcalloc(cs->in.num_chunks, sizeof(uint64_t), GFP_KERNEL);
 151         if (chunk_array == NULL) {
 152                 r = -ENOMEM;
 153                 goto out;
 154         }
 155
 156         chunk_array_user = (uint64_t *)(unsigned long)(cs->in.chunks);
 157         if (copy_from_user(chunk_array, chunk_array_user,
 158                            sizeof(uint64_t)*cs->in.num_chunks)) {
 159                 r = -EFAULT;
 160                 goto out;
 161         }
 162
 163         p->nchunks = cs->in.num_chunks;
 164         p->chunks = kcalloc(p->nchunks, sizeof(struct amdgpu_cs_chunk),
 165                             GFP_KERNEL);
 166         if (p->chunks == NULL) {
 167                 r = -ENOMEM;
 168                 goto out;
 169         }
 170
 171         for (i = 0; i < p->nchunks; i++) {
 172                 struct drm_amdgpu_cs_chunk __user **chunk_ptr = NULL;
 173                 struct drm_amdgpu_cs_chunk user_chunk;
 174                 uint32_t __user *cdata;
 175
 176                 chunk_ptr = (void __user *)(unsigned long)chunk_array[i];
 177                 if (copy_from_user(&user_chunk, chunk_ptr,
 178                                        sizeof(struct drm_amdgpu_cs_chunk))) {
 179                         r = -EFAULT;
 180                         goto out;
 181                 }
 182                 p->chunks[i].chunk_id = user_chunk.chunk_id;
 183                 p->chunks[i].length_dw = user_chunk.length_dw;
 184                 if (p->chunks[i].chunk_id == AMDGPU_CHUNK_ID_IB)
 185                         p->num_ibs++;
 186
 187                 size = p->chunks[i].length_dw;
 188                 cdata = (void __user *)(unsigned long)user_chunk.chunk_data;
 189                 p->chunks[i].user_ptr = cdata;
 190
 191                 p->chunks[i].kdata = drm_malloc_ab(size, sizeof(uint32_t));
 192                 if (p->chunks[i].kdata == NULL) {
 193                         r = -ENOMEM;
 194                         goto out;
 195                 }
 196                 size *= sizeof(uint32_t);
 197                 if (copy_from_user(p->chunks[i].kdata, cdata, size)) {
 198                         r = -EFAULT;
 199                         goto out;
 200                 }
 201
 202                 if (p->chunks[i].chunk_id == AMDGPU_CHUNK_ID_FENCE) {
 203                         size = sizeof(struct drm_amdgpu_cs_chunk_fence);
 204                         if (p->chunks[i].length_dw * sizeof(uint32_t) >= size) {
 205                                 uint32_t handle;
 206                                 struct drm_gem_object *gobj;
 207                                 struct drm_amdgpu_cs_chunk_fence *fence_data;
 208
 209                                 fence_data = (void *)p->chunks[i].kdata;
 210                                 handle = fence_data->handle;
 211                                 gobj = drm_gem_object_lookup(p->adev->ddev,
 212                                                              p->filp, handle);
 213                                 if (gobj == NULL) {
 214                                         r = -EINVAL;
 215                                         goto out;
 216                                 }
 217
 218                                 p->uf.bo = gem_to_amdgpu_bo(gobj);
 219                                 p->uf.offset = fence_data->offset;
 220                         } else {
 221                                 r = -EINVAL;
 222                                 goto out;
 223                         }
 224                 }
 225         }
 226
 227         p->ibs = kcalloc(p->num_ibs, sizeof(struct amdgpu_ib), GFP_KERNEL);
 228         if (!p->ibs) {
 229                 r = -ENOMEM;
 230                 goto out;
 231         }
 232
 233 out:
 234         kfree(chunk_array);
 235         return r;
 236 }
 237
 238 /* Returns how many bytes TTM can move per IB.
 239  */
 240 static u64 amdgpu_cs_get_threshold_for_moves(struct amdgpu_device *adev)
 241 {
 242         u64 real_vram_size = adev->mc.real_vram_size;
 243         u64 vram_usage = atomic64_read(&adev->vram_usage);
 244
 245         /* This function is based on the current VRAM usage.
 246          *
 247          * - If all of VRAM is free, allow relocating the number of bytes that
 248          *   is equal to 1/4 of the size of VRAM for this IB.
 249
 250          * - If more than one half of VRAM is occupied, only allow relocating
 251          *   1 MB of data for this IB.
 252          *
 253          * - From 0 to one half of used VRAM, the threshold decreases
 254          *   linearly.
 255          *         __________________
 256          * 1/4 of -|\               |
 257          * VRAM    | \              |
 258          *         |  \             |
 259          *         |   \            |
 260          *         |    \           |
 261          *         |     \          |
 262          *         |      \         |
 263          *         |       \________|1 MB
 264          *         |----------------|
 265          *    VRAM 0 %             100 %
 266          *         used            used
 267          *
 268          * Note: It's a threshold, not a limit. The threshold must be crossed
 269          * for buffer relocations to stop, so any buffer of an arbitrary size
 270          * can be moved as long as the threshold isn't crossed before
 271          * the relocation takes place. We don't want to disable buffer
 272          * relocations completely.
 273          *
 274          * The idea is that buffers should be placed in VRAM at creation time
 275          * and TTM should only do a minimum number of relocations during
 276          * command submission. In practice, you need to submit at least
 277          * a dozen IBs to move all buffers to VRAM if they are in GTT.
 278          *
 279          * Also, things can get pretty crazy under memory pressure and actual
 280          * VRAM usage can change a lot, so playing safe even at 50% does
 281          * consistently increase performance.
 282          */
 283
 284         u64 half_vram = real_vram_size >> 1;
 285         u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
 286         u64 bytes_moved_threshold = half_free_vram >> 1;
 287         return max(bytes_moved_threshold, 1024*1024ull);
 288 }
 289
 290 int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p)
 291 {
 292         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 293         struct amdgpu_vm *vm = &fpriv->vm;
 294         struct amdgpu_device *adev = p->adev;
 295         struct amdgpu_bo_list_entry *lobj;
 296         struct list_head duplicates;
 297         struct amdgpu_bo *bo;
 298         u64 bytes_moved = 0, initial_bytes_moved;
 299         u64 bytes_moved_threshold = amdgpu_cs_get_threshold_for_moves(adev);
 300         int r;
 301
 302         INIT_LIST_HEAD(&duplicates);
 303         r = ttm_eu_reserve_buffers(&p->ticket, &p->validated, true, &duplicates);
 304         if (unlikely(r != 0)) {
 305                 return r;
 306         }
 307
 308         list_for_each_entry(lobj, &p->validated, tv.head) {
 309                 bo = lobj->robj;
 310                 if (!bo->pin_count) {
 311                         u32 domain = lobj->prefered_domains;
 312                         u32 current_domain =
 313                                 amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
 314
 315                         /* Check if this buffer will be moved and don't move it
 316                          * if we have moved too many buffers for this IB already.
 317                          *
 318                          * Note that this allows moving at least one buffer of
 319                          * any size, because it doesn't take the current "bo"
 320                          * into account. We don't want to disallow buffer moves
 321                          * completely.
 322                          */
 323                         if (current_domain != AMDGPU_GEM_DOMAIN_CPU &&
 324                             (domain & current_domain) == 0 && /* will be moved */
 325                             bytes_moved > bytes_moved_threshold) {
 326                                 /* don't move it */
 327                                 domain = current_domain;
 328                         }
 329
 330                 retry:
 331                         amdgpu_ttm_placement_from_domain(bo, domain);
 332                         initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
 333                         r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
 334                         bytes_moved += atomic64_read(&adev->num_bytes_moved) -
 335                                        initial_bytes_moved;
 336
 337                         if (unlikely(r)) {
 338                                 if (r != -ERESTARTSYS && domain != lobj->allowed_domains) {
 339                                         domain = lobj->allowed_domains;
 340                                         goto retry;
 341                                 }
 342                                 ttm_eu_backoff_reservation(&p->ticket, &p->validated);
 343                                 return r;
 344                         }
 345                 }
 346                 lobj->bo_va = amdgpu_vm_bo_find(vm, bo);
 347         }
 348         return 0;
 349 }
 350
 351 static int amdgpu_cs_parser_relocs(struct amdgpu_cs_parser *p)
 352 {
 353         struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
 354         struct amdgpu_cs_buckets buckets;
 355         bool need_mmap_lock = false;
 356         int i, r;
 357
 358         if (p->bo_list) {
 359                 need_mmap_lock = p->bo_list->has_userptr;
 360                 amdgpu_cs_buckets_init(&buckets);
 361                 for (i = 0; i < p->bo_list->num_entries; i++)
 362                         amdgpu_cs_buckets_add(&buckets, &p->bo_list->array[i].tv.head,
 363                                                                   p->bo_list->array[i].priority);
 364
 365                 amdgpu_cs_buckets_get_list(&buckets, &p->validated);
 366         }
 367
 368         p->vm_bos = amdgpu_vm_get_bos(p->adev, &fpriv->vm,
 369                                       &p->validated);
 370
 371         if (need_mmap_lock)
 372                 down_read(&current->mm->mmap_sem);
 373
 374         r = amdgpu_cs_list_validate(p);
 375
 376         if (need_mmap_lock)
 377                 up_read(&current->mm->mmap_sem);
 378
 379         return r;
 380 }
 381
 382 static int amdgpu_cs_sync_rings(struct amdgpu_cs_parser *p)
 383 {
 384         struct amdgpu_bo_list_entry *e;
 385         int r;
 386
 387         list_for_each_entry(e, &p->validated, tv.head) {
 388                 struct reservation_object *resv = e->robj->tbo.resv;
 389                 r = amdgpu_sync_resv(p->adev, &p->ibs[0].sync, resv, p->filp);
 390
 391                 if (r)
 392                         return r;
 393         }
 394         return 0;
 395 }
 396
 397 static int cmp_size_smaller_first(void *priv, struct list_head *a,
 398                                   struct list_head *b)
 399 {
 400         struct amdgpu_bo_list_entry *la = list_entry(a, struct amdgpu_bo_list_entry, tv.head);
 401         struct amdgpu_bo_list_entry *lb = list_entry(b, struct amdgpu_bo_list_entry, tv.head);
 402
 403         /* Sort A before B if A is smaller. */
 404         return (int)la->robj->tbo.num_pages - (int)lb->robj->tbo.num_pages;
 405 }
 406
 407 /**
 408  * cs_parser_fini() - clean parser states
 409  * @parser:     parser structure holding parsing context.
 410  * @error:      error number
 411  *
 412  * If error is set than unvalidate buffer, otherwise just free memory
 413  * used by parsing context.
 414  **/
 415 static void amdgpu_cs_parser_fini(struct amdgpu_cs_parser *parser, int error, bool backoff)
 416 {
 417         unsigned i;
 418
 419         if (!error) {
 420                 /* Sort the buffer list from the smallest to largest buffer,
 421                  * which affects the order of buffers in the LRU list.
 422                  * This assures that the smallest buffers are added first
 423                  * to the LRU list, so they are likely to be later evicted
 424                  * first, instead of large buffers whose eviction is more
 425                  * expensive.
 426                  *
 427                  * This slightly lowers the number of bytes moved by TTM
 428                  * per frame under memory pressure.
 429                  */
 430                 list_sort(NULL, &parser->validated, cmp_size_smaller_first);
 431
 432                 ttm_eu_fence_buffer_objects(&parser->ticket,
 433                                 &parser->validated,
 434                                 &parser->ibs[parser->num_ibs-1].fence->base);
 435         } else if (backoff) {
 436                 ttm_eu_backoff_reservation(&parser->ticket,
 437                                            &parser->validated);
 438         }
 439
 440         if (parser->ctx)
 441                 amdgpu_ctx_put(parser->ctx);
 442         if (parser->bo_list)
 443                 amdgpu_bo_list_put(parser->bo_list);
 444         drm_free_large(parser->vm_bos);
 445         for (i = 0; i < parser->nchunks; i++)
 446                 drm_free_large(parser->chunks[i].kdata);
 447         kfree(parser->chunks);
 448         for (i = 0; i < parser->num_ibs; i++)
 449                 amdgpu_ib_free(parser->adev, &parser->ibs[i]);
 450         kfree(parser->ibs);
 451         if (parser->uf.bo)
 452                 drm_gem_object_unreference_unlocked(&parser->uf.bo->gem_base);
 453 }
 454
 455 static int amdgpu_bo_vm_update_pte(struct amdgpu_cs_parser *p,
 456                                    struct amdgpu_vm *vm)
 457 {
 458         struct amdgpu_device *adev = p->adev;
 459         struct amdgpu_bo_va *bo_va;
 460         struct amdgpu_bo *bo;
 461         int i, r;
 462
 463         r = amdgpu_vm_update_page_directory(adev, vm);
 464         if (r)
 465                 return r;
 466
 467         r = amdgpu_vm_clear_freed(adev, vm);
 468         if (r)
 469                 return r;
 470
 471         if (p->bo_list) {
 472                 for (i = 0; i < p->bo_list->num_entries; i++) {
 473                         /* ignore duplicates */
 474                         bo = p->bo_list->array[i].robj;
 475                         if (!bo)
 476                                 continue;
 477
 478                         bo_va = p->bo_list->array[i].bo_va;
 479                         if (bo_va == NULL)
 480                                 continue;
 481
 482                         r = amdgpu_vm_bo_update(adev, bo_va, &bo->tbo.mem);
 483                         if (r)
 484                                 return r;
 485
 486                         amdgpu_sync_fence(&p->ibs[0].sync, bo_va->last_pt_update);
 487                 }
 488         }
 489
 490         return amdgpu_vm_clear_invalids(adev, vm, &p->ibs[0].sync);
 491 }
 492
 493 static int amdgpu_cs_ib_vm_chunk(struct amdgpu_device *adev,
 494                                  struct amdgpu_cs_parser *parser)
 495 {
 496         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 497         struct amdgpu_vm *vm = &fpriv->vm;
 498         struct amdgpu_ring *ring;
 499         int i, r;
 500
 501         if (parser->num_ibs == 0)
 502                 return 0;
 503
 504         /* Only for UVD/VCE VM emulation */
 505         for (i = 0; i < parser->num_ibs; i++) {
 506                 ring = parser->ibs[i].ring;
 507                 if (ring->funcs->parse_cs) {
 508                         r = amdgpu_ring_parse_cs(ring, parser, i);
 509                         if (r)
 510                                 return r;
 511                 }
 512         }
 513
 514         mutex_lock(&vm->mutex);
 515         r = amdgpu_bo_vm_update_pte(parser, vm);
 516         if (r) {
 517                 goto out;
 518         }
 519         amdgpu_cs_sync_rings(parser);
 520
 521         r = amdgpu_ib_schedule(adev, parser->num_ibs, parser->ibs,
 522                                parser->filp);
 523
 524 out:
 525         mutex_unlock(&vm->mutex);
 526         return r;
 527 }
 528
 529 static int amdgpu_cs_handle_lockup(struct amdgpu_device *adev, int r)
 530 {
 531         if (r == -EDEADLK) {
 532                 r = amdgpu_gpu_reset(adev);
 533                 if (!r)
 534                         r = -EAGAIN;
 535         }
 536         return r;
 537 }
 538
 539 static int amdgpu_cs_ib_fill(struct amdgpu_device *adev,
 540                              struct amdgpu_cs_parser *parser)
 541 {
 542         struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
 543         struct amdgpu_vm *vm = &fpriv->vm;
 544         int i, j;
 545         int r;
 546
 547         for (i = 0, j = 0; i < parser->nchunks && j < parser->num_ibs; i++) {
 548                 struct amdgpu_cs_chunk *chunk;
 549                 struct amdgpu_ib *ib;
 550                 struct drm_amdgpu_cs_chunk_ib *chunk_ib;
 551                 struct amdgpu_ring *ring;
 552
 553                 chunk = &parser->chunks[i];
 554                 ib = &parser->ibs[j];
 555                 chunk_ib = (struct drm_amdgpu_cs_chunk_ib *)chunk->kdata;
 556
 557                 if (chunk->chunk_id != AMDGPU_CHUNK_ID_IB)
 558                         continue;
 559
 560                 r = amdgpu_cs_get_ring(adev, chunk_ib->ip_type,
 561                                        chunk_ib->ip_instance, chunk_ib->ring,
 562                                        &ring);
 563                 if (r)
 564                         return r;
 565
 566                 if (ring->funcs->parse_cs) {
 567                         struct amdgpu_bo_va_mapping *m;
 568                         struct amdgpu_bo *aobj = NULL;
 569                         uint64_t offset;
 570                         uint8_t *kptr;
 571
 572                         m = amdgpu_cs_find_mapping(parser, chunk_ib->va_start,
 573                                                    &aobj);
 574                         if (!aobj) {
 575                                 DRM_ERROR("IB va_start is invalid\n");
 576                                 return -EINVAL;
 577                         }
 578
 579                         if ((chunk_ib->va_start + chunk_ib->ib_bytes) >
 580                             (m->it.last + 1) * AMDGPU_GPU_PAGE_SIZE) {
 581                                 DRM_ERROR("IB va_start+ib_bytes is invalid\n");
 582                                 return -EINVAL;
 583                         }
 584
 585                         /* the IB should be reserved at this point */
 586                         r = amdgpu_bo_kmap(aobj, (void **)&kptr);
 587                         if (r) {
 588                                 return r;
 589                         }
 590
 591                         offset = ((uint64_t)m->it.start) * AMDGPU_GPU_PAGE_SIZE;
 592                         kptr += chunk_ib->va_start - offset;
 593
 594                         r =  amdgpu_ib_get(ring, NULL, chunk_ib->ib_bytes, ib);
 595                         if (r) {
 596                                 DRM_ERROR("Failed to get ib !\n");
 597                                 return r;
 598                         }
 599
 600                         memcpy(ib->ptr, kptr, chunk_ib->ib_bytes);
 601                         amdgpu_bo_kunmap(aobj);
 602                 } else {
 603                         r =  amdgpu_ib_get(ring, vm, 0, ib);
 604                         if (r) {
 605                                 DRM_ERROR("Failed to get ib !\n");
 606                                 return r;
 607                         }
 608
 609                         ib->gpu_addr = chunk_ib->va_start;
 610                 }
 611
 612                 ib->length_dw = chunk_ib->ib_bytes / 4;
 613                 ib->flags = chunk_ib->flags;
 614                 ib->ctx = parser->ctx;
 615                 j++;
 616         }
 617
 618         if (!parser->num_ibs)
 619                 return 0;
 620
 621         /* add GDS resources to first IB */
 622         if (parser->bo_list) {
 623                 struct amdgpu_bo *gds = parser->bo_list->gds_obj;
 624                 struct amdgpu_bo *gws = parser->bo_list->gws_obj;
 625                 struct amdgpu_bo *oa = parser->bo_list->oa_obj;
 626                 struct amdgpu_ib *ib = &parser->ibs[0];
 627
 628                 if (gds) {
 629                         ib->gds_base = amdgpu_bo_gpu_offset(gds);
 630                         ib->gds_size = amdgpu_bo_size(gds);
 631                 }
 632                 if (gws) {
 633                         ib->gws_base = amdgpu_bo_gpu_offset(gws);
 634                         ib->gws_size = amdgpu_bo_size(gws);
 635                 }
 636                 if (oa) {
 637                         ib->oa_base = amdgpu_bo_gpu_offset(oa);
 638                         ib->oa_size = amdgpu_bo_size(oa);
 639                 }
 640         }
 641
 642         /* wrap the last IB with user fence */
 643         if (parser->uf.bo) {
 644                 struct amdgpu_ib *ib = &parser->ibs[parser->num_ibs - 1];
 645
 646                 /* UVD & VCE fw doesn't support user fences */
 647                 if (ib->ring->type == AMDGPU_RING_TYPE_UVD ||
 648                     ib->ring->type == AMDGPU_RING_TYPE_VCE)
 649                         return -EINVAL;
 650
 651                 ib->user = &parser->uf;
 652         }
 653
 654         return 0;
 655 }
 656
 657 int amdgpu_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 658 {
 659         struct amdgpu_device *adev = dev->dev_private;
 660         union drm_amdgpu_cs *cs = data;
 661         struct amdgpu_cs_parser parser;
 662         int r, i;
 663         bool reserved_buffers = false;
 664
 665         down_read(&adev->exclusive_lock);
 666         if (!adev->accel_working) {
 667                 up_read(&adev->exclusive_lock);
 668                 return -EBUSY;
 669         }
 670         /* initialize parser */
 671         memset(&parser, 0, sizeof(struct amdgpu_cs_parser));
 672         parser.filp = filp;
 673         parser.adev = adev;
 674         r = amdgpu_cs_parser_init(&parser, data);
 675         if (r) {
 676                 DRM_ERROR("Failed to initialize parser !\n");
 677                 amdgpu_cs_parser_fini(&parser, r, false);
 678                 up_read(&adev->exclusive_lock);
 679                 r = amdgpu_cs_handle_lockup(adev, r);
 680                 return r;
 681         }
 682
 683         r = amdgpu_cs_parser_relocs(&parser);
 684         if (r) {
 685                 if (r != -ERESTARTSYS) {
 686                         if (r == -ENOMEM)
 687                                 DRM_ERROR("Not enough memory for command submission!\n");
 688                         else
 689                                 DRM_ERROR("Failed to process the buffer list %d!\n", r);
 690                 }
 691         } else {
 692                 reserved_buffers = true;
 693                 r = amdgpu_cs_ib_fill(adev, &parser);
 694         }
 695
 696         if (r) {
 697                 amdgpu_cs_parser_fini(&parser, r, reserved_buffers);
 698                 up_read(&adev->exclusive_lock);
 699                 r = amdgpu_cs_handle_lockup(adev, r);
 700                 return r;
 701         }
 702
 703         for (i = 0; i < parser.num_ibs; i++)
 704                 trace_amdgpu_cs(&parser, i);
 705
 706         r = amdgpu_cs_ib_vm_chunk(adev, &parser);
 707         if (r) {
 708                 goto out;
 709         }
 710
 711         cs->out.handle = parser.ibs[parser.num_ibs - 1].fence->seq;
 712 out:
 713         amdgpu_cs_parser_fini(&parser, r, true);
 714         up_read(&adev->exclusive_lock);
 715         r = amdgpu_cs_handle_lockup(adev, r);
 716         return r;
 717 }
 718
 719 /**
 720  * amdgpu_cs_wait_ioctl - wait for a command submission to finish
 721  *
 722  * @dev: drm device
 723  * @data: data from userspace
 724  * @filp: file private
 725  *
 726  * Wait for the command submission identified by handle to finish.
 727  */
 728 int amdgpu_cs_wait_ioctl(struct drm_device *dev, void *data,
 729                          struct drm_file *filp)
 730 {
 731         union drm_amdgpu_wait_cs *wait = data;
 732         struct amdgpu_device *adev = dev->dev_private;
 733         uint64_t seq[AMDGPU_MAX_RINGS] = {0};
 734         struct amdgpu_ring *ring = NULL;
 735         unsigned long timeout = amdgpu_gem_timeout(wait->in.timeout);
 736         struct amdgpu_ctx *ctx;
 737         long r;
 738
 739         ctx = amdgpu_ctx_get(filp->driver_priv, wait->in.ctx_id);
 740         if (ctx == NULL)
 741                 return -EINVAL;
 742
 743         r = amdgpu_cs_get_ring(adev, wait->in.ip_type, wait->in.ip_instance,
 744                                wait->in.ring, &ring);
 745         if (r)
 746                 return r;
 747
 748         seq[ring->idx] = wait->in.handle;
 749
 750         r = amdgpu_fence_wait_seq_timeout(adev, seq, true, timeout);
 751         amdgpu_ctx_put(ctx);
 752         if (r < 0)
 753                 return r;
 754
 755         memset(wait, 0, sizeof(*wait));
 756         wait->out.status = (r == 0);
 757
 758         return 0;
 759 }
 760
 761 /**
 762  * amdgpu_cs_find_bo_va - find bo_va for VM address
 763  *
 764  * @parser: command submission parser context
 765  * @addr: VM address
 766  * @bo: resulting BO of the mapping found
 767  *
 768  * Search the buffer objects in the command submission context for a certain
 769  * virtual memory address. Returns allocation structure when found, NULL
 770  * otherwise.
 771  */
 772 struct amdgpu_bo_va_mapping *
 773 amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser,
 774                        uint64_t addr, struct amdgpu_bo **bo)
 775 {
 776         struct amdgpu_bo_list_entry *reloc;
 777         struct amdgpu_bo_va_mapping *mapping;
 778
 779         addr /= AMDGPU_GPU_PAGE_SIZE;
 780
 781         list_for_each_entry(reloc, &parser->validated, tv.head) {
 782                 if (!reloc->bo_va)
 783                         continue;
 784
 785                 list_for_each_entry(mapping, &reloc->bo_va->mappings, list) {
 786                         if (mapping->it.start > addr ||
 787                             addr > mapping->it.last)
 788                                 continue;
 789
 790                         *bo = reloc->bo_va->bo;
 791                         return mapping;
 792                 }
 793         }
 794
 795         return NULL;
 796 }