drivers/gpu/drm/amd/pm/amdgpu_pm.c

   1 /*
   2  * Copyright 2017 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Rafał Miłecki <[email protected]>
  23  *          Alex Deucher <[email protected]>
  24  */
  25
  26 #include <drm/drm_debugfs.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_drv.h"
  30 #include "amdgpu_pm.h"
  31 #include "amdgpu_dpm.h"
  32 #include "amdgpu_smu.h"
  33 #include "atom.h"
  34 #include <linux/pci.h>
  35 #include <linux/hwmon.h>
  36 #include <linux/hwmon-sysfs.h>
  37 #include <linux/nospec.h>
  38 #include <linux/pm_runtime.h>
  39 #include "hwmgr.h"
  40
  41 static const struct cg_flag_name clocks[] = {
  42         {AMD_CG_SUPPORT_GFX_FGCG, "Graphics Fine Grain Clock Gating"},
  43         {AMD_CG_SUPPORT_GFX_MGCG, "Graphics Medium Grain Clock Gating"},
  44         {AMD_CG_SUPPORT_GFX_MGLS, "Graphics Medium Grain memory Light Sleep"},
  45         {AMD_CG_SUPPORT_GFX_CGCG, "Graphics Coarse Grain Clock Gating"},
  46         {AMD_CG_SUPPORT_GFX_CGLS, "Graphics Coarse Grain memory Light Sleep"},
  47         {AMD_CG_SUPPORT_GFX_CGTS, "Graphics Coarse Grain Tree Shader Clock Gating"},
  48         {AMD_CG_SUPPORT_GFX_CGTS_LS, "Graphics Coarse Grain Tree Shader Light Sleep"},
  49         {AMD_CG_SUPPORT_GFX_CP_LS, "Graphics Command Processor Light Sleep"},
  50         {AMD_CG_SUPPORT_GFX_RLC_LS, "Graphics Run List Controller Light Sleep"},
  51         {AMD_CG_SUPPORT_GFX_3D_CGCG, "Graphics 3D Coarse Grain Clock Gating"},
  52         {AMD_CG_SUPPORT_GFX_3D_CGLS, "Graphics 3D Coarse Grain memory Light Sleep"},
  53         {AMD_CG_SUPPORT_MC_LS, "Memory Controller Light Sleep"},
  54         {AMD_CG_SUPPORT_MC_MGCG, "Memory Controller Medium Grain Clock Gating"},
  55         {AMD_CG_SUPPORT_SDMA_LS, "System Direct Memory Access Light Sleep"},
  56         {AMD_CG_SUPPORT_SDMA_MGCG, "System Direct Memory Access Medium Grain Clock Gating"},
  57         {AMD_CG_SUPPORT_BIF_MGCG, "Bus Interface Medium Grain Clock Gating"},
  58         {AMD_CG_SUPPORT_BIF_LS, "Bus Interface Light Sleep"},
  59         {AMD_CG_SUPPORT_UVD_MGCG, "Unified Video Decoder Medium Grain Clock Gating"},
  60         {AMD_CG_SUPPORT_VCE_MGCG, "Video Compression Engine Medium Grain Clock Gating"},
  61         {AMD_CG_SUPPORT_HDP_LS, "Host Data Path Light Sleep"},
  62         {AMD_CG_SUPPORT_HDP_MGCG, "Host Data Path Medium Grain Clock Gating"},
  63         {AMD_CG_SUPPORT_DRM_MGCG, "Digital Right Management Medium Grain Clock Gating"},
  64         {AMD_CG_SUPPORT_DRM_LS, "Digital Right Management Light Sleep"},
  65         {AMD_CG_SUPPORT_ROM_MGCG, "Rom Medium Grain Clock Gating"},
  66         {AMD_CG_SUPPORT_DF_MGCG, "Data Fabric Medium Grain Clock Gating"},
  67         {AMD_CG_SUPPORT_VCN_MGCG, "VCN Medium Grain Clock Gating"},
  68         {AMD_CG_SUPPORT_HDP_DS, "Host Data Path Deep Sleep"},
  69         {AMD_CG_SUPPORT_HDP_SD, "Host Data Path Shutdown"},
  70         {AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"},
  71         {AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"},
  72
  73         {AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"},
  74         {AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
  75         {0, NULL},
  76 };
  77
  78 static const struct hwmon_temp_label {
  79         enum PP_HWMON_TEMP channel;
  80         const char *label;
  81 } temp_label[] = {
  82         {PP_TEMP_EDGE, "edge"},
  83         {PP_TEMP_JUNCTION, "junction"},
  84         {PP_TEMP_MEM, "mem"},
  85 };
  86
  87 /**
  88  * DOC: power_dpm_state
  89  *
  90  * The power_dpm_state file is a legacy interface and is only provided for
  91  * backwards compatibility. The amdgpu driver provides a sysfs API for adjusting
  92  * certain power related parameters.  The file power_dpm_state is used for this.
  93  * It accepts the following arguments:
  94  *
  95  * - battery
  96  *
  97  * - balanced
  98  *
  99  * - performance
 100  *
 101  * battery
 102  *
 103  * On older GPUs, the vbios provided a special power state for battery
 104  * operation.  Selecting battery switched to this state.  This is no
 105  * longer provided on newer GPUs so the option does nothing in that case.
 106  *
 107  * balanced
 108  *
 109  * On older GPUs, the vbios provided a special power state for balanced
 110  * operation.  Selecting balanced switched to this state.  This is no
 111  * longer provided on newer GPUs so the option does nothing in that case.
 112  *
 113  * performance
 114  *
 115  * On older GPUs, the vbios provided a special power state for performance
 116  * operation.  Selecting performance switched to this state.  This is no
 117  * longer provided on newer GPUs so the option does nothing in that case.
 118  *
 119  */
 120
 121 static ssize_t amdgpu_get_power_dpm_state(struct device *dev,
 122                                           struct device_attribute *attr,
 123                                           char *buf)
 124 {
 125         struct drm_device *ddev = dev_get_drvdata(dev);
 126         struct amdgpu_device *adev = drm_to_adev(ddev);
 127         enum amd_pm_state_type pm;
 128         int ret;
 129
 130         if (amdgpu_in_reset(adev))
 131                 return -EPERM;
 132
 133         ret = pm_runtime_get_sync(ddev->dev);
 134         if (ret < 0) {
 135                 pm_runtime_put_autosuspend(ddev->dev);
 136                 return ret;
 137         }
 138
 139         if (is_support_sw_smu(adev)) {
 140                 if (adev->smu.ppt_funcs->get_current_power_state)
 141                         pm = smu_get_current_power_state(&adev->smu);
 142                 else
 143                         pm = adev->pm.dpm.user_state;
 144         } else if (adev->powerplay.pp_funcs->get_current_power_state) {
 145                 pm = amdgpu_dpm_get_current_power_state(adev);
 146         } else {
 147                 pm = adev->pm.dpm.user_state;
 148         }
 149
 150         pm_runtime_mark_last_busy(ddev->dev);
 151         pm_runtime_put_autosuspend(ddev->dev);
 152
 153         return snprintf(buf, PAGE_SIZE, "%s\n",
 154                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 155                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 156 }
 157
 158 static ssize_t amdgpu_set_power_dpm_state(struct device *dev,
 159                                           struct device_attribute *attr,
 160                                           const char *buf,
 161                                           size_t count)
 162 {
 163         struct drm_device *ddev = dev_get_drvdata(dev);
 164         struct amdgpu_device *adev = drm_to_adev(ddev);
 165         enum amd_pm_state_type  state;
 166         int ret;
 167
 168         if (amdgpu_in_reset(adev))
 169                 return -EPERM;
 170
 171         if (strncmp("battery", buf, strlen("battery")) == 0)
 172                 state = POWER_STATE_TYPE_BATTERY;
 173         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 174                 state = POWER_STATE_TYPE_BALANCED;
 175         else if (strncmp("performance", buf, strlen("performance")) == 0)
 176                 state = POWER_STATE_TYPE_PERFORMANCE;
 177         else
 178                 return -EINVAL;
 179
 180         ret = pm_runtime_get_sync(ddev->dev);
 181         if (ret < 0) {
 182                 pm_runtime_put_autosuspend(ddev->dev);
 183                 return ret;
 184         }
 185
 186         if (is_support_sw_smu(adev)) {
 187                 mutex_lock(&adev->pm.mutex);
 188                 adev->pm.dpm.user_state = state;
 189                 mutex_unlock(&adev->pm.mutex);
 190         } else if (adev->powerplay.pp_funcs->dispatch_tasks) {
 191                 amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_ENABLE_USER_STATE, &state);
 192         } else {
 193                 mutex_lock(&adev->pm.mutex);
 194                 adev->pm.dpm.user_state = state;
 195                 mutex_unlock(&adev->pm.mutex);
 196
 197                 amdgpu_pm_compute_clocks(adev);
 198         }
 199         pm_runtime_mark_last_busy(ddev->dev);
 200         pm_runtime_put_autosuspend(ddev->dev);
 201
 202         return count;
 203 }
 204
 205
 206 /**
 207  * DOC: power_dpm_force_performance_level
 208  *
 209  * The amdgpu driver provides a sysfs API for adjusting certain power
 210  * related parameters.  The file power_dpm_force_performance_level is
 211  * used for this.  It accepts the following arguments:
 212  *
 213  * - auto
 214  *
 215  * - low
 216  *
 217  * - high
 218  *
 219  * - manual
 220  *
 221  * - profile_standard
 222  *
 223  * - profile_min_sclk
 224  *
 225  * - profile_min_mclk
 226  *
 227  * - profile_peak
 228  *
 229  * auto
 230  *
 231  * When auto is selected, the driver will attempt to dynamically select
 232  * the optimal power profile for current conditions in the driver.
 233  *
 234  * low
 235  *
 236  * When low is selected, the clocks are forced to the lowest power state.
 237  *
 238  * high
 239  *
 240  * When high is selected, the clocks are forced to the highest power state.
 241  *
 242  * manual
 243  *
 244  * When manual is selected, the user can manually adjust which power states
 245  * are enabled for each clock domain via the sysfs pp_dpm_mclk, pp_dpm_sclk,
 246  * and pp_dpm_pcie files and adjust the power state transition heuristics
 247  * via the pp_power_profile_mode sysfs file.
 248  *
 249  * profile_standard
 250  * profile_min_sclk
 251  * profile_min_mclk
 252  * profile_peak
 253  *
 254  * When the profiling modes are selected, clock and power gating are
 255  * disabled and the clocks are set for different profiling cases. This
 256  * mode is recommended for profiling specific work loads where you do
 257  * not want clock or power gating for clock fluctuation to interfere
 258  * with your results. profile_standard sets the clocks to a fixed clock
 259  * level which varies from asic to asic.  profile_min_sclk forces the sclk
 260  * to the lowest level.  profile_min_mclk forces the mclk to the lowest level.
 261  * profile_peak sets all clocks (mclk, sclk, pcie) to the highest levels.
 262  *
 263  */
 264
 265 static ssize_t amdgpu_get_power_dpm_force_performance_level(struct device *dev,
 266                                                             struct device_attribute *attr,
 267                                                             char *buf)
 268 {
 269         struct drm_device *ddev = dev_get_drvdata(dev);
 270         struct amdgpu_device *adev = drm_to_adev(ddev);
 271         enum amd_dpm_forced_level level = 0xff;
 272         int ret;
 273
 274         if (amdgpu_in_reset(adev))
 275                 return -EPERM;
 276
 277         ret = pm_runtime_get_sync(ddev->dev);
 278         if (ret < 0) {
 279                 pm_runtime_put_autosuspend(ddev->dev);
 280                 return ret;
 281         }
 282
 283         if (is_support_sw_smu(adev))
 284                 level = smu_get_performance_level(&adev->smu);
 285         else if (adev->powerplay.pp_funcs->get_performance_level)
 286                 level = amdgpu_dpm_get_performance_level(adev);
 287         else
 288                 level = adev->pm.dpm.forced_level;
 289
 290         pm_runtime_mark_last_busy(ddev->dev);
 291         pm_runtime_put_autosuspend(ddev->dev);
 292
 293         return snprintf(buf, PAGE_SIZE, "%s\n",
 294                         (level == AMD_DPM_FORCED_LEVEL_AUTO) ? "auto" :
 295                         (level == AMD_DPM_FORCED_LEVEL_LOW) ? "low" :
 296                         (level == AMD_DPM_FORCED_LEVEL_HIGH) ? "high" :
 297                         (level == AMD_DPM_FORCED_LEVEL_MANUAL) ? "manual" :
 298                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD) ? "profile_standard" :
 299                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK) ? "profile_min_sclk" :
 300                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK) ? "profile_min_mclk" :
 301                         (level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK) ? "profile_peak" :
 302                         "unknown");
 303 }
 304
 305 static ssize_t amdgpu_set_power_dpm_force_performance_level(struct device *dev,
 306                                                             struct device_attribute *attr,
 307                                                             const char *buf,
 308                                                             size_t count)
 309 {
 310         struct drm_device *ddev = dev_get_drvdata(dev);
 311         struct amdgpu_device *adev = drm_to_adev(ddev);
 312         enum amd_dpm_forced_level level;
 313         enum amd_dpm_forced_level current_level = 0xff;
 314         int ret = 0;
 315
 316         if (amdgpu_in_reset(adev))
 317                 return -EPERM;
 318
 319         if (strncmp("low", buf, strlen("low")) == 0) {
 320                 level = AMD_DPM_FORCED_LEVEL_LOW;
 321         } else if (strncmp("high", buf, strlen("high")) == 0) {
 322                 level = AMD_DPM_FORCED_LEVEL_HIGH;
 323         } else if (strncmp("auto", buf, strlen("auto")) == 0) {
 324                 level = AMD_DPM_FORCED_LEVEL_AUTO;
 325         } else if (strncmp("manual", buf, strlen("manual")) == 0) {
 326                 level = AMD_DPM_FORCED_LEVEL_MANUAL;
 327         } else if (strncmp("profile_exit", buf, strlen("profile_exit")) == 0) {
 328                 level = AMD_DPM_FORCED_LEVEL_PROFILE_EXIT;
 329         } else if (strncmp("profile_standard", buf, strlen("profile_standard")) == 0) {
 330                 level = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD;
 331         } else if (strncmp("profile_min_sclk", buf, strlen("profile_min_sclk")) == 0) {
 332                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK;
 333         } else if (strncmp("profile_min_mclk", buf, strlen("profile_min_mclk")) == 0) {
 334                 level = AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK;
 335         } else if (strncmp("profile_peak", buf, strlen("profile_peak")) == 0) {
 336                 level = AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
 337         }  else {
 338                 return -EINVAL;
 339         }
 340
 341         ret = pm_runtime_get_sync(ddev->dev);
 342         if (ret < 0) {
 343                 pm_runtime_put_autosuspend(ddev->dev);
 344                 return ret;
 345         }
 346
 347         if (is_support_sw_smu(adev))
 348                 current_level = smu_get_performance_level(&adev->smu);
 349         else if (adev->powerplay.pp_funcs->get_performance_level)
 350                 current_level = amdgpu_dpm_get_performance_level(adev);
 351
 352         if (current_level == level) {
 353                 pm_runtime_mark_last_busy(ddev->dev);
 354                 pm_runtime_put_autosuspend(ddev->dev);
 355                 return count;
 356         }
 357
 358         if (adev->asic_type == CHIP_RAVEN) {
 359                 if (!(adev->apu_flags & AMD_APU_IS_RAVEN2)) {
 360                         if (current_level != AMD_DPM_FORCED_LEVEL_MANUAL && level == AMD_DPM_FORCED_LEVEL_MANUAL)
 361                                 amdgpu_gfx_off_ctrl(adev, false);
 362                         else if (current_level == AMD_DPM_FORCED_LEVEL_MANUAL && level != AMD_DPM_FORCED_LEVEL_MANUAL)
 363                                 amdgpu_gfx_off_ctrl(adev, true);
 364                 }
 365         }
 366
 367         /* profile_exit setting is valid only when current mode is in profile mode */
 368         if (!(current_level & (AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
 369             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
 370             AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
 371             AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)) &&
 372             (level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)) {
 373                 pr_err("Currently not in any profile mode!\n");
 374                 pm_runtime_mark_last_busy(ddev->dev);
 375                 pm_runtime_put_autosuspend(ddev->dev);
 376                 return -EINVAL;
 377         }
 378
 379         if (is_support_sw_smu(adev)) {
 380                 ret = smu_force_performance_level(&adev->smu, level);
 381                 if (ret) {
 382                         pm_runtime_mark_last_busy(ddev->dev);
 383                         pm_runtime_put_autosuspend(ddev->dev);
 384                         return -EINVAL;
 385                 }
 386         } else if (adev->powerplay.pp_funcs->force_performance_level) {
 387                 mutex_lock(&adev->pm.mutex);
 388                 if (adev->pm.dpm.thermal_active) {
 389                         mutex_unlock(&adev->pm.mutex);
 390                         pm_runtime_mark_last_busy(ddev->dev);
 391                         pm_runtime_put_autosuspend(ddev->dev);
 392                         return -EINVAL;
 393                 }
 394                 ret = amdgpu_dpm_force_performance_level(adev, level);
 395                 if (ret) {
 396                         mutex_unlock(&adev->pm.mutex);
 397                         pm_runtime_mark_last_busy(ddev->dev);
 398                         pm_runtime_put_autosuspend(ddev->dev);
 399                         return -EINVAL;
 400                 } else {
 401                         adev->pm.dpm.forced_level = level;
 402                 }
 403                 mutex_unlock(&adev->pm.mutex);
 404         }
 405         pm_runtime_mark_last_busy(ddev->dev);
 406         pm_runtime_put_autosuspend(ddev->dev);
 407
 408         return count;
 409 }
 410
 411 static ssize_t amdgpu_get_pp_num_states(struct device *dev,
 412                 struct device_attribute *attr,
 413                 char *buf)
 414 {
 415         struct drm_device *ddev = dev_get_drvdata(dev);
 416         struct amdgpu_device *adev = drm_to_adev(ddev);
 417         struct pp_states_info data;
 418         int i, buf_len, ret;
 419
 420         if (amdgpu_in_reset(adev))
 421                 return -EPERM;
 422
 423         ret = pm_runtime_get_sync(ddev->dev);
 424         if (ret < 0) {
 425                 pm_runtime_put_autosuspend(ddev->dev);
 426                 return ret;
 427         }
 428
 429         if (is_support_sw_smu(adev)) {
 430                 ret = smu_get_power_num_states(&adev->smu, &data);
 431                 if (ret)
 432                         return ret;
 433         } else if (adev->powerplay.pp_funcs->get_pp_num_states) {
 434                 amdgpu_dpm_get_pp_num_states(adev, &data);
 435         } else {
 436                 memset(&data, 0, sizeof(data));
 437         }
 438
 439         pm_runtime_mark_last_busy(ddev->dev);
 440         pm_runtime_put_autosuspend(ddev->dev);
 441
 442         buf_len = snprintf(buf, PAGE_SIZE, "states: %d\n", data.nums);
 443         for (i = 0; i < data.nums; i++)
 444                 buf_len += snprintf(buf + buf_len, PAGE_SIZE, "%d %s\n", i,
 445                                 (data.states[i] == POWER_STATE_TYPE_INTERNAL_BOOT) ? "boot" :
 446                                 (data.states[i] == POWER_STATE_TYPE_BATTERY) ? "battery" :
 447                                 (data.states[i] == POWER_STATE_TYPE_BALANCED) ? "balanced" :
 448                                 (data.states[i] == POWER_STATE_TYPE_PERFORMANCE) ? "performance" : "default");
 449
 450         return buf_len;
 451 }
 452
 453 static ssize_t amdgpu_get_pp_cur_state(struct device *dev,
 454                 struct device_attribute *attr,
 455                 char *buf)
 456 {
 457         struct drm_device *ddev = dev_get_drvdata(dev);
 458         struct amdgpu_device *adev = drm_to_adev(ddev);
 459         struct pp_states_info data;
 460         struct smu_context *smu = &adev->smu;
 461         enum amd_pm_state_type pm = 0;
 462         int i = 0, ret = 0;
 463
 464         if (amdgpu_in_reset(adev))
 465                 return -EPERM;
 466
 467         ret = pm_runtime_get_sync(ddev->dev);
 468         if (ret < 0) {
 469                 pm_runtime_put_autosuspend(ddev->dev);
 470                 return ret;
 471         }
 472
 473         if (is_support_sw_smu(adev)) {
 474                 pm = smu_get_current_power_state(smu);
 475                 ret = smu_get_power_num_states(smu, &data);
 476                 if (ret)
 477                         return ret;
 478         } else if (adev->powerplay.pp_funcs->get_current_power_state
 479                  && adev->powerplay.pp_funcs->get_pp_num_states) {
 480                 pm = amdgpu_dpm_get_current_power_state(adev);
 481                 amdgpu_dpm_get_pp_num_states(adev, &data);
 482         }
 483
 484         pm_runtime_mark_last_busy(ddev->dev);
 485         pm_runtime_put_autosuspend(ddev->dev);
 486
 487         for (i = 0; i < data.nums; i++) {
 488                 if (pm == data.states[i])
 489                         break;
 490         }
 491
 492         if (i == data.nums)
 493                 i = -EINVAL;
 494
 495         return snprintf(buf, PAGE_SIZE, "%d\n", i);
 496 }
 497
 498 static ssize_t amdgpu_get_pp_force_state(struct device *dev,
 499                 struct device_attribute *attr,
 500                 char *buf)
 501 {
 502         struct drm_device *ddev = dev_get_drvdata(dev);
 503         struct amdgpu_device *adev = drm_to_adev(ddev);
 504
 505         if (amdgpu_in_reset(adev))
 506                 return -EPERM;
 507
 508         if (adev->pp_force_state_enabled)
 509                 return amdgpu_get_pp_cur_state(dev, attr, buf);
 510         else
 511                 return snprintf(buf, PAGE_SIZE, "\n");
 512 }
 513
 514 static ssize_t amdgpu_set_pp_force_state(struct device *dev,
 515                 struct device_attribute *attr,
 516                 const char *buf,
 517                 size_t count)
 518 {
 519         struct drm_device *ddev = dev_get_drvdata(dev);
 520         struct amdgpu_device *adev = drm_to_adev(ddev);
 521         enum amd_pm_state_type state = 0;
 522         unsigned long idx;
 523         int ret;
 524
 525         if (amdgpu_in_reset(adev))
 526                 return -EPERM;
 527
 528         if (strlen(buf) == 1)
 529                 adev->pp_force_state_enabled = false;
 530         else if (is_support_sw_smu(adev))
 531                 adev->pp_force_state_enabled = false;
 532         else if (adev->powerplay.pp_funcs->dispatch_tasks &&
 533                         adev->powerplay.pp_funcs->get_pp_num_states) {
 534                 struct pp_states_info data;
 535
 536                 ret = kstrtoul(buf, 0, &idx);
 537                 if (ret || idx >= ARRAY_SIZE(data.states))
 538                         return -EINVAL;
 539
 540                 idx = array_index_nospec(idx, ARRAY_SIZE(data.states));
 541
 542                 amdgpu_dpm_get_pp_num_states(adev, &data);
 543                 state = data.states[idx];
 544
 545                 ret = pm_runtime_get_sync(ddev->dev);
 546                 if (ret < 0) {
 547                         pm_runtime_put_autosuspend(ddev->dev);
 548                         return ret;
 549                 }
 550
 551                 /* only set user selected power states */
 552                 if (state != POWER_STATE_TYPE_INTERNAL_BOOT &&
 553                     state != POWER_STATE_TYPE_DEFAULT) {
 554                         amdgpu_dpm_dispatch_task(adev,
 555                                         AMD_PP_TASK_ENABLE_USER_STATE, &state);
 556                         adev->pp_force_state_enabled = true;
 557                 }
 558                 pm_runtime_mark_last_busy(ddev->dev);
 559                 pm_runtime_put_autosuspend(ddev->dev);
 560         }
 561
 562         return count;
 563 }
 564
 565 /**
 566  * DOC: pp_table
 567  *
 568  * The amdgpu driver provides a sysfs API for uploading new powerplay
 569  * tables.  The file pp_table is used for this.  Reading the file
 570  * will dump the current power play table.  Writing to the file
 571  * will attempt to upload a new powerplay table and re-initialize
 572  * powerplay using that new table.
 573  *
 574  */
 575
 576 static ssize_t amdgpu_get_pp_table(struct device *dev,
 577                 struct device_attribute *attr,
 578                 char *buf)
 579 {
 580         struct drm_device *ddev = dev_get_drvdata(dev);
 581         struct amdgpu_device *adev = drm_to_adev(ddev);
 582         char *table = NULL;
 583         int size, ret;
 584
 585         if (amdgpu_in_reset(adev))
 586                 return -EPERM;
 587
 588         ret = pm_runtime_get_sync(ddev->dev);
 589         if (ret < 0) {
 590                 pm_runtime_put_autosuspend(ddev->dev);
 591                 return ret;
 592         }
 593
 594         if (is_support_sw_smu(adev)) {
 595                 size = smu_sys_get_pp_table(&adev->smu, (void **)&table);
 596                 pm_runtime_mark_last_busy(ddev->dev);
 597                 pm_runtime_put_autosuspend(ddev->dev);
 598                 if (size < 0)
 599                         return size;
 600         } else if (adev->powerplay.pp_funcs->get_pp_table) {
 601                 size = amdgpu_dpm_get_pp_table(adev, &table);
 602                 pm_runtime_mark_last_busy(ddev->dev);
 603                 pm_runtime_put_autosuspend(ddev->dev);
 604                 if (size < 0)
 605                         return size;
 606         } else {
 607                 pm_runtime_mark_last_busy(ddev->dev);
 608                 pm_runtime_put_autosuspend(ddev->dev);
 609                 return 0;
 610         }
 611
 612         if (size >= PAGE_SIZE)
 613                 size = PAGE_SIZE - 1;
 614
 615         memcpy(buf, table, size);
 616
 617         return size;
 618 }
 619
 620 static ssize_t amdgpu_set_pp_table(struct device *dev,
 621                 struct device_attribute *attr,
 622                 const char *buf,
 623                 size_t count)
 624 {
 625         struct drm_device *ddev = dev_get_drvdata(dev);
 626         struct amdgpu_device *adev = drm_to_adev(ddev);
 627         int ret = 0;
 628
 629         if (amdgpu_in_reset(adev))
 630                 return -EPERM;
 631
 632         ret = pm_runtime_get_sync(ddev->dev);
 633         if (ret < 0) {
 634                 pm_runtime_put_autosuspend(ddev->dev);
 635                 return ret;
 636         }
 637
 638         if (is_support_sw_smu(adev)) {
 639                 ret = smu_sys_set_pp_table(&adev->smu, (void *)buf, count);
 640                 if (ret) {
 641                         pm_runtime_mark_last_busy(ddev->dev);
 642                         pm_runtime_put_autosuspend(ddev->dev);
 643                         return ret;
 644                 }
 645         } else if (adev->powerplay.pp_funcs->set_pp_table)
 646                 amdgpu_dpm_set_pp_table(adev, buf, count);
 647
 648         pm_runtime_mark_last_busy(ddev->dev);
 649         pm_runtime_put_autosuspend(ddev->dev);
 650
 651         return count;
 652 }
 653
 654 /**
 655  * DOC: pp_od_clk_voltage
 656  *
 657  * The amdgpu driver provides a sysfs API for adjusting the clocks and voltages
 658  * in each power level within a power state.  The pp_od_clk_voltage is used for
 659  * this.
 660  *
 661  * Note that the actual memory controller clock rate are exposed, not
 662  * the effective memory clock of the DRAMs. To translate it, use the
 663  * following formula:
 664  *
 665  * Clock conversion (Mhz):
 666  *
 667  * HBM: effective_memory_clock = memory_controller_clock * 1
 668  *
 669  * G5: effective_memory_clock = memory_controller_clock * 1
 670  *
 671  * G6: effective_memory_clock = memory_controller_clock * 2
 672  *
 673  * DRAM data rate (MT/s):
 674  *
 675  * HBM: effective_memory_clock * 2 = data_rate
 676  *
 677  * G5: effective_memory_clock * 4 = data_rate
 678  *
 679  * G6: effective_memory_clock * 8 = data_rate
 680  *
 681  * Bandwidth (MB/s):
 682  *
 683  * data_rate * vram_bit_width / 8 = memory_bandwidth
 684  *
 685  * Some examples:
 686  *
 687  * G5 on RX460:
 688  *
 689  * memory_controller_clock = 1750 Mhz
 690  *
 691  * effective_memory_clock = 1750 Mhz * 1 = 1750 Mhz
 692  *
 693  * data rate = 1750 * 4 = 7000 MT/s
 694  *
 695  * memory_bandwidth = 7000 * 128 bits / 8 = 112000 MB/s
 696  *
 697  * G6 on RX5700:
 698  *
 699  * memory_controller_clock = 875 Mhz
 700  *
 701  * effective_memory_clock = 875 Mhz * 2 = 1750 Mhz
 702  *
 703  * data rate = 1750 * 8 = 14000 MT/s
 704  *
 705  * memory_bandwidth = 14000 * 256 bits / 8 = 448000 MB/s
 706  *
 707  * < For Vega10 and previous ASICs >
 708  *
 709  * Reading the file will display:
 710  *
 711  * - a list of engine clock levels and voltages labeled OD_SCLK
 712  *
 713  * - a list of memory clock levels and voltages labeled OD_MCLK
 714  *
 715  * - a list of valid ranges for sclk, mclk, and voltage labeled OD_RANGE
 716  *
 717  * To manually adjust these settings, first select manual using
 718  * power_dpm_force_performance_level. Enter a new value for each
 719  * level by writing a string that contains "s/m level clock voltage" to
 720  * the file.  E.g., "s 1 500 820" will update sclk level 1 to be 500 MHz
 721  * at 820 mV; "m 0 350 810" will update mclk level 0 to be 350 MHz at
 722  * 810 mV.  When you have edited all of the states as needed, write
 723  * "c" (commit) to the file to commit your changes.  If you want to reset to the
 724  * default power levels, write "r" (reset) to the file to reset them.
 725  *
 726  *
 727  * < For Vega20 and newer ASICs >
 728  *
 729  * Reading the file will display:
 730  *
 731  * - minimum and maximum engine clock labeled OD_SCLK
 732  *
 733  * - maximum memory clock labeled OD_MCLK
 734  *
 735  * - three <frequency, voltage> points labeled OD_VDDC_CURVE.
 736  *   They can be used to calibrate the sclk voltage curve.
 737  *
 738  * - a list of valid ranges for sclk, mclk, and voltage curve points
 739  *   labeled OD_RANGE
 740  *
 741  * To manually adjust these settings:
 742  *
 743  * - First select manual using power_dpm_force_performance_level
 744  *
 745  * - For clock frequency setting, enter a new value by writing a
 746  *   string that contains "s/m index clock" to the file. The index
 747  *   should be 0 if to set minimum clock. And 1 if to set maximum
 748  *   clock. E.g., "s 0 500" will update minimum sclk to be 500 MHz.
 749  *   "m 1 800" will update maximum mclk to be 800Mhz.
 750  *
 751  *   For sclk voltage curve, enter the new values by writing a
 752  *   string that contains "vc point clock voltage" to the file. The
 753  *   points are indexed by 0, 1 and 2. E.g., "vc 0 300 600" will
 754  *   update point1 with clock set as 300Mhz and voltage as
 755  *   600mV. "vc 2 1000 1000" will update point3 with clock set
 756  *   as 1000Mhz and voltage 1000mV.
 757  *
 758  * - When you have edited all of the states as needed, write "c" (commit)
 759  *   to the file to commit your changes
 760  *
 761  * - If you want to reset to the default power levels, write "r" (reset)
 762  *   to the file to reset them
 763  *
 764  */
 765
 766 static ssize_t amdgpu_set_pp_od_clk_voltage(struct device *dev,
 767                 struct device_attribute *attr,
 768                 const char *buf,
 769                 size_t count)
 770 {
 771         struct drm_device *ddev = dev_get_drvdata(dev);
 772         struct amdgpu_device *adev = drm_to_adev(ddev);
 773         int ret;
 774         uint32_t parameter_size = 0;
 775         long parameter[64];
 776         char buf_cpy[128];
 777         char *tmp_str;
 778         char *sub_str;
 779         const char delimiter[3] = {' ', '\n', '\0'};
 780         uint32_t type;
 781
 782         if (amdgpu_in_reset(adev))
 783                 return -EPERM;
 784
 785         if (count > 127)
 786                 return -EINVAL;
 787
 788         if (*buf == 's')
 789                 type = PP_OD_EDIT_SCLK_VDDC_TABLE;
 790         else if (*buf == 'm')
 791                 type = PP_OD_EDIT_MCLK_VDDC_TABLE;
 792         else if(*buf == 'r')
 793                 type = PP_OD_RESTORE_DEFAULT_TABLE;
 794         else if (*buf == 'c')
 795                 type = PP_OD_COMMIT_DPM_TABLE;
 796         else if (!strncmp(buf, "vc", 2))
 797                 type = PP_OD_EDIT_VDDC_CURVE;
 798         else
 799                 return -EINVAL;
 800
 801         memcpy(buf_cpy, buf, count+1);
 802
 803         tmp_str = buf_cpy;
 804
 805         if (type == PP_OD_EDIT_VDDC_CURVE)
 806                 tmp_str++;
 807         while (isspace(*++tmp_str));
 808
 809         while (tmp_str[0]) {
 810                 sub_str = strsep(&tmp_str, delimiter);
 811                 ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
 812                 if (ret)
 813                         return -EINVAL;
 814                 parameter_size++;
 815
 816                 while (isspace(*tmp_str))
 817                         tmp_str++;
 818         }
 819
 820         ret = pm_runtime_get_sync(ddev->dev);
 821         if (ret < 0) {
 822                 pm_runtime_put_autosuspend(ddev->dev);
 823                 return ret;
 824         }
 825
 826         if (is_support_sw_smu(adev)) {
 827                 ret = smu_od_edit_dpm_table(&adev->smu, type,
 828                                             parameter, parameter_size);
 829
 830                 if (ret) {
 831                         pm_runtime_mark_last_busy(ddev->dev);
 832                         pm_runtime_put_autosuspend(ddev->dev);
 833                         return -EINVAL;
 834                 }
 835         } else {
 836
 837                 if (adev->powerplay.pp_funcs->set_fine_grain_clk_vol) {
 838                         ret = amdgpu_dpm_set_fine_grain_clk_vol(adev, type,
 839                                                                 parameter,
 840                                                                 parameter_size);
 841                         if (ret) {
 842                                 pm_runtime_mark_last_busy(ddev->dev);
 843                                 pm_runtime_put_autosuspend(ddev->dev);
 844                                 return -EINVAL;
 845                         }
 846                 }
 847
 848                 if (adev->powerplay.pp_funcs->odn_edit_dpm_table) {
 849                         ret = amdgpu_dpm_odn_edit_dpm_table(adev, type,
 850                                                 parameter, parameter_size);
 851                         if (ret) {
 852                                 pm_runtime_mark_last_busy(ddev->dev);
 853                                 pm_runtime_put_autosuspend(ddev->dev);
 854                                 return -EINVAL;
 855                         }
 856                 }
 857
 858                 if (type == PP_OD_COMMIT_DPM_TABLE) {
 859                         if (adev->powerplay.pp_funcs->dispatch_tasks) {
 860                                 amdgpu_dpm_dispatch_task(adev,
 861                                                 AMD_PP_TASK_READJUST_POWER_STATE,
 862                                                 NULL);
 863                                 pm_runtime_mark_last_busy(ddev->dev);
 864                                 pm_runtime_put_autosuspend(ddev->dev);
 865                                 return count;
 866                         } else {
 867                                 pm_runtime_mark_last_busy(ddev->dev);
 868                                 pm_runtime_put_autosuspend(ddev->dev);
 869                                 return -EINVAL;
 870                         }
 871                 }
 872         }
 873         pm_runtime_mark_last_busy(ddev->dev);
 874         pm_runtime_put_autosuspend(ddev->dev);
 875
 876         return count;
 877 }
 878
 879 static ssize_t amdgpu_get_pp_od_clk_voltage(struct device *dev,
 880                 struct device_attribute *attr,
 881                 char *buf)
 882 {
 883         struct drm_device *ddev = dev_get_drvdata(dev);
 884         struct amdgpu_device *adev = drm_to_adev(ddev);
 885         ssize_t size;
 886         int ret;
 887
 888         if (amdgpu_in_reset(adev))
 889                 return -EPERM;
 890
 891         ret = pm_runtime_get_sync(ddev->dev);
 892         if (ret < 0) {
 893                 pm_runtime_put_autosuspend(ddev->dev);
 894                 return ret;
 895         }
 896
 897         if (is_support_sw_smu(adev)) {
 898                 size = smu_print_clk_levels(&adev->smu, SMU_OD_SCLK, buf);
 899                 size += smu_print_clk_levels(&adev->smu, SMU_OD_MCLK, buf+size);
 900                 size += smu_print_clk_levels(&adev->smu, SMU_OD_VDDC_CURVE, buf+size);
 901                 size += smu_print_clk_levels(&adev->smu, SMU_OD_RANGE, buf+size);
 902         } else if (adev->powerplay.pp_funcs->print_clock_levels) {
 903                 size = amdgpu_dpm_print_clock_levels(adev, OD_SCLK, buf);
 904                 size += amdgpu_dpm_print_clock_levels(adev, OD_MCLK, buf+size);
 905                 size += amdgpu_dpm_print_clock_levels(adev, OD_VDDC_CURVE, buf+size);
 906                 size += amdgpu_dpm_print_clock_levels(adev, OD_RANGE, buf+size);
 907         } else {
 908                 size = snprintf(buf, PAGE_SIZE, "\n");
 909         }
 910         pm_runtime_mark_last_busy(ddev->dev);
 911         pm_runtime_put_autosuspend(ddev->dev);
 912
 913         return size;
 914 }
 915
 916 /**
 917  * DOC: pp_features
 918  *
 919  * The amdgpu driver provides a sysfs API for adjusting what powerplay
 920  * features to be enabled. The file pp_features is used for this. And
 921  * this is only available for Vega10 and later dGPUs.
 922  *
 923  * Reading back the file will show you the followings:
 924  * - Current ppfeature masks
 925  * - List of the all supported powerplay features with their naming,
 926  *   bitmasks and enablement status('Y'/'N' means "enabled"/"disabled").
 927  *
 928  * To manually enable or disable a specific feature, just set or clear
 929  * the corresponding bit from original ppfeature masks and input the
 930  * new ppfeature masks.
 931  */
 932 static ssize_t amdgpu_set_pp_features(struct device *dev,
 933                                       struct device_attribute *attr,
 934                                       const char *buf,
 935                                       size_t count)
 936 {
 937         struct drm_device *ddev = dev_get_drvdata(dev);
 938         struct amdgpu_device *adev = drm_to_adev(ddev);
 939         uint64_t featuremask;
 940         int ret;
 941
 942         if (amdgpu_in_reset(adev))
 943                 return -EPERM;
 944
 945         ret = kstrtou64(buf, 0, &featuremask);
 946         if (ret)
 947                 return -EINVAL;
 948
 949         ret = pm_runtime_get_sync(ddev->dev);
 950         if (ret < 0) {
 951                 pm_runtime_put_autosuspend(ddev->dev);
 952                 return ret;
 953         }
 954
 955         if (is_support_sw_smu(adev)) {
 956                 ret = smu_sys_set_pp_feature_mask(&adev->smu, featuremask);
 957                 if (ret) {
 958                         pm_runtime_mark_last_busy(ddev->dev);
 959                         pm_runtime_put_autosuspend(ddev->dev);
 960                         return -EINVAL;
 961                 }
 962         } else if (adev->powerplay.pp_funcs->set_ppfeature_status) {
 963                 ret = amdgpu_dpm_set_ppfeature_status(adev, featuremask);
 964                 if (ret) {
 965                         pm_runtime_mark_last_busy(ddev->dev);
 966                         pm_runtime_put_autosuspend(ddev->dev);
 967                         return -EINVAL;
 968                 }
 969         }
 970         pm_runtime_mark_last_busy(ddev->dev);
 971         pm_runtime_put_autosuspend(ddev->dev);
 972
 973         return count;
 974 }
 975
 976 static ssize_t amdgpu_get_pp_features(struct device *dev,
 977                                       struct device_attribute *attr,
 978                                       char *buf)
 979 {
 980         struct drm_device *ddev = dev_get_drvdata(dev);
 981         struct amdgpu_device *adev = drm_to_adev(ddev);
 982         ssize_t size;
 983         int ret;
 984
 985         if (amdgpu_in_reset(adev))
 986                 return -EPERM;
 987
 988         ret = pm_runtime_get_sync(ddev->dev);
 989         if (ret < 0) {
 990                 pm_runtime_put_autosuspend(ddev->dev);
 991                 return ret;
 992         }
 993
 994         if (is_support_sw_smu(adev))
 995                 size = smu_sys_get_pp_feature_mask(&adev->smu, buf);
 996         else if (adev->powerplay.pp_funcs->get_ppfeature_status)
 997                 size = amdgpu_dpm_get_ppfeature_status(adev, buf);
 998         else
 999                 size = snprintf(buf, PAGE_SIZE, "\n");
1000
1001         pm_runtime_mark_last_busy(ddev->dev);
1002         pm_runtime_put_autosuspend(ddev->dev);
1003
1004         return size;
1005 }
1006
1007 /**
1008  * DOC: pp_dpm_sclk pp_dpm_mclk pp_dpm_socclk pp_dpm_fclk pp_dpm_dcefclk pp_dpm_pcie
1009  *
1010  * The amdgpu driver provides a sysfs API for adjusting what power levels
1011  * are enabled for a given power state.  The files pp_dpm_sclk, pp_dpm_mclk,
1012  * pp_dpm_socclk, pp_dpm_fclk, pp_dpm_dcefclk and pp_dpm_pcie are used for
1013  * this.
1014  *
1015  * pp_dpm_socclk and pp_dpm_dcefclk interfaces are only available for
1016  * Vega10 and later ASICs.
1017  * pp_dpm_fclk interface is only available for Vega20 and later ASICs.
1018  *
1019  * Reading back the files will show you the available power levels within
1020  * the power state and the clock information for those levels.
1021  *
1022  * To manually adjust these states, first select manual using
1023  * power_dpm_force_performance_level.
1024  * Secondly, enter a new value for each level by inputing a string that
1025  * contains " echo xx xx xx > pp_dpm_sclk/mclk/pcie"
1026  * E.g.,
1027  *
1028  * .. code-block:: bash
1029  *
1030  *      echo "4 5 6" > pp_dpm_sclk
1031  *
1032  * will enable sclk levels 4, 5, and 6.
1033  *
1034  * NOTE: change to the dcefclk max dpm level is not supported now
1035  */
1036
1037 static ssize_t amdgpu_get_pp_dpm_sclk(struct device *dev,
1038                 struct device_attribute *attr,
1039                 char *buf)
1040 {
1041         struct drm_device *ddev = dev_get_drvdata(dev);
1042         struct amdgpu_device *adev = drm_to_adev(ddev);
1043         ssize_t size;
1044         int ret;
1045
1046         if (amdgpu_in_reset(adev))
1047                 return -EPERM;
1048
1049         ret = pm_runtime_get_sync(ddev->dev);
1050         if (ret < 0) {
1051                 pm_runtime_put_autosuspend(ddev->dev);
1052                 return ret;
1053         }
1054
1055         if (is_support_sw_smu(adev))
1056                 size = smu_print_clk_levels(&adev->smu, SMU_SCLK, buf);
1057         else if (adev->powerplay.pp_funcs->print_clock_levels)
1058                 size = amdgpu_dpm_print_clock_levels(adev, PP_SCLK, buf);
1059         else
1060                 size = snprintf(buf, PAGE_SIZE, "\n");
1061
1062         pm_runtime_mark_last_busy(ddev->dev);
1063         pm_runtime_put_autosuspend(ddev->dev);
1064
1065         return size;
1066 }
1067
1068 /*
1069  * Worst case: 32 bits individually specified, in octal at 12 characters
1070  * per line (+1 for \n).
1071  */
1072 #define AMDGPU_MASK_BUF_MAX     (32 * 13)
1073
1074 static ssize_t amdgpu_read_mask(const char *buf, size_t count, uint32_t *mask)
1075 {
1076         int ret;
1077         long level;
1078         char *sub_str = NULL;
1079         char *tmp;
1080         char buf_cpy[AMDGPU_MASK_BUF_MAX + 1];
1081         const char delimiter[3] = {' ', '\n', '\0'};
1082         size_t bytes;
1083
1084         *mask = 0;
1085
1086         bytes = min(count, sizeof(buf_cpy) - 1);
1087         memcpy(buf_cpy, buf, bytes);
1088         buf_cpy[bytes] = '\0';
1089         tmp = buf_cpy;
1090         while (tmp[0]) {
1091                 sub_str = strsep(&tmp, delimiter);
1092                 if (strlen(sub_str)) {
1093                         ret = kstrtol(sub_str, 0, &level);
1094                         if (ret)
1095                                 return -EINVAL;
1096                         *mask |= 1 << level;
1097                 } else
1098                         break;
1099         }
1100
1101         return 0;
1102 }
1103
1104 static ssize_t amdgpu_set_pp_dpm_sclk(struct device *dev,
1105                 struct device_attribute *attr,
1106                 const char *buf,
1107                 size_t count)
1108 {
1109         struct drm_device *ddev = dev_get_drvdata(dev);
1110         struct amdgpu_device *adev = drm_to_adev(ddev);
1111         int ret;
1112         uint32_t mask = 0;
1113
1114         if (amdgpu_in_reset(adev))
1115                 return -EPERM;
1116
1117         ret = amdgpu_read_mask(buf, count, &mask);
1118         if (ret)
1119                 return ret;
1120
1121         ret = pm_runtime_get_sync(ddev->dev);
1122         if (ret < 0) {
1123                 pm_runtime_put_autosuspend(ddev->dev);
1124                 return ret;
1125         }
1126
1127         if (is_support_sw_smu(adev))
1128                 ret = smu_force_clk_levels(&adev->smu, SMU_SCLK, mask);
1129         else if (adev->powerplay.pp_funcs->force_clock_level)
1130                 ret = amdgpu_dpm_force_clock_level(adev, PP_SCLK, mask);
1131
1132         pm_runtime_mark_last_busy(ddev->dev);
1133         pm_runtime_put_autosuspend(ddev->dev);
1134
1135         if (ret)
1136                 return -EINVAL;
1137
1138         return count;
1139 }
1140
1141 static ssize_t amdgpu_get_pp_dpm_mclk(struct device *dev,
1142                 struct device_attribute *attr,
1143                 char *buf)
1144 {
1145         struct drm_device *ddev = dev_get_drvdata(dev);
1146         struct amdgpu_device *adev = drm_to_adev(ddev);
1147         ssize_t size;
1148         int ret;
1149
1150         if (amdgpu_in_reset(adev))
1151                 return -EPERM;
1152
1153         ret = pm_runtime_get_sync(ddev->dev);
1154         if (ret < 0) {
1155                 pm_runtime_put_autosuspend(ddev->dev);
1156                 return ret;
1157         }
1158
1159         if (is_support_sw_smu(adev))
1160                 size = smu_print_clk_levels(&adev->smu, SMU_MCLK, buf);
1161         else if (adev->powerplay.pp_funcs->print_clock_levels)
1162                 size = amdgpu_dpm_print_clock_levels(adev, PP_MCLK, buf);
1163         else
1164                 size = snprintf(buf, PAGE_SIZE, "\n");
1165
1166         pm_runtime_mark_last_busy(ddev->dev);
1167         pm_runtime_put_autosuspend(ddev->dev);
1168
1169         return size;
1170 }
1171
1172 static ssize_t amdgpu_set_pp_dpm_mclk(struct device *dev,
1173                 struct device_attribute *attr,
1174                 const char *buf,
1175                 size_t count)
1176 {
1177         struct drm_device *ddev = dev_get_drvdata(dev);
1178         struct amdgpu_device *adev = drm_to_adev(ddev);
1179         uint32_t mask = 0;
1180         int ret;
1181
1182         if (amdgpu_in_reset(adev))
1183                 return -EPERM;
1184
1185         ret = amdgpu_read_mask(buf, count, &mask);
1186         if (ret)
1187                 return ret;
1188
1189         ret = pm_runtime_get_sync(ddev->dev);
1190         if (ret < 0) {
1191                 pm_runtime_put_autosuspend(ddev->dev);
1192                 return ret;
1193         }
1194
1195         if (is_support_sw_smu(adev))
1196                 ret = smu_force_clk_levels(&adev->smu, SMU_MCLK, mask);
1197         else if (adev->powerplay.pp_funcs->force_clock_level)
1198                 ret = amdgpu_dpm_force_clock_level(adev, PP_MCLK, mask);
1199
1200         pm_runtime_mark_last_busy(ddev->dev);
1201         pm_runtime_put_autosuspend(ddev->dev);
1202
1203         if (ret)
1204                 return -EINVAL;
1205
1206         return count;
1207 }
1208
1209 static ssize_t amdgpu_get_pp_dpm_socclk(struct device *dev,
1210                 struct device_attribute *attr,
1211                 char *buf)
1212 {
1213         struct drm_device *ddev = dev_get_drvdata(dev);
1214         struct amdgpu_device *adev = drm_to_adev(ddev);
1215         ssize_t size;
1216         int ret;
1217
1218         if (amdgpu_in_reset(adev))
1219                 return -EPERM;
1220
1221         ret = pm_runtime_get_sync(ddev->dev);
1222         if (ret < 0) {
1223                 pm_runtime_put_autosuspend(ddev->dev);
1224                 return ret;
1225         }
1226
1227         if (is_support_sw_smu(adev))
1228                 size = smu_print_clk_levels(&adev->smu, SMU_SOCCLK, buf);
1229         else if (adev->powerplay.pp_funcs->print_clock_levels)
1230                 size = amdgpu_dpm_print_clock_levels(adev, PP_SOCCLK, buf);
1231         else
1232                 size = snprintf(buf, PAGE_SIZE, "\n");
1233
1234         pm_runtime_mark_last_busy(ddev->dev);
1235         pm_runtime_put_autosuspend(ddev->dev);
1236
1237         return size;
1238 }
1239
1240 static ssize_t amdgpu_set_pp_dpm_socclk(struct device *dev,
1241                 struct device_attribute *attr,
1242                 const char *buf,
1243                 size_t count)
1244 {
1245         struct drm_device *ddev = dev_get_drvdata(dev);
1246         struct amdgpu_device *adev = drm_to_adev(ddev);
1247         int ret;
1248         uint32_t mask = 0;
1249
1250         if (amdgpu_in_reset(adev))
1251                 return -EPERM;
1252
1253         ret = amdgpu_read_mask(buf, count, &mask);
1254         if (ret)
1255                 return ret;
1256
1257         ret = pm_runtime_get_sync(ddev->dev);
1258         if (ret < 0) {
1259                 pm_runtime_put_autosuspend(ddev->dev);
1260                 return ret;
1261         }
1262
1263         if (is_support_sw_smu(adev))
1264                 ret = smu_force_clk_levels(&adev->smu, SMU_SOCCLK, mask);
1265         else if (adev->powerplay.pp_funcs->force_clock_level)
1266                 ret = amdgpu_dpm_force_clock_level(adev, PP_SOCCLK, mask);
1267         else
1268                 ret = 0;
1269
1270         pm_runtime_mark_last_busy(ddev->dev);
1271         pm_runtime_put_autosuspend(ddev->dev);
1272
1273         if (ret)
1274                 return -EINVAL;
1275
1276         return count;
1277 }
1278
1279 static ssize_t amdgpu_get_pp_dpm_fclk(struct device *dev,
1280                 struct device_attribute *attr,
1281                 char *buf)
1282 {
1283         struct drm_device *ddev = dev_get_drvdata(dev);
1284         struct amdgpu_device *adev = drm_to_adev(ddev);
1285         ssize_t size;
1286         int ret;
1287
1288         if (amdgpu_in_reset(adev))
1289                 return -EPERM;
1290
1291         ret = pm_runtime_get_sync(ddev->dev);
1292         if (ret < 0) {
1293                 pm_runtime_put_autosuspend(ddev->dev);
1294                 return ret;
1295         }
1296
1297         if (is_support_sw_smu(adev))
1298                 size = smu_print_clk_levels(&adev->smu, SMU_FCLK, buf);
1299         else if (adev->powerplay.pp_funcs->print_clock_levels)
1300                 size = amdgpu_dpm_print_clock_levels(adev, PP_FCLK, buf);
1301         else
1302                 size = snprintf(buf, PAGE_SIZE, "\n");
1303
1304         pm_runtime_mark_last_busy(ddev->dev);
1305         pm_runtime_put_autosuspend(ddev->dev);
1306
1307         return size;
1308 }
1309
1310 static ssize_t amdgpu_set_pp_dpm_fclk(struct device *dev,
1311                 struct device_attribute *attr,
1312                 const char *buf,
1313                 size_t count)
1314 {
1315         struct drm_device *ddev = dev_get_drvdata(dev);
1316         struct amdgpu_device *adev = drm_to_adev(ddev);
1317         int ret;
1318         uint32_t mask = 0;
1319
1320         if (amdgpu_in_reset(adev))
1321                 return -EPERM;
1322
1323         ret = amdgpu_read_mask(buf, count, &mask);
1324         if (ret)
1325                 return ret;
1326
1327         ret = pm_runtime_get_sync(ddev->dev);
1328         if (ret < 0) {
1329                 pm_runtime_put_autosuspend(ddev->dev);
1330                 return ret;
1331         }
1332
1333         if (is_support_sw_smu(adev))
1334                 ret = smu_force_clk_levels(&adev->smu, SMU_FCLK, mask);
1335         else if (adev->powerplay.pp_funcs->force_clock_level)
1336                 ret = amdgpu_dpm_force_clock_level(adev, PP_FCLK, mask);
1337         else
1338                 ret = 0;
1339
1340         pm_runtime_mark_last_busy(ddev->dev);
1341         pm_runtime_put_autosuspend(ddev->dev);
1342
1343         if (ret)
1344                 return -EINVAL;
1345
1346         return count;
1347 }
1348
1349 static ssize_t amdgpu_get_pp_dpm_dcefclk(struct device *dev,
1350                 struct device_attribute *attr,
1351                 char *buf)
1352 {
1353         struct drm_device *ddev = dev_get_drvdata(dev);
1354         struct amdgpu_device *adev = drm_to_adev(ddev);
1355         ssize_t size;
1356         int ret;
1357
1358         if (amdgpu_in_reset(adev))
1359                 return -EPERM;
1360
1361         ret = pm_runtime_get_sync(ddev->dev);
1362         if (ret < 0) {
1363                 pm_runtime_put_autosuspend(ddev->dev);
1364                 return ret;
1365         }
1366
1367         if (is_support_sw_smu(adev))
1368                 size = smu_print_clk_levels(&adev->smu, SMU_DCEFCLK, buf);
1369         else if (adev->powerplay.pp_funcs->print_clock_levels)
1370                 size = amdgpu_dpm_print_clock_levels(adev, PP_DCEFCLK, buf);
1371         else
1372                 size = snprintf(buf, PAGE_SIZE, "\n");
1373
1374         pm_runtime_mark_last_busy(ddev->dev);
1375         pm_runtime_put_autosuspend(ddev->dev);
1376
1377         return size;
1378 }
1379
1380 static ssize_t amdgpu_set_pp_dpm_dcefclk(struct device *dev,
1381                 struct device_attribute *attr,
1382                 const char *buf,
1383                 size_t count)
1384 {
1385         struct drm_device *ddev = dev_get_drvdata(dev);
1386         struct amdgpu_device *adev = drm_to_adev(ddev);
1387         int ret;
1388         uint32_t mask = 0;
1389
1390         if (amdgpu_in_reset(adev))
1391                 return -EPERM;
1392
1393         ret = amdgpu_read_mask(buf, count, &mask);
1394         if (ret)
1395                 return ret;
1396
1397         ret = pm_runtime_get_sync(ddev->dev);
1398         if (ret < 0) {
1399                 pm_runtime_put_autosuspend(ddev->dev);
1400                 return ret;
1401         }
1402
1403         if (is_support_sw_smu(adev))
1404                 ret = smu_force_clk_levels(&adev->smu, SMU_DCEFCLK, mask);
1405         else if (adev->powerplay.pp_funcs->force_clock_level)
1406                 ret = amdgpu_dpm_force_clock_level(adev, PP_DCEFCLK, mask);
1407         else
1408                 ret = 0;
1409
1410         pm_runtime_mark_last_busy(ddev->dev);
1411         pm_runtime_put_autosuspend(ddev->dev);
1412
1413         if (ret)
1414                 return -EINVAL;
1415
1416         return count;
1417 }
1418
1419 static ssize_t amdgpu_get_pp_dpm_pcie(struct device *dev,
1420                 struct device_attribute *attr,
1421                 char *buf)
1422 {
1423         struct drm_device *ddev = dev_get_drvdata(dev);
1424         struct amdgpu_device *adev = drm_to_adev(ddev);
1425         ssize_t size;
1426         int ret;
1427
1428         if (amdgpu_in_reset(adev))
1429                 return -EPERM;
1430
1431         ret = pm_runtime_get_sync(ddev->dev);
1432         if (ret < 0) {
1433                 pm_runtime_put_autosuspend(ddev->dev);
1434                 return ret;
1435         }
1436
1437         if (is_support_sw_smu(adev))
1438                 size = smu_print_clk_levels(&adev->smu, SMU_PCIE, buf);
1439         else if (adev->powerplay.pp_funcs->print_clock_levels)
1440                 size = amdgpu_dpm_print_clock_levels(adev, PP_PCIE, buf);
1441         else
1442                 size = snprintf(buf, PAGE_SIZE, "\n");
1443
1444         pm_runtime_mark_last_busy(ddev->dev);
1445         pm_runtime_put_autosuspend(ddev->dev);
1446
1447         return size;
1448 }
1449
1450 static ssize_t amdgpu_set_pp_dpm_pcie(struct device *dev,
1451                 struct device_attribute *attr,
1452                 const char *buf,
1453                 size_t count)
1454 {
1455         struct drm_device *ddev = dev_get_drvdata(dev);
1456         struct amdgpu_device *adev = drm_to_adev(ddev);
1457         int ret;
1458         uint32_t mask = 0;
1459
1460         if (amdgpu_in_reset(adev))
1461                 return -EPERM;
1462
1463         ret = amdgpu_read_mask(buf, count, &mask);
1464         if (ret)
1465                 return ret;
1466
1467         ret = pm_runtime_get_sync(ddev->dev);
1468         if (ret < 0) {
1469                 pm_runtime_put_autosuspend(ddev->dev);
1470                 return ret;
1471         }
1472
1473         if (is_support_sw_smu(adev))
1474                 ret = smu_force_clk_levels(&adev->smu, SMU_PCIE, mask);
1475         else if (adev->powerplay.pp_funcs->force_clock_level)
1476                 ret = amdgpu_dpm_force_clock_level(adev, PP_PCIE, mask);
1477         else
1478                 ret = 0;
1479
1480         pm_runtime_mark_last_busy(ddev->dev);
1481         pm_runtime_put_autosuspend(ddev->dev);
1482
1483         if (ret)
1484                 return -EINVAL;
1485
1486         return count;
1487 }
1488
1489 static ssize_t amdgpu_get_pp_sclk_od(struct device *dev,
1490                 struct device_attribute *attr,
1491                 char *buf)
1492 {
1493         struct drm_device *ddev = dev_get_drvdata(dev);
1494         struct amdgpu_device *adev = drm_to_adev(ddev);
1495         uint32_t value = 0;
1496         int ret;
1497
1498         if (amdgpu_in_reset(adev))
1499                 return -EPERM;
1500
1501         ret = pm_runtime_get_sync(ddev->dev);
1502         if (ret < 0) {
1503                 pm_runtime_put_autosuspend(ddev->dev);
1504                 return ret;
1505         }
1506
1507         if (is_support_sw_smu(adev))
1508                 value = 0;
1509         else if (adev->powerplay.pp_funcs->get_sclk_od)
1510                 value = amdgpu_dpm_get_sclk_od(adev);
1511
1512         pm_runtime_mark_last_busy(ddev->dev);
1513         pm_runtime_put_autosuspend(ddev->dev);
1514
1515         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1516 }
1517
1518 static ssize_t amdgpu_set_pp_sclk_od(struct device *dev,
1519                 struct device_attribute *attr,
1520                 const char *buf,
1521                 size_t count)
1522 {
1523         struct drm_device *ddev = dev_get_drvdata(dev);
1524         struct amdgpu_device *adev = drm_to_adev(ddev);
1525         int ret;
1526         long int value;
1527
1528         if (amdgpu_in_reset(adev))
1529                 return -EPERM;
1530
1531         ret = kstrtol(buf, 0, &value);
1532
1533         if (ret)
1534                 return -EINVAL;
1535
1536         ret = pm_runtime_get_sync(ddev->dev);
1537         if (ret < 0) {
1538                 pm_runtime_put_autosuspend(ddev->dev);
1539                 return ret;
1540         }
1541
1542         if (is_support_sw_smu(adev)) {
1543                 value = 0;
1544         } else {
1545                 if (adev->powerplay.pp_funcs->set_sclk_od)
1546                         amdgpu_dpm_set_sclk_od(adev, (uint32_t)value);
1547
1548                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1549                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1550                 } else {
1551                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1552                         amdgpu_pm_compute_clocks(adev);
1553                 }
1554         }
1555
1556         pm_runtime_mark_last_busy(ddev->dev);
1557         pm_runtime_put_autosuspend(ddev->dev);
1558
1559         return count;
1560 }
1561
1562 static ssize_t amdgpu_get_pp_mclk_od(struct device *dev,
1563                 struct device_attribute *attr,
1564                 char *buf)
1565 {
1566         struct drm_device *ddev = dev_get_drvdata(dev);
1567         struct amdgpu_device *adev = drm_to_adev(ddev);
1568         uint32_t value = 0;
1569         int ret;
1570
1571         if (amdgpu_in_reset(adev))
1572                 return -EPERM;
1573
1574         ret = pm_runtime_get_sync(ddev->dev);
1575         if (ret < 0) {
1576                 pm_runtime_put_autosuspend(ddev->dev);
1577                 return ret;
1578         }
1579
1580         if (is_support_sw_smu(adev))
1581                 value = 0;
1582         else if (adev->powerplay.pp_funcs->get_mclk_od)
1583                 value = amdgpu_dpm_get_mclk_od(adev);
1584
1585         pm_runtime_mark_last_busy(ddev->dev);
1586         pm_runtime_put_autosuspend(ddev->dev);
1587
1588         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1589 }
1590
1591 static ssize_t amdgpu_set_pp_mclk_od(struct device *dev,
1592                 struct device_attribute *attr,
1593                 const char *buf,
1594                 size_t count)
1595 {
1596         struct drm_device *ddev = dev_get_drvdata(dev);
1597         struct amdgpu_device *adev = drm_to_adev(ddev);
1598         int ret;
1599         long int value;
1600
1601         if (amdgpu_in_reset(adev))
1602                 return -EPERM;
1603
1604         ret = kstrtol(buf, 0, &value);
1605
1606         if (ret)
1607                 return -EINVAL;
1608
1609         ret = pm_runtime_get_sync(ddev->dev);
1610         if (ret < 0) {
1611                 pm_runtime_put_autosuspend(ddev->dev);
1612                 return ret;
1613         }
1614
1615         if (is_support_sw_smu(adev)) {
1616                 value = 0;
1617         } else {
1618                 if (adev->powerplay.pp_funcs->set_mclk_od)
1619                         amdgpu_dpm_set_mclk_od(adev, (uint32_t)value);
1620
1621                 if (adev->powerplay.pp_funcs->dispatch_tasks) {
1622                         amdgpu_dpm_dispatch_task(adev, AMD_PP_TASK_READJUST_POWER_STATE, NULL);
1623                 } else {
1624                         adev->pm.dpm.current_ps = adev->pm.dpm.boot_ps;
1625                         amdgpu_pm_compute_clocks(adev);
1626                 }
1627         }
1628
1629         pm_runtime_mark_last_busy(ddev->dev);
1630         pm_runtime_put_autosuspend(ddev->dev);
1631
1632         return count;
1633 }
1634
1635 /**
1636  * DOC: pp_power_profile_mode
1637  *
1638  * The amdgpu driver provides a sysfs API for adjusting the heuristics
1639  * related to switching between power levels in a power state.  The file
1640  * pp_power_profile_mode is used for this.
1641  *
1642  * Reading this file outputs a list of all of the predefined power profiles
1643  * and the relevant heuristics settings for that profile.
1644  *
1645  * To select a profile or create a custom profile, first select manual using
1646  * power_dpm_force_performance_level.  Writing the number of a predefined
1647  * profile to pp_power_profile_mode will enable those heuristics.  To
1648  * create a custom set of heuristics, write a string of numbers to the file
1649  * starting with the number of the custom profile along with a setting
1650  * for each heuristic parameter.  Due to differences across asic families
1651  * the heuristic parameters vary from family to family.
1652  *
1653  */
1654
1655 static ssize_t amdgpu_get_pp_power_profile_mode(struct device *dev,
1656                 struct device_attribute *attr,
1657                 char *buf)
1658 {
1659         struct drm_device *ddev = dev_get_drvdata(dev);
1660         struct amdgpu_device *adev = drm_to_adev(ddev);
1661         ssize_t size;
1662         int ret;
1663
1664         if (amdgpu_in_reset(adev))
1665                 return -EPERM;
1666
1667         ret = pm_runtime_get_sync(ddev->dev);
1668         if (ret < 0) {
1669                 pm_runtime_put_autosuspend(ddev->dev);
1670                 return ret;
1671         }
1672
1673         if (is_support_sw_smu(adev))
1674                 size = smu_get_power_profile_mode(&adev->smu, buf);
1675         else if (adev->powerplay.pp_funcs->get_power_profile_mode)
1676                 size = amdgpu_dpm_get_power_profile_mode(adev, buf);
1677         else
1678                 size = snprintf(buf, PAGE_SIZE, "\n");
1679
1680         pm_runtime_mark_last_busy(ddev->dev);
1681         pm_runtime_put_autosuspend(ddev->dev);
1682
1683         return size;
1684 }
1685
1686
1687 static ssize_t amdgpu_set_pp_power_profile_mode(struct device *dev,
1688                 struct device_attribute *attr,
1689                 const char *buf,
1690                 size_t count)
1691 {
1692         int ret;
1693         struct drm_device *ddev = dev_get_drvdata(dev);
1694         struct amdgpu_device *adev = drm_to_adev(ddev);
1695         uint32_t parameter_size = 0;
1696         long parameter[64];
1697         char *sub_str, buf_cpy[128];
1698         char *tmp_str;
1699         uint32_t i = 0;
1700         char tmp[2];
1701         long int profile_mode = 0;
1702         const char delimiter[3] = {' ', '\n', '\0'};
1703
1704         if (amdgpu_in_reset(adev))
1705                 return -EPERM;
1706
1707         tmp[0] = *(buf);
1708         tmp[1] = '\0';
1709         ret = kstrtol(tmp, 0, &profile_mode);
1710         if (ret)
1711                 return -EINVAL;
1712
1713         if (profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
1714                 if (count < 2 || count > 127)
1715                         return -EINVAL;
1716                 while (isspace(*++buf))
1717                         i++;
1718                 memcpy(buf_cpy, buf, count-i);
1719                 tmp_str = buf_cpy;
1720                 while (tmp_str[0]) {
1721                         sub_str = strsep(&tmp_str, delimiter);
1722                         ret = kstrtol(sub_str, 0, &parameter[parameter_size]);
1723                         if (ret)
1724                                 return -EINVAL;
1725                         parameter_size++;
1726                         while (isspace(*tmp_str))
1727                                 tmp_str++;
1728                 }
1729         }
1730         parameter[parameter_size] = profile_mode;
1731
1732         ret = pm_runtime_get_sync(ddev->dev);
1733         if (ret < 0) {
1734                 pm_runtime_put_autosuspend(ddev->dev);
1735                 return ret;
1736         }
1737
1738         if (is_support_sw_smu(adev))
1739                 ret = smu_set_power_profile_mode(&adev->smu, parameter, parameter_size, true);
1740         else if (adev->powerplay.pp_funcs->set_power_profile_mode)
1741                 ret = amdgpu_dpm_set_power_profile_mode(adev, parameter, parameter_size);
1742
1743         pm_runtime_mark_last_busy(ddev->dev);
1744         pm_runtime_put_autosuspend(ddev->dev);
1745
1746         if (!ret)
1747                 return count;
1748
1749         return -EINVAL;
1750 }
1751
1752 /**
1753  * DOC: gpu_busy_percent
1754  *
1755  * The amdgpu driver provides a sysfs API for reading how busy the GPU
1756  * is as a percentage.  The file gpu_busy_percent is used for this.
1757  * The SMU firmware computes a percentage of load based on the
1758  * aggregate activity level in the IP cores.
1759  */
1760 static ssize_t amdgpu_get_gpu_busy_percent(struct device *dev,
1761                                            struct device_attribute *attr,
1762                                            char *buf)
1763 {
1764         struct drm_device *ddev = dev_get_drvdata(dev);
1765         struct amdgpu_device *adev = drm_to_adev(ddev);
1766         int r, value, size = sizeof(value);
1767
1768         if (amdgpu_in_reset(adev))
1769                 return -EPERM;
1770
1771         r = pm_runtime_get_sync(ddev->dev);
1772         if (r < 0) {
1773                 pm_runtime_put_autosuspend(ddev->dev);
1774                 return r;
1775         }
1776
1777         /* read the IP busy sensor */
1778         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD,
1779                                    (void *)&value, &size);
1780
1781         pm_runtime_mark_last_busy(ddev->dev);
1782         pm_runtime_put_autosuspend(ddev->dev);
1783
1784         if (r)
1785                 return r;
1786
1787         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1788 }
1789
1790 /**
1791  * DOC: mem_busy_percent
1792  *
1793  * The amdgpu driver provides a sysfs API for reading how busy the VRAM
1794  * is as a percentage.  The file mem_busy_percent is used for this.
1795  * The SMU firmware computes a percentage of load based on the
1796  * aggregate activity level in the IP cores.
1797  */
1798 static ssize_t amdgpu_get_mem_busy_percent(struct device *dev,
1799                                            struct device_attribute *attr,
1800                                            char *buf)
1801 {
1802         struct drm_device *ddev = dev_get_drvdata(dev);
1803         struct amdgpu_device *adev = drm_to_adev(ddev);
1804         int r, value, size = sizeof(value);
1805
1806         if (amdgpu_in_reset(adev))
1807                 return -EPERM;
1808
1809         r = pm_runtime_get_sync(ddev->dev);
1810         if (r < 0) {
1811                 pm_runtime_put_autosuspend(ddev->dev);
1812                 return r;
1813         }
1814
1815         /* read the IP busy sensor */
1816         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD,
1817                                    (void *)&value, &size);
1818
1819         pm_runtime_mark_last_busy(ddev->dev);
1820         pm_runtime_put_autosuspend(ddev->dev);
1821
1822         if (r)
1823                 return r;
1824
1825         return snprintf(buf, PAGE_SIZE, "%d\n", value);
1826 }
1827
1828 /**
1829  * DOC: pcie_bw
1830  *
1831  * The amdgpu driver provides a sysfs API for estimating how much data
1832  * has been received and sent by the GPU in the last second through PCIe.
1833  * The file pcie_bw is used for this.
1834  * The Perf counters count the number of received and sent messages and return
1835  * those values, as well as the maximum payload size of a PCIe packet (mps).
1836  * Note that it is not possible to easily and quickly obtain the size of each
1837  * packet transmitted, so we output the max payload size (mps) to allow for
1838  * quick estimation of the PCIe bandwidth usage
1839  */
1840 static ssize_t amdgpu_get_pcie_bw(struct device *dev,
1841                 struct device_attribute *attr,
1842                 char *buf)
1843 {
1844         struct drm_device *ddev = dev_get_drvdata(dev);
1845         struct amdgpu_device *adev = drm_to_adev(ddev);
1846         uint64_t count0 = 0, count1 = 0;
1847         int ret;
1848
1849         if (amdgpu_in_reset(adev))
1850                 return -EPERM;
1851
1852         if (adev->flags & AMD_IS_APU)
1853                 return -ENODATA;
1854
1855         if (!adev->asic_funcs->get_pcie_usage)
1856                 return -ENODATA;
1857
1858         ret = pm_runtime_get_sync(ddev->dev);
1859         if (ret < 0) {
1860                 pm_runtime_put_autosuspend(ddev->dev);
1861                 return ret;
1862         }
1863
1864         amdgpu_asic_get_pcie_usage(adev, &count0, &count1);
1865
1866         pm_runtime_mark_last_busy(ddev->dev);
1867         pm_runtime_put_autosuspend(ddev->dev);
1868
1869         return snprintf(buf, PAGE_SIZE, "%llu %llu %i\n",
1870                         count0, count1, pcie_get_mps(adev->pdev));
1871 }
1872
1873 /**
1874  * DOC: unique_id
1875  *
1876  * The amdgpu driver provides a sysfs API for providing a unique ID for the GPU
1877  * The file unique_id is used for this.
1878  * This will provide a Unique ID that will persist from machine to machine
1879  *
1880  * NOTE: This will only work for GFX9 and newer. This file will be absent
1881  * on unsupported ASICs (GFX8 and older)
1882  */
1883 static ssize_t amdgpu_get_unique_id(struct device *dev,
1884                 struct device_attribute *attr,
1885                 char *buf)
1886 {
1887         struct drm_device *ddev = dev_get_drvdata(dev);
1888         struct amdgpu_device *adev = drm_to_adev(ddev);
1889
1890         if (amdgpu_in_reset(adev))
1891                 return -EPERM;
1892
1893         if (adev->unique_id)
1894                 return snprintf(buf, PAGE_SIZE, "%016llx\n", adev->unique_id);
1895
1896         return 0;
1897 }
1898
1899 /**
1900  * DOC: thermal_throttling_logging
1901  *
1902  * Thermal throttling pulls down the clock frequency and thus the performance.
1903  * It's an useful mechanism to protect the chip from overheating. Since it
1904  * impacts performance, the user controls whether it is enabled and if so,
1905  * the log frequency.
1906  *
1907  * Reading back the file shows you the status(enabled or disabled) and
1908  * the interval(in seconds) between each thermal logging.
1909  *
1910  * Writing an integer to the file, sets a new logging interval, in seconds.
1911  * The value should be between 1 and 3600. If the value is less than 1,
1912  * thermal logging is disabled. Values greater than 3600 are ignored.
1913  */
1914 static ssize_t amdgpu_get_thermal_throttling_logging(struct device *dev,
1915                                                      struct device_attribute *attr,
1916                                                      char *buf)
1917 {
1918         struct drm_device *ddev = dev_get_drvdata(dev);
1919         struct amdgpu_device *adev = drm_to_adev(ddev);
1920
1921         return snprintf(buf, PAGE_SIZE, "%s: thermal throttling logging %s, with interval %d seconds\n",
1922                         adev_to_drm(adev)->unique,
1923                         atomic_read(&adev->throttling_logging_enabled) ? "enabled" : "disabled",
1924                         adev->throttling_logging_rs.interval / HZ + 1);
1925 }
1926
1927 static ssize_t amdgpu_set_thermal_throttling_logging(struct device *dev,
1928                                                      struct device_attribute *attr,
1929                                                      const char *buf,
1930                                                      size_t count)
1931 {
1932         struct drm_device *ddev = dev_get_drvdata(dev);
1933         struct amdgpu_device *adev = drm_to_adev(ddev);
1934         long throttling_logging_interval;
1935         unsigned long flags;
1936         int ret = 0;
1937
1938         ret = kstrtol(buf, 0, &throttling_logging_interval);
1939         if (ret)
1940                 return ret;
1941
1942         if (throttling_logging_interval > 3600)
1943                 return -EINVAL;
1944
1945         if (throttling_logging_interval > 0) {
1946                 raw_spin_lock_irqsave(&adev->throttling_logging_rs.lock, flags);
1947                 /*
1948                  * Reset the ratelimit timer internals.
1949                  * This can effectively restart the timer.
1950                  */
1951                 adev->throttling_logging_rs.interval =
1952                         (throttling_logging_interval - 1) * HZ;
1953                 adev->throttling_logging_rs.begin = 0;
1954                 adev->throttling_logging_rs.printed = 0;
1955                 adev->throttling_logging_rs.missed = 0;
1956                 raw_spin_unlock_irqrestore(&adev->throttling_logging_rs.lock, flags);
1957
1958                 atomic_set(&adev->throttling_logging_enabled, 1);
1959         } else {
1960                 atomic_set(&adev->throttling_logging_enabled, 0);
1961         }
1962
1963         return count;
1964 }
1965
1966 /**
1967  * DOC: gpu_metrics
1968  *
1969  * The amdgpu driver provides a sysfs API for retrieving current gpu
1970  * metrics data. The file gpu_metrics is used for this. Reading the
1971  * file will dump all the current gpu metrics data.
1972  *
1973  * These data include temperature, frequency, engines utilization,
1974  * power consume, throttler status, fan speed and cpu core statistics(
1975  * available for APU only). That's it will give a snapshot of all sensors
1976  * at the same time.
1977  */
1978 static ssize_t amdgpu_get_gpu_metrics(struct device *dev,
1979                                       struct device_attribute *attr,
1980                                       char *buf)
1981 {
1982         struct drm_device *ddev = dev_get_drvdata(dev);
1983         struct amdgpu_device *adev = drm_to_adev(ddev);
1984         void *gpu_metrics;
1985         ssize_t size = 0;
1986         int ret;
1987
1988         if (amdgpu_in_reset(adev))
1989                 return -EPERM;
1990
1991         ret = pm_runtime_get_sync(ddev->dev);
1992         if (ret < 0) {
1993                 pm_runtime_put_autosuspend(ddev->dev);
1994                 return ret;
1995         }
1996
1997         if (is_support_sw_smu(adev))
1998                 size = smu_sys_get_gpu_metrics(&adev->smu, &gpu_metrics);
1999         else if (adev->powerplay.pp_funcs->get_gpu_metrics)
2000                 size = amdgpu_dpm_get_gpu_metrics(adev, &gpu_metrics);
2001
2002         if (size <= 0)
2003                 goto out;
2004
2005         if (size >= PAGE_SIZE)
2006                 size = PAGE_SIZE - 1;
2007
2008         memcpy(buf, gpu_metrics, size);
2009
2010 out:
2011         pm_runtime_mark_last_busy(ddev->dev);
2012         pm_runtime_put_autosuspend(ddev->dev);
2013
2014         return size;
2015 }
2016
2017 static struct amdgpu_device_attr amdgpu_device_attrs[] = {
2018         AMDGPU_DEVICE_ATTR_RW(power_dpm_state,                          ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2019         AMDGPU_DEVICE_ATTR_RW(power_dpm_force_performance_level,        ATTR_FLAG_BASIC),
2020         AMDGPU_DEVICE_ATTR_RO(pp_num_states,                            ATTR_FLAG_BASIC),
2021         AMDGPU_DEVICE_ATTR_RO(pp_cur_state,                             ATTR_FLAG_BASIC),
2022         AMDGPU_DEVICE_ATTR_RW(pp_force_state,                           ATTR_FLAG_BASIC),
2023         AMDGPU_DEVICE_ATTR_RW(pp_table,                                 ATTR_FLAG_BASIC),
2024         AMDGPU_DEVICE_ATTR_RW(pp_dpm_sclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2025         AMDGPU_DEVICE_ATTR_RW(pp_dpm_mclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2026         AMDGPU_DEVICE_ATTR_RW(pp_dpm_socclk,                            ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2027         AMDGPU_DEVICE_ATTR_RW(pp_dpm_fclk,                              ATTR_FLAG_BASIC|ATTR_FLAG_ONEVF),
2028         AMDGPU_DEVICE_ATTR_RW(pp_dpm_dcefclk,                           ATTR_FLAG_BASIC),
2029         AMDGPU_DEVICE_ATTR_RW(pp_dpm_pcie,                              ATTR_FLAG_BASIC),
2030         AMDGPU_DEVICE_ATTR_RW(pp_sclk_od,                               ATTR_FLAG_BASIC),
2031         AMDGPU_DEVICE_ATTR_RW(pp_mclk_od,                               ATTR_FLAG_BASIC),
2032         AMDGPU_DEVICE_ATTR_RW(pp_power_profile_mode,                    ATTR_FLAG_BASIC),
2033         AMDGPU_DEVICE_ATTR_RW(pp_od_clk_voltage,                        ATTR_FLAG_BASIC),
2034         AMDGPU_DEVICE_ATTR_RO(gpu_busy_percent,                         ATTR_FLAG_BASIC),
2035         AMDGPU_DEVICE_ATTR_RO(mem_busy_percent,                         ATTR_FLAG_BASIC),
2036         AMDGPU_DEVICE_ATTR_RO(pcie_bw,                                  ATTR_FLAG_BASIC),
2037         AMDGPU_DEVICE_ATTR_RW(pp_features,                              ATTR_FLAG_BASIC),
2038         AMDGPU_DEVICE_ATTR_RO(unique_id,                                ATTR_FLAG_BASIC),
2039         AMDGPU_DEVICE_ATTR_RW(thermal_throttling_logging,               ATTR_FLAG_BASIC),
2040         AMDGPU_DEVICE_ATTR_RO(gpu_metrics,                              ATTR_FLAG_BASIC),
2041 };
2042
2043 static int default_attr_update(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2044                                uint32_t mask, enum amdgpu_device_attr_states *states)
2045 {
2046         struct device_attribute *dev_attr = &attr->dev_attr;
2047         const char *attr_name = dev_attr->attr.name;
2048         struct pp_hwmgr *hwmgr = adev->powerplay.pp_handle;
2049         enum amd_asic_type asic_type = adev->asic_type;
2050
2051         if (!(attr->flags & mask)) {
2052                 *states = ATTR_STATE_UNSUPPORTED;
2053                 return 0;
2054         }
2055
2056 #define DEVICE_ATTR_IS(_name)   (!strcmp(attr_name, #_name))
2057
2058         if (DEVICE_ATTR_IS(pp_dpm_socclk)) {
2059                 if (asic_type < CHIP_VEGA10)
2060                         *states = ATTR_STATE_UNSUPPORTED;
2061         } else if (DEVICE_ATTR_IS(pp_dpm_dcefclk)) {
2062                 if (asic_type < CHIP_VEGA10 || asic_type == CHIP_ARCTURUS)
2063                         *states = ATTR_STATE_UNSUPPORTED;
2064         } else if (DEVICE_ATTR_IS(pp_dpm_fclk)) {
2065                 if (asic_type < CHIP_VEGA20)
2066                         *states = ATTR_STATE_UNSUPPORTED;
2067         } else if (DEVICE_ATTR_IS(pp_od_clk_voltage)) {
2068                 *states = ATTR_STATE_UNSUPPORTED;
2069                 if ((is_support_sw_smu(adev) && adev->smu.od_enabled) ||
2070                     (!is_support_sw_smu(adev) && hwmgr->od_enabled))
2071                         *states = ATTR_STATE_SUPPORTED;
2072         } else if (DEVICE_ATTR_IS(mem_busy_percent)) {
2073                 if (adev->flags & AMD_IS_APU || asic_type == CHIP_VEGA10)
2074                         *states = ATTR_STATE_UNSUPPORTED;
2075         } else if (DEVICE_ATTR_IS(pcie_bw)) {
2076                 /* PCIe Perf counters won't work on APU nodes */
2077                 if (adev->flags & AMD_IS_APU)
2078                         *states = ATTR_STATE_UNSUPPORTED;
2079         } else if (DEVICE_ATTR_IS(unique_id)) {
2080                 if (asic_type != CHIP_VEGA10 &&
2081                     asic_type != CHIP_VEGA20 &&
2082                     asic_type != CHIP_ARCTURUS)
2083                         *states = ATTR_STATE_UNSUPPORTED;
2084         } else if (DEVICE_ATTR_IS(pp_features)) {
2085                 if (adev->flags & AMD_IS_APU || asic_type < CHIP_VEGA10)
2086                         *states = ATTR_STATE_UNSUPPORTED;
2087         } else if (DEVICE_ATTR_IS(gpu_metrics)) {
2088                 if (asic_type < CHIP_VEGA12)
2089                         *states = ATTR_STATE_UNSUPPORTED;
2090         }
2091
2092         if (asic_type == CHIP_ARCTURUS) {
2093                 /* Arcturus does not support standalone mclk/socclk/fclk level setting */
2094                 if (DEVICE_ATTR_IS(pp_dpm_mclk) ||
2095                     DEVICE_ATTR_IS(pp_dpm_socclk) ||
2096                     DEVICE_ATTR_IS(pp_dpm_fclk)) {
2097                         dev_attr->attr.mode &= ~S_IWUGO;
2098                         dev_attr->store = NULL;
2099                 }
2100         }
2101
2102 #undef DEVICE_ATTR_IS
2103
2104         return 0;
2105 }
2106
2107
2108 static int amdgpu_device_attr_create(struct amdgpu_device *adev,
2109                                      struct amdgpu_device_attr *attr,
2110                                      uint32_t mask, struct list_head *attr_list)
2111 {
2112         int ret = 0;
2113         struct device_attribute *dev_attr = &attr->dev_attr;
2114         const char *name = dev_attr->attr.name;
2115         enum amdgpu_device_attr_states attr_states = ATTR_STATE_SUPPORTED;
2116         struct amdgpu_device_attr_entry *attr_entry;
2117
2118         int (*attr_update)(struct amdgpu_device *adev, struct amdgpu_device_attr *attr,
2119                            uint32_t mask, enum amdgpu_device_attr_states *states) = default_attr_update;
2120
2121         BUG_ON(!attr);
2122
2123         attr_update = attr->attr_update ? attr_update : default_attr_update;
2124
2125         ret = attr_update(adev, attr, mask, &attr_states);
2126         if (ret) {
2127                 dev_err(adev->dev, "failed to update device file %s, ret = %d\n",
2128                         name, ret);
2129                 return ret;
2130         }
2131
2132         if (attr_states == ATTR_STATE_UNSUPPORTED)
2133                 return 0;
2134
2135         ret = device_create_file(adev->dev, dev_attr);
2136         if (ret) {
2137                 dev_err(adev->dev, "failed to create device file %s, ret = %d\n",
2138                         name, ret);
2139         }
2140
2141         attr_entry = kmalloc(sizeof(*attr_entry), GFP_KERNEL);
2142         if (!attr_entry)
2143                 return -ENOMEM;
2144
2145         attr_entry->attr = attr;
2146         INIT_LIST_HEAD(&attr_entry->entry);
2147
2148         list_add_tail(&attr_entry->entry, attr_list);
2149
2150         return ret;
2151 }
2152
2153 static void amdgpu_device_attr_remove(struct amdgpu_device *adev, struct amdgpu_device_attr *attr)
2154 {
2155         struct device_attribute *dev_attr = &attr->dev_attr;
2156
2157         device_remove_file(adev->dev, dev_attr);
2158 }
2159
2160 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2161                                              struct list_head *attr_list);
2162
2163 static int amdgpu_device_attr_create_groups(struct amdgpu_device *adev,
2164                                             struct amdgpu_device_attr *attrs,
2165                                             uint32_t counts,
2166                                             uint32_t mask,
2167                                             struct list_head *attr_list)
2168 {
2169         int ret = 0;
2170         uint32_t i = 0;
2171
2172         for (i = 0; i < counts; i++) {
2173                 ret = amdgpu_device_attr_create(adev, &attrs[i], mask, attr_list);
2174                 if (ret)
2175                         goto failed;
2176         }
2177
2178         return 0;
2179
2180 failed:
2181         amdgpu_device_attr_remove_groups(adev, attr_list);
2182
2183         return ret;
2184 }
2185
2186 static void amdgpu_device_attr_remove_groups(struct amdgpu_device *adev,
2187                                              struct list_head *attr_list)
2188 {
2189         struct amdgpu_device_attr_entry *entry, *entry_tmp;
2190
2191         if (list_empty(attr_list))
2192                 return ;
2193
2194         list_for_each_entry_safe(entry, entry_tmp, attr_list, entry) {
2195                 amdgpu_device_attr_remove(adev, entry->attr);
2196                 list_del(&entry->entry);
2197                 kfree(entry);
2198         }
2199 }
2200
2201 static ssize_t amdgpu_hwmon_show_temp(struct device *dev,
2202                                       struct device_attribute *attr,
2203                                       char *buf)
2204 {
2205         struct amdgpu_device *adev = dev_get_drvdata(dev);
2206         int channel = to_sensor_dev_attr(attr)->index;
2207         int r, temp = 0, size = sizeof(temp);
2208
2209         if (amdgpu_in_reset(adev))
2210                 return -EPERM;
2211
2212         if (channel >= PP_TEMP_MAX)
2213                 return -EINVAL;
2214
2215         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2216         if (r < 0) {
2217                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2218                 return r;
2219         }
2220
2221         switch (channel) {
2222         case PP_TEMP_JUNCTION:
2223                 /* get current junction temperature */
2224                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_HOTSPOT_TEMP,
2225                                            (void *)&temp, &size);
2226                 break;
2227         case PP_TEMP_EDGE:
2228                 /* get current edge temperature */
2229                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_EDGE_TEMP,
2230                                            (void *)&temp, &size);
2231                 break;
2232         case PP_TEMP_MEM:
2233                 /* get current memory temperature */
2234                 r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_TEMP,
2235                                            (void *)&temp, &size);
2236                 break;
2237         default:
2238                 r = -EINVAL;
2239                 break;
2240         }
2241
2242         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2243         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2244
2245         if (r)
2246                 return r;
2247
2248         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
2249 }
2250
2251 static ssize_t amdgpu_hwmon_show_temp_thresh(struct device *dev,
2252                                              struct device_attribute *attr,
2253                                              char *buf)
2254 {
2255         struct amdgpu_device *adev = dev_get_drvdata(dev);
2256         int hyst = to_sensor_dev_attr(attr)->index;
2257         int temp;
2258
2259         if (hyst)
2260                 temp = adev->pm.dpm.thermal.min_temp;
2261         else
2262                 temp = adev->pm.dpm.thermal.max_temp;
2263
2264         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
2265 }
2266
2267 static ssize_t amdgpu_hwmon_show_hotspot_temp_thresh(struct device *dev,
2268                                              struct device_attribute *attr,
2269                                              char *buf)
2270 {
2271         struct amdgpu_device *adev = dev_get_drvdata(dev);
2272         int hyst = to_sensor_dev_attr(attr)->index;
2273         int temp;
2274
2275         if (hyst)
2276                 temp = adev->pm.dpm.thermal.min_hotspot_temp;
2277         else
2278                 temp = adev->pm.dpm.thermal.max_hotspot_crit_temp;
2279
2280         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
2281 }
2282
2283 static ssize_t amdgpu_hwmon_show_mem_temp_thresh(struct device *dev,
2284                                              struct device_attribute *attr,
2285                                              char *buf)
2286 {
2287         struct amdgpu_device *adev = dev_get_drvdata(dev);
2288         int hyst = to_sensor_dev_attr(attr)->index;
2289         int temp;
2290
2291         if (hyst)
2292                 temp = adev->pm.dpm.thermal.min_mem_temp;
2293         else
2294                 temp = adev->pm.dpm.thermal.max_mem_crit_temp;
2295
2296         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
2297 }
2298
2299 static ssize_t amdgpu_hwmon_show_temp_label(struct device *dev,
2300                                              struct device_attribute *attr,
2301                                              char *buf)
2302 {
2303         int channel = to_sensor_dev_attr(attr)->index;
2304
2305         if (channel >= PP_TEMP_MAX)
2306                 return -EINVAL;
2307
2308         return snprintf(buf, PAGE_SIZE, "%s\n", temp_label[channel].label);
2309 }
2310
2311 static ssize_t amdgpu_hwmon_show_temp_emergency(struct device *dev,
2312                                              struct device_attribute *attr,
2313                                              char *buf)
2314 {
2315         struct amdgpu_device *adev = dev_get_drvdata(dev);
2316         int channel = to_sensor_dev_attr(attr)->index;
2317         int temp = 0;
2318
2319         if (channel >= PP_TEMP_MAX)
2320                 return -EINVAL;
2321
2322         switch (channel) {
2323         case PP_TEMP_JUNCTION:
2324                 temp = adev->pm.dpm.thermal.max_hotspot_emergency_temp;
2325                 break;
2326         case PP_TEMP_EDGE:
2327                 temp = adev->pm.dpm.thermal.max_edge_emergency_temp;
2328                 break;
2329         case PP_TEMP_MEM:
2330                 temp = adev->pm.dpm.thermal.max_mem_emergency_temp;
2331                 break;
2332         }
2333
2334         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
2335 }
2336
2337 static ssize_t amdgpu_hwmon_get_pwm1_enable(struct device *dev,
2338                                             struct device_attribute *attr,
2339                                             char *buf)
2340 {
2341         struct amdgpu_device *adev = dev_get_drvdata(dev);
2342         u32 pwm_mode = 0;
2343         int ret;
2344
2345         if (amdgpu_in_reset(adev))
2346                 return -EPERM;
2347
2348         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2349         if (ret < 0) {
2350                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2351                 return ret;
2352         }
2353
2354         if (is_support_sw_smu(adev)) {
2355                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
2356         } else {
2357                 if (!adev->powerplay.pp_funcs->get_fan_control_mode) {
2358                         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2359                         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2360                         return -EINVAL;
2361                 }
2362
2363                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2364         }
2365
2366         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2367         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2368
2369         return sprintf(buf, "%i\n", pwm_mode);
2370 }
2371
2372 static ssize_t amdgpu_hwmon_set_pwm1_enable(struct device *dev,
2373                                             struct device_attribute *attr,
2374                                             const char *buf,
2375                                             size_t count)
2376 {
2377         struct amdgpu_device *adev = dev_get_drvdata(dev);
2378         int err, ret;
2379         int value;
2380
2381         if (amdgpu_in_reset(adev))
2382                 return -EPERM;
2383
2384         err = kstrtoint(buf, 10, &value);
2385         if (err)
2386                 return err;
2387
2388         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2389         if (ret < 0) {
2390                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2391                 return ret;
2392         }
2393
2394         if (is_support_sw_smu(adev)) {
2395                 smu_set_fan_control_mode(&adev->smu, value);
2396         } else {
2397                 if (!adev->powerplay.pp_funcs->set_fan_control_mode) {
2398                         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2399                         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2400                         return -EINVAL;
2401                 }
2402
2403                 amdgpu_dpm_set_fan_control_mode(adev, value);
2404         }
2405
2406         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2407         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2408
2409         return count;
2410 }
2411
2412 static ssize_t amdgpu_hwmon_get_pwm1_min(struct device *dev,
2413                                          struct device_attribute *attr,
2414                                          char *buf)
2415 {
2416         return sprintf(buf, "%i\n", 0);
2417 }
2418
2419 static ssize_t amdgpu_hwmon_get_pwm1_max(struct device *dev,
2420                                          struct device_attribute *attr,
2421                                          char *buf)
2422 {
2423         return sprintf(buf, "%i\n", 255);
2424 }
2425
2426 static ssize_t amdgpu_hwmon_set_pwm1(struct device *dev,
2427                                      struct device_attribute *attr,
2428                                      const char *buf, size_t count)
2429 {
2430         struct amdgpu_device *adev = dev_get_drvdata(dev);
2431         int err;
2432         u32 value;
2433         u32 pwm_mode;
2434
2435         if (amdgpu_in_reset(adev))
2436                 return -EPERM;
2437
2438         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2439         if (err < 0) {
2440                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2441                 return err;
2442         }
2443
2444         if (is_support_sw_smu(adev))
2445                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
2446         else
2447                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2448
2449         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2450                 pr_info("manual fan speed control should be enabled first\n");
2451                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2452                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2453                 return -EINVAL;
2454         }
2455
2456         err = kstrtou32(buf, 10, &value);
2457         if (err) {
2458                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2459                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2460                 return err;
2461         }
2462
2463         value = (value * 100) / 255;
2464
2465         if (is_support_sw_smu(adev))
2466                 err = smu_set_fan_speed_percent(&adev->smu, value);
2467         else if (adev->powerplay.pp_funcs->set_fan_speed_percent)
2468                 err = amdgpu_dpm_set_fan_speed_percent(adev, value);
2469         else
2470                 err = -EINVAL;
2471
2472         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2473         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2474
2475         if (err)
2476                 return err;
2477
2478         return count;
2479 }
2480
2481 static ssize_t amdgpu_hwmon_get_pwm1(struct device *dev,
2482                                      struct device_attribute *attr,
2483                                      char *buf)
2484 {
2485         struct amdgpu_device *adev = dev_get_drvdata(dev);
2486         int err;
2487         u32 speed = 0;
2488
2489         if (amdgpu_in_reset(adev))
2490                 return -EPERM;
2491
2492         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2493         if (err < 0) {
2494                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2495                 return err;
2496         }
2497
2498         if (is_support_sw_smu(adev))
2499                 err = smu_get_fan_speed_percent(&adev->smu, &speed);
2500         else if (adev->powerplay.pp_funcs->get_fan_speed_percent)
2501                 err = amdgpu_dpm_get_fan_speed_percent(adev, &speed);
2502         else
2503                 err = -EINVAL;
2504
2505         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2506         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2507
2508         if (err)
2509                 return err;
2510
2511         speed = (speed * 255) / 100;
2512
2513         return sprintf(buf, "%i\n", speed);
2514 }
2515
2516 static ssize_t amdgpu_hwmon_get_fan1_input(struct device *dev,
2517                                            struct device_attribute *attr,
2518                                            char *buf)
2519 {
2520         struct amdgpu_device *adev = dev_get_drvdata(dev);
2521         int err;
2522         u32 speed = 0;
2523
2524         if (amdgpu_in_reset(adev))
2525                 return -EPERM;
2526
2527         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2528         if (err < 0) {
2529                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2530                 return err;
2531         }
2532
2533         if (is_support_sw_smu(adev))
2534                 err = smu_get_fan_speed_rpm(&adev->smu, &speed);
2535         else if (adev->powerplay.pp_funcs->get_fan_speed_rpm)
2536                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &speed);
2537         else
2538                 err = -EINVAL;
2539
2540         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2541         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2542
2543         if (err)
2544                 return err;
2545
2546         return sprintf(buf, "%i\n", speed);
2547 }
2548
2549 static ssize_t amdgpu_hwmon_get_fan1_min(struct device *dev,
2550                                          struct device_attribute *attr,
2551                                          char *buf)
2552 {
2553         struct amdgpu_device *adev = dev_get_drvdata(dev);
2554         u32 min_rpm = 0;
2555         u32 size = sizeof(min_rpm);
2556         int r;
2557
2558         if (amdgpu_in_reset(adev))
2559                 return -EPERM;
2560
2561         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2562         if (r < 0) {
2563                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2564                 return r;
2565         }
2566
2567         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MIN_FAN_RPM,
2568                                    (void *)&min_rpm, &size);
2569
2570         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2571         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2572
2573         if (r)
2574                 return r;
2575
2576         return snprintf(buf, PAGE_SIZE, "%d\n", min_rpm);
2577 }
2578
2579 static ssize_t amdgpu_hwmon_get_fan1_max(struct device *dev,
2580                                          struct device_attribute *attr,
2581                                          char *buf)
2582 {
2583         struct amdgpu_device *adev = dev_get_drvdata(dev);
2584         u32 max_rpm = 0;
2585         u32 size = sizeof(max_rpm);
2586         int r;
2587
2588         if (amdgpu_in_reset(adev))
2589                 return -EPERM;
2590
2591         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2592         if (r < 0) {
2593                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2594                 return r;
2595         }
2596
2597         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MAX_FAN_RPM,
2598                                    (void *)&max_rpm, &size);
2599
2600         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2601         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2602
2603         if (r)
2604                 return r;
2605
2606         return snprintf(buf, PAGE_SIZE, "%d\n", max_rpm);
2607 }
2608
2609 static ssize_t amdgpu_hwmon_get_fan1_target(struct device *dev,
2610                                            struct device_attribute *attr,
2611                                            char *buf)
2612 {
2613         struct amdgpu_device *adev = dev_get_drvdata(dev);
2614         int err;
2615         u32 rpm = 0;
2616
2617         if (amdgpu_in_reset(adev))
2618                 return -EPERM;
2619
2620         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2621         if (err < 0) {
2622                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2623                 return err;
2624         }
2625
2626         if (is_support_sw_smu(adev))
2627                 err = smu_get_fan_speed_rpm(&adev->smu, &rpm);
2628         else if (adev->powerplay.pp_funcs->get_fan_speed_rpm)
2629                 err = amdgpu_dpm_get_fan_speed_rpm(adev, &rpm);
2630         else
2631                 err = -EINVAL;
2632
2633         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2634         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2635
2636         if (err)
2637                 return err;
2638
2639         return sprintf(buf, "%i\n", rpm);
2640 }
2641
2642 static ssize_t amdgpu_hwmon_set_fan1_target(struct device *dev,
2643                                      struct device_attribute *attr,
2644                                      const char *buf, size_t count)
2645 {
2646         struct amdgpu_device *adev = dev_get_drvdata(dev);
2647         int err;
2648         u32 value;
2649         u32 pwm_mode;
2650
2651         if (amdgpu_in_reset(adev))
2652                 return -EPERM;
2653
2654         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2655         if (err < 0) {
2656                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2657                 return err;
2658         }
2659
2660         if (is_support_sw_smu(adev))
2661                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
2662         else
2663                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2664
2665         if (pwm_mode != AMD_FAN_CTRL_MANUAL) {
2666                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2667                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2668                 return -ENODATA;
2669         }
2670
2671         err = kstrtou32(buf, 10, &value);
2672         if (err) {
2673                 pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2674                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2675                 return err;
2676         }
2677
2678         if (is_support_sw_smu(adev))
2679                 err = smu_set_fan_speed_rpm(&adev->smu, value);
2680         else if (adev->powerplay.pp_funcs->set_fan_speed_rpm)
2681                 err = amdgpu_dpm_set_fan_speed_rpm(adev, value);
2682         else
2683                 err = -EINVAL;
2684
2685         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2686         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2687
2688         if (err)
2689                 return err;
2690
2691         return count;
2692 }
2693
2694 static ssize_t amdgpu_hwmon_get_fan1_enable(struct device *dev,
2695                                             struct device_attribute *attr,
2696                                             char *buf)
2697 {
2698         struct amdgpu_device *adev = dev_get_drvdata(dev);
2699         u32 pwm_mode = 0;
2700         int ret;
2701
2702         if (amdgpu_in_reset(adev))
2703                 return -EPERM;
2704
2705         ret = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2706         if (ret < 0) {
2707                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2708                 return ret;
2709         }
2710
2711         if (is_support_sw_smu(adev)) {
2712                 pwm_mode = smu_get_fan_control_mode(&adev->smu);
2713         } else {
2714                 if (!adev->powerplay.pp_funcs->get_fan_control_mode) {
2715                         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2716                         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2717                         return -EINVAL;
2718                 }
2719
2720                 pwm_mode = amdgpu_dpm_get_fan_control_mode(adev);
2721         }
2722
2723         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2724         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2725
2726         return sprintf(buf, "%i\n", pwm_mode == AMD_FAN_CTRL_AUTO ? 0 : 1);
2727 }
2728
2729 static ssize_t amdgpu_hwmon_set_fan1_enable(struct device *dev,
2730                                             struct device_attribute *attr,
2731                                             const char *buf,
2732                                             size_t count)
2733 {
2734         struct amdgpu_device *adev = dev_get_drvdata(dev);
2735         int err;
2736         int value;
2737         u32 pwm_mode;
2738
2739         if (amdgpu_in_reset(adev))
2740                 return -EPERM;
2741
2742         err = kstrtoint(buf, 10, &value);
2743         if (err)
2744                 return err;
2745
2746         if (value == 0)
2747                 pwm_mode = AMD_FAN_CTRL_AUTO;
2748         else if (value == 1)
2749                 pwm_mode = AMD_FAN_CTRL_MANUAL;
2750         else
2751                 return -EINVAL;
2752
2753         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2754         if (err < 0) {
2755                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2756                 return err;
2757         }
2758
2759         if (is_support_sw_smu(adev)) {
2760                 smu_set_fan_control_mode(&adev->smu, pwm_mode);
2761         } else {
2762                 if (!adev->powerplay.pp_funcs->set_fan_control_mode) {
2763                         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2764                         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2765                         return -EINVAL;
2766                 }
2767                 amdgpu_dpm_set_fan_control_mode(adev, pwm_mode);
2768         }
2769
2770         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2771         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2772
2773         return count;
2774 }
2775
2776 static ssize_t amdgpu_hwmon_show_vddgfx(struct device *dev,
2777                                         struct device_attribute *attr,
2778                                         char *buf)
2779 {
2780         struct amdgpu_device *adev = dev_get_drvdata(dev);
2781         u32 vddgfx;
2782         int r, size = sizeof(vddgfx);
2783
2784         if (amdgpu_in_reset(adev))
2785                 return -EPERM;
2786
2787         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2788         if (r < 0) {
2789                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2790                 return r;
2791         }
2792
2793         /* get the voltage */
2794         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX,
2795                                    (void *)&vddgfx, &size);
2796
2797         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2798         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2799
2800         if (r)
2801                 return r;
2802
2803         return snprintf(buf, PAGE_SIZE, "%d\n", vddgfx);
2804 }
2805
2806 static ssize_t amdgpu_hwmon_show_vddgfx_label(struct device *dev,
2807                                               struct device_attribute *attr,
2808                                               char *buf)
2809 {
2810         return snprintf(buf, PAGE_SIZE, "vddgfx\n");
2811 }
2812
2813 static ssize_t amdgpu_hwmon_show_vddnb(struct device *dev,
2814                                        struct device_attribute *attr,
2815                                        char *buf)
2816 {
2817         struct amdgpu_device *adev = dev_get_drvdata(dev);
2818         u32 vddnb;
2819         int r, size = sizeof(vddnb);
2820
2821         if (amdgpu_in_reset(adev))
2822                 return -EPERM;
2823
2824         /* only APUs have vddnb */
2825         if  (!(adev->flags & AMD_IS_APU))
2826                 return -EINVAL;
2827
2828         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2829         if (r < 0) {
2830                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2831                 return r;
2832         }
2833
2834         /* get the voltage */
2835         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB,
2836                                    (void *)&vddnb, &size);
2837
2838         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2839         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2840
2841         if (r)
2842                 return r;
2843
2844         return snprintf(buf, PAGE_SIZE, "%d\n", vddnb);
2845 }
2846
2847 static ssize_t amdgpu_hwmon_show_vddnb_label(struct device *dev,
2848                                               struct device_attribute *attr,
2849                                               char *buf)
2850 {
2851         return snprintf(buf, PAGE_SIZE, "vddnb\n");
2852 }
2853
2854 static ssize_t amdgpu_hwmon_show_power_avg(struct device *dev,
2855                                            struct device_attribute *attr,
2856                                            char *buf)
2857 {
2858         struct amdgpu_device *adev = dev_get_drvdata(dev);
2859         u32 query = 0;
2860         int r, size = sizeof(u32);
2861         unsigned uw;
2862
2863         if (amdgpu_in_reset(adev))
2864                 return -EPERM;
2865
2866         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2867         if (r < 0) {
2868                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2869                 return r;
2870         }
2871
2872         /* get the voltage */
2873         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER,
2874                                    (void *)&query, &size);
2875
2876         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2877         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2878
2879         if (r)
2880                 return r;
2881
2882         /* convert to microwatts */
2883         uw = (query >> 8) * 1000000 + (query & 0xff) * 1000;
2884
2885         return snprintf(buf, PAGE_SIZE, "%u\n", uw);
2886 }
2887
2888 static ssize_t amdgpu_hwmon_show_power_cap_min(struct device *dev,
2889                                          struct device_attribute *attr,
2890                                          char *buf)
2891 {
2892         return sprintf(buf, "%i\n", 0);
2893 }
2894
2895 static ssize_t amdgpu_hwmon_show_power_cap_max(struct device *dev,
2896                                          struct device_attribute *attr,
2897                                          char *buf)
2898 {
2899         struct amdgpu_device *adev = dev_get_drvdata(dev);
2900         uint32_t limit = 0;
2901         ssize_t size;
2902         int r;
2903
2904         if (amdgpu_in_reset(adev))
2905                 return -EPERM;
2906
2907         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2908         if (r < 0) {
2909                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2910                 return r;
2911         }
2912
2913         if (is_support_sw_smu(adev)) {
2914                 smu_get_power_limit(&adev->smu, &limit, true);
2915                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2916         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
2917                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, true);
2918                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2919         } else {
2920                 size = snprintf(buf, PAGE_SIZE, "\n");
2921         }
2922
2923         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2924         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2925
2926         return size;
2927 }
2928
2929 static ssize_t amdgpu_hwmon_show_power_cap(struct device *dev,
2930                                          struct device_attribute *attr,
2931                                          char *buf)
2932 {
2933         struct amdgpu_device *adev = dev_get_drvdata(dev);
2934         uint32_t limit = 0;
2935         ssize_t size;
2936         int r;
2937
2938         if (amdgpu_in_reset(adev))
2939                 return -EPERM;
2940
2941         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2942         if (r < 0) {
2943                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2944                 return r;
2945         }
2946
2947         if (is_support_sw_smu(adev)) {
2948                 smu_get_power_limit(&adev->smu, &limit, false);
2949                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2950         } else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->get_power_limit) {
2951                 adev->powerplay.pp_funcs->get_power_limit(adev->powerplay.pp_handle, &limit, false);
2952                 size = snprintf(buf, PAGE_SIZE, "%u\n", limit * 1000000);
2953         } else {
2954                 size = snprintf(buf, PAGE_SIZE, "\n");
2955         }
2956
2957         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
2958         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2959
2960         return size;
2961 }
2962
2963
2964 static ssize_t amdgpu_hwmon_set_power_cap(struct device *dev,
2965                 struct device_attribute *attr,
2966                 const char *buf,
2967                 size_t count)
2968 {
2969         struct amdgpu_device *adev = dev_get_drvdata(dev);
2970         int err;
2971         u32 value;
2972
2973         if (amdgpu_in_reset(adev))
2974                 return -EPERM;
2975
2976         if (amdgpu_sriov_vf(adev))
2977                 return -EINVAL;
2978
2979         err = kstrtou32(buf, 10, &value);
2980         if (err)
2981                 return err;
2982
2983         value = value / 1000000; /* convert to Watt */
2984
2985
2986         err = pm_runtime_get_sync(adev_to_drm(adev)->dev);
2987         if (err < 0) {
2988                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
2989                 return err;
2990         }
2991
2992         if (is_support_sw_smu(adev))
2993                 err = smu_set_power_limit(&adev->smu, value);
2994         else if (adev->powerplay.pp_funcs && adev->powerplay.pp_funcs->set_power_limit)
2995                 err = adev->powerplay.pp_funcs->set_power_limit(adev->powerplay.pp_handle, value);
2996         else
2997                 err = -EINVAL;
2998
2999         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
3000         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3001
3002         if (err)
3003                 return err;
3004
3005         return count;
3006 }
3007
3008 static ssize_t amdgpu_hwmon_show_sclk(struct device *dev,
3009                                       struct device_attribute *attr,
3010                                       char *buf)
3011 {
3012         struct amdgpu_device *adev = dev_get_drvdata(dev);
3013         uint32_t sclk;
3014         int r, size = sizeof(sclk);
3015
3016         if (amdgpu_in_reset(adev))
3017                 return -EPERM;
3018
3019         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
3020         if (r < 0) {
3021                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3022                 return r;
3023         }
3024
3025         /* get the sclk */
3026         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK,
3027                                    (void *)&sclk, &size);
3028
3029         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
3030         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3031
3032         if (r)
3033                 return r;
3034
3035         return snprintf(buf, PAGE_SIZE, "%u\n", sclk * 10 * 1000);
3036 }
3037
3038 static ssize_t amdgpu_hwmon_show_sclk_label(struct device *dev,
3039                                             struct device_attribute *attr,
3040                                             char *buf)
3041 {
3042         return snprintf(buf, PAGE_SIZE, "sclk\n");
3043 }
3044
3045 static ssize_t amdgpu_hwmon_show_mclk(struct device *dev,
3046                                       struct device_attribute *attr,
3047                                       char *buf)
3048 {
3049         struct amdgpu_device *adev = dev_get_drvdata(dev);
3050         uint32_t mclk;
3051         int r, size = sizeof(mclk);
3052
3053         if (amdgpu_in_reset(adev))
3054                 return -EPERM;
3055
3056         r = pm_runtime_get_sync(adev_to_drm(adev)->dev);
3057         if (r < 0) {
3058                 pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3059                 return r;
3060         }
3061
3062         /* get the sclk */
3063         r = amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK,
3064                                    (void *)&mclk, &size);
3065
3066         pm_runtime_mark_last_busy(adev_to_drm(adev)->dev);
3067         pm_runtime_put_autosuspend(adev_to_drm(adev)->dev);
3068
3069         if (r)
3070                 return r;
3071
3072         return snprintf(buf, PAGE_SIZE, "%u\n", mclk * 10 * 1000);
3073 }
3074
3075 static ssize_t amdgpu_hwmon_show_mclk_label(struct device *dev,
3076                                             struct device_attribute *attr,
3077                                             char *buf)
3078 {
3079         return snprintf(buf, PAGE_SIZE, "mclk\n");
3080 }
3081
3082 /**
3083  * DOC: hwmon
3084  *
3085  * The amdgpu driver exposes the following sensor interfaces:
3086  *
3087  * - GPU temperature (via the on-die sensor)
3088  *
3089  * - GPU voltage
3090  *
3091  * - Northbridge voltage (APUs only)
3092  *
3093  * - GPU power
3094  *
3095  * - GPU fan
3096  *
3097  * - GPU gfx/compute engine clock
3098  *
3099  * - GPU memory clock (dGPU only)
3100  *
3101  * hwmon interfaces for GPU temperature:
3102  *
3103  * - temp[1-3]_input: the on die GPU temperature in millidegrees Celsius
3104  *   - temp2_input and temp3_input are supported on SOC15 dGPUs only
3105  *
3106  * - temp[1-3]_label: temperature channel label
3107  *   - temp2_label and temp3_label are supported on SOC15 dGPUs only
3108  *
3109  * - temp[1-3]_crit: temperature critical max value in millidegrees Celsius
3110  *   - temp2_crit and temp3_crit are supported on SOC15 dGPUs only
3111  *
3112  * - temp[1-3]_crit_hyst: temperature hysteresis for critical limit in millidegrees Celsius
3113  *   - temp2_crit_hyst and temp3_crit_hyst are supported on SOC15 dGPUs only
3114  *
3115  * - temp[1-3]_emergency: temperature emergency max value(asic shutdown) in millidegrees Celsius
3116  *   - these are supported on SOC15 dGPUs only
3117  *
3118  * hwmon interfaces for GPU voltage:
3119  *
3120  * - in0_input: the voltage on the GPU in millivolts
3121  *
3122  * - in1_input: the voltage on the Northbridge in millivolts
3123  *
3124  * hwmon interfaces for GPU power:
3125  *
3126  * - power1_average: average power used by the GPU in microWatts
3127  *
3128  * - power1_cap_min: minimum cap supported in microWatts
3129  *
3130  * - power1_cap_max: maximum cap supported in microWatts
3131  *
3132  * - power1_cap: selected power cap in microWatts
3133  *
3134  * hwmon interfaces for GPU fan:
3135  *
3136  * - pwm1: pulse width modulation fan level (0-255)
3137  *
3138  * - pwm1_enable: pulse width modulation fan control method (0: no fan speed control, 1: manual fan speed control using pwm interface, 2: automatic fan speed control)
3139  *
3140  * - pwm1_min: pulse width modulation fan control minimum level (0)
3141  *
3142  * - pwm1_max: pulse width modulation fan control maximum level (255)
3143  *
3144  * - fan1_min: an minimum value Unit: revolution/min (RPM)
3145  *
3146  * - fan1_max: an maxmum value Unit: revolution/max (RPM)
3147  *
3148  * - fan1_input: fan speed in RPM
3149  *
3150  * - fan[1-\*]_target: Desired fan speed Unit: revolution/min (RPM)
3151  *
3152  * - fan[1-\*]_enable: Enable or disable the sensors.1: Enable 0: Disable
3153  *
3154  * hwmon interfaces for GPU clocks:
3155  *
3156  * - freq1_input: the gfx/compute clock in hertz
3157  *
3158  * - freq2_input: the memory clock in hertz
3159  *
3160  * You can use hwmon tools like sensors to view this information on your system.
3161  *
3162  */
3163
3164 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_EDGE);
3165 static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 0);
3166 static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, amdgpu_hwmon_show_temp_thresh, NULL, 1);
3167 static SENSOR_DEVICE_ATTR(temp1_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_EDGE);
3168 static SENSOR_DEVICE_ATTR(temp2_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_JUNCTION);
3169 static SENSOR_DEVICE_ATTR(temp2_crit, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 0);
3170 static SENSOR_DEVICE_ATTR(temp2_crit_hyst, S_IRUGO, amdgpu_hwmon_show_hotspot_temp_thresh, NULL, 1);
3171 static SENSOR_DEVICE_ATTR(temp2_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_JUNCTION);
3172 static SENSOR_DEVICE_ATTR(temp3_input, S_IRUGO, amdgpu_hwmon_show_temp, NULL, PP_TEMP_MEM);
3173 static SENSOR_DEVICE_ATTR(temp3_crit, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 0);
3174 static SENSOR_DEVICE_ATTR(temp3_crit_hyst, S_IRUGO, amdgpu_hwmon_show_mem_temp_thresh, NULL, 1);
3175 static SENSOR_DEVICE_ATTR(temp3_emergency, S_IRUGO, amdgpu_hwmon_show_temp_emergency, NULL, PP_TEMP_MEM);
3176 static SENSOR_DEVICE_ATTR(temp1_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_EDGE);
3177 static SENSOR_DEVICE_ATTR(temp2_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_JUNCTION);
3178 static SENSOR_DEVICE_ATTR(temp3_label, S_IRUGO, amdgpu_hwmon_show_temp_label, NULL, PP_TEMP_MEM);
3179 static SENSOR_DEVICE_ATTR(pwm1, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1, amdgpu_hwmon_set_pwm1, 0);
3180 static SENSOR_DEVICE_ATTR(pwm1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_pwm1_enable, amdgpu_hwmon_set_pwm1_enable, 0);
3181 static SENSOR_DEVICE_ATTR(pwm1_min, S_IRUGO, amdgpu_hwmon_get_pwm1_min, NULL, 0);
3182 static SENSOR_DEVICE_ATTR(pwm1_max, S_IRUGO, amdgpu_hwmon_get_pwm1_max, NULL, 0);
3183 static SENSOR_DEVICE_ATTR(fan1_input, S_IRUGO, amdgpu_hwmon_get_fan1_input, NULL, 0);
3184 static SENSOR_DEVICE_ATTR(fan1_min, S_IRUGO, amdgpu_hwmon_get_fan1_min, NULL, 0);
3185 static SENSOR_DEVICE_ATTR(fan1_max, S_IRUGO, amdgpu_hwmon_get_fan1_max, NULL, 0);
3186 static SENSOR_DEVICE_ATTR(fan1_target, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_target, amdgpu_hwmon_set_fan1_target, 0);
3187 static SENSOR_DEVICE_ATTR(fan1_enable, S_IRUGO | S_IWUSR, amdgpu_hwmon_get_fan1_enable, amdgpu_hwmon_set_fan1_enable, 0);
3188 static SENSOR_DEVICE_ATTR(in0_input, S_IRUGO, amdgpu_hwmon_show_vddgfx, NULL, 0);
3189 static SENSOR_DEVICE_ATTR(in0_label, S_IRUGO, amdgpu_hwmon_show_vddgfx_label, NULL, 0);
3190 static SENSOR_DEVICE_ATTR(in1_input, S_IRUGO, amdgpu_hwmon_show_vddnb, NULL, 0);
3191 static SENSOR_DEVICE_ATTR(in1_label, S_IRUGO, amdgpu_hwmon_show_vddnb_label, NULL, 0);
3192 static SENSOR_DEVICE_ATTR(power1_average, S_IRUGO, amdgpu_hwmon_show_power_avg, NULL, 0);
3193 static SENSOR_DEVICE_ATTR(power1_cap_max, S_IRUGO, amdgpu_hwmon_show_power_cap_max, NULL, 0);
3194 static SENSOR_DEVICE_ATTR(power1_cap_min, S_IRUGO, amdgpu_hwmon_show_power_cap_min, NULL, 0);
3195 static SENSOR_DEVICE_ATTR(power1_cap, S_IRUGO | S_IWUSR, amdgpu_hwmon_show_power_cap, amdgpu_hwmon_set_power_cap, 0);
3196 static SENSOR_DEVICE_ATTR(freq1_input, S_IRUGO, amdgpu_hwmon_show_sclk, NULL, 0);
3197 static SENSOR_DEVICE_ATTR(freq1_label, S_IRUGO, amdgpu_hwmon_show_sclk_label, NULL, 0);
3198 static SENSOR_DEVICE_ATTR(freq2_input, S_IRUGO, amdgpu_hwmon_show_mclk, NULL, 0);
3199 static SENSOR_DEVICE_ATTR(freq2_label, S_IRUGO, amdgpu_hwmon_show_mclk_label, NULL, 0);
3200
3201 static struct attribute *hwmon_attributes[] = {
3202         &sensor_dev_attr_temp1_input.dev_attr.attr,
3203         &sensor_dev_attr_temp1_crit.dev_attr.attr,
3204         &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
3205         &sensor_dev_attr_temp2_input.dev_attr.attr,
3206         &sensor_dev_attr_temp2_crit.dev_attr.attr,
3207         &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr,
3208         &sensor_dev_attr_temp3_input.dev_attr.attr,
3209         &sensor_dev_attr_temp3_crit.dev_attr.attr,
3210         &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr,
3211         &sensor_dev_attr_temp1_emergency.dev_attr.attr,
3212         &sensor_dev_attr_temp2_emergency.dev_attr.attr,
3213         &sensor_dev_attr_temp3_emergency.dev_attr.attr,
3214         &sensor_dev_attr_temp1_label.dev_attr.attr,
3215         &sensor_dev_attr_temp2_label.dev_attr.attr,
3216         &sensor_dev_attr_temp3_label.dev_attr.attr,
3217         &sensor_dev_attr_pwm1.dev_attr.attr,
3218         &sensor_dev_attr_pwm1_enable.dev_attr.attr,
3219         &sensor_dev_attr_pwm1_min.dev_attr.attr,
3220         &sensor_dev_attr_pwm1_max.dev_attr.attr,
3221         &sensor_dev_attr_fan1_input.dev_attr.attr,
3222         &sensor_dev_attr_fan1_min.dev_attr.attr,
3223         &sensor_dev_attr_fan1_max.dev_attr.attr,
3224         &sensor_dev_attr_fan1_target.dev_attr.attr,
3225         &sensor_dev_attr_fan1_enable.dev_attr.attr,
3226         &sensor_dev_attr_in0_input.dev_attr.attr,
3227         &sensor_dev_attr_in0_label.dev_attr.attr,
3228         &sensor_dev_attr_in1_input.dev_attr.attr,
3229         &sensor_dev_attr_in1_label.dev_attr.attr,
3230         &sensor_dev_attr_power1_average.dev_attr.attr,
3231         &sensor_dev_attr_power1_cap_max.dev_attr.attr,
3232         &sensor_dev_attr_power1_cap_min.dev_attr.attr,
3233         &sensor_dev_attr_power1_cap.dev_attr.attr,
3234         &sensor_dev_attr_freq1_input.dev_attr.attr,
3235         &sensor_dev_attr_freq1_label.dev_attr.attr,
3236         &sensor_dev_attr_freq2_input.dev_attr.attr,
3237         &sensor_dev_attr_freq2_label.dev_attr.attr,
3238         NULL
3239 };
3240
3241 static umode_t hwmon_attributes_visible(struct kobject *kobj,
3242                                         struct attribute *attr, int index)
3243 {
3244         struct device *dev = kobj_to_dev(kobj);
3245         struct amdgpu_device *adev = dev_get_drvdata(dev);
3246         umode_t effective_mode = attr->mode;
3247
3248         /* under multi-vf mode, the hwmon attributes are all not supported */
3249         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev))
3250                 return 0;
3251
3252         /* there is no fan under pp one vf mode */
3253         if (amdgpu_sriov_is_pp_one_vf(adev) &&
3254             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3255              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3256              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3257              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3258              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3259              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3260              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3261              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3262              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3263                 return 0;
3264
3265         /* Skip fan attributes if fan is not present */
3266         if (adev->pm.no_fan && (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3267             attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3268             attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3269             attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3270             attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3271             attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3272             attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3273             attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3274             attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3275                 return 0;
3276
3277         /* Skip fan attributes on APU */
3278         if ((adev->flags & AMD_IS_APU) &&
3279             (attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3280              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3281              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3282              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3283              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3284              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3285              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3286              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3287              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3288                 return 0;
3289
3290         /* Skip crit temp on APU */
3291         if ((adev->flags & AMD_IS_APU) && (adev->family >= AMDGPU_FAMILY_CZ) &&
3292             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3293              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr))
3294                 return 0;
3295
3296         /* Skip limit attributes if DPM is not enabled */
3297         if (!adev->pm.dpm_enabled &&
3298             (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr ||
3299              attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr ||
3300              attr == &sensor_dev_attr_pwm1.dev_attr.attr ||
3301              attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr ||
3302              attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3303              attr == &sensor_dev_attr_pwm1_min.dev_attr.attr ||
3304              attr == &sensor_dev_attr_fan1_input.dev_attr.attr ||
3305              attr == &sensor_dev_attr_fan1_min.dev_attr.attr ||
3306              attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3307              attr == &sensor_dev_attr_fan1_target.dev_attr.attr ||
3308              attr == &sensor_dev_attr_fan1_enable.dev_attr.attr))
3309                 return 0;
3310
3311         if (!is_support_sw_smu(adev)) {
3312                 /* mask fan attributes if we have no bindings for this asic to expose */
3313                 if ((!adev->powerplay.pp_funcs->get_fan_speed_percent &&
3314                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't query fan */
3315                     (!adev->powerplay.pp_funcs->get_fan_control_mode &&
3316                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't query state */
3317                         effective_mode &= ~S_IRUGO;
3318
3319                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
3320                      attr == &sensor_dev_attr_pwm1.dev_attr.attr) || /* can't manage fan */
3321                     (!adev->powerplay.pp_funcs->set_fan_control_mode &&
3322                      attr == &sensor_dev_attr_pwm1_enable.dev_attr.attr)) /* can't manage state */
3323                         effective_mode &= ~S_IWUSR;
3324         }
3325
3326         if (((adev->flags & AMD_IS_APU) ||
3327              adev->family == AMDGPU_FAMILY_SI) &&       /* not implemented yet */
3328             (attr == &sensor_dev_attr_power1_cap_max.dev_attr.attr ||
3329              attr == &sensor_dev_attr_power1_cap_min.dev_attr.attr||
3330              attr == &sensor_dev_attr_power1_cap.dev_attr.attr))
3331                 return 0;
3332
3333         if (((adev->family == AMDGPU_FAMILY_SI) ||
3334              ((adev->flags & AMD_IS_APU) &&
3335               (adev->asic_type < CHIP_RENOIR))) &&      /* not implemented yet */
3336             (attr == &sensor_dev_attr_power1_average.dev_attr.attr))
3337                 return 0;
3338
3339         if (!is_support_sw_smu(adev)) {
3340                 /* hide max/min values if we can't both query and manage the fan */
3341                 if ((!adev->powerplay.pp_funcs->set_fan_speed_percent &&
3342                      !adev->powerplay.pp_funcs->get_fan_speed_percent) &&
3343                      (!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
3344                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
3345                     (attr == &sensor_dev_attr_pwm1_max.dev_attr.attr ||
3346                      attr == &sensor_dev_attr_pwm1_min.dev_attr.attr))
3347                         return 0;
3348
3349                 if ((!adev->powerplay.pp_funcs->set_fan_speed_rpm &&
3350                      !adev->powerplay.pp_funcs->get_fan_speed_rpm) &&
3351                     (attr == &sensor_dev_attr_fan1_max.dev_attr.attr ||
3352                      attr == &sensor_dev_attr_fan1_min.dev_attr.attr))
3353                         return 0;
3354         }
3355
3356         if ((adev->family == AMDGPU_FAMILY_SI ||        /* not implemented yet */
3357              adev->family == AMDGPU_FAMILY_KV) &&       /* not implemented yet */
3358             (attr == &sensor_dev_attr_in0_input.dev_attr.attr ||
3359              attr == &sensor_dev_attr_in0_label.dev_attr.attr))
3360                 return 0;
3361
3362         /* only APUs have vddnb */
3363         if (!(adev->flags & AMD_IS_APU) &&
3364             (attr == &sensor_dev_attr_in1_input.dev_attr.attr ||
3365              attr == &sensor_dev_attr_in1_label.dev_attr.attr))
3366                 return 0;
3367
3368         /* no mclk on APUs */
3369         if ((adev->flags & AMD_IS_APU) &&
3370             (attr == &sensor_dev_attr_freq2_input.dev_attr.attr ||
3371              attr == &sensor_dev_attr_freq2_label.dev_attr.attr))
3372                 return 0;
3373
3374         /* only SOC15 dGPUs support hotspot and mem temperatures */
3375         if (((adev->flags & AMD_IS_APU) ||
3376              adev->asic_type < CHIP_VEGA10) &&
3377             (attr == &sensor_dev_attr_temp2_crit.dev_attr.attr ||
3378              attr == &sensor_dev_attr_temp2_crit_hyst.dev_attr.attr ||
3379              attr == &sensor_dev_attr_temp3_crit.dev_attr.attr ||
3380              attr == &sensor_dev_attr_temp3_crit_hyst.dev_attr.attr ||
3381              attr == &sensor_dev_attr_temp1_emergency.dev_attr.attr ||
3382              attr == &sensor_dev_attr_temp2_emergency.dev_attr.attr ||
3383              attr == &sensor_dev_attr_temp3_emergency.dev_attr.attr ||
3384              attr == &sensor_dev_attr_temp2_input.dev_attr.attr ||
3385              attr == &sensor_dev_attr_temp3_input.dev_attr.attr ||
3386              attr == &sensor_dev_attr_temp2_label.dev_attr.attr ||
3387              attr == &sensor_dev_attr_temp3_label.dev_attr.attr))
3388                 return 0;
3389
3390         return effective_mode;
3391 }
3392
3393 static const struct attribute_group hwmon_attrgroup = {
3394         .attrs = hwmon_attributes,
3395         .is_visible = hwmon_attributes_visible,
3396 };
3397
3398 static const struct attribute_group *hwmon_groups[] = {
3399         &hwmon_attrgroup,
3400         NULL
3401 };
3402
3403 int amdgpu_pm_sysfs_init(struct amdgpu_device *adev)
3404 {
3405         int ret;
3406         uint32_t mask = 0;
3407
3408         if (adev->pm.sysfs_initialized)
3409                 return 0;
3410
3411         if (adev->pm.dpm_enabled == 0)
3412                 return 0;
3413
3414         INIT_LIST_HEAD(&adev->pm.pm_attr_list);
3415
3416         adev->pm.int_hwmon_dev = hwmon_device_register_with_groups(adev->dev,
3417                                                                    DRIVER_NAME, adev,
3418                                                                    hwmon_groups);
3419         if (IS_ERR(adev->pm.int_hwmon_dev)) {
3420                 ret = PTR_ERR(adev->pm.int_hwmon_dev);
3421                 dev_err(adev->dev,
3422                         "Unable to register hwmon device: %d\n", ret);
3423                 return ret;
3424         }
3425
3426         switch (amdgpu_virt_get_sriov_vf_mode(adev)) {
3427         case SRIOV_VF_MODE_ONE_VF:
3428                 mask = ATTR_FLAG_ONEVF;
3429                 break;
3430         case SRIOV_VF_MODE_MULTI_VF:
3431                 mask = 0;
3432                 break;
3433         case SRIOV_VF_MODE_BARE_METAL:
3434         default:
3435                 mask = ATTR_FLAG_MASK_ALL;
3436                 break;
3437         }
3438
3439         ret = amdgpu_device_attr_create_groups(adev,
3440                                                amdgpu_device_attrs,
3441                                                ARRAY_SIZE(amdgpu_device_attrs),
3442                                                mask,
3443                                                &adev->pm.pm_attr_list);
3444         if (ret)
3445                 return ret;
3446
3447         adev->pm.sysfs_initialized = true;
3448
3449         return 0;
3450 }
3451
3452 void amdgpu_pm_sysfs_fini(struct amdgpu_device *adev)
3453 {
3454         if (adev->pm.dpm_enabled == 0)
3455                 return;
3456
3457         if (adev->pm.int_hwmon_dev)
3458                 hwmon_device_unregister(adev->pm.int_hwmon_dev);
3459
3460         amdgpu_device_attr_remove_groups(adev, &adev->pm.pm_attr_list);
3461 }
3462
3463 /*
3464  * Debugfs info
3465  */
3466 #if defined(CONFIG_DEBUG_FS)
3467
3468 static int amdgpu_debugfs_pm_info_pp(struct seq_file *m, struct amdgpu_device *adev)
3469 {
3470         uint32_t value;
3471         uint64_t value64 = 0;
3472         uint32_t query = 0;
3473         int size;
3474
3475         /* GPU Clocks */
3476         size = sizeof(value);
3477         seq_printf(m, "GFX Clocks and Power:\n");
3478         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_MCLK, (void *)&value, &size))
3479                 seq_printf(m, "\t%u MHz (MCLK)\n", value/100);
3480         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GFX_SCLK, (void *)&value, &size))
3481                 seq_printf(m, "\t%u MHz (SCLK)\n", value/100);
3482         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK, (void *)&value, &size))
3483                 seq_printf(m, "\t%u MHz (PSTATE_SCLK)\n", value/100);
3484         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK, (void *)&value, &size))
3485                 seq_printf(m, "\t%u MHz (PSTATE_MCLK)\n", value/100);
3486         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDGFX, (void *)&value, &size))
3487                 seq_printf(m, "\t%u mV (VDDGFX)\n", value);
3488         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VDDNB, (void *)&value, &size))
3489                 seq_printf(m, "\t%u mV (VDDNB)\n", value);
3490         size = sizeof(uint32_t);
3491         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_POWER, (void *)&query, &size))
3492                 seq_printf(m, "\t%u.%u W (average GPU)\n", query >> 8, query & 0xff);
3493         size = sizeof(value);
3494         seq_printf(m, "\n");
3495
3496         /* GPU Temp */
3497         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_TEMP, (void *)&value, &size))
3498                 seq_printf(m, "GPU Temperature: %u C\n", value/1000);
3499
3500         /* GPU Load */
3501         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_GPU_LOAD, (void *)&value, &size))
3502                 seq_printf(m, "GPU Load: %u %%\n", value);
3503         /* MEM Load */
3504         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_MEM_LOAD, (void *)&value, &size))
3505                 seq_printf(m, "MEM Load: %u %%\n", value);
3506
3507         seq_printf(m, "\n");
3508
3509         /* SMC feature mask */
3510         if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK, (void *)&value64, &size))
3511                 seq_printf(m, "SMC Feature Mask: 0x%016llx\n", value64);
3512
3513         if (adev->asic_type > CHIP_VEGA20) {
3514                 /* VCN clocks */
3515                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCN_POWER_STATE, (void *)&value, &size)) {
3516                         if (!value) {
3517                                 seq_printf(m, "VCN: Disabled\n");
3518                         } else {
3519                                 seq_printf(m, "VCN: Enabled\n");
3520                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3521                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3522                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3523                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3524                         }
3525                 }
3526                 seq_printf(m, "\n");
3527         } else {
3528                 /* UVD clocks */
3529                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_POWER, (void *)&value, &size)) {
3530                         if (!value) {
3531                                 seq_printf(m, "UVD: Disabled\n");
3532                         } else {
3533                                 seq_printf(m, "UVD: Enabled\n");
3534                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_DCLK, (void *)&value, &size))
3535                                         seq_printf(m, "\t%u MHz (DCLK)\n", value/100);
3536                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_UVD_VCLK, (void *)&value, &size))
3537                                         seq_printf(m, "\t%u MHz (VCLK)\n", value/100);
3538                         }
3539                 }
3540                 seq_printf(m, "\n");
3541
3542                 /* VCE clocks */
3543                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_POWER, (void *)&value, &size)) {
3544                         if (!value) {
3545                                 seq_printf(m, "VCE: Disabled\n");
3546                         } else {
3547                                 seq_printf(m, "VCE: Enabled\n");
3548                                 if (!amdgpu_dpm_read_sensor(adev, AMDGPU_PP_SENSOR_VCE_ECCLK, (void *)&value, &size))
3549                                         seq_printf(m, "\t%u MHz (ECCLK)\n", value/100);
3550                         }
3551                 }
3552         }
3553
3554         return 0;
3555 }
3556
3557 static void amdgpu_parse_cg_state(struct seq_file *m, u32 flags)
3558 {
3559         int i;
3560
3561         for (i = 0; clocks[i].flag; i++)
3562                 seq_printf(m, "\t%s: %s\n", clocks[i].name,
3563                            (flags & clocks[i].flag) ? "On" : "Off");
3564 }
3565
3566 static int amdgpu_debugfs_pm_info(struct seq_file *m, void *data)
3567 {
3568         struct drm_info_node *node = (struct drm_info_node *) m->private;
3569         struct drm_device *dev = node->minor->dev;
3570         struct amdgpu_device *adev = drm_to_adev(dev);
3571         u32 flags = 0;
3572         int r;
3573
3574         if (amdgpu_in_reset(adev))
3575                 return -EPERM;
3576
3577         r = pm_runtime_get_sync(dev->dev);
3578         if (r < 0) {
3579                 pm_runtime_put_autosuspend(dev->dev);
3580                 return r;
3581         }
3582
3583         if (!adev->pm.dpm_enabled) {
3584                 seq_printf(m, "dpm not enabled\n");
3585                 pm_runtime_mark_last_busy(dev->dev);
3586                 pm_runtime_put_autosuspend(dev->dev);
3587                 return 0;
3588         }
3589
3590         if (!is_support_sw_smu(adev) &&
3591             adev->powerplay.pp_funcs->debugfs_print_current_performance_level) {
3592                 mutex_lock(&adev->pm.mutex);
3593                 if (adev->powerplay.pp_funcs->debugfs_print_current_performance_level)
3594                         adev->powerplay.pp_funcs->debugfs_print_current_performance_level(adev, m);
3595                 else
3596                         seq_printf(m, "Debugfs support not implemented for this asic\n");
3597                 mutex_unlock(&adev->pm.mutex);
3598                 r = 0;
3599         } else {
3600                 r = amdgpu_debugfs_pm_info_pp(m, adev);
3601         }
3602         if (r)
3603                 goto out;
3604
3605         amdgpu_device_ip_get_clockgating_state(adev, &flags);
3606
3607         seq_printf(m, "Clock Gating Flags Mask: 0x%x\n", flags);
3608         amdgpu_parse_cg_state(m, flags);
3609         seq_printf(m, "\n");
3610
3611 out:
3612         pm_runtime_mark_last_busy(dev->dev);
3613         pm_runtime_put_autosuspend(dev->dev);
3614
3615         return r;
3616 }
3617
3618 static const struct drm_info_list amdgpu_pm_info_list[] = {
3619         {"amdgpu_pm_info", amdgpu_debugfs_pm_info, 0, NULL},
3620 };
3621 #endif
3622
3623 int amdgpu_debugfs_pm_init(struct amdgpu_device *adev)
3624 {
3625 #if defined(CONFIG_DEBUG_FS)
3626         return amdgpu_debugfs_add_files(adev, amdgpu_pm_info_list, ARRAY_SIZE(amdgpu_pm_info_list));
3627 #else
3628         return 0;
3629 #endif
3630 }