drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include <linux/firmware.h>
  25
  26 #include "amdgpu.h"
  27 #include "amdgpu_vcn.h"
  28 #include "amdgpu_pm.h"
  29 #include "soc15.h"
  30 #include "soc15d.h"
  31 #include "soc15_common.h"
  32
  33 #include "vcn/vcn_1_0_offset.h"
  34 #include "vcn/vcn_1_0_sh_mask.h"
  35 #include "hdp/hdp_4_0_offset.h"
  36 #include "mmhub/mmhub_9_1_offset.h"
  37 #include "mmhub/mmhub_9_1_sh_mask.h"
  38
  39 #include "ivsrcid/vcn/irqsrcs_vcn_1_0.h"
  40 #include "jpeg_v1_0.h"
  41 #include "vcn_v1_0.h"
  42
  43 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0           0x05ab
  44 #define mmUVD_RBC_XX_IB_REG_CHECK_1_0_BASE_IDX  1
  45 #define mmUVD_REG_XX_MASK_1_0                   0x05ac
  46 #define mmUVD_REG_XX_MASK_1_0_BASE_IDX          1
  47
  48 static int vcn_v1_0_stop(struct amdgpu_device *adev);
  49 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev);
  50 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev);
  51 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev);
  52 static int vcn_v1_0_set_powergating_state(void *handle, enum amd_powergating_state state);
  53 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
  54                                 int inst_idx, struct dpg_pause_state *new_state);
  55
  56 static void vcn_v1_0_idle_work_handler(struct work_struct *work);
  57 static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring);
  58
  59 /**
  60  * vcn_v1_0_early_init - set function pointers
  61  *
  62  * @handle: amdgpu_device pointer
  63  *
  64  * Set ring and irq function pointers
  65  */
  66 static int vcn_v1_0_early_init(void *handle)
  67 {
  68         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  69
  70         adev->vcn.num_vcn_inst = 1;
  71         adev->vcn.num_enc_rings = 2;
  72
  73         vcn_v1_0_set_dec_ring_funcs(adev);
  74         vcn_v1_0_set_enc_ring_funcs(adev);
  75         vcn_v1_0_set_irq_funcs(adev);
  76
  77         jpeg_v1_0_early_init(handle);
  78
  79         return 0;
  80 }
  81
  82 /**
  83  * vcn_v1_0_sw_init - sw init for VCN block
  84  *
  85  * @handle: amdgpu_device pointer
  86  *
  87  * Load firmware and sw initialization
  88  */
  89 static int vcn_v1_0_sw_init(void *handle)
  90 {
  91         struct amdgpu_ring *ring;
  92         int i, r;
  93         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  94
  95         /* VCN DEC TRAP */
  96         r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN,
  97                         VCN_1_0__SRCID__UVD_SYSTEM_MESSAGE_INTERRUPT, &adev->vcn.inst->irq);
  98         if (r)
  99                 return r;
 100
 101         /* VCN ENC TRAP */
 102         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 103                 r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VCN_1_0__SRCID__UVD_ENC_GENERAL_PURPOSE,
 104                                         &adev->vcn.inst->irq);
 105                 if (r)
 106                         return r;
 107         }
 108
 109         r = amdgpu_vcn_sw_init(adev);
 110         if (r)
 111                 return r;
 112
 113         /* Override the work func */
 114         adev->vcn.idle_work.work.func = vcn_v1_0_idle_work_handler;
 115
 116         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 117                 const struct common_firmware_header *hdr;
 118                 hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
 119                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].ucode_id = AMDGPU_UCODE_ID_VCN;
 120                 adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].fw = adev->vcn.fw;
 121                 adev->firmware.fw_size +=
 122                         ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
 123                 DRM_INFO("PSP loading VCN firmware\n");
 124         }
 125
 126         r = amdgpu_vcn_resume(adev);
 127         if (r)
 128                 return r;
 129
 130         ring = &adev->vcn.inst->ring_dec;
 131         sprintf(ring->name, "vcn_dec");
 132         r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
 133                              AMDGPU_RING_PRIO_DEFAULT);
 134         if (r)
 135                 return r;
 136
 137         adev->vcn.internal.scratch9 = adev->vcn.inst->external.scratch9 =
 138                 SOC15_REG_OFFSET(UVD, 0, mmUVD_SCRATCH9);
 139         adev->vcn.internal.data0 = adev->vcn.inst->external.data0 =
 140                 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0);
 141         adev->vcn.internal.data1 = adev->vcn.inst->external.data1 =
 142                 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1);
 143         adev->vcn.internal.cmd = adev->vcn.inst->external.cmd =
 144                 SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD);
 145         adev->vcn.internal.nop = adev->vcn.inst->external.nop =
 146                 SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP);
 147
 148         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 149                 ring = &adev->vcn.inst->ring_enc[i];
 150                 sprintf(ring->name, "vcn_enc%d", i);
 151                 r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.inst->irq, 0,
 152                                      AMDGPU_RING_PRIO_DEFAULT);
 153                 if (r)
 154                         return r;
 155         }
 156
 157         adev->vcn.pause_dpg_mode = vcn_v1_0_pause_dpg_mode;
 158
 159         r = jpeg_v1_0_sw_init(handle);
 160
 161         return r;
 162 }
 163
 164 /**
 165  * vcn_v1_0_sw_fini - sw fini for VCN block
 166  *
 167  * @handle: amdgpu_device pointer
 168  *
 169  * VCN suspend and free up sw allocation
 170  */
 171 static int vcn_v1_0_sw_fini(void *handle)
 172 {
 173         int r;
 174         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 175
 176         r = amdgpu_vcn_suspend(adev);
 177         if (r)
 178                 return r;
 179
 180         jpeg_v1_0_sw_fini(handle);
 181
 182         r = amdgpu_vcn_sw_fini(adev);
 183
 184         return r;
 185 }
 186
 187 /**
 188  * vcn_v1_0_hw_init - start and test VCN block
 189  *
 190  * @handle: amdgpu_device pointer
 191  *
 192  * Initialize the hardware, boot up the VCPU and do some testing
 193  */
 194 static int vcn_v1_0_hw_init(void *handle)
 195 {
 196         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 197         struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
 198         int i, r;
 199
 200         r = amdgpu_ring_test_helper(ring);
 201         if (r)
 202                 goto done;
 203
 204         for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
 205                 ring = &adev->vcn.inst->ring_enc[i];
 206                 r = amdgpu_ring_test_helper(ring);
 207                 if (r)
 208                         goto done;
 209         }
 210
 211         ring = &adev->jpeg.inst->ring_dec;
 212         r = amdgpu_ring_test_helper(ring);
 213         if (r)
 214                 goto done;
 215
 216 done:
 217         if (!r)
 218                 DRM_INFO("VCN decode and encode initialized successfully(under %s).\n",
 219                         (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)?"DPG Mode":"SPG Mode");
 220
 221         return r;
 222 }
 223
 224 /**
 225  * vcn_v1_0_hw_fini - stop the hardware block
 226  *
 227  * @handle: amdgpu_device pointer
 228  *
 229  * Stop the VCN block, mark ring as not ready any more
 230  */
 231 static int vcn_v1_0_hw_fini(void *handle)
 232 {
 233         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 234
 235         if ((adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) ||
 236                 RREG32_SOC15(VCN, 0, mmUVD_STATUS))
 237                 vcn_v1_0_set_powergating_state(adev, AMD_PG_STATE_GATE);
 238
 239         return 0;
 240 }
 241
 242 /**
 243  * vcn_v1_0_suspend - suspend VCN block
 244  *
 245  * @handle: amdgpu_device pointer
 246  *
 247  * HW fini and suspend VCN block
 248  */
 249 static int vcn_v1_0_suspend(void *handle)
 250 {
 251         int r;
 252         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 253
 254         r = vcn_v1_0_hw_fini(adev);
 255         if (r)
 256                 return r;
 257
 258         r = amdgpu_vcn_suspend(adev);
 259
 260         return r;
 261 }
 262
 263 /**
 264  * vcn_v1_0_resume - resume VCN block
 265  *
 266  * @handle: amdgpu_device pointer
 267  *
 268  * Resume firmware and hw init VCN block
 269  */
 270 static int vcn_v1_0_resume(void *handle)
 271 {
 272         int r;
 273         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 274
 275         r = amdgpu_vcn_resume(adev);
 276         if (r)
 277                 return r;
 278
 279         r = vcn_v1_0_hw_init(adev);
 280
 281         return r;
 282 }
 283
 284 /**
 285  * vcn_v1_0_mc_resume_spg_mode - memory controller programming
 286  *
 287  * @adev: amdgpu_device pointer
 288  *
 289  * Let the VCN memory controller know it's offsets
 290  */
 291 static void vcn_v1_0_mc_resume_spg_mode(struct amdgpu_device *adev)
 292 {
 293         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
 294         uint32_t offset;
 295
 296         /* cache window 0: fw */
 297         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 298                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 299                              (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo));
 300                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 301                              (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi));
 302                 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0);
 303                 offset = 0;
 304         } else {
 305                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 306                         lower_32_bits(adev->vcn.inst->gpu_addr));
 307                 WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 308                         upper_32_bits(adev->vcn.inst->gpu_addr));
 309                 offset = size;
 310                 WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
 311                              AMDGPU_UVD_FIRMWARE_OFFSET >> 3);
 312         }
 313
 314         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size);
 315
 316         /* cache window 1: stack */
 317         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 318                      lower_32_bits(adev->vcn.inst->gpu_addr + offset));
 319         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 320                      upper_32_bits(adev->vcn.inst->gpu_addr + offset));
 321         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0);
 322         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE);
 323
 324         /* cache window 2: context */
 325         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 326                      lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 327         WREG32_SOC15(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 328                      upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE));
 329         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0);
 330         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE);
 331
 332         WREG32_SOC15(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
 333                         adev->gfx.config.gb_addr_config);
 334         WREG32_SOC15(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
 335                         adev->gfx.config.gb_addr_config);
 336         WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
 337                         adev->gfx.config.gb_addr_config);
 338         WREG32_SOC15(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,
 339                         adev->gfx.config.gb_addr_config);
 340         WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,
 341                         adev->gfx.config.gb_addr_config);
 342         WREG32_SOC15(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,
 343                         adev->gfx.config.gb_addr_config);
 344         WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,
 345                         adev->gfx.config.gb_addr_config);
 346         WREG32_SOC15(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,
 347                         adev->gfx.config.gb_addr_config);
 348         WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,
 349                         adev->gfx.config.gb_addr_config);
 350         WREG32_SOC15(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,
 351                         adev->gfx.config.gb_addr_config);
 352         WREG32_SOC15(UVD, 0, mmUVD_JPEG_ADDR_CONFIG,
 353                         adev->gfx.config.gb_addr_config);
 354         WREG32_SOC15(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG,
 355                         adev->gfx.config.gb_addr_config);
 356 }
 357
 358 static void vcn_v1_0_mc_resume_dpg_mode(struct amdgpu_device *adev)
 359 {
 360         uint32_t size = AMDGPU_GPU_PAGE_ALIGN(adev->vcn.fw->size + 4);
 361         uint32_t offset;
 362
 363         /* cache window 0: fw */
 364         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
 365                 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 366                              (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_lo),
 367                              0xFFFFFFFF, 0);
 368                 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 369                              (adev->firmware.ucode[AMDGPU_UCODE_ID_VCN].tmr_mc_addr_hi),
 370                              0xFFFFFFFF, 0);
 371                 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0, 0,
 372                              0xFFFFFFFF, 0);
 373                 offset = 0;
 374         } else {
 375                 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_LOW,
 376                         lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);
 377                 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH,
 378                         upper_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0);
 379                 offset = size;
 380                 WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET0,
 381                              AMDGPU_UVD_FIRMWARE_OFFSET >> 3, 0xFFFFFFFF, 0);
 382         }
 383
 384         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE0, size, 0xFFFFFFFF, 0);
 385
 386         /* cache window 1: stack */
 387         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW,
 388                      lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);
 389         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH,
 390                      upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0);
 391         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET1, 0,
 392                              0xFFFFFFFF, 0);
 393         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE1, AMDGPU_VCN_STACK_SIZE,
 394                              0xFFFFFFFF, 0);
 395
 396         /* cache window 2: context */
 397         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW,
 398                      lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
 399                              0xFFFFFFFF, 0);
 400         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH,
 401                      upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE),
 402                              0xFFFFFFFF, 0);
 403         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_OFFSET2, 0, 0xFFFFFFFF, 0);
 404         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CACHE_SIZE2, AMDGPU_VCN_CONTEXT_SIZE,
 405                              0xFFFFFFFF, 0);
 406
 407         /* VCN global tiling registers */
 408         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_ADDR_CONFIG,
 409                         adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 410         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DB_ADDR_CONFIG,
 411                         adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 412         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_ADDR_CONFIG,
 413                         adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 414         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_UDEC_DBW_UV_ADDR_CONFIG,
 415                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 416         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_ADDR_CONFIG,
 417                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 418         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_CURR_UV_ADDR_CONFIG,
 419                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 420         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_ADDR_CONFIG,
 421                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 422         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_RECON1_UV_ADDR_CONFIG,
 423                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 424         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_ADDR_CONFIG,
 425                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 426         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MIF_REF_UV_ADDR_CONFIG,
 427                 adev->gfx.config.gb_addr_config, 0xFFFFFFFF, 0);
 428 }
 429
 430 /**
 431  * vcn_v1_0_disable_clock_gating - disable VCN clock gating
 432  *
 433  * @adev: amdgpu_device pointer
 434  *
 435  * Disable clock gating for VCN block
 436  */
 437 static void vcn_v1_0_disable_clock_gating(struct amdgpu_device *adev)
 438 {
 439         uint32_t data;
 440
 441         /* JPEG disable CGC */
 442         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
 443
 444         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 445                 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 446         else
 447                 data &= ~JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 448
 449         data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 450         data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 451         WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);
 452
 453         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
 454         data &= ~(JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
 455         WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);
 456
 457         /* UVD disable CGC */
 458         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 459         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 460                 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 461         else
 462                 data &= ~ UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK;
 463
 464         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 465         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 466         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 467
 468         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_GATE);
 469         data &= ~(UVD_CGC_GATE__SYS_MASK
 470                 | UVD_CGC_GATE__UDEC_MASK
 471                 | UVD_CGC_GATE__MPEG2_MASK
 472                 | UVD_CGC_GATE__REGS_MASK
 473                 | UVD_CGC_GATE__RBC_MASK
 474                 | UVD_CGC_GATE__LMI_MC_MASK
 475                 | UVD_CGC_GATE__LMI_UMC_MASK
 476                 | UVD_CGC_GATE__IDCT_MASK
 477                 | UVD_CGC_GATE__MPRD_MASK
 478                 | UVD_CGC_GATE__MPC_MASK
 479                 | UVD_CGC_GATE__LBSI_MASK
 480                 | UVD_CGC_GATE__LRBBM_MASK
 481                 | UVD_CGC_GATE__UDEC_RE_MASK
 482                 | UVD_CGC_GATE__UDEC_CM_MASK
 483                 | UVD_CGC_GATE__UDEC_IT_MASK
 484                 | UVD_CGC_GATE__UDEC_DB_MASK
 485                 | UVD_CGC_GATE__UDEC_MP_MASK
 486                 | UVD_CGC_GATE__WCB_MASK
 487                 | UVD_CGC_GATE__VCPU_MASK
 488                 | UVD_CGC_GATE__SCPU_MASK);
 489         WREG32_SOC15(VCN, 0, mmUVD_CGC_GATE, data);
 490
 491         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 492         data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 493                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 494                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 495                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 496                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 497                 | UVD_CGC_CTRL__SYS_MODE_MASK
 498                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 499                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 500                 | UVD_CGC_CTRL__REGS_MODE_MASK
 501                 | UVD_CGC_CTRL__RBC_MODE_MASK
 502                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 503                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 504                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 505                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 506                 | UVD_CGC_CTRL__MPC_MODE_MASK
 507                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 508                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 509                 | UVD_CGC_CTRL__WCB_MODE_MASK
 510                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 511                 | UVD_CGC_CTRL__SCPU_MODE_MASK);
 512         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 513
 514         /* turn on */
 515         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE);
 516         data |= (UVD_SUVD_CGC_GATE__SRE_MASK
 517                 | UVD_SUVD_CGC_GATE__SIT_MASK
 518                 | UVD_SUVD_CGC_GATE__SMP_MASK
 519                 | UVD_SUVD_CGC_GATE__SCM_MASK
 520                 | UVD_SUVD_CGC_GATE__SDB_MASK
 521                 | UVD_SUVD_CGC_GATE__SRE_H264_MASK
 522                 | UVD_SUVD_CGC_GATE__SRE_HEVC_MASK
 523                 | UVD_SUVD_CGC_GATE__SIT_H264_MASK
 524                 | UVD_SUVD_CGC_GATE__SIT_HEVC_MASK
 525                 | UVD_SUVD_CGC_GATE__SCM_H264_MASK
 526                 | UVD_SUVD_CGC_GATE__SCM_HEVC_MASK
 527                 | UVD_SUVD_CGC_GATE__SDB_H264_MASK
 528                 | UVD_SUVD_CGC_GATE__SDB_HEVC_MASK
 529                 | UVD_SUVD_CGC_GATE__SCLR_MASK
 530                 | UVD_SUVD_CGC_GATE__UVD_SC_MASK
 531                 | UVD_SUVD_CGC_GATE__ENT_MASK
 532                 | UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK
 533                 | UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK
 534                 | UVD_SUVD_CGC_GATE__SITE_MASK
 535                 | UVD_SUVD_CGC_GATE__SRE_VP9_MASK
 536                 | UVD_SUVD_CGC_GATE__SCM_VP9_MASK
 537                 | UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK
 538                 | UVD_SUVD_CGC_GATE__SDB_VP9_MASK
 539                 | UVD_SUVD_CGC_GATE__IME_HEVC_MASK);
 540         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_GATE, data);
 541
 542         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
 543         data &= ~(UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 544                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 545                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 546                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 547                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 548                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 549                 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 550                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 551                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 552                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 553         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
 554 }
 555
 556 /**
 557  * vcn_v1_0_enable_clock_gating - enable VCN clock gating
 558  *
 559  * @adev: amdgpu_device pointer
 560  *
 561  * Enable clock gating for VCN block
 562  */
 563 static void vcn_v1_0_enable_clock_gating(struct amdgpu_device *adev)
 564 {
 565         uint32_t data = 0;
 566
 567         /* enable JPEG CGC */
 568         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL);
 569         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 570                 data |= 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 571         else
 572                 data |= 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 573         data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 574         data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 575         WREG32_SOC15(VCN, 0, mmJPEG_CGC_CTRL, data);
 576
 577         data = RREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE);
 578         data |= (JPEG_CGC_GATE__JPEG_MASK | JPEG_CGC_GATE__JPEG2_MASK);
 579         WREG32_SOC15(VCN, 0, mmJPEG_CGC_GATE, data);
 580
 581         /* enable UVD CGC */
 582         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 583         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 584                 data |= 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 585         else
 586                 data |= 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 587         data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 588         data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 589         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 590
 591         data = RREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL);
 592         data |= (UVD_CGC_CTRL__UDEC_RE_MODE_MASK
 593                 | UVD_CGC_CTRL__UDEC_CM_MODE_MASK
 594                 | UVD_CGC_CTRL__UDEC_IT_MODE_MASK
 595                 | UVD_CGC_CTRL__UDEC_DB_MODE_MASK
 596                 | UVD_CGC_CTRL__UDEC_MP_MODE_MASK
 597                 | UVD_CGC_CTRL__SYS_MODE_MASK
 598                 | UVD_CGC_CTRL__UDEC_MODE_MASK
 599                 | UVD_CGC_CTRL__MPEG2_MODE_MASK
 600                 | UVD_CGC_CTRL__REGS_MODE_MASK
 601                 | UVD_CGC_CTRL__RBC_MODE_MASK
 602                 | UVD_CGC_CTRL__LMI_MC_MODE_MASK
 603                 | UVD_CGC_CTRL__LMI_UMC_MODE_MASK
 604                 | UVD_CGC_CTRL__IDCT_MODE_MASK
 605                 | UVD_CGC_CTRL__MPRD_MODE_MASK
 606                 | UVD_CGC_CTRL__MPC_MODE_MASK
 607                 | UVD_CGC_CTRL__LBSI_MODE_MASK
 608                 | UVD_CGC_CTRL__LRBBM_MODE_MASK
 609                 | UVD_CGC_CTRL__WCB_MODE_MASK
 610                 | UVD_CGC_CTRL__VCPU_MODE_MASK
 611                 | UVD_CGC_CTRL__SCPU_MODE_MASK);
 612         WREG32_SOC15(VCN, 0, mmUVD_CGC_CTRL, data);
 613
 614         data = RREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL);
 615         data |= (UVD_SUVD_CGC_CTRL__SRE_MODE_MASK
 616                 | UVD_SUVD_CGC_CTRL__SIT_MODE_MASK
 617                 | UVD_SUVD_CGC_CTRL__SMP_MODE_MASK
 618                 | UVD_SUVD_CGC_CTRL__SCM_MODE_MASK
 619                 | UVD_SUVD_CGC_CTRL__SDB_MODE_MASK
 620                 | UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK
 621                 | UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK
 622                 | UVD_SUVD_CGC_CTRL__ENT_MODE_MASK
 623                 | UVD_SUVD_CGC_CTRL__IME_MODE_MASK
 624                 | UVD_SUVD_CGC_CTRL__SITE_MODE_MASK);
 625         WREG32_SOC15(VCN, 0, mmUVD_SUVD_CGC_CTRL, data);
 626 }
 627
 628 static void vcn_v1_0_clock_gating_dpg_mode(struct amdgpu_device *adev, uint8_t sram_sel)
 629 {
 630         uint32_t reg_data = 0;
 631
 632         /* disable JPEG CGC */
 633         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 634                 reg_data = 1 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 635         else
 636                 reg_data = 0 << JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 637         reg_data |= 1 << JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 638         reg_data |= 4 << JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 639         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
 640
 641         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmJPEG_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
 642
 643         /* enable sw clock gating control */
 644         if (adev->cg_flags & AMD_CG_SUPPORT_VCN_MGCG)
 645                 reg_data = 1 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 646         else
 647                 reg_data = 0 << UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT;
 648         reg_data |= 1 << UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT;
 649         reg_data |= 4 << UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT;
 650         reg_data &= ~(UVD_CGC_CTRL__UDEC_RE_MODE_MASK |
 651                  UVD_CGC_CTRL__UDEC_CM_MODE_MASK |
 652                  UVD_CGC_CTRL__UDEC_IT_MODE_MASK |
 653                  UVD_CGC_CTRL__UDEC_DB_MODE_MASK |
 654                  UVD_CGC_CTRL__UDEC_MP_MODE_MASK |
 655                  UVD_CGC_CTRL__SYS_MODE_MASK |
 656                  UVD_CGC_CTRL__UDEC_MODE_MASK |
 657                  UVD_CGC_CTRL__MPEG2_MODE_MASK |
 658                  UVD_CGC_CTRL__REGS_MODE_MASK |
 659                  UVD_CGC_CTRL__RBC_MODE_MASK |
 660                  UVD_CGC_CTRL__LMI_MC_MODE_MASK |
 661                  UVD_CGC_CTRL__LMI_UMC_MODE_MASK |
 662                  UVD_CGC_CTRL__IDCT_MODE_MASK |
 663                  UVD_CGC_CTRL__MPRD_MODE_MASK |
 664                  UVD_CGC_CTRL__MPC_MODE_MASK |
 665                  UVD_CGC_CTRL__LBSI_MODE_MASK |
 666                  UVD_CGC_CTRL__LRBBM_MODE_MASK |
 667                  UVD_CGC_CTRL__WCB_MODE_MASK |
 668                  UVD_CGC_CTRL__VCPU_MODE_MASK |
 669                  UVD_CGC_CTRL__SCPU_MODE_MASK);
 670         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_CTRL, reg_data, 0xFFFFFFFF, sram_sel);
 671
 672         /* turn off clock gating */
 673         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_CGC_GATE, 0, 0xFFFFFFFF, sram_sel);
 674
 675         /* turn on SUVD clock gating */
 676         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_GATE, 1, 0xFFFFFFFF, sram_sel);
 677
 678         /* turn on sw mode in UVD_SUVD_CGC_CTRL */
 679         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SUVD_CGC_CTRL, 0, 0xFFFFFFFF, sram_sel);
 680 }
 681
 682 static void vcn_1_0_disable_static_power_gating(struct amdgpu_device *adev)
 683 {
 684         uint32_t data = 0;
 685
 686         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 687                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 688                         | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 689                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 690                         | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 691                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 692                         | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
 693                         | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
 694                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 695                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 696                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 697                         | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
 698
 699                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
 700                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, UVD_PGFSM_STATUS__UVDM_UVDU_PWR_ON, 0xFFFFFF);
 701         } else {
 702                 data = (1 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 703                         | 1 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 704                         | 1 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 705                         | 1 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 706                         | 1 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 707                         | 1 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
 708                         | 1 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
 709                         | 1 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 710                         | 1 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 711                         | 1 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 712                         | 1 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
 713                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
 714                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, 0,  0xFFFFFFFF);
 715         }
 716
 717         /* polling UVD_PGFSM_STATUS to confirm UVDM_PWR_STATUS , UVDU_PWR_STATUS are 0 (power on) */
 718
 719         data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
 720         data &= ~0x103;
 721         if (adev->pg_flags & AMD_PG_SUPPORT_VCN)
 722                 data |= UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON | UVD_POWER_STATUS__UVD_PG_EN_MASK;
 723
 724         WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
 725 }
 726
 727 static void vcn_1_0_enable_static_power_gating(struct amdgpu_device *adev)
 728 {
 729         uint32_t data = 0;
 730
 731         if (adev->pg_flags & AMD_PG_SUPPORT_VCN) {
 732                 /* Before power off, this indicator has to be turned on */
 733                 data = RREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS);
 734                 data &= ~UVD_POWER_STATUS__UVD_POWER_STATUS_MASK;
 735                 data |= UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF;
 736                 WREG32_SOC15(VCN, 0, mmUVD_POWER_STATUS, data);
 737
 738
 739                 data = (2 << UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT
 740                         | 2 << UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT
 741                         | 2 << UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT
 742                         | 2 << UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT
 743                         | 2 << UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT
 744                         | 2 << UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT
 745                         | 2 << UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT
 746                         | 2 << UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT
 747                         | 2 << UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT
 748                         | 2 << UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT
 749                         | 2 << UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT);
 750
 751                 WREG32_SOC15(VCN, 0, mmUVD_PGFSM_CONFIG, data);
 752
 753                 data = (2 << UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT
 754                         | 2 << UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT
 755                         | 2 << UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT
 756                         | 2 << UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT
 757                         | 2 << UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT
 758                         | 2 << UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT
 759                         | 2 << UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT
 760                         | 2 << UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT
 761                         | 2 << UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT
 762                         | 2 << UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT
 763                         | 2 << UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT);
 764                 SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_PGFSM_STATUS, data, 0xFFFFFFFF);
 765         }
 766 }
 767
 768 /**
 769  * vcn_v1_0_start - start VCN block
 770  *
 771  * @adev: amdgpu_device pointer
 772  *
 773  * Setup and start the VCN block
 774  */
 775 static int vcn_v1_0_start_spg_mode(struct amdgpu_device *adev)
 776 {
 777         struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
 778         uint32_t rb_bufsz, tmp;
 779         uint32_t lmi_swap_cntl;
 780         int i, j, r;
 781
 782         /* disable byte swapping */
 783         lmi_swap_cntl = 0;
 784
 785         vcn_1_0_disable_static_power_gating(adev);
 786
 787         tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) | UVD_STATUS__UVD_BUSY;
 788         WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
 789
 790         /* disable clock gating */
 791         vcn_v1_0_disable_clock_gating(adev);
 792
 793         /* disable interupt */
 794         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN), 0,
 795                         ~UVD_MASTINT_EN__VCPU_EN_MASK);
 796
 797         /* initialize VCN memory controller */
 798         tmp = RREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL);
 799         WREG32_SOC15(UVD, 0, mmUVD_LMI_CTRL, tmp                |
 800                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 801                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK                       |
 802                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK            |
 803                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK);
 804
 805 #ifdef __BIG_ENDIAN
 806         /* swap (8 in 32) RB and IB */
 807         lmi_swap_cntl = 0xa;
 808 #endif
 809         WREG32_SOC15(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl);
 810
 811         tmp = RREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL);
 812         tmp &= ~UVD_MPC_CNTL__REPLACEMENT_MODE_MASK;
 813         tmp |= 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT;
 814         WREG32_SOC15(UVD, 0, mmUVD_MPC_CNTL, tmp);
 815
 816         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXA0,
 817                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
 818                 (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
 819                 (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
 820                 (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)));
 821
 822         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUXB0,
 823                 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
 824                 (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
 825                 (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
 826                 (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)));
 827
 828         WREG32_SOC15(UVD, 0, mmUVD_MPC_SET_MUX,
 829                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
 830                 (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
 831                 (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)));
 832
 833         vcn_v1_0_mc_resume_spg_mode(adev);
 834
 835         WREG32_SOC15(UVD, 0, mmUVD_REG_XX_MASK_1_0, 0x10);
 836         WREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0,
 837                 RREG32_SOC15(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK_1_0) | 0x3);
 838
 839         /* enable VCPU clock */
 840         WREG32_SOC15(UVD, 0, mmUVD_VCPU_CNTL, UVD_VCPU_CNTL__CLK_EN_MASK);
 841
 842         /* boot up the VCPU */
 843         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
 844                         ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 845
 846         /* enable UMC */
 847         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_CTRL2), 0,
 848                         ~UVD_LMI_CTRL2__STALL_ARB_UMC_MASK);
 849
 850         tmp = RREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET);
 851         tmp &= ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK;
 852         tmp &= ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK;
 853         WREG32_SOC15(UVD, 0, mmUVD_SOFT_RESET, tmp);
 854
 855         for (i = 0; i < 10; ++i) {
 856                 uint32_t status;
 857
 858                 for (j = 0; j < 100; ++j) {
 859                         status = RREG32_SOC15(UVD, 0, mmUVD_STATUS);
 860                         if (status & UVD_STATUS__IDLE)
 861                                 break;
 862                         mdelay(10);
 863                 }
 864                 r = 0;
 865                 if (status & UVD_STATUS__IDLE)
 866                         break;
 867
 868                 DRM_ERROR("VCN decode not responding, trying to reset the VCPU!!!\n");
 869                 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
 870                                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
 871                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 872                 mdelay(10);
 873                 WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET), 0,
 874                                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
 875                 mdelay(10);
 876                 r = -1;
 877         }
 878
 879         if (r) {
 880                 DRM_ERROR("VCN decode not responding, giving up!!!\n");
 881                 return r;
 882         }
 883         /* enable master interrupt */
 884         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_MASTINT_EN),
 885                 UVD_MASTINT_EN__VCPU_EN_MASK, ~UVD_MASTINT_EN__VCPU_EN_MASK);
 886
 887         /* enable system interrupt for JRBC, TODO: move to set interrupt*/
 888         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SYS_INT_EN),
 889                 UVD_SYS_INT_EN__UVD_JRBC_EN_MASK,
 890                 ~UVD_SYS_INT_EN__UVD_JRBC_EN_MASK);
 891
 892         /* clear the busy bit of UVD_STATUS */
 893         tmp = RREG32_SOC15(UVD, 0, mmUVD_STATUS) & ~UVD_STATUS__UVD_BUSY;
 894         WREG32_SOC15(UVD, 0, mmUVD_STATUS, tmp);
 895
 896         /* force RBC into idle state */
 897         rb_bufsz = order_base_2(ring->ring_size);
 898         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
 899         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
 900         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
 901         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
 902         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
 903         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
 904
 905         /* set the write pointer delay */
 906         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
 907
 908         /* set the wb address */
 909         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
 910                         (upper_32_bits(ring->gpu_addr) >> 2));
 911
 912         /* program the RB_BASE for ring buffer */
 913         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
 914                         lower_32_bits(ring->gpu_addr));
 915         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
 916                         upper_32_bits(ring->gpu_addr));
 917
 918         /* Initialize the ring buffer's read and write pointers */
 919         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
 920
 921         WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
 922
 923         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
 924         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
 925                         lower_32_bits(ring->wptr));
 926
 927         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
 928                         ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
 929
 930         ring = &adev->vcn.inst->ring_enc[0];
 931         WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
 932         WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
 933         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
 934         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
 935         WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
 936
 937         ring = &adev->vcn.inst->ring_enc[1];
 938         WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
 939         WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
 940         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
 941         WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
 942         WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
 943
 944         jpeg_v1_0_start(adev, 0);
 945
 946         return 0;
 947 }
 948
 949 static int vcn_v1_0_start_dpg_mode(struct amdgpu_device *adev)
 950 {
 951         struct amdgpu_ring *ring = &adev->vcn.inst->ring_dec;
 952         uint32_t rb_bufsz, tmp;
 953         uint32_t lmi_swap_cntl;
 954
 955         /* disable byte swapping */
 956         lmi_swap_cntl = 0;
 957
 958         vcn_1_0_enable_static_power_gating(adev);
 959
 960         /* enable dynamic power gating mode */
 961         tmp = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
 962         tmp |= UVD_POWER_STATUS__UVD_PG_MODE_MASK;
 963         tmp |= UVD_POWER_STATUS__UVD_PG_EN_MASK;
 964         WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, tmp);
 965
 966         /* enable clock gating */
 967         vcn_v1_0_clock_gating_dpg_mode(adev, 0);
 968
 969         /* enable VCPU clock */
 970         tmp = (0xFF << UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT);
 971         tmp |= UVD_VCPU_CNTL__CLK_EN_MASK;
 972         tmp |= UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK;
 973         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_VCPU_CNTL, tmp, 0xFFFFFFFF, 0);
 974
 975         /* disable interupt */
 976         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN,
 977                         0, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
 978
 979         /* initialize VCN memory controller */
 980         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL,
 981                 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
 982                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
 983                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
 984                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
 985                 UVD_LMI_CTRL__REQ_MODE_MASK |
 986                 UVD_LMI_CTRL__CRC_RESET_MASK |
 987                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
 988                 0x00100000L, 0xFFFFFFFF, 0);
 989
 990 #ifdef __BIG_ENDIAN
 991         /* swap (8 in 32) RB and IB */
 992         lmi_swap_cntl = 0xa;
 993 #endif
 994         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_SWAP_CNTL, lmi_swap_cntl, 0xFFFFFFFF, 0);
 995
 996         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_CNTL,
 997                 0x2 << UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT, 0xFFFFFFFF, 0);
 998
 999         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXA0,
1000                 ((0x1 << UVD_MPC_SET_MUXA0__VARA_1__SHIFT) |
1001                  (0x2 << UVD_MPC_SET_MUXA0__VARA_2__SHIFT) |
1002                  (0x3 << UVD_MPC_SET_MUXA0__VARA_3__SHIFT) |
1003                  (0x4 << UVD_MPC_SET_MUXA0__VARA_4__SHIFT)), 0xFFFFFFFF, 0);
1004
1005         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUXB0,
1006                 ((0x1 << UVD_MPC_SET_MUXB0__VARB_1__SHIFT) |
1007                  (0x2 << UVD_MPC_SET_MUXB0__VARB_2__SHIFT) |
1008                  (0x3 << UVD_MPC_SET_MUXB0__VARB_3__SHIFT) |
1009                  (0x4 << UVD_MPC_SET_MUXB0__VARB_4__SHIFT)), 0xFFFFFFFF, 0);
1010
1011         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MPC_SET_MUX,
1012                 ((0x0 << UVD_MPC_SET_MUX__SET_0__SHIFT) |
1013                  (0x1 << UVD_MPC_SET_MUX__SET_1__SHIFT) |
1014                  (0x2 << UVD_MPC_SET_MUX__SET_2__SHIFT)), 0xFFFFFFFF, 0);
1015
1016         vcn_v1_0_mc_resume_dpg_mode(adev);
1017
1018         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_REG_XX_MASK, 0x10, 0xFFFFFFFF, 0);
1019         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_RBC_XX_IB_REG_CHECK, 0x3, 0xFFFFFFFF, 0);
1020
1021         /* boot up the VCPU */
1022         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SOFT_RESET, 0, 0xFFFFFFFF, 0);
1023
1024         /* enable UMC */
1025         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL2,
1026                 0x1F << UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT,
1027                 0xFFFFFFFF, 0);
1028
1029         /* enable master interrupt */
1030         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_MASTINT_EN,
1031                         UVD_MASTINT_EN__VCPU_EN_MASK, UVD_MASTINT_EN__VCPU_EN_MASK, 0);
1032
1033         vcn_v1_0_clock_gating_dpg_mode(adev, 1);
1034         /* setup mmUVD_LMI_CTRL */
1035         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_LMI_CTRL,
1036                 (8 << UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT) |
1037                 UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK |
1038                 UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK |
1039                 UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK |
1040                 UVD_LMI_CTRL__REQ_MODE_MASK |
1041                 UVD_LMI_CTRL__CRC_RESET_MASK |
1042                 UVD_LMI_CTRL__MASK_MC_URGENT_MASK |
1043                 0x00100000L, 0xFFFFFFFF, 1);
1044
1045         tmp = adev->gfx.config.gb_addr_config;
1046         /* setup VCN global tiling registers */
1047         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
1048         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_JPEG_UV_ADDR_CONFIG, tmp, 0xFFFFFFFF, 1);
1049
1050         /* enable System Interrupt for JRBC */
1051         WREG32_SOC15_DPG_MODE_1_0(UVD, 0, mmUVD_SYS_INT_EN,
1052                                                                         UVD_SYS_INT_EN__UVD_JRBC_EN_MASK, 0xFFFFFFFF, 1);
1053
1054         /* force RBC into idle state */
1055         rb_bufsz = order_base_2(ring->ring_size);
1056         tmp = REG_SET_FIELD(0, UVD_RBC_RB_CNTL, RB_BUFSZ, rb_bufsz);
1057         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_BLKSZ, 1);
1058         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_FETCH, 1);
1059         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_NO_UPDATE, 1);
1060         tmp = REG_SET_FIELD(tmp, UVD_RBC_RB_CNTL, RB_RPTR_WR_EN, 1);
1061         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_CNTL, tmp);
1062
1063         /* set the write pointer delay */
1064         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR_CNTL, 0);
1065
1066         /* set the wb address */
1067         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR_ADDR,
1068                                                                 (upper_32_bits(ring->gpu_addr) >> 2));
1069
1070         /* program the RB_BASE for ring buffer */
1071         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_LOW,
1072                                                                 lower_32_bits(ring->gpu_addr));
1073         WREG32_SOC15(UVD, 0, mmUVD_LMI_RBC_RB_64BIT_BAR_HIGH,
1074                                                                 upper_32_bits(ring->gpu_addr));
1075
1076         /* Initialize the ring buffer's read and write pointers */
1077         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR, 0);
1078
1079         WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2, 0);
1080
1081         ring->wptr = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1082         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1083                                                                 lower_32_bits(ring->wptr));
1084
1085         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_RB_CNTL), 0,
1086                         ~UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK);
1087
1088         jpeg_v1_0_start(adev, 1);
1089
1090         return 0;
1091 }
1092
1093 static int vcn_v1_0_start(struct amdgpu_device *adev)
1094 {
1095         int r;
1096
1097         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1098                 r = vcn_v1_0_start_dpg_mode(adev);
1099         else
1100                 r = vcn_v1_0_start_spg_mode(adev);
1101         return r;
1102 }
1103
1104 /**
1105  * vcn_v1_0_stop - stop VCN block
1106  *
1107  * @adev: amdgpu_device pointer
1108  *
1109  * stop the VCN block
1110  */
1111 static int vcn_v1_0_stop_spg_mode(struct amdgpu_device *adev)
1112 {
1113         int tmp;
1114
1115         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_STATUS, UVD_STATUS__IDLE, 0x7);
1116
1117         tmp = UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK |
1118                 UVD_LMI_STATUS__READ_CLEAN_MASK |
1119                 UVD_LMI_STATUS__WRITE_CLEAN_MASK |
1120                 UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK;
1121         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp);
1122
1123         /* put VCPU into reset */
1124         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1125                 UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK,
1126                 ~UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK);
1127
1128         tmp = UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK |
1129                 UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK;
1130         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_LMI_STATUS, tmp, tmp);
1131
1132         /* disable VCPU clock */
1133         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_VCPU_CNTL), 0,
1134                 ~UVD_VCPU_CNTL__CLK_EN_MASK);
1135
1136         /* reset LMI UMC/LMI */
1137         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1138                 UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK,
1139                 ~UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK);
1140
1141         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_SOFT_RESET),
1142                 UVD_SOFT_RESET__LMI_SOFT_RESET_MASK,
1143                 ~UVD_SOFT_RESET__LMI_SOFT_RESET_MASK);
1144
1145         WREG32_SOC15(UVD, 0, mmUVD_STATUS, 0);
1146
1147         vcn_v1_0_enable_clock_gating(adev);
1148         vcn_1_0_enable_static_power_gating(adev);
1149         return 0;
1150 }
1151
1152 static int vcn_v1_0_stop_dpg_mode(struct amdgpu_device *adev)
1153 {
1154         uint32_t tmp;
1155
1156         /* Wait for power status to be UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF */
1157         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1158                         UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1159                         UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1160
1161         /* wait for read ptr to be equal to write ptr */
1162         tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1163         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR, tmp, 0xFFFFFFFF);
1164
1165         tmp = RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1166         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RB_RPTR2, tmp, 0xFFFFFFFF);
1167
1168         tmp = RREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR);
1169         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_JRBC_RB_RPTR, tmp, 0xFFFFFFFF);
1170
1171         tmp = RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR) & 0x7FFFFFFF;
1172         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_RBC_RB_RPTR, tmp, 0xFFFFFFFF);
1173
1174         SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1175                 UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1176                 UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1177
1178         /* disable dynamic power gating mode */
1179         WREG32_P(SOC15_REG_OFFSET(UVD, 0, mmUVD_POWER_STATUS), 0,
1180                         ~UVD_POWER_STATUS__UVD_PG_MODE_MASK);
1181
1182         return 0;
1183 }
1184
1185 static int vcn_v1_0_stop(struct amdgpu_device *adev)
1186 {
1187         int r;
1188
1189         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1190                 r = vcn_v1_0_stop_dpg_mode(adev);
1191         else
1192                 r = vcn_v1_0_stop_spg_mode(adev);
1193
1194         return r;
1195 }
1196
1197 static int vcn_v1_0_pause_dpg_mode(struct amdgpu_device *adev,
1198                                 int inst_idx, struct dpg_pause_state *new_state)
1199 {
1200         int ret_code;
1201         uint32_t reg_data = 0;
1202         uint32_t reg_data2 = 0;
1203         struct amdgpu_ring *ring;
1204
1205         /* pause/unpause if state is changed */
1206         if (adev->vcn.inst[inst_idx].pause_state.fw_based != new_state->fw_based) {
1207                 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",
1208                         adev->vcn.inst[inst_idx].pause_state.fw_based,
1209                         adev->vcn.inst[inst_idx].pause_state.jpeg,
1210                         new_state->fw_based, new_state->jpeg);
1211
1212                 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1213                         (~UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1214
1215                 if (new_state->fw_based == VCN_DPG_STATE__PAUSE) {
1216                         ret_code = 0;
1217
1218                         if (!(reg_data & UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK))
1219                                 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1220                                                    UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1221                                                    UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1222
1223                         if (!ret_code) {
1224                                 /* pause DPG non-jpeg */
1225                                 reg_data |= UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1226                                 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1227                                 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
1228                                                    UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK,
1229                                                    UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK);
1230
1231                                 /* Restore */
1232                                 ring = &adev->vcn.inst->ring_enc[0];
1233                                 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO, ring->gpu_addr);
1234                                 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
1235                                 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE, ring->ring_size / 4);
1236                                 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr));
1237                                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr));
1238
1239                                 ring = &adev->vcn.inst->ring_enc[1];
1240                                 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_LO2, ring->gpu_addr);
1241                                 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr));
1242                                 WREG32_SOC15(UVD, 0, mmUVD_RB_SIZE2, ring->ring_size / 4);
1243                                 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2, lower_32_bits(ring->wptr));
1244                                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2, lower_32_bits(ring->wptr));
1245
1246                                 ring = &adev->vcn.inst->ring_dec;
1247                                 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1248                                                    RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
1249                                 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1250                                                    UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
1251                                                    UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1252                         }
1253                 } else {
1254                         /* unpause dpg non-jpeg, no need to wait */
1255                         reg_data &= ~UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK;
1256                         WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1257                 }
1258                 adev->vcn.inst[inst_idx].pause_state.fw_based = new_state->fw_based;
1259         }
1260
1261         /* pause/unpause if state is changed */
1262         if (adev->vcn.inst[inst_idx].pause_state.jpeg != new_state->jpeg) {
1263                 DRM_DEBUG("dpg pause state changed %d:%d -> %d:%d",
1264                         adev->vcn.inst[inst_idx].pause_state.fw_based,
1265                         adev->vcn.inst[inst_idx].pause_state.jpeg,
1266                         new_state->fw_based, new_state->jpeg);
1267
1268                 reg_data = RREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE) &
1269                         (~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK);
1270
1271                 if (new_state->jpeg == VCN_DPG_STATE__PAUSE) {
1272                         ret_code = 0;
1273
1274                         if (!(reg_data & UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK))
1275                                 ret_code = SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1276                                                    UVD_POWER_STATUS__UVD_POWER_STATUS_TILES_OFF,
1277                                                    UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1278
1279                         if (!ret_code) {
1280                                 /* Make sure JPRG Snoop is disabled before sending the pause */
1281                                 reg_data2 = RREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS);
1282                                 reg_data2 |= UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK;
1283                                 WREG32_SOC15(UVD, 0, mmUVD_POWER_STATUS, reg_data2);
1284
1285                                 /* pause DPG jpeg */
1286                                 reg_data |= UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK;
1287                                 WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1288                                 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_DPG_PAUSE,
1289                                                         UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK,
1290                                                         UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK);
1291
1292                                 /* Restore */
1293                                 ring = &adev->jpeg.inst->ring_dec;
1294                                 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_VMID, 0);
1295                                 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
1296                                                         UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK |
1297                                                         UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
1298                                 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW,
1299                                                         lower_32_bits(ring->gpu_addr));
1300                                 WREG32_SOC15(UVD, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_HIGH,
1301                                                         upper_32_bits(ring->gpu_addr));
1302                                 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_RPTR, ring->wptr);
1303                                 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_WPTR, ring->wptr);
1304                                 WREG32_SOC15(UVD, 0, mmUVD_JRBC_RB_CNTL,
1305                                                         UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK);
1306
1307                                 ring = &adev->vcn.inst->ring_dec;
1308                                 WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR,
1309                                                    RREG32_SOC15(UVD, 0, mmUVD_SCRATCH2) & 0x7FFFFFFF);
1310                                 SOC15_WAIT_ON_RREG(UVD, 0, mmUVD_POWER_STATUS,
1311                                                    UVD_PGFSM_CONFIG__UVDM_UVDU_PWR_ON,
1312                                                    UVD_POWER_STATUS__UVD_POWER_STATUS_MASK);
1313                         }
1314                 } else {
1315                         /* unpause dpg jpeg, no need to wait */
1316                         reg_data &= ~UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK;
1317                         WREG32_SOC15(UVD, 0, mmUVD_DPG_PAUSE, reg_data);
1318                 }
1319                 adev->vcn.inst[inst_idx].pause_state.jpeg = new_state->jpeg;
1320         }
1321
1322         return 0;
1323 }
1324
1325 static bool vcn_v1_0_is_idle(void *handle)
1326 {
1327         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1328
1329         return (RREG32_SOC15(VCN, 0, mmUVD_STATUS) == UVD_STATUS__IDLE);
1330 }
1331
1332 static int vcn_v1_0_wait_for_idle(void *handle)
1333 {
1334         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1335         int ret;
1336
1337         ret = SOC15_WAIT_ON_RREG(VCN, 0, mmUVD_STATUS, UVD_STATUS__IDLE,
1338                 UVD_STATUS__IDLE);
1339
1340         return ret;
1341 }
1342
1343 static int vcn_v1_0_set_clockgating_state(void *handle,
1344                                           enum amd_clockgating_state state)
1345 {
1346         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1347         bool enable = (state == AMD_CG_STATE_GATE);
1348
1349         if (enable) {
1350                 /* wait for STATUS to clear */
1351                 if (!vcn_v1_0_is_idle(handle))
1352                         return -EBUSY;
1353                 vcn_v1_0_enable_clock_gating(adev);
1354         } else {
1355                 /* disable HW gating and enable Sw gating */
1356                 vcn_v1_0_disable_clock_gating(adev);
1357         }
1358         return 0;
1359 }
1360
1361 /**
1362  * vcn_v1_0_dec_ring_get_rptr - get read pointer
1363  *
1364  * @ring: amdgpu_ring pointer
1365  *
1366  * Returns the current hardware read pointer
1367  */
1368 static uint64_t vcn_v1_0_dec_ring_get_rptr(struct amdgpu_ring *ring)
1369 {
1370         struct amdgpu_device *adev = ring->adev;
1371
1372         return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_RPTR);
1373 }
1374
1375 /**
1376  * vcn_v1_0_dec_ring_get_wptr - get write pointer
1377  *
1378  * @ring: amdgpu_ring pointer
1379  *
1380  * Returns the current hardware write pointer
1381  */
1382 static uint64_t vcn_v1_0_dec_ring_get_wptr(struct amdgpu_ring *ring)
1383 {
1384         struct amdgpu_device *adev = ring->adev;
1385
1386         return RREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR);
1387 }
1388
1389 /**
1390  * vcn_v1_0_dec_ring_set_wptr - set write pointer
1391  *
1392  * @ring: amdgpu_ring pointer
1393  *
1394  * Commits the write pointer to the hardware
1395  */
1396 static void vcn_v1_0_dec_ring_set_wptr(struct amdgpu_ring *ring)
1397 {
1398         struct amdgpu_device *adev = ring->adev;
1399
1400         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG)
1401                 WREG32_SOC15(UVD, 0, mmUVD_SCRATCH2,
1402                         lower_32_bits(ring->wptr) | 0x80000000);
1403
1404         WREG32_SOC15(UVD, 0, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr));
1405 }
1406
1407 /**
1408  * vcn_v1_0_dec_ring_insert_start - insert a start command
1409  *
1410  * @ring: amdgpu_ring pointer
1411  *
1412  * Write a start command to the ring.
1413  */
1414 static void vcn_v1_0_dec_ring_insert_start(struct amdgpu_ring *ring)
1415 {
1416         struct amdgpu_device *adev = ring->adev;
1417
1418         amdgpu_ring_write(ring,
1419                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1420         amdgpu_ring_write(ring, 0);
1421         amdgpu_ring_write(ring,
1422                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1423         amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_START << 1);
1424 }
1425
1426 /**
1427  * vcn_v1_0_dec_ring_insert_end - insert a end command
1428  *
1429  * @ring: amdgpu_ring pointer
1430  *
1431  * Write a end command to the ring.
1432  */
1433 static void vcn_v1_0_dec_ring_insert_end(struct amdgpu_ring *ring)
1434 {
1435         struct amdgpu_device *adev = ring->adev;
1436
1437         amdgpu_ring_write(ring,
1438                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1439         amdgpu_ring_write(ring, VCN_DEC_CMD_PACKET_END << 1);
1440 }
1441
1442 /**
1443  * vcn_v1_0_dec_ring_emit_fence - emit an fence & trap command
1444  *
1445  * @ring: amdgpu_ring pointer
1446  * @addr: address
1447  * @seq: sequence number
1448  * @flags: fence related flags
1449  *
1450  * Write a fence and a trap command to the ring.
1451  */
1452 static void vcn_v1_0_dec_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
1453                                      unsigned flags)
1454 {
1455         struct amdgpu_device *adev = ring->adev;
1456
1457         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1458
1459         amdgpu_ring_write(ring,
1460                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_CONTEXT_ID), 0));
1461         amdgpu_ring_write(ring, seq);
1462         amdgpu_ring_write(ring,
1463                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1464         amdgpu_ring_write(ring, addr & 0xffffffff);
1465         amdgpu_ring_write(ring,
1466                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1467         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xff);
1468         amdgpu_ring_write(ring,
1469                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1470         amdgpu_ring_write(ring, VCN_DEC_CMD_FENCE << 1);
1471
1472         amdgpu_ring_write(ring,
1473                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1474         amdgpu_ring_write(ring, 0);
1475         amdgpu_ring_write(ring,
1476                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1477         amdgpu_ring_write(ring, 0);
1478         amdgpu_ring_write(ring,
1479                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1480         amdgpu_ring_write(ring, VCN_DEC_CMD_TRAP << 1);
1481 }
1482
1483 /**
1484  * vcn_v1_0_dec_ring_emit_ib - execute indirect buffer
1485  *
1486  * @ring: amdgpu_ring pointer
1487  * @job: job to retrieve vmid from
1488  * @ib: indirect buffer to execute
1489  * @flags: unused
1490  *
1491  * Write ring commands to execute the indirect buffer
1492  */
1493 static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
1494                                         struct amdgpu_job *job,
1495                                         struct amdgpu_ib *ib,
1496                                         uint32_t flags)
1497 {
1498         struct amdgpu_device *adev = ring->adev;
1499         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1500
1501         amdgpu_ring_write(ring,
1502                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
1503         amdgpu_ring_write(ring, vmid);
1504
1505         amdgpu_ring_write(ring,
1506                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
1507         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1508         amdgpu_ring_write(ring,
1509                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_HIGH), 0));
1510         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1511         amdgpu_ring_write(ring,
1512                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_RBC_IB_SIZE), 0));
1513         amdgpu_ring_write(ring, ib->length_dw);
1514 }
1515
1516 static void vcn_v1_0_dec_ring_emit_reg_wait(struct amdgpu_ring *ring,
1517                                             uint32_t reg, uint32_t val,
1518                                             uint32_t mask)
1519 {
1520         struct amdgpu_device *adev = ring->adev;
1521
1522         amdgpu_ring_write(ring,
1523                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1524         amdgpu_ring_write(ring, reg << 2);
1525         amdgpu_ring_write(ring,
1526                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1527         amdgpu_ring_write(ring, val);
1528         amdgpu_ring_write(ring,
1529                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GP_SCRATCH8), 0));
1530         amdgpu_ring_write(ring, mask);
1531         amdgpu_ring_write(ring,
1532                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1533         amdgpu_ring_write(ring, VCN_DEC_CMD_REG_READ_COND_WAIT << 1);
1534 }
1535
1536 static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
1537                                             unsigned vmid, uint64_t pd_addr)
1538 {
1539         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1540         uint32_t data0, data1, mask;
1541
1542         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1543
1544         /* wait for register write */
1545         data0 = hub->ctx0_ptb_addr_lo32 + vmid * hub->ctx_addr_distance;
1546         data1 = lower_32_bits(pd_addr);
1547         mask = 0xffffffff;
1548         vcn_v1_0_dec_ring_emit_reg_wait(ring, data0, data1, mask);
1549 }
1550
1551 static void vcn_v1_0_dec_ring_emit_wreg(struct amdgpu_ring *ring,
1552                                         uint32_t reg, uint32_t val)
1553 {
1554         struct amdgpu_device *adev = ring->adev;
1555
1556         amdgpu_ring_write(ring,
1557                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA0), 0));
1558         amdgpu_ring_write(ring, reg << 2);
1559         amdgpu_ring_write(ring,
1560                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_DATA1), 0));
1561         amdgpu_ring_write(ring, val);
1562         amdgpu_ring_write(ring,
1563                 PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_GPCOM_VCPU_CMD), 0));
1564         amdgpu_ring_write(ring, VCN_DEC_CMD_WRITE_REG << 1);
1565 }
1566
1567 /**
1568  * vcn_v1_0_enc_ring_get_rptr - get enc read pointer
1569  *
1570  * @ring: amdgpu_ring pointer
1571  *
1572  * Returns the current hardware enc read pointer
1573  */
1574 static uint64_t vcn_v1_0_enc_ring_get_rptr(struct amdgpu_ring *ring)
1575 {
1576         struct amdgpu_device *adev = ring->adev;
1577
1578         if (ring == &adev->vcn.inst->ring_enc[0])
1579                 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR);
1580         else
1581                 return RREG32_SOC15(UVD, 0, mmUVD_RB_RPTR2);
1582 }
1583
1584  /**
1585  * vcn_v1_0_enc_ring_get_wptr - get enc write pointer
1586  *
1587  * @ring: amdgpu_ring pointer
1588  *
1589  * Returns the current hardware enc write pointer
1590  */
1591 static uint64_t vcn_v1_0_enc_ring_get_wptr(struct amdgpu_ring *ring)
1592 {
1593         struct amdgpu_device *adev = ring->adev;
1594
1595         if (ring == &adev->vcn.inst->ring_enc[0])
1596                 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR);
1597         else
1598                 return RREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2);
1599 }
1600
1601  /**
1602  * vcn_v1_0_enc_ring_set_wptr - set enc write pointer
1603  *
1604  * @ring: amdgpu_ring pointer
1605  *
1606  * Commits the enc write pointer to the hardware
1607  */
1608 static void vcn_v1_0_enc_ring_set_wptr(struct amdgpu_ring *ring)
1609 {
1610         struct amdgpu_device *adev = ring->adev;
1611
1612         if (ring == &adev->vcn.inst->ring_enc[0])
1613                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR,
1614                         lower_32_bits(ring->wptr));
1615         else
1616                 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR2,
1617                         lower_32_bits(ring->wptr));
1618 }
1619
1620 /**
1621  * vcn_v1_0_enc_ring_emit_fence - emit an enc fence & trap command
1622  *
1623  * @ring: amdgpu_ring pointer
1624  * @addr: address
1625  * @seq: sequence number
1626  * @flags: fence related flags
1627  *
1628  * Write enc a fence and a trap command to the ring.
1629  */
1630 static void vcn_v1_0_enc_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
1631                         u64 seq, unsigned flags)
1632 {
1633         WARN_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
1634
1635         amdgpu_ring_write(ring, VCN_ENC_CMD_FENCE);
1636         amdgpu_ring_write(ring, addr);
1637         amdgpu_ring_write(ring, upper_32_bits(addr));
1638         amdgpu_ring_write(ring, seq);
1639         amdgpu_ring_write(ring, VCN_ENC_CMD_TRAP);
1640 }
1641
1642 static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring)
1643 {
1644         amdgpu_ring_write(ring, VCN_ENC_CMD_END);
1645 }
1646
1647 /**
1648  * vcn_v1_0_enc_ring_emit_ib - enc execute indirect buffer
1649  *
1650  * @ring: amdgpu_ring pointer
1651  * @job: job to retrive vmid from
1652  * @ib: indirect buffer to execute
1653  * @flags: unused
1654  *
1655  * Write enc ring commands to execute the indirect buffer
1656  */
1657 static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
1658                                         struct amdgpu_job *job,
1659                                         struct amdgpu_ib *ib,
1660                                         uint32_t flags)
1661 {
1662         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
1663
1664         amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
1665         amdgpu_ring_write(ring, vmid);
1666         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
1667         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
1668         amdgpu_ring_write(ring, ib->length_dw);
1669 }
1670
1671 static void vcn_v1_0_enc_ring_emit_reg_wait(struct amdgpu_ring *ring,
1672                                             uint32_t reg, uint32_t val,
1673                                             uint32_t mask)
1674 {
1675         amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
1676         amdgpu_ring_write(ring, reg << 2);
1677         amdgpu_ring_write(ring, mask);
1678         amdgpu_ring_write(ring, val);
1679 }
1680
1681 static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
1682                                             unsigned int vmid, uint64_t pd_addr)
1683 {
1684         struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
1685
1686         pd_addr = amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1687
1688         /* wait for reg writes */
1689         vcn_v1_0_enc_ring_emit_reg_wait(ring, hub->ctx0_ptb_addr_lo32 +
1690                                         vmid * hub->ctx_addr_distance,
1691                                         lower_32_bits(pd_addr), 0xffffffff);
1692 }
1693
1694 static void vcn_v1_0_enc_ring_emit_wreg(struct amdgpu_ring *ring,
1695                                         uint32_t reg, uint32_t val)
1696 {
1697         amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
1698         amdgpu_ring_write(ring, reg << 2);
1699         amdgpu_ring_write(ring, val);
1700 }
1701
1702 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,
1703                                         struct amdgpu_irq_src *source,
1704                                         unsigned type,
1705                                         enum amdgpu_interrupt_state state)
1706 {
1707         return 0;
1708 }
1709
1710 static int vcn_v1_0_process_interrupt(struct amdgpu_device *adev,
1711                                       struct amdgpu_irq_src *source,
1712                                       struct amdgpu_iv_entry *entry)
1713 {
1714         DRM_DEBUG("IH: VCN TRAP\n");
1715
1716         switch (entry->src_id) {
1717         case 124:
1718                 amdgpu_fence_process(&adev->vcn.inst->ring_dec);
1719                 break;
1720         case 119:
1721                 amdgpu_fence_process(&adev->vcn.inst->ring_enc[0]);
1722                 break;
1723         case 120:
1724                 amdgpu_fence_process(&adev->vcn.inst->ring_enc[1]);
1725                 break;
1726         default:
1727                 DRM_ERROR("Unhandled interrupt: %d %d\n",
1728                           entry->src_id, entry->src_data[0]);
1729                 break;
1730         }
1731
1732         return 0;
1733 }
1734
1735 static void vcn_v1_0_dec_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
1736 {
1737         struct amdgpu_device *adev = ring->adev;
1738         int i;
1739
1740         WARN_ON(ring->wptr % 2 || count % 2);
1741
1742         for (i = 0; i < count / 2; i++) {
1743                 amdgpu_ring_write(ring, PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_NO_OP), 0));
1744                 amdgpu_ring_write(ring, 0);
1745         }
1746 }
1747
1748 static int vcn_v1_0_set_powergating_state(void *handle,
1749                                           enum amd_powergating_state state)
1750 {
1751         /* This doesn't actually powergate the VCN block.
1752          * That's done in the dpm code via the SMC.  This
1753          * just re-inits the block as necessary.  The actual
1754          * gating still happens in the dpm code.  We should
1755          * revisit this when there is a cleaner line between
1756          * the smc and the hw blocks
1757          */
1758         int ret;
1759         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1760
1761         if(state == adev->vcn.cur_state)
1762                 return 0;
1763
1764         if (state == AMD_PG_STATE_GATE)
1765                 ret = vcn_v1_0_stop(adev);
1766         else
1767                 ret = vcn_v1_0_start(adev);
1768
1769         if(!ret)
1770                 adev->vcn.cur_state = state;
1771         return ret;
1772 }
1773
1774 static void vcn_v1_0_idle_work_handler(struct work_struct *work)
1775 {
1776         struct amdgpu_device *adev =
1777                 container_of(work, struct amdgpu_device, vcn.idle_work.work);
1778         unsigned int fences = 0, i;
1779
1780         for (i = 0; i < adev->vcn.num_enc_rings; ++i)
1781                 fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]);
1782
1783         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1784                 struct dpg_pause_state new_state;
1785
1786                 if (fences)
1787                         new_state.fw_based = VCN_DPG_STATE__PAUSE;
1788                 else
1789                         new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
1790
1791                 if (amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec))
1792                         new_state.jpeg = VCN_DPG_STATE__PAUSE;
1793                 else
1794                         new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
1795
1796                 adev->vcn.pause_dpg_mode(adev, 0, &new_state);
1797         }
1798
1799         fences += amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec);
1800         fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_dec);
1801
1802         if (fences == 0) {
1803                 amdgpu_gfx_off_ctrl(adev, true);
1804                 if (adev->pm.dpm_enabled)
1805                         amdgpu_dpm_enable_uvd(adev, false);
1806                 else
1807                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
1808                                AMD_PG_STATE_GATE);
1809         } else {
1810                 schedule_delayed_work(&adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
1811         }
1812 }
1813
1814 static void vcn_v1_0_ring_begin_use(struct amdgpu_ring *ring)
1815 {
1816         struct  amdgpu_device *adev = ring->adev;
1817         bool set_clocks = !cancel_delayed_work_sync(&adev->vcn.idle_work);
1818
1819         mutex_lock(&adev->vcn.vcn1_jpeg1_workaround);
1820
1821         if (amdgpu_fence_wait_empty(&ring->adev->jpeg.inst->ring_dec))
1822                 DRM_ERROR("VCN dec: jpeg dec ring may not be empty\n");
1823
1824         vcn_v1_0_set_pg_for_begin_use(ring, set_clocks);
1825
1826 }
1827
1828 void vcn_v1_0_set_pg_for_begin_use(struct amdgpu_ring *ring, bool set_clocks)
1829 {
1830         struct amdgpu_device *adev = ring->adev;
1831
1832         if (set_clocks) {
1833                 amdgpu_gfx_off_ctrl(adev, false);
1834                 if (adev->pm.dpm_enabled)
1835                         amdgpu_dpm_enable_uvd(adev, true);
1836                 else
1837                         amdgpu_device_ip_set_powergating_state(adev, AMD_IP_BLOCK_TYPE_VCN,
1838                                AMD_PG_STATE_UNGATE);
1839         }
1840
1841         if (adev->pg_flags & AMD_PG_SUPPORT_VCN_DPG) {
1842                 struct dpg_pause_state new_state;
1843                 unsigned int fences = 0, i;
1844
1845                 for (i = 0; i < adev->vcn.num_enc_rings; ++i)
1846                         fences += amdgpu_fence_count_emitted(&adev->vcn.inst->ring_enc[i]);
1847
1848                 if (fences)
1849                         new_state.fw_based = VCN_DPG_STATE__PAUSE;
1850                 else
1851                         new_state.fw_based = VCN_DPG_STATE__UNPAUSE;
1852
1853                 if (amdgpu_fence_count_emitted(&adev->jpeg.inst->ring_dec))
1854                         new_state.jpeg = VCN_DPG_STATE__PAUSE;
1855                 else
1856                         new_state.jpeg = VCN_DPG_STATE__UNPAUSE;
1857
1858                 if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_ENC)
1859                         new_state.fw_based = VCN_DPG_STATE__PAUSE;
1860                 else if (ring->funcs->type == AMDGPU_RING_TYPE_VCN_JPEG)
1861                         new_state.jpeg = VCN_DPG_STATE__PAUSE;
1862
1863                 adev->vcn.pause_dpg_mode(adev, 0, &new_state);
1864         }
1865 }
1866
1867 void vcn_v1_0_ring_end_use(struct amdgpu_ring *ring)
1868 {
1869         schedule_delayed_work(&ring->adev->vcn.idle_work, VCN_IDLE_TIMEOUT);
1870         mutex_unlock(&ring->adev->vcn.vcn1_jpeg1_workaround);
1871 }
1872
1873 static const struct amd_ip_funcs vcn_v1_0_ip_funcs = {
1874         .name = "vcn_v1_0",
1875         .early_init = vcn_v1_0_early_init,
1876         .late_init = NULL,
1877         .sw_init = vcn_v1_0_sw_init,
1878         .sw_fini = vcn_v1_0_sw_fini,
1879         .hw_init = vcn_v1_0_hw_init,
1880         .hw_fini = vcn_v1_0_hw_fini,
1881         .suspend = vcn_v1_0_suspend,
1882         .resume = vcn_v1_0_resume,
1883         .is_idle = vcn_v1_0_is_idle,
1884         .wait_for_idle = vcn_v1_0_wait_for_idle,
1885         .check_soft_reset = NULL /* vcn_v1_0_check_soft_reset */,
1886         .pre_soft_reset = NULL /* vcn_v1_0_pre_soft_reset */,
1887         .soft_reset = NULL /* vcn_v1_0_soft_reset */,
1888         .post_soft_reset = NULL /* vcn_v1_0_post_soft_reset */,
1889         .set_clockgating_state = vcn_v1_0_set_clockgating_state,
1890         .set_powergating_state = vcn_v1_0_set_powergating_state,
1891 };
1892
1893 static const struct amdgpu_ring_funcs vcn_v1_0_dec_ring_vm_funcs = {
1894         .type = AMDGPU_RING_TYPE_VCN_DEC,
1895         .align_mask = 0xf,
1896         .support_64bit_ptrs = false,
1897         .no_user_fence = true,
1898         .vmhub = AMDGPU_MMHUB_0,
1899         .get_rptr = vcn_v1_0_dec_ring_get_rptr,
1900         .get_wptr = vcn_v1_0_dec_ring_get_wptr,
1901         .set_wptr = vcn_v1_0_dec_ring_set_wptr,
1902         .emit_frame_size =
1903                 6 + 6 + /* hdp invalidate / flush */
1904                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 6 +
1905                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 8 +
1906                 8 + /* vcn_v1_0_dec_ring_emit_vm_flush */
1907                 14 + 14 + /* vcn_v1_0_dec_ring_emit_fence x2 vm fence */
1908                 6,
1909         .emit_ib_size = 8, /* vcn_v1_0_dec_ring_emit_ib */
1910         .emit_ib = vcn_v1_0_dec_ring_emit_ib,
1911         .emit_fence = vcn_v1_0_dec_ring_emit_fence,
1912         .emit_vm_flush = vcn_v1_0_dec_ring_emit_vm_flush,
1913         .test_ring = amdgpu_vcn_dec_ring_test_ring,
1914         .test_ib = amdgpu_vcn_dec_ring_test_ib,
1915         .insert_nop = vcn_v1_0_dec_ring_insert_nop,
1916         .insert_start = vcn_v1_0_dec_ring_insert_start,
1917         .insert_end = vcn_v1_0_dec_ring_insert_end,
1918         .pad_ib = amdgpu_ring_generic_pad_ib,
1919         .begin_use = vcn_v1_0_ring_begin_use,
1920         .end_use = vcn_v1_0_ring_end_use,
1921         .emit_wreg = vcn_v1_0_dec_ring_emit_wreg,
1922         .emit_reg_wait = vcn_v1_0_dec_ring_emit_reg_wait,
1923         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1924 };
1925
1926 static const struct amdgpu_ring_funcs vcn_v1_0_enc_ring_vm_funcs = {
1927         .type = AMDGPU_RING_TYPE_VCN_ENC,
1928         .align_mask = 0x3f,
1929         .nop = VCN_ENC_CMD_NO_OP,
1930         .support_64bit_ptrs = false,
1931         .no_user_fence = true,
1932         .vmhub = AMDGPU_MMHUB_0,
1933         .get_rptr = vcn_v1_0_enc_ring_get_rptr,
1934         .get_wptr = vcn_v1_0_enc_ring_get_wptr,
1935         .set_wptr = vcn_v1_0_enc_ring_set_wptr,
1936         .emit_frame_size =
1937                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 3 +
1938                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 4 +
1939                 4 + /* vcn_v1_0_enc_ring_emit_vm_flush */
1940                 5 + 5 + /* vcn_v1_0_enc_ring_emit_fence x2 vm fence */
1941                 1, /* vcn_v1_0_enc_ring_insert_end */
1942         .emit_ib_size = 5, /* vcn_v1_0_enc_ring_emit_ib */
1943         .emit_ib = vcn_v1_0_enc_ring_emit_ib,
1944         .emit_fence = vcn_v1_0_enc_ring_emit_fence,
1945         .emit_vm_flush = vcn_v1_0_enc_ring_emit_vm_flush,
1946         .test_ring = amdgpu_vcn_enc_ring_test_ring,
1947         .test_ib = amdgpu_vcn_enc_ring_test_ib,
1948         .insert_nop = amdgpu_ring_insert_nop,
1949         .insert_end = vcn_v1_0_enc_ring_insert_end,
1950         .pad_ib = amdgpu_ring_generic_pad_ib,
1951         .begin_use = vcn_v1_0_ring_begin_use,
1952         .end_use = vcn_v1_0_ring_end_use,
1953         .emit_wreg = vcn_v1_0_enc_ring_emit_wreg,
1954         .emit_reg_wait = vcn_v1_0_enc_ring_emit_reg_wait,
1955         .emit_reg_write_reg_wait = amdgpu_ring_emit_reg_write_reg_wait_helper,
1956 };
1957
1958 static void vcn_v1_0_set_dec_ring_funcs(struct amdgpu_device *adev)
1959 {
1960         adev->vcn.inst->ring_dec.funcs = &vcn_v1_0_dec_ring_vm_funcs;
1961         DRM_INFO("VCN decode is enabled in VM mode\n");
1962 }
1963
1964 static void vcn_v1_0_set_enc_ring_funcs(struct amdgpu_device *adev)
1965 {
1966         int i;
1967
1968         for (i = 0; i < adev->vcn.num_enc_rings; ++i)
1969                 adev->vcn.inst->ring_enc[i].funcs = &vcn_v1_0_enc_ring_vm_funcs;
1970
1971         DRM_INFO("VCN encode is enabled in VM mode\n");
1972 }
1973
1974 static const struct amdgpu_irq_src_funcs vcn_v1_0_irq_funcs = {
1975         .set = vcn_v1_0_set_interrupt_state,
1976         .process = vcn_v1_0_process_interrupt,
1977 };
1978
1979 static void vcn_v1_0_set_irq_funcs(struct amdgpu_device *adev)
1980 {
1981         adev->vcn.inst->irq.num_types = adev->vcn.num_enc_rings + 2;
1982         adev->vcn.inst->irq.funcs = &vcn_v1_0_irq_funcs;
1983 }
1984
1985 const struct amdgpu_ip_block_version vcn_v1_0_ip_block =
1986 {
1987                 .type = AMD_IP_BLOCK_TYPE_VCN,
1988                 .major = 1,
1989                 .minor = 0,
1990                 .rev = 0,
1991                 .funcs = &vcn_v1_0_ip_funcs,
1992 };