drivers/clk/clk-stm32f4.c

   1 /*
   2  * Author: Daniel Thompson <[email protected]>
   3  *
   4  * Inspired by clk-asm9260.c .
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  */
  18
  19 #include <linux/clk-provider.h>
  20 #include <linux/err.h>
  21 #include <linux/io.h>
  22 #include <linux/iopoll.h>
  23 #include <linux/ioport.h>
  24 #include <linux/slab.h>
  25 #include <linux/spinlock.h>
  26 #include <linux/of.h>
  27 #include <linux/of_address.h>
  28 #include <linux/regmap.h>
  29 #include <linux/mfd/syscon.h>
  30
  31 /*
  32  * Include list of clocks wich are not derived from system clock (SYSCLOCK)
  33  * The index of these clocks is the secondary index of DT bindings
  34  *
  35  */
  36 #include <dt-bindings/clock/stm32fx-clock.h>
  37
  38 #define STM32F4_RCC_CR                  0x00
  39 #define STM32F4_RCC_PLLCFGR             0x04
  40 #define STM32F4_RCC_CFGR                0x08
  41 #define STM32F4_RCC_AHB1ENR             0x30
  42 #define STM32F4_RCC_AHB2ENR             0x34
  43 #define STM32F4_RCC_AHB3ENR             0x38
  44 #define STM32F4_RCC_APB1ENR             0x40
  45 #define STM32F4_RCC_APB2ENR             0x44
  46 #define STM32F4_RCC_BDCR                0x70
  47 #define STM32F4_RCC_CSR                 0x74
  48 #define STM32F4_RCC_PLLI2SCFGR          0x84
  49 #define STM32F4_RCC_PLLSAICFGR          0x88
  50 #define STM32F4_RCC_DCKCFGR             0x8c
  51 #define STM32F7_RCC_DCKCFGR2            0x90
  52
  53 #define NONE -1
  54 #define NO_IDX  NONE
  55 #define NO_MUX  NONE
  56 #define NO_GATE NONE
  57
  58 struct stm32f4_gate_data {
  59         u8      offset;
  60         u8      bit_idx;
  61         const char *name;
  62         const char *parent_name;
  63         unsigned long flags;
  64 };
  65
  66 static const struct stm32f4_gate_data stm32f429_gates[] __initconst = {
  67         { STM32F4_RCC_AHB1ENR,  0,      "gpioa",        "ahb_div" },
  68         { STM32F4_RCC_AHB1ENR,  1,      "gpiob",        "ahb_div" },
  69         { STM32F4_RCC_AHB1ENR,  2,      "gpioc",        "ahb_div" },
  70         { STM32F4_RCC_AHB1ENR,  3,      "gpiod",        "ahb_div" },
  71         { STM32F4_RCC_AHB1ENR,  4,      "gpioe",        "ahb_div" },
  72         { STM32F4_RCC_AHB1ENR,  5,      "gpiof",        "ahb_div" },
  73         { STM32F4_RCC_AHB1ENR,  6,      "gpiog",        "ahb_div" },
  74         { STM32F4_RCC_AHB1ENR,  7,      "gpioh",        "ahb_div" },
  75         { STM32F4_RCC_AHB1ENR,  8,      "gpioi",        "ahb_div" },
  76         { STM32F4_RCC_AHB1ENR,  9,      "gpioj",        "ahb_div" },
  77         { STM32F4_RCC_AHB1ENR, 10,      "gpiok",        "ahb_div" },
  78         { STM32F4_RCC_AHB1ENR, 12,      "crc",          "ahb_div" },
  79         { STM32F4_RCC_AHB1ENR, 18,      "bkpsra",       "ahb_div" },
  80         { STM32F4_RCC_AHB1ENR, 20,      "ccmdatam",     "ahb_div" },
  81         { STM32F4_RCC_AHB1ENR, 21,      "dma1",         "ahb_div" },
  82         { STM32F4_RCC_AHB1ENR, 22,      "dma2",         "ahb_div" },
  83         { STM32F4_RCC_AHB1ENR, 23,      "dma2d",        "ahb_div" },
  84         { STM32F4_RCC_AHB1ENR, 25,      "ethmac",       "ahb_div" },
  85         { STM32F4_RCC_AHB1ENR, 26,      "ethmactx",     "ahb_div" },
  86         { STM32F4_RCC_AHB1ENR, 27,      "ethmacrx",     "ahb_div" },
  87         { STM32F4_RCC_AHB1ENR, 28,      "ethmacptp",    "ahb_div" },
  88         { STM32F4_RCC_AHB1ENR, 29,      "otghs",        "ahb_div" },
  89         { STM32F4_RCC_AHB1ENR, 30,      "otghsulpi",    "ahb_div" },
  90
  91         { STM32F4_RCC_AHB2ENR,  0,      "dcmi",         "ahb_div" },
  92         { STM32F4_RCC_AHB2ENR,  4,      "cryp",         "ahb_div" },
  93         { STM32F4_RCC_AHB2ENR,  5,      "hash",         "ahb_div" },
  94         { STM32F4_RCC_AHB2ENR,  6,      "rng",          "pll48" },
  95         { STM32F4_RCC_AHB2ENR,  7,      "otgfs",        "pll48" },
  96
  97         { STM32F4_RCC_AHB3ENR,  0,      "fmc",          "ahb_div",
  98                 CLK_IGNORE_UNUSED },
  99
 100         { STM32F4_RCC_APB1ENR,  0,      "tim2",         "apb1_mul" },
 101         { STM32F4_RCC_APB1ENR,  1,      "tim3",         "apb1_mul" },
 102         { STM32F4_RCC_APB1ENR,  2,      "tim4",         "apb1_mul" },
 103         { STM32F4_RCC_APB1ENR,  3,      "tim5",         "apb1_mul" },
 104         { STM32F4_RCC_APB1ENR,  4,      "tim6",         "apb1_mul" },
 105         { STM32F4_RCC_APB1ENR,  5,      "tim7",         "apb1_mul" },
 106         { STM32F4_RCC_APB1ENR,  6,      "tim12",        "apb1_mul" },
 107         { STM32F4_RCC_APB1ENR,  7,      "tim13",        "apb1_mul" },
 108         { STM32F4_RCC_APB1ENR,  8,      "tim14",        "apb1_mul" },
 109         { STM32F4_RCC_APB1ENR, 11,      "wwdg",         "apb1_div" },
 110         { STM32F4_RCC_APB1ENR, 14,      "spi2",         "apb1_div" },
 111         { STM32F4_RCC_APB1ENR, 15,      "spi3",         "apb1_div" },
 112         { STM32F4_RCC_APB1ENR, 17,      "uart2",        "apb1_div" },
 113         { STM32F4_RCC_APB1ENR, 18,      "uart3",        "apb1_div" },
 114         { STM32F4_RCC_APB1ENR, 19,      "uart4",        "apb1_div" },
 115         { STM32F4_RCC_APB1ENR, 20,      "uart5",        "apb1_div" },
 116         { STM32F4_RCC_APB1ENR, 21,      "i2c1",         "apb1_div" },
 117         { STM32F4_RCC_APB1ENR, 22,      "i2c2",         "apb1_div" },
 118         { STM32F4_RCC_APB1ENR, 23,      "i2c3",         "apb1_div" },
 119         { STM32F4_RCC_APB1ENR, 25,      "can1",         "apb1_div" },
 120         { STM32F4_RCC_APB1ENR, 26,      "can2",         "apb1_div" },
 121         { STM32F4_RCC_APB1ENR, 28,      "pwr",          "apb1_div" },
 122         { STM32F4_RCC_APB1ENR, 29,      "dac",          "apb1_div" },
 123         { STM32F4_RCC_APB1ENR, 30,      "uart7",        "apb1_div" },
 124         { STM32F4_RCC_APB1ENR, 31,      "uart8",        "apb1_div" },
 125
 126         { STM32F4_RCC_APB2ENR,  0,      "tim1",         "apb2_mul" },
 127         { STM32F4_RCC_APB2ENR,  1,      "tim8",         "apb2_mul" },
 128         { STM32F4_RCC_APB2ENR,  4,      "usart1",       "apb2_div" },
 129         { STM32F4_RCC_APB2ENR,  5,      "usart6",       "apb2_div" },
 130         { STM32F4_RCC_APB2ENR,  8,      "adc1",         "apb2_div" },
 131         { STM32F4_RCC_APB2ENR,  9,      "adc2",         "apb2_div" },
 132         { STM32F4_RCC_APB2ENR, 10,      "adc3",         "apb2_div" },
 133         { STM32F4_RCC_APB2ENR, 11,      "sdio",         "pll48" },
 134         { STM32F4_RCC_APB2ENR, 12,      "spi1",         "apb2_div" },
 135         { STM32F4_RCC_APB2ENR, 13,      "spi4",         "apb2_div" },
 136         { STM32F4_RCC_APB2ENR, 14,      "syscfg",       "apb2_div" },
 137         { STM32F4_RCC_APB2ENR, 16,      "tim9",         "apb2_mul" },
 138         { STM32F4_RCC_APB2ENR, 17,      "tim10",        "apb2_mul" },
 139         { STM32F4_RCC_APB2ENR, 18,      "tim11",        "apb2_mul" },
 140         { STM32F4_RCC_APB2ENR, 20,      "spi5",         "apb2_div" },
 141         { STM32F4_RCC_APB2ENR, 21,      "spi6",         "apb2_div" },
 142         { STM32F4_RCC_APB2ENR, 22,      "sai1",         "apb2_div" },
 143         { STM32F4_RCC_APB2ENR, 26,      "ltdc",         "apb2_div" },
 144 };
 145
 146 static const struct stm32f4_gate_data stm32f469_gates[] __initconst = {
 147         { STM32F4_RCC_AHB1ENR,  0,      "gpioa",        "ahb_div" },
 148         { STM32F4_RCC_AHB1ENR,  1,      "gpiob",        "ahb_div" },
 149         { STM32F4_RCC_AHB1ENR,  2,      "gpioc",        "ahb_div" },
 150         { STM32F4_RCC_AHB1ENR,  3,      "gpiod",        "ahb_div" },
 151         { STM32F4_RCC_AHB1ENR,  4,      "gpioe",        "ahb_div" },
 152         { STM32F4_RCC_AHB1ENR,  5,      "gpiof",        "ahb_div" },
 153         { STM32F4_RCC_AHB1ENR,  6,      "gpiog",        "ahb_div" },
 154         { STM32F4_RCC_AHB1ENR,  7,      "gpioh",        "ahb_div" },
 155         { STM32F4_RCC_AHB1ENR,  8,      "gpioi",        "ahb_div" },
 156         { STM32F4_RCC_AHB1ENR,  9,      "gpioj",        "ahb_div" },
 157         { STM32F4_RCC_AHB1ENR, 10,      "gpiok",        "ahb_div" },
 158         { STM32F4_RCC_AHB1ENR, 12,      "crc",          "ahb_div" },
 159         { STM32F4_RCC_AHB1ENR, 18,      "bkpsra",       "ahb_div" },
 160         { STM32F4_RCC_AHB1ENR, 20,      "ccmdatam",     "ahb_div" },
 161         { STM32F4_RCC_AHB1ENR, 21,      "dma1",         "ahb_div" },
 162         { STM32F4_RCC_AHB1ENR, 22,      "dma2",         "ahb_div" },
 163         { STM32F4_RCC_AHB1ENR, 23,      "dma2d",        "ahb_div" },
 164         { STM32F4_RCC_AHB1ENR, 25,      "ethmac",       "ahb_div" },
 165         { STM32F4_RCC_AHB1ENR, 26,      "ethmactx",     "ahb_div" },
 166         { STM32F4_RCC_AHB1ENR, 27,      "ethmacrx",     "ahb_div" },
 167         { STM32F4_RCC_AHB1ENR, 28,      "ethmacptp",    "ahb_div" },
 168         { STM32F4_RCC_AHB1ENR, 29,      "otghs",        "ahb_div" },
 169         { STM32F4_RCC_AHB1ENR, 30,      "otghsulpi",    "ahb_div" },
 170
 171         { STM32F4_RCC_AHB2ENR,  0,      "dcmi",         "ahb_div" },
 172         { STM32F4_RCC_AHB2ENR,  4,      "cryp",         "ahb_div" },
 173         { STM32F4_RCC_AHB2ENR,  5,      "hash",         "ahb_div" },
 174         { STM32F4_RCC_AHB2ENR,  6,      "rng",          "pll48" },
 175         { STM32F4_RCC_AHB2ENR,  7,      "otgfs",        "pll48" },
 176
 177         { STM32F4_RCC_AHB3ENR,  0,      "fmc",          "ahb_div",
 178                 CLK_IGNORE_UNUSED },
 179         { STM32F4_RCC_AHB3ENR,  1,      "qspi",         "ahb_div",
 180                 CLK_IGNORE_UNUSED },
 181
 182         { STM32F4_RCC_APB1ENR,  0,      "tim2",         "apb1_mul" },
 183         { STM32F4_RCC_APB1ENR,  1,      "tim3",         "apb1_mul" },
 184         { STM32F4_RCC_APB1ENR,  2,      "tim4",         "apb1_mul" },
 185         { STM32F4_RCC_APB1ENR,  3,      "tim5",         "apb1_mul" },
 186         { STM32F4_RCC_APB1ENR,  4,      "tim6",         "apb1_mul" },
 187         { STM32F4_RCC_APB1ENR,  5,      "tim7",         "apb1_mul" },
 188         { STM32F4_RCC_APB1ENR,  6,      "tim12",        "apb1_mul" },
 189         { STM32F4_RCC_APB1ENR,  7,      "tim13",        "apb1_mul" },
 190         { STM32F4_RCC_APB1ENR,  8,      "tim14",        "apb1_mul" },
 191         { STM32F4_RCC_APB1ENR, 11,      "wwdg",         "apb1_div" },
 192         { STM32F4_RCC_APB1ENR, 14,      "spi2",         "apb1_div" },
 193         { STM32F4_RCC_APB1ENR, 15,      "spi3",         "apb1_div" },
 194         { STM32F4_RCC_APB1ENR, 17,      "uart2",        "apb1_div" },
 195         { STM32F4_RCC_APB1ENR, 18,      "uart3",        "apb1_div" },
 196         { STM32F4_RCC_APB1ENR, 19,      "uart4",        "apb1_div" },
 197         { STM32F4_RCC_APB1ENR, 20,      "uart5",        "apb1_div" },
 198         { STM32F4_RCC_APB1ENR, 21,      "i2c1",         "apb1_div" },
 199         { STM32F4_RCC_APB1ENR, 22,      "i2c2",         "apb1_div" },
 200         { STM32F4_RCC_APB1ENR, 23,      "i2c3",         "apb1_div" },
 201         { STM32F4_RCC_APB1ENR, 25,      "can1",         "apb1_div" },
 202         { STM32F4_RCC_APB1ENR, 26,      "can2",         "apb1_div" },
 203         { STM32F4_RCC_APB1ENR, 28,      "pwr",          "apb1_div" },
 204         { STM32F4_RCC_APB1ENR, 29,      "dac",          "apb1_div" },
 205         { STM32F4_RCC_APB1ENR, 30,      "uart7",        "apb1_div" },
 206         { STM32F4_RCC_APB1ENR, 31,      "uart8",        "apb1_div" },
 207
 208         { STM32F4_RCC_APB2ENR,  0,      "tim1",         "apb2_mul" },
 209         { STM32F4_RCC_APB2ENR,  1,      "tim8",         "apb2_mul" },
 210         { STM32F4_RCC_APB2ENR,  4,      "usart1",       "apb2_div" },
 211         { STM32F4_RCC_APB2ENR,  5,      "usart6",       "apb2_div" },
 212         { STM32F4_RCC_APB2ENR,  8,      "adc1",         "apb2_div" },
 213         { STM32F4_RCC_APB2ENR,  9,      "adc2",         "apb2_div" },
 214         { STM32F4_RCC_APB2ENR, 10,      "adc3",         "apb2_div" },
 215         { STM32F4_RCC_APB2ENR, 11,      "sdio",         "sdmux" },
 216         { STM32F4_RCC_APB2ENR, 12,      "spi1",         "apb2_div" },
 217         { STM32F4_RCC_APB2ENR, 13,      "spi4",         "apb2_div" },
 218         { STM32F4_RCC_APB2ENR, 14,      "syscfg",       "apb2_div" },
 219         { STM32F4_RCC_APB2ENR, 16,      "tim9",         "apb2_mul" },
 220         { STM32F4_RCC_APB2ENR, 17,      "tim10",        "apb2_mul" },
 221         { STM32F4_RCC_APB2ENR, 18,      "tim11",        "apb2_mul" },
 222         { STM32F4_RCC_APB2ENR, 20,      "spi5",         "apb2_div" },
 223         { STM32F4_RCC_APB2ENR, 21,      "spi6",         "apb2_div" },
 224         { STM32F4_RCC_APB2ENR, 22,      "sai1",         "apb2_div" },
 225         { STM32F4_RCC_APB2ENR, 26,      "ltdc",         "apb2_div" },
 226 };
 227
 228 static const struct stm32f4_gate_data stm32f746_gates[] __initconst = {
 229         { STM32F4_RCC_AHB1ENR,  0,      "gpioa",        "ahb_div" },
 230         { STM32F4_RCC_AHB1ENR,  1,      "gpiob",        "ahb_div" },
 231         { STM32F4_RCC_AHB1ENR,  2,      "gpioc",        "ahb_div" },
 232         { STM32F4_RCC_AHB1ENR,  3,      "gpiod",        "ahb_div" },
 233         { STM32F4_RCC_AHB1ENR,  4,      "gpioe",        "ahb_div" },
 234         { STM32F4_RCC_AHB1ENR,  5,      "gpiof",        "ahb_div" },
 235         { STM32F4_RCC_AHB1ENR,  6,      "gpiog",        "ahb_div" },
 236         { STM32F4_RCC_AHB1ENR,  7,      "gpioh",        "ahb_div" },
 237         { STM32F4_RCC_AHB1ENR,  8,      "gpioi",        "ahb_div" },
 238         { STM32F4_RCC_AHB1ENR,  9,      "gpioj",        "ahb_div" },
 239         { STM32F4_RCC_AHB1ENR, 10,      "gpiok",        "ahb_div" },
 240         { STM32F4_RCC_AHB1ENR, 12,      "crc",          "ahb_div" },
 241         { STM32F4_RCC_AHB1ENR, 18,      "bkpsra",       "ahb_div" },
 242         { STM32F4_RCC_AHB1ENR, 20,      "dtcmram",      "ahb_div" },
 243         { STM32F4_RCC_AHB1ENR, 21,      "dma1",         "ahb_div" },
 244         { STM32F4_RCC_AHB1ENR, 22,      "dma2",         "ahb_div" },
 245         { STM32F4_RCC_AHB1ENR, 23,      "dma2d",        "ahb_div" },
 246         { STM32F4_RCC_AHB1ENR, 25,      "ethmac",       "ahb_div" },
 247         { STM32F4_RCC_AHB1ENR, 26,      "ethmactx",     "ahb_div" },
 248         { STM32F4_RCC_AHB1ENR, 27,      "ethmacrx",     "ahb_div" },
 249         { STM32F4_RCC_AHB1ENR, 28,      "ethmacptp",    "ahb_div" },
 250         { STM32F4_RCC_AHB1ENR, 29,      "otghs",        "ahb_div" },
 251         { STM32F4_RCC_AHB1ENR, 30,      "otghsulpi",    "ahb_div" },
 252
 253         { STM32F4_RCC_AHB2ENR,  0,      "dcmi",         "ahb_div" },
 254         { STM32F4_RCC_AHB2ENR,  4,      "cryp",         "ahb_div" },
 255         { STM32F4_RCC_AHB2ENR,  5,      "hash",         "ahb_div" },
 256         { STM32F4_RCC_AHB2ENR,  6,      "rng",          "pll48"   },
 257         { STM32F4_RCC_AHB2ENR,  7,      "otgfs",        "pll48"   },
 258
 259         { STM32F4_RCC_AHB3ENR,  0,      "fmc",          "ahb_div",
 260                 CLK_IGNORE_UNUSED },
 261         { STM32F4_RCC_AHB3ENR,  1,      "qspi",         "ahb_div",
 262                 CLK_IGNORE_UNUSED },
 263
 264         { STM32F4_RCC_APB1ENR,  0,      "tim2",         "apb1_mul" },
 265         { STM32F4_RCC_APB1ENR,  1,      "tim3",         "apb1_mul" },
 266         { STM32F4_RCC_APB1ENR,  2,      "tim4",         "apb1_mul" },
 267         { STM32F4_RCC_APB1ENR,  3,      "tim5",         "apb1_mul" },
 268         { STM32F4_RCC_APB1ENR,  4,      "tim6",         "apb1_mul" },
 269         { STM32F4_RCC_APB1ENR,  5,      "tim7",         "apb1_mul" },
 270         { STM32F4_RCC_APB1ENR,  6,      "tim12",        "apb1_mul" },
 271         { STM32F4_RCC_APB1ENR,  7,      "tim13",        "apb1_mul" },
 272         { STM32F4_RCC_APB1ENR,  8,      "tim14",        "apb1_mul" },
 273         { STM32F4_RCC_APB1ENR, 11,      "wwdg",         "apb1_div" },
 274         { STM32F4_RCC_APB1ENR, 14,      "spi2",         "apb1_div" },
 275         { STM32F4_RCC_APB1ENR, 15,      "spi3",         "apb1_div" },
 276         { STM32F4_RCC_APB1ENR, 16,      "spdifrx",      "apb1_div" },
 277         { STM32F4_RCC_APB1ENR, 25,      "can1",         "apb1_div" },
 278         { STM32F4_RCC_APB1ENR, 26,      "can2",         "apb1_div" },
 279         { STM32F4_RCC_APB1ENR, 27,      "cec",          "apb1_div" },
 280         { STM32F4_RCC_APB1ENR, 28,      "pwr",          "apb1_div" },
 281         { STM32F4_RCC_APB1ENR, 29,      "dac",          "apb1_div" },
 282
 283         { STM32F4_RCC_APB2ENR,  0,      "tim1",         "apb2_mul" },
 284         { STM32F4_RCC_APB2ENR,  1,      "tim8",         "apb2_mul" },
 285         { STM32F4_RCC_APB2ENR,  7,      "sdmmc2",       "sdmux"    },
 286         { STM32F4_RCC_APB2ENR,  8,      "adc1",         "apb2_div" },
 287         { STM32F4_RCC_APB2ENR,  9,      "adc2",         "apb2_div" },
 288         { STM32F4_RCC_APB2ENR, 10,      "adc3",         "apb2_div" },
 289         { STM32F4_RCC_APB2ENR, 11,      "sdmmc",        "sdmux"    },
 290         { STM32F4_RCC_APB2ENR, 12,      "spi1",         "apb2_div" },
 291         { STM32F4_RCC_APB2ENR, 13,      "spi4",         "apb2_div" },
 292         { STM32F4_RCC_APB2ENR, 14,      "syscfg",       "apb2_div" },
 293         { STM32F4_RCC_APB2ENR, 16,      "tim9",         "apb2_mul" },
 294         { STM32F4_RCC_APB2ENR, 17,      "tim10",        "apb2_mul" },
 295         { STM32F4_RCC_APB2ENR, 18,      "tim11",        "apb2_mul" },
 296         { STM32F4_RCC_APB2ENR, 20,      "spi5",         "apb2_div" },
 297         { STM32F4_RCC_APB2ENR, 21,      "spi6",         "apb2_div" },
 298         { STM32F4_RCC_APB2ENR, 22,      "sai1",         "apb2_div" },
 299         { STM32F4_RCC_APB2ENR, 23,      "sai2",         "apb2_div" },
 300         { STM32F4_RCC_APB2ENR, 26,      "ltdc",         "apb2_div" },
 301 };
 302
 303 static const struct stm32f4_gate_data stm32f769_gates[] __initconst = {
 304         { STM32F4_RCC_AHB1ENR,  0,      "gpioa",        "ahb_div" },
 305         { STM32F4_RCC_AHB1ENR,  1,      "gpiob",        "ahb_div" },
 306         { STM32F4_RCC_AHB1ENR,  2,      "gpioc",        "ahb_div" },
 307         { STM32F4_RCC_AHB1ENR,  3,      "gpiod",        "ahb_div" },
 308         { STM32F4_RCC_AHB1ENR,  4,      "gpioe",        "ahb_div" },
 309         { STM32F4_RCC_AHB1ENR,  5,      "gpiof",        "ahb_div" },
 310         { STM32F4_RCC_AHB1ENR,  6,      "gpiog",        "ahb_div" },
 311         { STM32F4_RCC_AHB1ENR,  7,      "gpioh",        "ahb_div" },
 312         { STM32F4_RCC_AHB1ENR,  8,      "gpioi",        "ahb_div" },
 313         { STM32F4_RCC_AHB1ENR,  9,      "gpioj",        "ahb_div" },
 314         { STM32F4_RCC_AHB1ENR, 10,      "gpiok",        "ahb_div" },
 315         { STM32F4_RCC_AHB1ENR, 12,      "crc",          "ahb_div" },
 316         { STM32F4_RCC_AHB1ENR, 18,      "bkpsra",       "ahb_div" },
 317         { STM32F4_RCC_AHB1ENR, 20,      "dtcmram",      "ahb_div" },
 318         { STM32F4_RCC_AHB1ENR, 21,      "dma1",         "ahb_div" },
 319         { STM32F4_RCC_AHB1ENR, 22,      "dma2",         "ahb_div" },
 320         { STM32F4_RCC_AHB1ENR, 23,      "dma2d",        "ahb_div" },
 321         { STM32F4_RCC_AHB1ENR, 25,      "ethmac",       "ahb_div" },
 322         { STM32F4_RCC_AHB1ENR, 26,      "ethmactx",     "ahb_div" },
 323         { STM32F4_RCC_AHB1ENR, 27,      "ethmacrx",     "ahb_div" },
 324         { STM32F4_RCC_AHB1ENR, 28,      "ethmacptp",    "ahb_div" },
 325         { STM32F4_RCC_AHB1ENR, 29,      "otghs",        "ahb_div" },
 326         { STM32F4_RCC_AHB1ENR, 30,      "otghsulpi",    "ahb_div" },
 327
 328         { STM32F4_RCC_AHB2ENR,  0,      "dcmi",         "ahb_div" },
 329         { STM32F4_RCC_AHB2ENR,  1,      "jpeg",         "ahb_div" },
 330         { STM32F4_RCC_AHB2ENR,  4,      "cryp",         "ahb_div" },
 331         { STM32F4_RCC_AHB2ENR,  5,      "hash",         "ahb_div" },
 332         { STM32F4_RCC_AHB2ENR,  6,      "rng",          "pll48"   },
 333         { STM32F4_RCC_AHB2ENR,  7,      "otgfs",        "pll48"   },
 334
 335         { STM32F4_RCC_AHB3ENR,  0,      "fmc",          "ahb_div",
 336                 CLK_IGNORE_UNUSED },
 337         { STM32F4_RCC_AHB3ENR,  1,      "qspi",         "ahb_div",
 338                 CLK_IGNORE_UNUSED },
 339
 340         { STM32F4_RCC_APB1ENR,  0,      "tim2",         "apb1_mul" },
 341         { STM32F4_RCC_APB1ENR,  1,      "tim3",         "apb1_mul" },
 342         { STM32F4_RCC_APB1ENR,  2,      "tim4",         "apb1_mul" },
 343         { STM32F4_RCC_APB1ENR,  3,      "tim5",         "apb1_mul" },
 344         { STM32F4_RCC_APB1ENR,  4,      "tim6",         "apb1_mul" },
 345         { STM32F4_RCC_APB1ENR,  5,      "tim7",         "apb1_mul" },
 346         { STM32F4_RCC_APB1ENR,  6,      "tim12",        "apb1_mul" },
 347         { STM32F4_RCC_APB1ENR,  7,      "tim13",        "apb1_mul" },
 348         { STM32F4_RCC_APB1ENR,  8,      "tim14",        "apb1_mul" },
 349         { STM32F4_RCC_APB1ENR, 10,      "rtcapb",       "apb1_mul" },
 350         { STM32F4_RCC_APB1ENR, 11,      "wwdg",         "apb1_div" },
 351         { STM32F4_RCC_APB1ENR, 13,      "can3",         "apb1_div" },
 352         { STM32F4_RCC_APB1ENR, 14,      "spi2",         "apb1_div" },
 353         { STM32F4_RCC_APB1ENR, 15,      "spi3",         "apb1_div" },
 354         { STM32F4_RCC_APB1ENR, 16,      "spdifrx",      "apb1_div" },
 355         { STM32F4_RCC_APB1ENR, 25,      "can1",         "apb1_div" },
 356         { STM32F4_RCC_APB1ENR, 26,      "can2",         "apb1_div" },
 357         { STM32F4_RCC_APB1ENR, 27,      "cec",          "apb1_div" },
 358         { STM32F4_RCC_APB1ENR, 28,      "pwr",          "apb1_div" },
 359         { STM32F4_RCC_APB1ENR, 29,      "dac",          "apb1_div" },
 360
 361         { STM32F4_RCC_APB2ENR,  0,      "tim1",         "apb2_mul" },
 362         { STM32F4_RCC_APB2ENR,  1,      "tim8",         "apb2_mul" },
 363         { STM32F4_RCC_APB2ENR,  7,      "sdmmc2",       "sdmux2" },
 364         { STM32F4_RCC_APB2ENR,  8,      "adc1",         "apb2_div" },
 365         { STM32F4_RCC_APB2ENR,  9,      "adc2",         "apb2_div" },
 366         { STM32F4_RCC_APB2ENR, 10,      "adc3",         "apb2_div" },
 367         { STM32F4_RCC_APB2ENR, 11,      "sdmmc1",       "sdmux1" },
 368         { STM32F4_RCC_APB2ENR, 12,      "spi1",         "apb2_div" },
 369         { STM32F4_RCC_APB2ENR, 13,      "spi4",         "apb2_div" },
 370         { STM32F4_RCC_APB2ENR, 14,      "syscfg",       "apb2_div" },
 371         { STM32F4_RCC_APB2ENR, 16,      "tim9",         "apb2_mul" },
 372         { STM32F4_RCC_APB2ENR, 17,      "tim10",        "apb2_mul" },
 373         { STM32F4_RCC_APB2ENR, 18,      "tim11",        "apb2_mul" },
 374         { STM32F4_RCC_APB2ENR, 20,      "spi5",         "apb2_div" },
 375         { STM32F4_RCC_APB2ENR, 21,      "spi6",         "apb2_div" },
 376         { STM32F4_RCC_APB2ENR, 22,      "sai1",         "apb2_div" },
 377         { STM32F4_RCC_APB2ENR, 23,      "sai2",         "apb2_div" },
 378         { STM32F4_RCC_APB2ENR, 26,      "ltdc",         "apb2_div" },
 379         { STM32F4_RCC_APB2ENR, 30,      "mdio",         "apb2_div" },
 380 };
 381
 382 /*
 383  * This bitmask tells us which bit offsets (0..192) on STM32F4[23]xxx
 384  * have gate bits associated with them. Its combined hweight is 71.
 385  */
 386 #define MAX_GATE_MAP 3
 387
 388 static const u64 stm32f42xx_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
 389                                                        0x0000000000000001ull,
 390                                                        0x04777f33f6fec9ffull };
 391
 392 static const u64 stm32f46xx_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
 393                                                        0x0000000000000003ull,
 394                                                        0x0c777f33f6fec9ffull };
 395
 396 static const u64 stm32f746_gate_map[MAX_GATE_MAP] = { 0x000000f17ef417ffull,
 397                                                       0x0000000000000003ull,
 398                                                       0x04f77f833e01c9ffull };
 399
 400 static const u64 stm32f769_gate_map[MAX_GATE_MAP] = { 0x000000f37ef417ffull,
 401                                                       0x0000000000000003ull,
 402                                                       0x44F77F833E01EDFFull };
 403
 404 static const u64 *stm32f4_gate_map;
 405
 406 static struct clk_hw **clks;
 407
 408 static DEFINE_SPINLOCK(stm32f4_clk_lock);
 409 static void __iomem *base;
 410
 411 static struct regmap *pdrm;
 412
 413 static int stm32fx_end_primary_clk;
 414
 415 /*
 416  * "Multiplier" device for APBx clocks.
 417  *
 418  * The APBx dividers are power-of-two dividers and, if *not* running in 1:1
 419  * mode, they also tap out the one of the low order state bits to run the
 420  * timers. ST datasheets represent this feature as a (conditional) clock
 421  * multiplier.
 422  */
 423 struct clk_apb_mul {
 424         struct clk_hw hw;
 425         u8 bit_idx;
 426 };
 427
 428 #define to_clk_apb_mul(_hw) container_of(_hw, struct clk_apb_mul, hw)
 429
 430 static unsigned long clk_apb_mul_recalc_rate(struct clk_hw *hw,
 431                                              unsigned long parent_rate)
 432 {
 433         struct clk_apb_mul *am = to_clk_apb_mul(hw);
 434
 435         if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
 436                 return parent_rate * 2;
 437
 438         return parent_rate;
 439 }
 440
 441 static long clk_apb_mul_round_rate(struct clk_hw *hw, unsigned long rate,
 442                                    unsigned long *prate)
 443 {
 444         struct clk_apb_mul *am = to_clk_apb_mul(hw);
 445         unsigned long mult = 1;
 446
 447         if (readl(base + STM32F4_RCC_CFGR) & BIT(am->bit_idx))
 448                 mult = 2;
 449
 450         if (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) {
 451                 unsigned long best_parent = rate / mult;
 452
 453                 *prate = clk_hw_round_rate(clk_hw_get_parent(hw), best_parent);
 454         }
 455
 456         return *prate * mult;
 457 }
 458
 459 static int clk_apb_mul_set_rate(struct clk_hw *hw, unsigned long rate,
 460                                 unsigned long parent_rate)
 461 {
 462         /*
 463          * We must report success but we can do so unconditionally because
 464          * clk_apb_mul_round_rate returns values that ensure this call is a
 465          * nop.
 466          */
 467
 468         return 0;
 469 }
 470
 471 static const struct clk_ops clk_apb_mul_factor_ops = {
 472         .round_rate = clk_apb_mul_round_rate,
 473         .set_rate = clk_apb_mul_set_rate,
 474         .recalc_rate = clk_apb_mul_recalc_rate,
 475 };
 476
 477 static struct clk *clk_register_apb_mul(struct device *dev, const char *name,
 478                                         const char *parent_name,
 479                                         unsigned long flags, u8 bit_idx)
 480 {
 481         struct clk_apb_mul *am;
 482         struct clk_init_data init;
 483         struct clk *clk;
 484
 485         am = kzalloc(sizeof(*am), GFP_KERNEL);
 486         if (!am)
 487                 return ERR_PTR(-ENOMEM);
 488
 489         am->bit_idx = bit_idx;
 490         am->hw.init = &init;
 491
 492         init.name = name;
 493         init.ops = &clk_apb_mul_factor_ops;
 494         init.flags = flags;
 495         init.parent_names = &parent_name;
 496         init.num_parents = 1;
 497
 498         clk = clk_register(dev, &am->hw);
 499
 500         if (IS_ERR(clk))
 501                 kfree(am);
 502
 503         return clk;
 504 }
 505
 506 enum {
 507         PLL,
 508         PLL_I2S,
 509         PLL_SAI,
 510 };
 511
 512 static const struct clk_div_table pll_divp_table[] = {
 513         { 0, 2 }, { 1, 4 }, { 2, 6 }, { 3, 8 }, { 0 }
 514 };
 515
 516 static const struct clk_div_table pll_divq_table[] = {
 517         { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 },
 518         { 8, 8 }, { 9, 9 }, { 10, 10 }, { 11, 11 }, { 12, 12 }, { 13, 13 },
 519         { 14, 14 }, { 15, 15 },
 520         { 0 }
 521 };
 522
 523 static const struct clk_div_table pll_divr_table[] = {
 524         { 2, 2 }, { 3, 3 }, { 4, 4 }, { 5, 5 }, { 6, 6 }, { 7, 7 }, { 0 }
 525 };
 526
 527 struct stm32f4_pll {
 528         spinlock_t *lock;
 529         struct  clk_gate gate;
 530         u8 offset;
 531         u8 bit_rdy_idx;
 532         u8 status;
 533         u8 n_start;
 534 };
 535
 536 #define to_stm32f4_pll(_gate) container_of(_gate, struct stm32f4_pll, gate)
 537
 538 struct stm32f4_pll_post_div_data {
 539         int idx;
 540         u8 pll_num;
 541         const char *name;
 542         const char *parent;
 543         u8 flag;
 544         u8 offset;
 545         u8 shift;
 546         u8 width;
 547         u8 flag_div;
 548         const struct clk_div_table *div_table;
 549 };
 550
 551 struct stm32f4_vco_data {
 552         const char *vco_name;
 553         u8 offset;
 554         u8 bit_idx;
 555         u8 bit_rdy_idx;
 556 };
 557
 558 static const struct stm32f4_vco_data  vco_data[] = {
 559         { "vco",     STM32F4_RCC_PLLCFGR,    24, 25 },
 560         { "vco-i2s", STM32F4_RCC_PLLI2SCFGR, 26, 27 },
 561         { "vco-sai", STM32F4_RCC_PLLSAICFGR, 28, 29 },
 562 };
 563
 564
 565 static const struct clk_div_table post_divr_table[] = {
 566         { 0, 2 }, { 1, 4 }, { 2, 8 }, { 3, 16 }, { 0 }
 567 };
 568
 569 #define MAX_POST_DIV 3
 570 static const struct stm32f4_pll_post_div_data  post_div_data[MAX_POST_DIV] = {
 571         { CLK_I2SQ_PDIV, PLL_I2S, "plli2s-q-div", "plli2s-q",
 572                 CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 0, 5, 0, NULL},
 573
 574         { CLK_SAIQ_PDIV, PLL_SAI, "pllsai-q-div", "pllsai-q",
 575                 CLK_SET_RATE_PARENT, STM32F4_RCC_DCKCFGR, 8, 5, 0, NULL },
 576
 577         { NO_IDX, PLL_SAI, "pllsai-r-div", "pllsai-r", CLK_SET_RATE_PARENT,
 578                 STM32F4_RCC_DCKCFGR, 16, 2, 0, post_divr_table },
 579 };
 580
 581 struct stm32f4_div_data {
 582         u8 shift;
 583         u8 width;
 584         u8 flag_div;
 585         const struct clk_div_table *div_table;
 586 };
 587
 588 #define MAX_PLL_DIV 3
 589 static const struct stm32f4_div_data  div_data[MAX_PLL_DIV] = {
 590         { 16, 2, 0, pll_divp_table },
 591         { 24, 4, 0, pll_divq_table },
 592         { 28, 3, 0, pll_divr_table },
 593 };
 594
 595 struct stm32f4_pll_data {
 596         u8 pll_num;
 597         u8 n_start;
 598         const char *div_name[MAX_PLL_DIV];
 599 };
 600
 601 static const struct stm32f4_pll_data stm32f429_pll[MAX_PLL_DIV] = {
 602         { PLL,     192, { "pll", "pll48",    NULL       } },
 603         { PLL_I2S, 192, { NULL,  "plli2s-q", "plli2s-r" } },
 604         { PLL_SAI,  49, { NULL,  "pllsai-q", "pllsai-r" } },
 605 };
 606
 607 static const struct stm32f4_pll_data stm32f469_pll[MAX_PLL_DIV] = {
 608         { PLL,     50, { "pll",      "pll-q",    "pll-r"    } },
 609         { PLL_I2S, 50, { "plli2s-p", "plli2s-q", "plli2s-r" } },
 610         { PLL_SAI, 50, { "pllsai-p", "pllsai-q", "pllsai-r" } },
 611 };
 612
 613 static int stm32f4_pll_is_enabled(struct clk_hw *hw)
 614 {
 615         return clk_gate_ops.is_enabled(hw);
 616 }
 617
 618 #define PLL_TIMEOUT 10000
 619
 620 static int stm32f4_pll_enable(struct clk_hw *hw)
 621 {
 622         struct clk_gate *gate = to_clk_gate(hw);
 623         struct stm32f4_pll *pll = to_stm32f4_pll(gate);
 624         int bit_status;
 625         unsigned int timeout = PLL_TIMEOUT;
 626
 627         if (clk_gate_ops.is_enabled(hw))
 628                 return 0;
 629
 630         clk_gate_ops.enable(hw);
 631
 632         do {
 633                 bit_status = !(readl(gate->reg) & BIT(pll->bit_rdy_idx));
 634
 635         } while (bit_status && --timeout);
 636
 637         return bit_status;
 638 }
 639
 640 static void stm32f4_pll_disable(struct clk_hw *hw)
 641 {
 642         clk_gate_ops.disable(hw);
 643 }
 644
 645 static unsigned long stm32f4_pll_recalc(struct clk_hw *hw,
 646                 unsigned long parent_rate)
 647 {
 648         struct clk_gate *gate = to_clk_gate(hw);
 649         struct stm32f4_pll *pll = to_stm32f4_pll(gate);
 650         unsigned long n;
 651
 652         n = (readl(base + pll->offset) >> 6) & 0x1ff;
 653
 654         return parent_rate * n;
 655 }
 656
 657 static long stm32f4_pll_round_rate(struct clk_hw *hw, unsigned long rate,
 658                 unsigned long *prate)
 659 {
 660         struct clk_gate *gate = to_clk_gate(hw);
 661         struct stm32f4_pll *pll = to_stm32f4_pll(gate);
 662         unsigned long n;
 663
 664         n = rate / *prate;
 665
 666         if (n < pll->n_start)
 667                 n = pll->n_start;
 668         else if (n > 432)
 669                 n = 432;
 670
 671         return *prate * n;
 672 }
 673
 674 static int stm32f4_pll_set_rate(struct clk_hw *hw, unsigned long rate,
 675                                 unsigned long parent_rate)
 676 {
 677         struct clk_gate *gate = to_clk_gate(hw);
 678         struct stm32f4_pll *pll = to_stm32f4_pll(gate);
 679
 680         unsigned long n;
 681         unsigned long val;
 682         int pll_state;
 683
 684         pll_state = stm32f4_pll_is_enabled(hw);
 685
 686         if (pll_state)
 687                 stm32f4_pll_disable(hw);
 688
 689         n = rate  / parent_rate;
 690
 691         val = readl(base + pll->offset) & ~(0x1ff << 6);
 692
 693         writel(val | ((n & 0x1ff) <<  6), base + pll->offset);
 694
 695         if (pll_state)
 696                 stm32f4_pll_enable(hw);
 697
 698         return 0;
 699 }
 700
 701 static const struct clk_ops stm32f4_pll_gate_ops = {
 702         .enable         = stm32f4_pll_enable,
 703         .disable        = stm32f4_pll_disable,
 704         .is_enabled     = stm32f4_pll_is_enabled,
 705         .recalc_rate    = stm32f4_pll_recalc,
 706         .round_rate     = stm32f4_pll_round_rate,
 707         .set_rate       = stm32f4_pll_set_rate,
 708 };
 709
 710 struct stm32f4_pll_div {
 711         struct clk_divider div;
 712         struct clk_hw *hw_pll;
 713 };
 714
 715 #define to_pll_div_clk(_div) container_of(_div, struct stm32f4_pll_div, div)
 716
 717 static unsigned long stm32f4_pll_div_recalc_rate(struct clk_hw *hw,
 718                 unsigned long parent_rate)
 719 {
 720         return clk_divider_ops.recalc_rate(hw, parent_rate);
 721 }
 722
 723 static long stm32f4_pll_div_round_rate(struct clk_hw *hw, unsigned long rate,
 724                                 unsigned long *prate)
 725 {
 726         return clk_divider_ops.round_rate(hw, rate, prate);
 727 }
 728
 729 static int stm32f4_pll_div_set_rate(struct clk_hw *hw, unsigned long rate,
 730                                 unsigned long parent_rate)
 731 {
 732         int pll_state, ret;
 733
 734         struct clk_divider *div = to_clk_divider(hw);
 735         struct stm32f4_pll_div *pll_div = to_pll_div_clk(div);
 736
 737         pll_state = stm32f4_pll_is_enabled(pll_div->hw_pll);
 738
 739         if (pll_state)
 740                 stm32f4_pll_disable(pll_div->hw_pll);
 741
 742         ret = clk_divider_ops.set_rate(hw, rate, parent_rate);
 743
 744         if (pll_state)
 745                 stm32f4_pll_enable(pll_div->hw_pll);
 746
 747         return ret;
 748 }
 749
 750 static const struct clk_ops stm32f4_pll_div_ops = {
 751         .recalc_rate = stm32f4_pll_div_recalc_rate,
 752         .round_rate = stm32f4_pll_div_round_rate,
 753         .set_rate = stm32f4_pll_div_set_rate,
 754 };
 755
 756 static struct clk_hw *clk_register_pll_div(const char *name,
 757                 const char *parent_name, unsigned long flags,
 758                 void __iomem *reg, u8 shift, u8 width,
 759                 u8 clk_divider_flags, const struct clk_div_table *table,
 760                 struct clk_hw *pll_hw, spinlock_t *lock)
 761 {
 762         struct stm32f4_pll_div *pll_div;
 763         struct clk_hw *hw;
 764         struct clk_init_data init;
 765         int ret;
 766
 767         /* allocate the divider */
 768         pll_div = kzalloc(sizeof(*pll_div), GFP_KERNEL);
 769         if (!pll_div)
 770                 return ERR_PTR(-ENOMEM);
 771
 772         init.name = name;
 773         init.ops = &stm32f4_pll_div_ops;
 774         init.flags = flags;
 775         init.parent_names = (parent_name ? &parent_name : NULL);
 776         init.num_parents = (parent_name ? 1 : 0);
 777
 778         /* struct clk_divider assignments */
 779         pll_div->div.reg = reg;
 780         pll_div->div.shift = shift;
 781         pll_div->div.width = width;
 782         pll_div->div.flags = clk_divider_flags;
 783         pll_div->div.lock = lock;
 784         pll_div->div.table = table;
 785         pll_div->div.hw.init = &init;
 786
 787         pll_div->hw_pll = pll_hw;
 788
 789         /* register the clock */
 790         hw = &pll_div->div.hw;
 791         ret = clk_hw_register(NULL, hw);
 792         if (ret) {
 793                 kfree(pll_div);
 794                 hw = ERR_PTR(ret);
 795         }
 796
 797         return hw;
 798 }
 799
 800 static struct clk_hw *stm32f4_rcc_register_pll(const char *pllsrc,
 801                 const struct stm32f4_pll_data *data,  spinlock_t *lock)
 802 {
 803         struct stm32f4_pll *pll;
 804         struct clk_init_data init = { NULL };
 805         void __iomem *reg;
 806         struct clk_hw *pll_hw;
 807         int ret;
 808         int i;
 809         const struct stm32f4_vco_data *vco;
 810
 811
 812         pll = kzalloc(sizeof(*pll), GFP_KERNEL);
 813         if (!pll)
 814                 return ERR_PTR(-ENOMEM);
 815
 816         vco = &vco_data[data->pll_num];
 817
 818         init.name = vco->vco_name;
 819         init.ops = &stm32f4_pll_gate_ops;
 820         init.flags = CLK_SET_RATE_GATE;
 821         init.parent_names = &pllsrc;
 822         init.num_parents = 1;
 823
 824         pll->gate.lock = lock;
 825         pll->gate.reg = base + STM32F4_RCC_CR;
 826         pll->gate.bit_idx = vco->bit_idx;
 827         pll->gate.hw.init = &init;
 828
 829         pll->offset = vco->offset;
 830         pll->n_start = data->n_start;
 831         pll->bit_rdy_idx = vco->bit_rdy_idx;
 832         pll->status = (readl(base + STM32F4_RCC_CR) >> vco->bit_idx) & 0x1;
 833
 834         reg = base + pll->offset;
 835
 836         pll_hw = &pll->gate.hw;
 837         ret = clk_hw_register(NULL, pll_hw);
 838         if (ret) {
 839                 kfree(pll);
 840                 return ERR_PTR(ret);
 841         }
 842
 843         for (i = 0; i < MAX_PLL_DIV; i++)
 844                 if (data->div_name[i])
 845                         clk_register_pll_div(data->div_name[i],
 846                                         vco->vco_name,
 847                                         0,
 848                                         reg,
 849                                         div_data[i].shift,
 850                                         div_data[i].width,
 851                                         div_data[i].flag_div,
 852                                         div_data[i].div_table,
 853                                         pll_hw,
 854                                         lock);
 855         return pll_hw;
 856 }
 857
 858 /*
 859  * Converts the primary and secondary indices (as they appear in DT) to an
 860  * offset into our struct clock array.
 861  */
 862 static int stm32f4_rcc_lookup_clk_idx(u8 primary, u8 secondary)
 863 {
 864         u64 table[MAX_GATE_MAP];
 865
 866         if (primary == 1) {
 867                 if (WARN_ON(secondary >= stm32fx_end_primary_clk))
 868                         return -EINVAL;
 869                 return secondary;
 870         }
 871
 872         memcpy(table, stm32f4_gate_map, sizeof(table));
 873
 874         /* only bits set in table can be used as indices */
 875         if (WARN_ON(secondary >= BITS_PER_BYTE * sizeof(table) ||
 876                     0 == (table[BIT_ULL_WORD(secondary)] &
 877                           BIT_ULL_MASK(secondary))))
 878                 return -EINVAL;
 879
 880         /* mask out bits above our current index */
 881         table[BIT_ULL_WORD(secondary)] &=
 882             GENMASK_ULL(secondary % BITS_PER_LONG_LONG, 0);
 883
 884         return stm32fx_end_primary_clk - 1 + hweight64(table[0]) +
 885                (BIT_ULL_WORD(secondary) >= 1 ? hweight64(table[1]) : 0) +
 886                (BIT_ULL_WORD(secondary) >= 2 ? hweight64(table[2]) : 0);
 887 }
 888
 889 static struct clk_hw *
 890 stm32f4_rcc_lookup_clk(struct of_phandle_args *clkspec, void *data)
 891 {
 892         int i = stm32f4_rcc_lookup_clk_idx(clkspec->args[0], clkspec->args[1]);
 893
 894         if (i < 0)
 895                 return ERR_PTR(-EINVAL);
 896
 897         return clks[i];
 898 }
 899
 900 #define to_rgclk(_rgate) container_of(_rgate, struct stm32_rgate, gate)
 901
 902 static inline void disable_power_domain_write_protection(void)
 903 {
 904         if (pdrm)
 905                 regmap_update_bits(pdrm, 0x00, (1 << 8), (1 << 8));
 906 }
 907
 908 static inline void enable_power_domain_write_protection(void)
 909 {
 910         if (pdrm)
 911                 regmap_update_bits(pdrm, 0x00, (1 << 8), (0 << 8));
 912 }
 913
 914 static inline void sofware_reset_backup_domain(void)
 915 {
 916         unsigned long val;
 917
 918         val = readl(base + STM32F4_RCC_BDCR);
 919         writel(val | BIT(16), base + STM32F4_RCC_BDCR);
 920         writel(val & ~BIT(16), base + STM32F4_RCC_BDCR);
 921 }
 922
 923 struct stm32_rgate {
 924         struct  clk_gate gate;
 925         u8      bit_rdy_idx;
 926 };
 927
 928 #define RGATE_TIMEOUT 50000
 929
 930 static int rgclk_enable(struct clk_hw *hw)
 931 {
 932         struct clk_gate *gate = to_clk_gate(hw);
 933         struct stm32_rgate *rgate = to_rgclk(gate);
 934         int bit_status;
 935         unsigned int timeout = RGATE_TIMEOUT;
 936
 937         if (clk_gate_ops.is_enabled(hw))
 938                 return 0;
 939
 940         disable_power_domain_write_protection();
 941
 942         clk_gate_ops.enable(hw);
 943
 944         do {
 945                 bit_status = !(readl(gate->reg) & BIT(rgate->bit_rdy_idx));
 946                 if (bit_status)
 947                         udelay(100);
 948
 949         } while (bit_status && --timeout);
 950
 951         enable_power_domain_write_protection();
 952
 953         return bit_status;
 954 }
 955
 956 static void rgclk_disable(struct clk_hw *hw)
 957 {
 958         clk_gate_ops.disable(hw);
 959 }
 960
 961 static int rgclk_is_enabled(struct clk_hw *hw)
 962 {
 963         return clk_gate_ops.is_enabled(hw);
 964 }
 965
 966 static const struct clk_ops rgclk_ops = {
 967         .enable = rgclk_enable,
 968         .disable = rgclk_disable,
 969         .is_enabled = rgclk_is_enabled,
 970 };
 971
 972 static struct clk_hw *clk_register_rgate(struct device *dev, const char *name,
 973                 const char *parent_name, unsigned long flags,
 974                 void __iomem *reg, u8 bit_idx, u8 bit_rdy_idx,
 975                 u8 clk_gate_flags, spinlock_t *lock)
 976 {
 977         struct stm32_rgate *rgate;
 978         struct clk_init_data init = { NULL };
 979         struct clk_hw *hw;
 980         int ret;
 981
 982         rgate = kzalloc(sizeof(*rgate), GFP_KERNEL);
 983         if (!rgate)
 984                 return ERR_PTR(-ENOMEM);
 985
 986         init.name = name;
 987         init.ops = &rgclk_ops;
 988         init.flags = flags;
 989         init.parent_names = &parent_name;
 990         init.num_parents = 1;
 991
 992         rgate->bit_rdy_idx = bit_rdy_idx;
 993
 994         rgate->gate.lock = lock;
 995         rgate->gate.reg = reg;
 996         rgate->gate.bit_idx = bit_idx;
 997         rgate->gate.hw.init = &init;
 998
 999         hw = &rgate->gate.hw;
1000         ret = clk_hw_register(dev, hw);
1001         if (ret) {
1002                 kfree(rgate);
1003                 hw = ERR_PTR(ret);
1004         }
1005
1006         return hw;
1007 }
1008
1009 static int cclk_gate_enable(struct clk_hw *hw)
1010 {
1011         int ret;
1012
1013         disable_power_domain_write_protection();
1014
1015         ret = clk_gate_ops.enable(hw);
1016
1017         enable_power_domain_write_protection();
1018
1019         return ret;
1020 }
1021
1022 static void cclk_gate_disable(struct clk_hw *hw)
1023 {
1024         disable_power_domain_write_protection();
1025
1026         clk_gate_ops.disable(hw);
1027
1028         enable_power_domain_write_protection();
1029 }
1030
1031 static int cclk_gate_is_enabled(struct clk_hw *hw)
1032 {
1033         return clk_gate_ops.is_enabled(hw);
1034 }
1035
1036 static const struct clk_ops cclk_gate_ops = {
1037         .enable         = cclk_gate_enable,
1038         .disable        = cclk_gate_disable,
1039         .is_enabled     = cclk_gate_is_enabled,
1040 };
1041
1042 static u8 cclk_mux_get_parent(struct clk_hw *hw)
1043 {
1044         return clk_mux_ops.get_parent(hw);
1045 }
1046
1047 static int cclk_mux_set_parent(struct clk_hw *hw, u8 index)
1048 {
1049         int ret;
1050
1051         disable_power_domain_write_protection();
1052
1053         sofware_reset_backup_domain();
1054
1055         ret = clk_mux_ops.set_parent(hw, index);
1056
1057         enable_power_domain_write_protection();
1058
1059         return ret;
1060 }
1061
1062 static const struct clk_ops cclk_mux_ops = {
1063         .get_parent = cclk_mux_get_parent,
1064         .set_parent = cclk_mux_set_parent,
1065 };
1066
1067 static struct clk_hw *stm32_register_cclk(struct device *dev, const char *name,
1068                 const char * const *parent_names, int num_parents,
1069                 void __iomem *reg, u8 bit_idx, u8 shift, unsigned long flags,
1070                 spinlock_t *lock)
1071 {
1072         struct clk_hw *hw;
1073         struct clk_gate *gate;
1074         struct clk_mux *mux;
1075
1076         gate = kzalloc(sizeof(*gate), GFP_KERNEL);
1077         if (!gate) {
1078                 hw = ERR_PTR(-EINVAL);
1079                 goto fail;
1080         }
1081
1082         mux = kzalloc(sizeof(*mux), GFP_KERNEL);
1083         if (!mux) {
1084                 kfree(gate);
1085                 hw = ERR_PTR(-EINVAL);
1086                 goto fail;
1087         }
1088
1089         gate->reg = reg;
1090         gate->bit_idx = bit_idx;
1091         gate->flags = 0;
1092         gate->lock = lock;
1093
1094         mux->reg = reg;
1095         mux->shift = shift;
1096         mux->mask = 3;
1097         mux->flags = 0;
1098
1099         hw = clk_hw_register_composite(dev, name, parent_names, num_parents,
1100                         &mux->hw, &cclk_mux_ops,
1101                         NULL, NULL,
1102                         &gate->hw, &cclk_gate_ops,
1103                         flags);
1104
1105         if (IS_ERR(hw)) {
1106                 kfree(gate);
1107                 kfree(mux);
1108         }
1109
1110 fail:
1111         return hw;
1112 }
1113
1114 static const char *sys_parents[] __initdata =   { "hsi", NULL, "pll" };
1115
1116 static const struct clk_div_table ahb_div_table[] = {
1117         { 0x0,   1 }, { 0x1,   1 }, { 0x2,   1 }, { 0x3,   1 },
1118         { 0x4,   1 }, { 0x5,   1 }, { 0x6,   1 }, { 0x7,   1 },
1119         { 0x8,   2 }, { 0x9,   4 }, { 0xa,   8 }, { 0xb,  16 },
1120         { 0xc,  64 }, { 0xd, 128 }, { 0xe, 256 }, { 0xf, 512 },
1121         { 0 },
1122 };
1123
1124 static const struct clk_div_table apb_div_table[] = {
1125         { 0,  1 }, { 0,  1 }, { 0,  1 }, { 0,  1 },
1126         { 4,  2 }, { 5,  4 }, { 6,  8 }, { 7, 16 },
1127         { 0 },
1128 };
1129
1130 static const char *rtc_parents[4] = {
1131         "no-clock", "lse", "lsi", "hse-rtc"
1132 };
1133
1134 static const char *pll_src = "pll-src";
1135
1136 static const char *pllsrc_parent[2] = { "hsi", NULL };
1137
1138 static const char *dsi_parent[2] = { NULL, "pll-r" };
1139
1140 static const char *lcd_parent[1] = { "pllsai-r-div" };
1141
1142 static const char *i2s_parents[2] = { "plli2s-r", NULL };
1143
1144 static const char *sai_parents[4] = { "pllsai-q-div", "plli2s-q-div", NULL,
1145         "no-clock" };
1146
1147 static const char *pll48_parents[2] = { "pll-q", "pllsai-p" };
1148
1149 static const char *sdmux_parents[2] = { "pll48", "sys" };
1150
1151 static const char *hdmi_parents[2] = { "lse", "hsi_div488" };
1152
1153 static const char *spdif_parent[1] = { "plli2s-p" };
1154
1155 static const char *lptim_parent[4] = { "apb1_mul", "lsi", "hsi", "lse" };
1156
1157 static const char *uart_parents1[4] = { "apb2_div", "sys", "hsi", "lse" };
1158 static const char *uart_parents2[4] = { "apb1_div", "sys", "hsi", "lse" };
1159
1160 static const char *i2c_parents[4] = { "apb1_div", "sys", "hsi", "no-clock" };
1161
1162 static const char * const dfsdm1_src[] = { "apb2_div", "sys" };
1163 static const char * const adsfdm1_parent[] = { "sai1_clk", "sai2_clk" };
1164
1165 struct stm32_aux_clk {
1166         int idx;
1167         const char *name;
1168         const char * const *parent_names;
1169         int num_parents;
1170         int offset_mux;
1171         u8 shift;
1172         u8 mask;
1173         int offset_gate;
1174         u8 bit_idx;
1175         unsigned long flags;
1176 };
1177
1178 struct stm32f4_clk_data {
1179         const struct stm32f4_gate_data *gates_data;
1180         const u64 *gates_map;
1181         int gates_num;
1182         const struct stm32f4_pll_data *pll_data;
1183         const struct stm32_aux_clk *aux_clk;
1184         int aux_clk_num;
1185         int end_primary;
1186 };
1187
1188 static const struct stm32_aux_clk stm32f429_aux_clk[] = {
1189         {
1190                 CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1191                 NO_MUX, 0, 0,
1192                 STM32F4_RCC_APB2ENR, 26,
1193                 CLK_SET_RATE_PARENT
1194         },
1195         {
1196                 CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
1197                 STM32F4_RCC_CFGR, 23, 1,
1198                 NO_GATE, 0,
1199                 CLK_SET_RATE_PARENT
1200         },
1201         {
1202                 CLK_SAI1, "sai1-a", sai_parents, ARRAY_SIZE(sai_parents),
1203                 STM32F4_RCC_DCKCFGR, 20, 3,
1204                 STM32F4_RCC_APB2ENR, 22,
1205                 CLK_SET_RATE_PARENT
1206         },
1207         {
1208                 CLK_SAI2, "sai1-b", sai_parents, ARRAY_SIZE(sai_parents),
1209                 STM32F4_RCC_DCKCFGR, 22, 3,
1210                 STM32F4_RCC_APB2ENR, 22,
1211                 CLK_SET_RATE_PARENT
1212         },
1213 };
1214
1215 static const struct stm32_aux_clk stm32f469_aux_clk[] = {
1216         {
1217                 CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1218                 NO_MUX, 0, 0,
1219                 STM32F4_RCC_APB2ENR, 26,
1220                 CLK_SET_RATE_PARENT
1221         },
1222         {
1223                 CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
1224                 STM32F4_RCC_CFGR, 23, 1,
1225                 NO_GATE, 0,
1226                 CLK_SET_RATE_PARENT
1227         },
1228         {
1229                 CLK_SAI1, "sai1-a", sai_parents, ARRAY_SIZE(sai_parents),
1230                 STM32F4_RCC_DCKCFGR, 20, 3,
1231                 STM32F4_RCC_APB2ENR, 22,
1232                 CLK_SET_RATE_PARENT
1233         },
1234         {
1235                 CLK_SAI2, "sai1-b", sai_parents, ARRAY_SIZE(sai_parents),
1236                 STM32F4_RCC_DCKCFGR, 22, 3,
1237                 STM32F4_RCC_APB2ENR, 22,
1238                 CLK_SET_RATE_PARENT
1239         },
1240         {
1241                 NO_IDX, "pll48", pll48_parents, ARRAY_SIZE(pll48_parents),
1242                 STM32F4_RCC_DCKCFGR, 27, 1,
1243                 NO_GATE, 0,
1244                 0
1245         },
1246         {
1247                 NO_IDX, "sdmux", sdmux_parents, ARRAY_SIZE(sdmux_parents),
1248                 STM32F4_RCC_DCKCFGR, 28, 1,
1249                 NO_GATE, 0,
1250                 0
1251         },
1252         {
1253                 CLK_F469_DSI, "dsi", dsi_parent, ARRAY_SIZE(dsi_parent),
1254                 STM32F4_RCC_DCKCFGR, 29, 1,
1255                 STM32F4_RCC_APB2ENR, 27,
1256                 CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT
1257         },
1258 };
1259
1260 static const struct stm32_aux_clk stm32f746_aux_clk[] = {
1261         {
1262                 CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1263                 NO_MUX, 0, 0,
1264                 STM32F4_RCC_APB2ENR, 26,
1265                 CLK_SET_RATE_PARENT
1266         },
1267         {
1268                 CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
1269                 STM32F4_RCC_CFGR, 23, 1,
1270                 NO_GATE, 0,
1271                 CLK_SET_RATE_PARENT
1272         },
1273         {
1274                 CLK_SAI1, "sai1_clk", sai_parents, ARRAY_SIZE(sai_parents),
1275                 STM32F4_RCC_DCKCFGR, 20, 3,
1276                 STM32F4_RCC_APB2ENR, 22,
1277                 CLK_SET_RATE_PARENT
1278         },
1279         {
1280                 CLK_SAI2, "sai2_clk", sai_parents, ARRAY_SIZE(sai_parents),
1281                 STM32F4_RCC_DCKCFGR, 22, 3,
1282                 STM32F4_RCC_APB2ENR, 23,
1283                 CLK_SET_RATE_PARENT
1284         },
1285         {
1286                 NO_IDX, "pll48", pll48_parents, ARRAY_SIZE(pll48_parents),
1287                 STM32F7_RCC_DCKCFGR2, 27, 1,
1288                 NO_GATE, 0,
1289                 0
1290         },
1291         {
1292                 NO_IDX, "sdmux", sdmux_parents, ARRAY_SIZE(sdmux_parents),
1293                 STM32F7_RCC_DCKCFGR2, 28, 1,
1294                 NO_GATE, 0,
1295                 0
1296         },
1297         {
1298                 CLK_HDMI_CEC, "hdmi-cec",
1299                 hdmi_parents, ARRAY_SIZE(hdmi_parents),
1300                 STM32F7_RCC_DCKCFGR2, 26, 1,
1301                 NO_GATE, 0,
1302                 0
1303         },
1304         {
1305                 CLK_SPDIF, "spdif-rx",
1306                 spdif_parent, ARRAY_SIZE(spdif_parent),
1307                 STM32F7_RCC_DCKCFGR2, 22, 3,
1308                 STM32F4_RCC_APB2ENR, 23,
1309                 CLK_SET_RATE_PARENT
1310         },
1311         {
1312                 CLK_USART1, "usart1",
1313                 uart_parents1, ARRAY_SIZE(uart_parents1),
1314                 STM32F7_RCC_DCKCFGR2, 0, 3,
1315                 STM32F4_RCC_APB2ENR, 4,
1316                 CLK_SET_RATE_PARENT,
1317         },
1318         {
1319                 CLK_USART2, "usart2",
1320                 uart_parents2, ARRAY_SIZE(uart_parents1),
1321                 STM32F7_RCC_DCKCFGR2, 2, 3,
1322                 STM32F4_RCC_APB1ENR, 17,
1323                 CLK_SET_RATE_PARENT,
1324         },
1325         {
1326                 CLK_USART3, "usart3",
1327                 uart_parents2, ARRAY_SIZE(uart_parents1),
1328                 STM32F7_RCC_DCKCFGR2, 4, 3,
1329                 STM32F4_RCC_APB1ENR, 18,
1330                 CLK_SET_RATE_PARENT,
1331         },
1332         {
1333                 CLK_UART4, "uart4",
1334                 uart_parents2, ARRAY_SIZE(uart_parents1),
1335                 STM32F7_RCC_DCKCFGR2, 6, 3,
1336                 STM32F4_RCC_APB1ENR, 19,
1337                 CLK_SET_RATE_PARENT,
1338         },
1339         {
1340                 CLK_UART5, "uart5",
1341                 uart_parents2, ARRAY_SIZE(uart_parents1),
1342                 STM32F7_RCC_DCKCFGR2, 8, 3,
1343                 STM32F4_RCC_APB1ENR, 20,
1344                 CLK_SET_RATE_PARENT,
1345         },
1346         {
1347                 CLK_USART6, "usart6",
1348                 uart_parents1, ARRAY_SIZE(uart_parents1),
1349                 STM32F7_RCC_DCKCFGR2, 10, 3,
1350                 STM32F4_RCC_APB2ENR, 5,
1351                 CLK_SET_RATE_PARENT,
1352         },
1353
1354         {
1355                 CLK_UART7, "uart7",
1356                 uart_parents2, ARRAY_SIZE(uart_parents1),
1357                 STM32F7_RCC_DCKCFGR2, 12, 3,
1358                 STM32F4_RCC_APB1ENR, 30,
1359                 CLK_SET_RATE_PARENT,
1360         },
1361         {
1362                 CLK_UART8, "uart8",
1363                 uart_parents2, ARRAY_SIZE(uart_parents1),
1364                 STM32F7_RCC_DCKCFGR2, 14, 3,
1365                 STM32F4_RCC_APB1ENR, 31,
1366                 CLK_SET_RATE_PARENT,
1367         },
1368         {
1369                 CLK_I2C1, "i2c1",
1370                 i2c_parents, ARRAY_SIZE(i2c_parents),
1371                 STM32F7_RCC_DCKCFGR2, 16, 3,
1372                 STM32F4_RCC_APB1ENR, 21,
1373                 CLK_SET_RATE_PARENT,
1374         },
1375         {
1376                 CLK_I2C2, "i2c2",
1377                 i2c_parents, ARRAY_SIZE(i2c_parents),
1378                 STM32F7_RCC_DCKCFGR2, 18, 3,
1379                 STM32F4_RCC_APB1ENR, 22,
1380                 CLK_SET_RATE_PARENT,
1381         },
1382         {
1383                 CLK_I2C3, "i2c3",
1384                 i2c_parents, ARRAY_SIZE(i2c_parents),
1385                 STM32F7_RCC_DCKCFGR2, 20, 3,
1386                 STM32F4_RCC_APB1ENR, 23,
1387                 CLK_SET_RATE_PARENT,
1388         },
1389         {
1390                 CLK_I2C4, "i2c4",
1391                 i2c_parents, ARRAY_SIZE(i2c_parents),
1392                 STM32F7_RCC_DCKCFGR2, 22, 3,
1393                 STM32F4_RCC_APB1ENR, 24,
1394                 CLK_SET_RATE_PARENT,
1395         },
1396
1397         {
1398                 CLK_LPTIMER, "lptim1",
1399                 lptim_parent, ARRAY_SIZE(lptim_parent),
1400                 STM32F7_RCC_DCKCFGR2, 24, 3,
1401                 STM32F4_RCC_APB1ENR, 9,
1402                 CLK_SET_RATE_PARENT
1403         },
1404 };
1405
1406 static const struct stm32_aux_clk stm32f769_aux_clk[] = {
1407         {
1408                 CLK_LCD, "lcd-tft", lcd_parent, ARRAY_SIZE(lcd_parent),
1409                 NO_MUX, 0, 0,
1410                 STM32F4_RCC_APB2ENR, 26,
1411                 CLK_SET_RATE_PARENT
1412         },
1413         {
1414                 CLK_I2S, "i2s", i2s_parents, ARRAY_SIZE(i2s_parents),
1415                 STM32F4_RCC_CFGR, 23, 1,
1416                 NO_GATE, 0,
1417                 CLK_SET_RATE_PARENT
1418         },
1419         {
1420                 CLK_SAI1, "sai1_clk", sai_parents, ARRAY_SIZE(sai_parents),
1421                 STM32F4_RCC_DCKCFGR, 20, 3,
1422                 STM32F4_RCC_APB2ENR, 22,
1423                 CLK_SET_RATE_PARENT
1424         },
1425         {
1426                 CLK_SAI2, "sai2_clk", sai_parents, ARRAY_SIZE(sai_parents),
1427                 STM32F4_RCC_DCKCFGR, 22, 3,
1428                 STM32F4_RCC_APB2ENR, 23,
1429                 CLK_SET_RATE_PARENT
1430         },
1431         {
1432                 NO_IDX, "pll48", pll48_parents, ARRAY_SIZE(pll48_parents),
1433                 STM32F7_RCC_DCKCFGR2, 27, 1,
1434                 NO_GATE, 0,
1435                 0
1436         },
1437         {
1438                 NO_IDX, "sdmux1", sdmux_parents, ARRAY_SIZE(sdmux_parents),
1439                 STM32F7_RCC_DCKCFGR2, 28, 1,
1440                 NO_GATE, 0,
1441                 0
1442         },
1443         {
1444                 NO_IDX, "sdmux2", sdmux_parents, ARRAY_SIZE(sdmux_parents),
1445                 STM32F7_RCC_DCKCFGR2, 29, 1,
1446                 NO_GATE, 0,
1447                 0
1448         },
1449         {
1450                 CLK_HDMI_CEC, "hdmi-cec",
1451                 hdmi_parents, ARRAY_SIZE(hdmi_parents),
1452                 STM32F7_RCC_DCKCFGR2, 26, 1,
1453                 NO_GATE, 0,
1454                 0
1455         },
1456         {
1457                 CLK_SPDIF, "spdif-rx",
1458                 spdif_parent, ARRAY_SIZE(spdif_parent),
1459                 STM32F7_RCC_DCKCFGR2, 22, 3,
1460                 STM32F4_RCC_APB2ENR, 23,
1461                 CLK_SET_RATE_PARENT
1462         },
1463         {
1464                 CLK_USART1, "usart1",
1465                 uart_parents1, ARRAY_SIZE(uart_parents1),
1466                 STM32F7_RCC_DCKCFGR2, 0, 3,
1467                 STM32F4_RCC_APB2ENR, 4,
1468                 CLK_SET_RATE_PARENT,
1469         },
1470         {
1471                 CLK_USART2, "usart2",
1472                 uart_parents2, ARRAY_SIZE(uart_parents1),
1473                 STM32F7_RCC_DCKCFGR2, 2, 3,
1474                 STM32F4_RCC_APB1ENR, 17,
1475                 CLK_SET_RATE_PARENT,
1476         },
1477         {
1478                 CLK_USART3, "usart3",
1479                 uart_parents2, ARRAY_SIZE(uart_parents1),
1480                 STM32F7_RCC_DCKCFGR2, 4, 3,
1481                 STM32F4_RCC_APB1ENR, 18,
1482                 CLK_SET_RATE_PARENT,
1483         },
1484         {
1485                 CLK_UART4, "uart4",
1486                 uart_parents2, ARRAY_SIZE(uart_parents1),
1487                 STM32F7_RCC_DCKCFGR2, 6, 3,
1488                 STM32F4_RCC_APB1ENR, 19,
1489                 CLK_SET_RATE_PARENT,
1490         },
1491         {
1492                 CLK_UART5, "uart5",
1493                 uart_parents2, ARRAY_SIZE(uart_parents1),
1494                 STM32F7_RCC_DCKCFGR2, 8, 3,
1495                 STM32F4_RCC_APB1ENR, 20,
1496                 CLK_SET_RATE_PARENT,
1497         },
1498         {
1499                 CLK_USART6, "usart6",
1500                 uart_parents1, ARRAY_SIZE(uart_parents1),
1501                 STM32F7_RCC_DCKCFGR2, 10, 3,
1502                 STM32F4_RCC_APB2ENR, 5,
1503                 CLK_SET_RATE_PARENT,
1504         },
1505         {
1506                 CLK_UART7, "uart7",
1507                 uart_parents2, ARRAY_SIZE(uart_parents1),
1508                 STM32F7_RCC_DCKCFGR2, 12, 3,
1509                 STM32F4_RCC_APB1ENR, 30,
1510                 CLK_SET_RATE_PARENT,
1511         },
1512         {
1513                 CLK_UART8, "uart8",
1514                 uart_parents2, ARRAY_SIZE(uart_parents1),
1515                 STM32F7_RCC_DCKCFGR2, 14, 3,
1516                 STM32F4_RCC_APB1ENR, 31,
1517                 CLK_SET_RATE_PARENT,
1518         },
1519         {
1520                 CLK_I2C1, "i2c1",
1521                 i2c_parents, ARRAY_SIZE(i2c_parents),
1522                 STM32F7_RCC_DCKCFGR2, 16, 3,
1523                 STM32F4_RCC_APB1ENR, 21,
1524                 CLK_SET_RATE_PARENT,
1525         },
1526         {
1527                 CLK_I2C2, "i2c2",
1528                 i2c_parents, ARRAY_SIZE(i2c_parents),
1529                 STM32F7_RCC_DCKCFGR2, 18, 3,
1530                 STM32F4_RCC_APB1ENR, 22,
1531                 CLK_SET_RATE_PARENT,
1532         },
1533         {
1534                 CLK_I2C3, "i2c3",
1535                 i2c_parents, ARRAY_SIZE(i2c_parents),
1536                 STM32F7_RCC_DCKCFGR2, 20, 3,
1537                 STM32F4_RCC_APB1ENR, 23,
1538                 CLK_SET_RATE_PARENT,
1539         },
1540         {
1541                 CLK_I2C4, "i2c4",
1542                 i2c_parents, ARRAY_SIZE(i2c_parents),
1543                 STM32F7_RCC_DCKCFGR2, 22, 3,
1544                 STM32F4_RCC_APB1ENR, 24,
1545                 CLK_SET_RATE_PARENT,
1546         },
1547         {
1548                 CLK_LPTIMER, "lptim1",
1549                 lptim_parent, ARRAY_SIZE(lptim_parent),
1550                 STM32F7_RCC_DCKCFGR2, 24, 3,
1551                 STM32F4_RCC_APB1ENR, 9,
1552                 CLK_SET_RATE_PARENT
1553         },
1554         {
1555                 CLK_F769_DSI, "dsi",
1556                 dsi_parent, ARRAY_SIZE(dsi_parent),
1557                 STM32F7_RCC_DCKCFGR2, 0, 1,
1558                 STM32F4_RCC_APB2ENR, 27,
1559                 CLK_SET_RATE_PARENT
1560         },
1561         {
1562                 CLK_DFSDM1, "dfsdm1",
1563                 dfsdm1_src, ARRAY_SIZE(dfsdm1_src),
1564                 STM32F4_RCC_DCKCFGR, 25, 1,
1565                 STM32F4_RCC_APB2ENR, 29,
1566                 CLK_SET_RATE_PARENT
1567         },
1568         {
1569                 CLK_ADFSDM1, "adfsdm1",
1570                 adsfdm1_parent, ARRAY_SIZE(adsfdm1_parent),
1571                 STM32F4_RCC_DCKCFGR, 26, 1,
1572                 STM32F4_RCC_APB2ENR, 29,
1573                 CLK_SET_RATE_PARENT
1574         },
1575 };
1576
1577 static const struct stm32f4_clk_data stm32f429_clk_data = {
1578         .end_primary    = END_PRIMARY_CLK,
1579         .gates_data     = stm32f429_gates,
1580         .gates_map      = stm32f42xx_gate_map,
1581         .gates_num      = ARRAY_SIZE(stm32f429_gates),
1582         .pll_data       = stm32f429_pll,
1583         .aux_clk        = stm32f429_aux_clk,
1584         .aux_clk_num    = ARRAY_SIZE(stm32f429_aux_clk),
1585 };
1586
1587 static const struct stm32f4_clk_data stm32f469_clk_data = {
1588         .end_primary    = END_PRIMARY_CLK,
1589         .gates_data     = stm32f469_gates,
1590         .gates_map      = stm32f46xx_gate_map,
1591         .gates_num      = ARRAY_SIZE(stm32f469_gates),
1592         .pll_data       = stm32f469_pll,
1593         .aux_clk        = stm32f469_aux_clk,
1594         .aux_clk_num    = ARRAY_SIZE(stm32f469_aux_clk),
1595 };
1596
1597 static const struct stm32f4_clk_data stm32f746_clk_data = {
1598         .end_primary    = END_PRIMARY_CLK_F7,
1599         .gates_data     = stm32f746_gates,
1600         .gates_map      = stm32f746_gate_map,
1601         .gates_num      = ARRAY_SIZE(stm32f746_gates),
1602         .pll_data       = stm32f469_pll,
1603         .aux_clk        = stm32f746_aux_clk,
1604         .aux_clk_num    = ARRAY_SIZE(stm32f746_aux_clk),
1605 };
1606
1607 static const struct stm32f4_clk_data stm32f769_clk_data = {
1608         .end_primary    = END_PRIMARY_CLK_F7,
1609         .gates_data     = stm32f769_gates,
1610         .gates_map      = stm32f769_gate_map,
1611         .gates_num      = ARRAY_SIZE(stm32f769_gates),
1612         .pll_data       = stm32f469_pll,
1613         .aux_clk        = stm32f769_aux_clk,
1614         .aux_clk_num    = ARRAY_SIZE(stm32f769_aux_clk),
1615 };
1616
1617 static const struct of_device_id stm32f4_of_match[] = {
1618         {
1619                 .compatible = "st,stm32f42xx-rcc",
1620                 .data = &stm32f429_clk_data
1621         },
1622         {
1623                 .compatible = "st,stm32f469-rcc",
1624                 .data = &stm32f469_clk_data
1625         },
1626         {
1627                 .compatible = "st,stm32f746-rcc",
1628                 .data = &stm32f746_clk_data
1629         },
1630         {
1631                 .compatible = "st,stm32f769-rcc",
1632                 .data = &stm32f769_clk_data
1633         },
1634         {}
1635 };
1636
1637 static struct clk_hw *stm32_register_aux_clk(const char *name,
1638                 const char * const *parent_names, int num_parents,
1639                 int offset_mux, u8 shift, u8 mask,
1640                 int offset_gate, u8 bit_idx,
1641                 unsigned long flags, spinlock_t *lock)
1642 {
1643         struct clk_hw *hw;
1644         struct clk_gate *gate = NULL;
1645         struct clk_mux *mux = NULL;
1646         struct clk_hw *mux_hw = NULL, *gate_hw = NULL;
1647         const struct clk_ops *mux_ops = NULL, *gate_ops = NULL;
1648
1649         if (offset_gate != NO_GATE) {
1650                 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
1651                 if (!gate) {
1652                         hw = ERR_PTR(-EINVAL);
1653                         goto fail;
1654                 }
1655
1656                 gate->reg = base + offset_gate;
1657                 gate->bit_idx = bit_idx;
1658                 gate->flags = 0;
1659                 gate->lock = lock;
1660                 gate_hw = &gate->hw;
1661                 gate_ops = &clk_gate_ops;
1662         }
1663
1664         if (offset_mux != NO_MUX) {
1665                 mux = kzalloc(sizeof(*mux), GFP_KERNEL);
1666                 if (!mux) {
1667                         hw = ERR_PTR(-EINVAL);
1668                         goto fail;
1669                 }
1670
1671                 mux->reg = base + offset_mux;
1672                 mux->shift = shift;
1673                 mux->mask = mask;
1674                 mux->flags = 0;
1675                 mux_hw = &mux->hw;
1676                 mux_ops = &clk_mux_ops;
1677         }
1678
1679         if (mux_hw == NULL && gate_hw == NULL) {
1680                 hw = ERR_PTR(-EINVAL);
1681                 goto fail;
1682         }
1683
1684         hw = clk_hw_register_composite(NULL, name, parent_names, num_parents,
1685                         mux_hw, mux_ops,
1686                         NULL, NULL,
1687                         gate_hw, gate_ops,
1688                         flags);
1689
1690 fail:
1691         if (IS_ERR(hw)) {
1692                 kfree(gate);
1693                 kfree(mux);
1694         }
1695
1696         return hw;
1697 }
1698
1699 static void __init stm32f4_rcc_init(struct device_node *np)
1700 {
1701         const char *hse_clk, *i2s_in_clk;
1702         int n;
1703         const struct of_device_id *match;
1704         const struct stm32f4_clk_data *data;
1705         unsigned long pllm;
1706         struct clk_hw *pll_src_hw;
1707
1708         base = of_iomap(np, 0);
1709         if (!base) {
1710                 pr_err("%pOFn: unable to map resource\n", np);
1711                 return;
1712         }
1713
1714         pdrm = syscon_regmap_lookup_by_phandle(np, "st,syscfg");
1715         if (IS_ERR(pdrm)) {
1716                 pdrm = NULL;
1717                 pr_warn("%s: Unable to get syscfg\n", __func__);
1718         }
1719
1720         match = of_match_node(stm32f4_of_match, np);
1721         if (WARN_ON(!match))
1722                 return;
1723
1724         data = match->data;
1725
1726         stm32fx_end_primary_clk = data->end_primary;
1727
1728         clks = kmalloc_array(data->gates_num + stm32fx_end_primary_clk,
1729                         sizeof(*clks), GFP_KERNEL);
1730         if (!clks)
1731                 goto fail;
1732
1733         stm32f4_gate_map = data->gates_map;
1734
1735         hse_clk = of_clk_get_parent_name(np, 0);
1736         dsi_parent[0] = hse_clk;
1737         pllsrc_parent[1] = hse_clk;
1738
1739         i2s_in_clk = of_clk_get_parent_name(np, 1);
1740
1741         i2s_parents[1] = i2s_in_clk;
1742         sai_parents[2] = i2s_in_clk;
1743
1744         if (of_device_is_compatible(np, "st,stm32f769-rcc")) {
1745                 clk_hw_register_gate(NULL, "dfsdm1_apb", "apb2_div", 0,
1746                                      base + STM32F4_RCC_APB2ENR, 29,
1747                                      CLK_IGNORE_UNUSED, &stm32f4_clk_lock);
1748                 dsi_parent[0] = pll_src;
1749                 sai_parents[3] = pll_src;
1750         }
1751
1752         clks[CLK_HSI] = clk_hw_register_fixed_rate_with_accuracy(NULL, "hsi",
1753                         NULL, 0, 16000000, 160000);
1754
1755         pll_src_hw = clk_hw_register_mux(NULL, pll_src, pllsrc_parent,
1756                                          ARRAY_SIZE(pllsrc_parent), 0,
1757                                          base + STM32F4_RCC_PLLCFGR, 22, 1, 0,
1758                                          &stm32f4_clk_lock);
1759
1760         pllm = readl(base + STM32F4_RCC_PLLCFGR) & 0x3f;
1761
1762         clk_hw_register_fixed_factor(NULL, "vco_in", pll_src,
1763                                      0, 1, pllm);
1764
1765         stm32f4_rcc_register_pll("vco_in", &data->pll_data[0],
1766                         &stm32f4_clk_lock);
1767
1768         clks[PLL_VCO_I2S] = stm32f4_rcc_register_pll("vco_in",
1769                         &data->pll_data[1], &stm32f4_clk_lock);
1770
1771         clks[PLL_VCO_SAI] = stm32f4_rcc_register_pll("vco_in",
1772                         &data->pll_data[2], &stm32f4_clk_lock);
1773
1774         for (n = 0; n < MAX_POST_DIV; n++) {
1775                 const struct stm32f4_pll_post_div_data *post_div;
1776                 struct clk_hw *hw;
1777
1778                 post_div = &post_div_data[n];
1779
1780                 hw = clk_register_pll_div(post_div->name,
1781                                 post_div->parent,
1782                                 post_div->flag,
1783                                 base + post_div->offset,
1784                                 post_div->shift,
1785                                 post_div->width,
1786                                 post_div->flag_div,
1787                                 post_div->div_table,
1788                                 clks[post_div->pll_num],
1789                                 &stm32f4_clk_lock);
1790
1791                 if (post_div->idx != NO_IDX)
1792                         clks[post_div->idx] = hw;
1793         }
1794
1795         sys_parents[1] = hse_clk;
1796
1797         clks[CLK_SYSCLK] = clk_hw_register_mux_table(
1798             NULL, "sys", sys_parents, ARRAY_SIZE(sys_parents), 0,
1799             base + STM32F4_RCC_CFGR, 0, 3, 0, NULL, &stm32f4_clk_lock);
1800
1801         clk_register_divider_table(NULL, "ahb_div", "sys",
1802                                    CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
1803                                    4, 4, 0, ahb_div_table, &stm32f4_clk_lock);
1804
1805         clk_register_divider_table(NULL, "apb1_div", "ahb_div",
1806                                    CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
1807                                    10, 3, 0, apb_div_table, &stm32f4_clk_lock);
1808         clk_register_apb_mul(NULL, "apb1_mul", "apb1_div",
1809                              CLK_SET_RATE_PARENT, 12);
1810
1811         clk_register_divider_table(NULL, "apb2_div", "ahb_div",
1812                                    CLK_SET_RATE_PARENT, base + STM32F4_RCC_CFGR,
1813                                    13, 3, 0, apb_div_table, &stm32f4_clk_lock);
1814         clk_register_apb_mul(NULL, "apb2_mul", "apb2_div",
1815                              CLK_SET_RATE_PARENT, 15);
1816
1817         clks[SYSTICK] = clk_hw_register_fixed_factor(NULL, "systick", "ahb_div",
1818                                                   0, 1, 8);
1819         clks[FCLK] = clk_hw_register_fixed_factor(NULL, "fclk", "ahb_div",
1820                                                0, 1, 1);
1821
1822         for (n = 0; n < data->gates_num; n++) {
1823                 const struct stm32f4_gate_data *gd;
1824                 unsigned int secondary;
1825                 int idx;
1826
1827                 gd = &data->gates_data[n];
1828                 secondary = 8 * (gd->offset - STM32F4_RCC_AHB1ENR) +
1829                         gd->bit_idx;
1830                 idx = stm32f4_rcc_lookup_clk_idx(0, secondary);
1831
1832                 if (idx < 0)
1833                         goto fail;
1834
1835                 clks[idx] = clk_hw_register_gate(
1836                     NULL, gd->name, gd->parent_name, gd->flags,
1837                     base + gd->offset, gd->bit_idx, 0, &stm32f4_clk_lock);
1838
1839                 if (IS_ERR(clks[idx])) {
1840                         pr_err("%pOF: Unable to register leaf clock %s\n",
1841                                np, gd->name);
1842                         goto fail;
1843                 }
1844         }
1845
1846         clks[CLK_LSI] = clk_register_rgate(NULL, "lsi", "clk-lsi", 0,
1847                         base + STM32F4_RCC_CSR, 0, 1, 0, &stm32f4_clk_lock);
1848
1849         if (IS_ERR(clks[CLK_LSI])) {
1850                 pr_err("Unable to register lsi clock\n");
1851                 goto fail;
1852         }
1853
1854         clks[CLK_LSE] = clk_register_rgate(NULL, "lse", "clk-lse", 0,
1855                         base + STM32F4_RCC_BDCR, 0, 1, 0, &stm32f4_clk_lock);
1856
1857         if (IS_ERR(clks[CLK_LSE])) {
1858                 pr_err("Unable to register lse clock\n");
1859                 goto fail;
1860         }
1861
1862         clks[CLK_HSE_RTC] = clk_hw_register_divider(NULL, "hse-rtc", "clk-hse",
1863                         0, base + STM32F4_RCC_CFGR, 16, 5, 0,
1864                         &stm32f4_clk_lock);
1865
1866         if (IS_ERR(clks[CLK_HSE_RTC])) {
1867                 pr_err("Unable to register hse-rtc clock\n");
1868                 goto fail;
1869         }
1870
1871         clks[CLK_RTC] = stm32_register_cclk(NULL, "rtc", rtc_parents, 4,
1872                         base + STM32F4_RCC_BDCR, 15, 8, 0, &stm32f4_clk_lock);
1873
1874         if (IS_ERR(clks[CLK_RTC])) {
1875                 pr_err("Unable to register rtc clock\n");
1876                 goto fail;
1877         }
1878
1879         for (n = 0; n < data->aux_clk_num; n++) {
1880                 const struct stm32_aux_clk *aux_clk;
1881                 struct clk_hw *hw;
1882
1883                 aux_clk = &data->aux_clk[n];
1884
1885                 hw = stm32_register_aux_clk(aux_clk->name,
1886                                 aux_clk->parent_names, aux_clk->num_parents,
1887                                 aux_clk->offset_mux, aux_clk->shift,
1888                                 aux_clk->mask, aux_clk->offset_gate,
1889                                 aux_clk->bit_idx, aux_clk->flags,
1890                                 &stm32f4_clk_lock);
1891
1892                 if (IS_ERR(hw)) {
1893                         pr_warn("Unable to register %s clk\n", aux_clk->name);
1894                         continue;
1895                 }
1896
1897                 if (aux_clk->idx != NO_IDX)
1898                         clks[aux_clk->idx] = hw;
1899         }
1900
1901         if (of_device_is_compatible(np, "st,stm32f746-rcc")) {
1902
1903                 clk_hw_register_fixed_factor(NULL, "hsi_div488", "hsi", 0,
1904                                 1, 488);
1905
1906                 clks[CLK_PLL_SRC] = pll_src_hw;
1907         }
1908
1909         of_clk_add_hw_provider(np, stm32f4_rcc_lookup_clk, NULL);
1910
1911         return;
1912 fail:
1913         kfree(clks);
1914         iounmap(base);
1915 }
1916 CLK_OF_DECLARE_DRIVER(stm32f42xx_rcc, "st,stm32f42xx-rcc", stm32f4_rcc_init);
1917 CLK_OF_DECLARE_DRIVER(stm32f46xx_rcc, "st,stm32f469-rcc", stm32f4_rcc_init);
1918 CLK_OF_DECLARE_DRIVER(stm32f746_rcc, "st,stm32f746-rcc", stm32f4_rcc_init);
1919 CLK_OF_DECLARE_DRIVER(stm32f769_rcc, "st,stm32f769-rcc", stm32f4_rcc_init);