drivers/gpu/drm/i915/intel_guc.c

   1 /*
   2  * Copyright © 2014-2017 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  */
  24
  25 #include "intel_guc.h"
  26 #include "intel_guc_ads.h"
  27 #include "intel_guc_submission.h"
  28 #include "i915_drv.h"
  29
  30 static void gen8_guc_raise_irq(struct intel_guc *guc)
  31 {
  32         struct drm_i915_private *dev_priv = guc_to_i915(guc);
  33
  34         I915_WRITE(GUC_SEND_INTERRUPT, GUC_SEND_TRIGGER);
  35 }
  36
  37 static inline i915_reg_t guc_send_reg(struct intel_guc *guc, u32 i)
  38 {
  39         GEM_BUG_ON(!guc->send_regs.base);
  40         GEM_BUG_ON(!guc->send_regs.count);
  41         GEM_BUG_ON(i >= guc->send_regs.count);
  42
  43         return _MMIO(guc->send_regs.base + 4 * i);
  44 }
  45
  46 void intel_guc_init_send_regs(struct intel_guc *guc)
  47 {
  48         struct drm_i915_private *dev_priv = guc_to_i915(guc);
  49         enum forcewake_domains fw_domains = 0;
  50         unsigned int i;
  51
  52         guc->send_regs.base = i915_mmio_reg_offset(SOFT_SCRATCH(0));
  53         guc->send_regs.count = SOFT_SCRATCH_COUNT - 1;
  54
  55         for (i = 0; i < guc->send_regs.count; i++) {
  56                 fw_domains |= intel_uncore_forcewake_for_reg(dev_priv,
  57                                         guc_send_reg(guc, i),
  58                                         FW_REG_READ | FW_REG_WRITE);
  59         }
  60         guc->send_regs.fw_domains = fw_domains;
  61 }
  62
  63 void intel_guc_init_early(struct intel_guc *guc)
  64 {
  65         intel_guc_fw_init_early(guc);
  66         intel_guc_ct_init_early(&guc->ct);
  67         intel_guc_log_init_early(&guc->log);
  68
  69         mutex_init(&guc->send_mutex);
  70         spin_lock_init(&guc->irq_lock);
  71         guc->send = intel_guc_send_nop;
  72         guc->handler = intel_guc_to_host_event_handler_nop;
  73         guc->notify = gen8_guc_raise_irq;
  74 }
  75
  76 int intel_guc_init_wq(struct intel_guc *guc)
  77 {
  78         struct drm_i915_private *dev_priv = guc_to_i915(guc);
  79
  80         /*
  81          * GuC log buffer flush work item has to do register access to
  82          * send the ack to GuC and this work item, if not synced before
  83          * suspend, can potentially get executed after the GFX device is
  84          * suspended.
  85          * By marking the WQ as freezable, we don't have to bother about
  86          * flushing of this work item from the suspend hooks, the pending
  87          * work item if any will be either executed before the suspend
  88          * or scheduled later on resume. This way the handling of work
  89          * item can be kept same between system suspend & rpm suspend.
  90          */
  91         guc->log.relay.flush_wq =
  92                 alloc_ordered_workqueue("i915-guc_log",
  93                                         WQ_HIGHPRI | WQ_FREEZABLE);
  94         if (!guc->log.relay.flush_wq) {
  95                 DRM_ERROR("Couldn't allocate workqueue for GuC log\n");
  96                 return -ENOMEM;
  97         }
  98
  99         /*
 100          * Even though both sending GuC action, and adding a new workitem to
 101          * GuC workqueue are serialized (each with its own locking), since
 102          * we're using mutliple engines, it's possible that we're going to
 103          * issue a preempt request with two (or more - each for different
 104          * engine) workitems in GuC queue. In this situation, GuC may submit
 105          * all of them, which will make us very confused.
 106          * Our preemption contexts may even already be complete - before we
 107          * even had the chance to sent the preempt action to GuC!. Rather
 108          * than introducing yet another lock, we can just use ordered workqueue
 109          * to make sure we're always sending a single preemption request with a
 110          * single workitem.
 111          */
 112         if (HAS_LOGICAL_RING_PREEMPTION(dev_priv) &&
 113             USES_GUC_SUBMISSION(dev_priv)) {
 114                 guc->preempt_wq = alloc_ordered_workqueue("i915-guc_preempt",
 115                                                           WQ_HIGHPRI);
 116                 if (!guc->preempt_wq) {
 117                         destroy_workqueue(guc->log.relay.flush_wq);
 118                         DRM_ERROR("Couldn't allocate workqueue for GuC "
 119                                   "preemption\n");
 120                         return -ENOMEM;
 121                 }
 122         }
 123
 124         return 0;
 125 }
 126
 127 void intel_guc_fini_wq(struct intel_guc *guc)
 128 {
 129         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 130
 131         if (HAS_LOGICAL_RING_PREEMPTION(dev_priv) &&
 132             USES_GUC_SUBMISSION(dev_priv))
 133                 destroy_workqueue(guc->preempt_wq);
 134
 135         destroy_workqueue(guc->log.relay.flush_wq);
 136 }
 137
 138 static int guc_shared_data_create(struct intel_guc *guc)
 139 {
 140         struct i915_vma *vma;
 141         void *vaddr;
 142
 143         vma = intel_guc_allocate_vma(guc, PAGE_SIZE);
 144         if (IS_ERR(vma))
 145                 return PTR_ERR(vma);
 146
 147         vaddr = i915_gem_object_pin_map(vma->obj, I915_MAP_WB);
 148         if (IS_ERR(vaddr)) {
 149                 i915_vma_unpin_and_release(&vma);
 150                 return PTR_ERR(vaddr);
 151         }
 152
 153         guc->shared_data = vma;
 154         guc->shared_data_vaddr = vaddr;
 155
 156         return 0;
 157 }
 158
 159 static void guc_shared_data_destroy(struct intel_guc *guc)
 160 {
 161         i915_gem_object_unpin_map(guc->shared_data->obj);
 162         i915_vma_unpin_and_release(&guc->shared_data);
 163 }
 164
 165 int intel_guc_init(struct intel_guc *guc)
 166 {
 167         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 168         int ret;
 169
 170         ret = guc_shared_data_create(guc);
 171         if (ret)
 172                 return ret;
 173         GEM_BUG_ON(!guc->shared_data);
 174
 175         ret = intel_guc_log_create(&guc->log);
 176         if (ret)
 177                 goto err_shared;
 178
 179         ret = intel_guc_ads_create(guc);
 180         if (ret)
 181                 goto err_log;
 182         GEM_BUG_ON(!guc->ads_vma);
 183
 184         /* We need to notify the guc whenever we change the GGTT */
 185         i915_ggtt_enable_guc(dev_priv);
 186
 187         return 0;
 188
 189 err_log:
 190         intel_guc_log_destroy(&guc->log);
 191 err_shared:
 192         guc_shared_data_destroy(guc);
 193         return ret;
 194 }
 195
 196 void intel_guc_fini(struct intel_guc *guc)
 197 {
 198         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 199
 200         i915_ggtt_disable_guc(dev_priv);
 201         intel_guc_ads_destroy(guc);
 202         intel_guc_log_destroy(&guc->log);
 203         guc_shared_data_destroy(guc);
 204 }
 205
 206 static u32 get_log_control_flags(void)
 207 {
 208         u32 level = i915_modparams.guc_log_level;
 209         u32 flags = 0;
 210
 211         GEM_BUG_ON(level < 0);
 212
 213         if (!GUC_LOG_LEVEL_IS_ENABLED(level))
 214                 flags |= GUC_LOG_DEFAULT_DISABLED;
 215
 216         if (!GUC_LOG_LEVEL_IS_VERBOSE(level))
 217                 flags |= GUC_LOG_DISABLED;
 218         else
 219                 flags |= GUC_LOG_LEVEL_TO_VERBOSITY(level) <<
 220                          GUC_LOG_VERBOSITY_SHIFT;
 221
 222         return flags;
 223 }
 224
 225 /*
 226  * Initialise the GuC parameter block before starting the firmware
 227  * transfer. These parameters are read by the firmware on startup
 228  * and cannot be changed thereafter.
 229  */
 230 void intel_guc_init_params(struct intel_guc *guc)
 231 {
 232         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 233         u32 params[GUC_CTL_MAX_DWORDS];
 234         int i;
 235
 236         memset(params, 0, sizeof(params));
 237
 238         /*
 239          * GuC ARAT increment is 10 ns. GuC default scheduler quantum is one
 240          * second. This ARAR is calculated by:
 241          * Scheduler-Quantum-in-ns / ARAT-increment-in-ns = 1000000000 / 10
 242          */
 243         params[GUC_CTL_ARAT_HIGH] = 0;
 244         params[GUC_CTL_ARAT_LOW] = 100000000;
 245
 246         params[GUC_CTL_WA] |= GUC_CTL_WA_UK_BY_DRIVER;
 247
 248         params[GUC_CTL_FEATURE] |= GUC_CTL_DISABLE_SCHEDULER |
 249                         GUC_CTL_VCS2_ENABLED;
 250
 251         params[GUC_CTL_LOG_PARAMS] = guc->log.flags;
 252
 253         params[GUC_CTL_DEBUG] = get_log_control_flags();
 254
 255         /* If GuC submission is enabled, set up additional parameters here */
 256         if (USES_GUC_SUBMISSION(dev_priv)) {
 257                 u32 ads = intel_guc_ggtt_offset(guc,
 258                                                 guc->ads_vma) >> PAGE_SHIFT;
 259                 u32 pgs = intel_guc_ggtt_offset(guc, guc->stage_desc_pool);
 260                 u32 ctx_in_16 = GUC_MAX_STAGE_DESCRIPTORS / 16;
 261
 262                 params[GUC_CTL_DEBUG] |= ads << GUC_ADS_ADDR_SHIFT;
 263                 params[GUC_CTL_DEBUG] |= GUC_ADS_ENABLED;
 264
 265                 pgs >>= PAGE_SHIFT;
 266                 params[GUC_CTL_CTXINFO] = (pgs << GUC_CTL_BASE_ADDR_SHIFT) |
 267                         (ctx_in_16 << GUC_CTL_CTXNUM_IN16_SHIFT);
 268
 269                 params[GUC_CTL_FEATURE] |= GUC_CTL_KERNEL_SUBMISSIONS;
 270
 271                 /* Unmask this bit to enable the GuC's internal scheduler */
 272                 params[GUC_CTL_FEATURE] &= ~GUC_CTL_DISABLE_SCHEDULER;
 273         }
 274
 275         /*
 276          * All SOFT_SCRATCH registers are in FORCEWAKE_BLITTER domain and
 277          * they are power context saved so it's ok to release forcewake
 278          * when we are done here and take it again at xfer time.
 279          */
 280         intel_uncore_forcewake_get(dev_priv, FORCEWAKE_BLITTER);
 281
 282         I915_WRITE(SOFT_SCRATCH(0), 0);
 283
 284         for (i = 0; i < GUC_CTL_MAX_DWORDS; i++)
 285                 I915_WRITE(SOFT_SCRATCH(1 + i), params[i]);
 286
 287         intel_uncore_forcewake_put(dev_priv, FORCEWAKE_BLITTER);
 288 }
 289
 290 int intel_guc_send_nop(struct intel_guc *guc, const u32 *action, u32 len,
 291                        u32 *response_buf, u32 response_buf_size)
 292 {
 293         WARN(1, "Unexpected send: action=%#x\n", *action);
 294         return -ENODEV;
 295 }
 296
 297 void intel_guc_to_host_event_handler_nop(struct intel_guc *guc)
 298 {
 299         WARN(1, "Unexpected event: no suitable handler\n");
 300 }
 301
 302 /*
 303  * This function implements the MMIO based host to GuC interface.
 304  */
 305 int intel_guc_send_mmio(struct intel_guc *guc, const u32 *action, u32 len,
 306                         u32 *response_buf, u32 response_buf_size)
 307 {
 308         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 309         u32 status;
 310         int i;
 311         int ret;
 312
 313         GEM_BUG_ON(!len);
 314         GEM_BUG_ON(len > guc->send_regs.count);
 315
 316         /* We expect only action code */
 317         GEM_BUG_ON(*action & ~INTEL_GUC_MSG_CODE_MASK);
 318
 319         /* If CT is available, we expect to use MMIO only during init/fini */
 320         GEM_BUG_ON(HAS_GUC_CT(dev_priv) &&
 321                 *action != INTEL_GUC_ACTION_REGISTER_COMMAND_TRANSPORT_BUFFER &&
 322                 *action != INTEL_GUC_ACTION_DEREGISTER_COMMAND_TRANSPORT_BUFFER);
 323
 324         mutex_lock(&guc->send_mutex);
 325         intel_uncore_forcewake_get(dev_priv, guc->send_regs.fw_domains);
 326
 327         for (i = 0; i < len; i++)
 328                 I915_WRITE(guc_send_reg(guc, i), action[i]);
 329
 330         POSTING_READ(guc_send_reg(guc, i - 1));
 331
 332         intel_guc_notify(guc);
 333
 334         /*
 335          * No GuC command should ever take longer than 10ms.
 336          * Fast commands should still complete in 10us.
 337          */
 338         ret = __intel_wait_for_register_fw(dev_priv,
 339                                            guc_send_reg(guc, 0),
 340                                            INTEL_GUC_MSG_TYPE_MASK,
 341                                            INTEL_GUC_MSG_TYPE_RESPONSE <<
 342                                            INTEL_GUC_MSG_TYPE_SHIFT,
 343                                            10, 10, &status);
 344         /* If GuC explicitly returned an error, convert it to -EIO */
 345         if (!ret && !INTEL_GUC_MSG_IS_RESPONSE_SUCCESS(status))
 346                 ret = -EIO;
 347
 348         if (ret) {
 349                 DRM_DEBUG_DRIVER("INTEL_GUC_SEND: Action 0x%X failed;"
 350                                  " ret=%d status=0x%08X response=0x%08X\n",
 351                                  action[0], ret, status,
 352                                  I915_READ(SOFT_SCRATCH(15)));
 353                 goto out;
 354         }
 355
 356         if (response_buf) {
 357                 int count = min(response_buf_size, guc->send_regs.count - 1);
 358
 359                 for (i = 0; i < count; i++)
 360                         response_buf[i] = I915_READ(guc_send_reg(guc, i + 1));
 361         }
 362
 363         /* Use data from the GuC response as our return value */
 364         ret = INTEL_GUC_MSG_TO_DATA(status);
 365
 366 out:
 367         intel_uncore_forcewake_put(dev_priv, guc->send_regs.fw_domains);
 368         mutex_unlock(&guc->send_mutex);
 369
 370         return ret;
 371 }
 372
 373 void intel_guc_to_host_event_handler_mmio(struct intel_guc *guc)
 374 {
 375         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 376         u32 msg, val;
 377
 378         /*
 379          * Sample the log buffer flush related bits & clear them out now
 380          * itself from the message identity register to minimize the
 381          * probability of losing a flush interrupt, when there are back
 382          * to back flush interrupts.
 383          * There can be a new flush interrupt, for different log buffer
 384          * type (like for ISR), whilst Host is handling one (for DPC).
 385          * Since same bit is used in message register for ISR & DPC, it
 386          * could happen that GuC sets the bit for 2nd interrupt but Host
 387          * clears out the bit on handling the 1st interrupt.
 388          */
 389         spin_lock(&guc->irq_lock);
 390         val = I915_READ(SOFT_SCRATCH(15));
 391         msg = val & guc->msg_enabled_mask;
 392         I915_WRITE(SOFT_SCRATCH(15), val & ~msg);
 393         spin_unlock(&guc->irq_lock);
 394
 395         intel_guc_to_host_process_recv_msg(guc, msg);
 396 }
 397
 398 void intel_guc_to_host_process_recv_msg(struct intel_guc *guc, u32 msg)
 399 {
 400         /* Make sure to handle only enabled messages */
 401         msg &= guc->msg_enabled_mask;
 402
 403         if (msg & (INTEL_GUC_RECV_MSG_FLUSH_LOG_BUFFER |
 404                    INTEL_GUC_RECV_MSG_CRASH_DUMP_POSTED))
 405                 intel_guc_log_handle_flush_event(&guc->log);
 406 }
 407
 408 int intel_guc_sample_forcewake(struct intel_guc *guc)
 409 {
 410         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 411         u32 action[2];
 412
 413         action[0] = INTEL_GUC_ACTION_SAMPLE_FORCEWAKE;
 414         /* WaRsDisableCoarsePowerGating:skl,cnl */
 415         if (!HAS_RC6(dev_priv) || NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
 416                 action[1] = 0;
 417         else
 418                 /* bit 0 and 1 are for Render and Media domain separately */
 419                 action[1] = GUC_FORCEWAKE_RENDER | GUC_FORCEWAKE_MEDIA;
 420
 421         return intel_guc_send(guc, action, ARRAY_SIZE(action));
 422 }
 423
 424 /**
 425  * intel_guc_auth_huc() - Send action to GuC to authenticate HuC ucode
 426  * @guc: intel_guc structure
 427  * @rsa_offset: rsa offset w.r.t ggtt base of huc vma
 428  *
 429  * Triggers a HuC firmware authentication request to the GuC via intel_guc_send
 430  * INTEL_GUC_ACTION_AUTHENTICATE_HUC interface. This function is invoked by
 431  * intel_huc_auth().
 432  *
 433  * Return:      non-zero code on error
 434  */
 435 int intel_guc_auth_huc(struct intel_guc *guc, u32 rsa_offset)
 436 {
 437         u32 action[] = {
 438                 INTEL_GUC_ACTION_AUTHENTICATE_HUC,
 439                 rsa_offset
 440         };
 441
 442         return intel_guc_send(guc, action, ARRAY_SIZE(action));
 443 }
 444
 445 /**
 446  * intel_guc_suspend() - notify GuC entering suspend state
 447  * @guc:        the guc
 448  */
 449 int intel_guc_suspend(struct intel_guc *guc)
 450 {
 451         u32 data[] = {
 452                 INTEL_GUC_ACTION_ENTER_S_STATE,
 453                 GUC_POWER_D1, /* any value greater than GUC_POWER_D0 */
 454                 intel_guc_ggtt_offset(guc, guc->shared_data)
 455         };
 456
 457         return intel_guc_send(guc, data, ARRAY_SIZE(data));
 458 }
 459
 460 /**
 461  * intel_guc_reset_engine() - ask GuC to reset an engine
 462  * @guc:        intel_guc structure
 463  * @engine:     engine to be reset
 464  */
 465 int intel_guc_reset_engine(struct intel_guc *guc,
 466                            struct intel_engine_cs *engine)
 467 {
 468         u32 data[7];
 469
 470         GEM_BUG_ON(!guc->execbuf_client);
 471
 472         data[0] = INTEL_GUC_ACTION_REQUEST_ENGINE_RESET;
 473         data[1] = engine->guc_id;
 474         data[2] = 0;
 475         data[3] = 0;
 476         data[4] = 0;
 477         data[5] = guc->execbuf_client->stage_id;
 478         data[6] = intel_guc_ggtt_offset(guc, guc->shared_data);
 479
 480         return intel_guc_send(guc, data, ARRAY_SIZE(data));
 481 }
 482
 483 /**
 484  * intel_guc_resume() - notify GuC resuming from suspend state
 485  * @guc:        the guc
 486  */
 487 int intel_guc_resume(struct intel_guc *guc)
 488 {
 489         u32 data[] = {
 490                 INTEL_GUC_ACTION_EXIT_S_STATE,
 491                 GUC_POWER_D0,
 492                 intel_guc_ggtt_offset(guc, guc->shared_data)
 493         };
 494
 495         return intel_guc_send(guc, data, ARRAY_SIZE(data));
 496 }
 497
 498 /**
 499  * DOC: GuC Address Space
 500  *
 501  * The layout of GuC address space is shown below:
 502  *
 503  * ::
 504  *
 505  *     +==============> +====================+ <== GUC_GGTT_TOP
 506  *     ^                |                    |
 507  *     |                |                    |
 508  *     |                |        DRAM        |
 509  *     |                |       Memory       |
 510  *     |                |                    |
 511  *    GuC               |                    |
 512  *  Address  +========> +====================+ <== WOPCM Top
 513  *   Space   ^          |   HW contexts RSVD |
 514  *     |     |          |        WOPCM       |
 515  *     |     |     +==> +--------------------+ <== GuC WOPCM Top
 516  *     |    GuC    ^    |                    |
 517  *     |    GGTT   |    |                    |
 518  *     |    Pin   GuC   |        GuC         |
 519  *     |    Bias WOPCM  |       WOPCM        |
 520  *     |     |    Size  |                    |
 521  *     |     |     |    |                    |
 522  *     v     v     v    |                    |
 523  *     +=====+=====+==> +====================+ <== GuC WOPCM Base
 524  *                      |   Non-GuC WOPCM    |
 525  *                      |   (HuC/Reserved)   |
 526  *                      +====================+ <== WOPCM Base
 527  *
 528  * The lower part of GuC Address Space [0, ggtt_pin_bias) is mapped to WOPCM
 529  * while upper part of GuC Address Space [ggtt_pin_bias, GUC_GGTT_TOP) is mapped
 530  * to DRAM. The value of the GuC ggtt_pin_bias is determined by WOPCM size and
 531  * actual GuC WOPCM size.
 532  */
 533
 534 /**
 535  * intel_guc_init_ggtt_pin_bias() - Initialize the GuC ggtt_pin_bias value.
 536  * @guc: intel_guc structure.
 537  *
 538  * This function will calculate and initialize the ggtt_pin_bias value based on
 539  * overall WOPCM size and GuC WOPCM size.
 540  */
 541 void intel_guc_init_ggtt_pin_bias(struct intel_guc *guc)
 542 {
 543         struct drm_i915_private *i915 = guc_to_i915(guc);
 544
 545         GEM_BUG_ON(!i915->wopcm.size);
 546         GEM_BUG_ON(i915->wopcm.size < i915->wopcm.guc.base);
 547
 548         guc->ggtt_pin_bias = i915->wopcm.size - i915->wopcm.guc.base;
 549 }
 550
 551 /**
 552  * intel_guc_allocate_vma() - Allocate a GGTT VMA for GuC usage
 553  * @guc:        the guc
 554  * @size:       size of area to allocate (both virtual space and memory)
 555  *
 556  * This is a wrapper to create an object for use with the GuC. In order to
 557  * use it inside the GuC, an object needs to be pinned lifetime, so we allocate
 558  * both some backing storage and a range inside the Global GTT. We must pin
 559  * it in the GGTT somewhere other than than [0, GUC ggtt_pin_bias) because that
 560  * range is reserved inside GuC.
 561  *
 562  * Return:      A i915_vma if successful, otherwise an ERR_PTR.
 563  */
 564 struct i915_vma *intel_guc_allocate_vma(struct intel_guc *guc, u32 size)
 565 {
 566         struct drm_i915_private *dev_priv = guc_to_i915(guc);
 567         struct drm_i915_gem_object *obj;
 568         struct i915_vma *vma;
 569         int ret;
 570
 571         obj = i915_gem_object_create(dev_priv, size);
 572         if (IS_ERR(obj))
 573                 return ERR_CAST(obj);
 574
 575         vma = i915_vma_instance(obj, &dev_priv->ggtt.base, NULL);
 576         if (IS_ERR(vma))
 577                 goto err;
 578
 579         ret = i915_vma_pin(vma, 0, PAGE_SIZE,
 580                            PIN_GLOBAL | PIN_OFFSET_BIAS | guc->ggtt_pin_bias);
 581         if (ret) {
 582                 vma = ERR_PTR(ret);
 583                 goto err;
 584         }
 585
 586         return vma;
 587
 588 err:
 589         i915_gem_object_put(obj);
 590         return vma;
 591 }