drivers/usb/dwc3/ep0.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * ep0.c - DesignWare USB3 DRD Controller Endpoint 0 Handling
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <[email protected]>,
   8  *          Sebastian Andrzej Siewior <[email protected]>
   9  */
  10
  11 #include <linux/kernel.h>
  12 #include <linux/slab.h>
  13 #include <linux/spinlock.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/pm_runtime.h>
  16 #include <linux/interrupt.h>
  17 #include <linux/io.h>
  18 #include <linux/list.h>
  19 #include <linux/dma-mapping.h>
  20
  21 #include <linux/usb/ch9.h>
  22 #include <linux/usb/gadget.h>
  23 #include <linux/usb/composite.h>
  24
  25 #include "core.h"
  26 #include "debug.h"
  27 #include "gadget.h"
  28 #include "io.h"
  29
  30 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep);
  31 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
  32                 struct dwc3_ep *dep, struct dwc3_request *req);
  33
  34 static void dwc3_ep0_prepare_one_trb(struct dwc3_ep *dep,
  35                 dma_addr_t buf_dma, u32 len, u32 type, bool chain)
  36 {
  37         struct dwc3_trb                 *trb;
  38         struct dwc3                     *dwc;
  39
  40         dwc = dep->dwc;
  41         trb = &dwc->ep0_trb[dep->trb_enqueue];
  42
  43         if (chain)
  44                 dep->trb_enqueue++;
  45
  46         trb->bpl = lower_32_bits(buf_dma);
  47         trb->bph = upper_32_bits(buf_dma);
  48         trb->size = len;
  49         trb->ctrl = type;
  50
  51         trb->ctrl |= (DWC3_TRB_CTRL_HWO
  52                         | DWC3_TRB_CTRL_ISP_IMI);
  53
  54         if (chain)
  55                 trb->ctrl |= DWC3_TRB_CTRL_CHN;
  56         else
  57                 trb->ctrl |= (DWC3_TRB_CTRL_IOC
  58                                 | DWC3_TRB_CTRL_LST);
  59
  60         trace_dwc3_prepare_trb(dep, trb);
  61 }
  62
  63 static int dwc3_ep0_start_trans(struct dwc3_ep *dep)
  64 {
  65         struct dwc3_gadget_ep_cmd_params params;
  66         struct dwc3                     *dwc;
  67         int                             ret;
  68
  69         if (dep->flags & DWC3_EP_TRANSFER_STARTED)
  70                 return 0;
  71
  72         dwc = dep->dwc;
  73
  74         memset(&params, 0, sizeof(params));
  75         params.param0 = upper_32_bits(dwc->ep0_trb_addr);
  76         params.param1 = lower_32_bits(dwc->ep0_trb_addr);
  77
  78         ret = dwc3_send_gadget_ep_cmd(dep, DWC3_DEPCMD_STARTTRANSFER, &params);
  79         if (ret < 0)
  80                 return ret;
  81
  82         dwc->ep0_next_event = DWC3_EP0_COMPLETE;
  83
  84         return 0;
  85 }
  86
  87 static int __dwc3_gadget_ep0_queue(struct dwc3_ep *dep,
  88                 struct dwc3_request *req)
  89 {
  90         struct dwc3             *dwc = dep->dwc;
  91
  92         req->request.actual     = 0;
  93         req->request.status     = -EINPROGRESS;
  94         req->epnum              = dep->number;
  95
  96         list_add_tail(&req->list, &dep->pending_list);
  97
  98         /*
  99          * Gadget driver might not be quick enough to queue a request
 100          * before we get a Transfer Not Ready event on this endpoint.
 101          *
 102          * In that case, we will set DWC3_EP_PENDING_REQUEST. When that
 103          * flag is set, it's telling us that as soon as Gadget queues the
 104          * required request, we should kick the transfer here because the
 105          * IRQ we were waiting for is long gone.
 106          */
 107         if (dep->flags & DWC3_EP_PENDING_REQUEST) {
 108                 unsigned int direction;
 109
 110                 direction = !!(dep->flags & DWC3_EP0_DIR_IN);
 111
 112                 if (dwc->ep0state != EP0_DATA_PHASE) {
 113                         dev_WARN(dwc->dev, "Unexpected pending request\n");
 114                         return 0;
 115                 }
 116
 117                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 118
 119                 dep->flags &= ~(DWC3_EP_PENDING_REQUEST |
 120                                 DWC3_EP0_DIR_IN);
 121
 122                 return 0;
 123         }
 124
 125         /*
 126          * In case gadget driver asked us to delay the STATUS phase,
 127          * handle it here.
 128          */
 129         if (dwc->delayed_status) {
 130                 unsigned int direction;
 131
 132                 direction = !dwc->ep0_expect_in;
 133                 dwc->delayed_status = false;
 134                 usb_gadget_set_state(dwc->gadget, USB_STATE_CONFIGURED);
 135
 136                 if (dwc->ep0state == EP0_STATUS_PHASE)
 137                         __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
 138
 139                 return 0;
 140         }
 141
 142         /*
 143          * Unfortunately we have uncovered a limitation wrt the Data Phase.
 144          *
 145          * Section 9.4 says we can wait for the XferNotReady(DATA) event to
 146          * come before issueing Start Transfer command, but if we do, we will
 147          * miss situations where the host starts another SETUP phase instead of
 148          * the DATA phase.  Such cases happen at least on TD.7.6 of the Link
 149          * Layer Compliance Suite.
 150          *
 151          * The problem surfaces due to the fact that in case of back-to-back
 152          * SETUP packets there will be no XferNotReady(DATA) generated and we
 153          * will be stuck waiting for XferNotReady(DATA) forever.
 154          *
 155          * By looking at tables 9-13 and 9-14 of the Databook, we can see that
 156          * it tells us to start Data Phase right away. It also mentions that if
 157          * we receive a SETUP phase instead of the DATA phase, core will issue
 158          * XferComplete for the DATA phase, before actually initiating it in
 159          * the wire, with the TRB's status set to "SETUP_PENDING". Such status
 160          * can only be used to print some debugging logs, as the core expects
 161          * us to go through to the STATUS phase and start a CONTROL_STATUS TRB,
 162          * just so it completes right away, without transferring anything and,
 163          * only then, we can go back to the SETUP phase.
 164          *
 165          * Because of this scenario, SNPS decided to change the programming
 166          * model of control transfers and support on-demand transfers only for
 167          * the STATUS phase. To fix the issue we have now, we will always wait
 168          * for gadget driver to queue the DATA phase's struct usb_request, then
 169          * start it right away.
 170          *
 171          * If we're actually in a 2-stage transfer, we will wait for
 172          * XferNotReady(STATUS).
 173          */
 174         if (dwc->three_stage_setup) {
 175                 unsigned int direction;
 176
 177                 direction = dwc->ep0_expect_in;
 178                 dwc->ep0state = EP0_DATA_PHASE;
 179
 180                 __dwc3_ep0_do_control_data(dwc, dwc->eps[direction], req);
 181
 182                 dep->flags &= ~DWC3_EP0_DIR_IN;
 183         }
 184
 185         return 0;
 186 }
 187
 188 int dwc3_gadget_ep0_queue(struct usb_ep *ep, struct usb_request *request,
 189                 gfp_t gfp_flags)
 190 {
 191         struct dwc3_request             *req = to_dwc3_request(request);
 192         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 193         struct dwc3                     *dwc = dep->dwc;
 194
 195         unsigned long                   flags;
 196
 197         int                             ret;
 198
 199         spin_lock_irqsave(&dwc->lock, flags);
 200         if (!dep->endpoint.desc || !dwc->pullups_connected) {
 201                 dev_err(dwc->dev, "%s: can't queue to disabled endpoint\n",
 202                                 dep->name);
 203                 ret = -ESHUTDOWN;
 204                 goto out;
 205         }
 206
 207         /* we share one TRB for ep0/1 */
 208         if (!list_empty(&dep->pending_list)) {
 209                 ret = -EBUSY;
 210                 goto out;
 211         }
 212
 213         ret = __dwc3_gadget_ep0_queue(dep, req);
 214
 215 out:
 216         spin_unlock_irqrestore(&dwc->lock, flags);
 217
 218         return ret;
 219 }
 220
 221 void dwc3_ep0_stall_and_restart(struct dwc3 *dwc)
 222 {
 223         struct dwc3_ep          *dep;
 224
 225         /* reinitialize physical ep1 */
 226         dep = dwc->eps[1];
 227         dep->flags = DWC3_EP_ENABLED;
 228
 229         /* stall is always issued on EP0 */
 230         dep = dwc->eps[0];
 231         __dwc3_gadget_ep_set_halt(dep, 1, false);
 232         dep->flags = DWC3_EP_ENABLED;
 233         dwc->delayed_status = false;
 234
 235         if (!list_empty(&dep->pending_list)) {
 236                 struct dwc3_request     *req;
 237
 238                 req = next_request(&dep->pending_list);
 239                 dwc3_gadget_giveback(dep, req, -ECONNRESET);
 240         }
 241
 242         dwc->eps[0]->trb_enqueue = 0;
 243         dwc->eps[1]->trb_enqueue = 0;
 244         dwc->ep0state = EP0_SETUP_PHASE;
 245         dwc3_ep0_out_start(dwc);
 246 }
 247
 248 int __dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 249 {
 250         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 251         struct dwc3                     *dwc = dep->dwc;
 252
 253         dwc3_ep0_stall_and_restart(dwc);
 254
 255         return 0;
 256 }
 257
 258 int dwc3_gadget_ep0_set_halt(struct usb_ep *ep, int value)
 259 {
 260         struct dwc3_ep                  *dep = to_dwc3_ep(ep);
 261         struct dwc3                     *dwc = dep->dwc;
 262         unsigned long                   flags;
 263         int                             ret;
 264
 265         spin_lock_irqsave(&dwc->lock, flags);
 266         ret = __dwc3_gadget_ep0_set_halt(ep, value);
 267         spin_unlock_irqrestore(&dwc->lock, flags);
 268
 269         return ret;
 270 }
 271
 272 void dwc3_ep0_out_start(struct dwc3 *dwc)
 273 {
 274         struct dwc3_ep                  *dep;
 275         int                             ret;
 276         int                             i;
 277
 278         complete(&dwc->ep0_in_setup);
 279
 280         dep = dwc->eps[0];
 281         dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 8,
 282                         DWC3_TRBCTL_CONTROL_SETUP, false);
 283         ret = dwc3_ep0_start_trans(dep);
 284         WARN_ON(ret < 0);
 285         for (i = 2; i < DWC3_ENDPOINTS_NUM; i++) {
 286                 struct dwc3_ep *dwc3_ep;
 287
 288                 dwc3_ep = dwc->eps[i];
 289                 if (!dwc3_ep)
 290                         continue;
 291
 292                 if (!(dwc3_ep->flags & DWC3_EP_DELAY_STOP))
 293                         continue;
 294
 295                 dwc3_ep->flags &= ~DWC3_EP_DELAY_STOP;
 296                 dwc3_stop_active_transfer(dwc3_ep, true, true);
 297         }
 298 }
 299
 300 static struct dwc3_ep *dwc3_wIndex_to_dep(struct dwc3 *dwc, __le16 wIndex_le)
 301 {
 302         struct dwc3_ep          *dep;
 303         u32                     windex = le16_to_cpu(wIndex_le);
 304         u32                     epnum;
 305
 306         epnum = (windex & USB_ENDPOINT_NUMBER_MASK) << 1;
 307         if ((windex & USB_ENDPOINT_DIR_MASK) == USB_DIR_IN)
 308                 epnum |= 1;
 309
 310         dep = dwc->eps[epnum];
 311         if (dep == NULL)
 312                 return NULL;
 313
 314         if (dep->flags & DWC3_EP_ENABLED)
 315                 return dep;
 316
 317         return NULL;
 318 }
 319
 320 static void dwc3_ep0_status_cmpl(struct usb_ep *ep, struct usb_request *req)
 321 {
 322 }
 323 /*
 324  * ch 9.4.5
 325  */
 326 static int dwc3_ep0_handle_status(struct dwc3 *dwc,
 327                 struct usb_ctrlrequest *ctrl)
 328 {
 329         struct dwc3_ep          *dep;
 330         u32                     recip;
 331         u32                     value;
 332         u32                     reg;
 333         u16                     usb_status = 0;
 334         __le16                  *response_pkt;
 335
 336         /* We don't support PTM_STATUS */
 337         value = le16_to_cpu(ctrl->wValue);
 338         if (value != 0)
 339                 return -EINVAL;
 340
 341         recip = ctrl->bRequestType & USB_RECIP_MASK;
 342         switch (recip) {
 343         case USB_RECIP_DEVICE:
 344                 /*
 345                  * LTM will be set once we know how to set this in HW.
 346                  */
 347                 usb_status |= dwc->gadget->is_selfpowered;
 348
 349                 if ((dwc->speed == DWC3_DSTS_SUPERSPEED) ||
 350                     (dwc->speed == DWC3_DSTS_SUPERSPEED_PLUS)) {
 351                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 352                         if (reg & DWC3_DCTL_INITU1ENA)
 353                                 usb_status |= 1 << USB_DEV_STAT_U1_ENABLED;
 354                         if (reg & DWC3_DCTL_INITU2ENA)
 355                                 usb_status |= 1 << USB_DEV_STAT_U2_ENABLED;
 356                 }
 357
 358                 break;
 359
 360         case USB_RECIP_INTERFACE:
 361                 /*
 362                  * Function Remote Wake Capable D0
 363                  * Function Remote Wakeup       D1
 364                  */
 365                 break;
 366
 367         case USB_RECIP_ENDPOINT:
 368                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 369                 if (!dep)
 370                         return -EINVAL;
 371
 372                 if (dep->flags & DWC3_EP_STALL)
 373                         usb_status = 1 << USB_ENDPOINT_HALT;
 374                 break;
 375         default:
 376                 return -EINVAL;
 377         }
 378
 379         response_pkt = (__le16 *) dwc->setup_buf;
 380         *response_pkt = cpu_to_le16(usb_status);
 381
 382         dep = dwc->eps[0];
 383         dwc->ep0_usb_req.dep = dep;
 384         dwc->ep0_usb_req.request.length = sizeof(*response_pkt);
 385         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 386         dwc->ep0_usb_req.request.complete = dwc3_ep0_status_cmpl;
 387
 388         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 389 }
 390
 391 static int dwc3_ep0_handle_u1(struct dwc3 *dwc, enum usb_device_state state,
 392                 int set)
 393 {
 394         u32 reg;
 395
 396         if (state != USB_STATE_CONFIGURED)
 397                 return -EINVAL;
 398         if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
 399                         (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
 400                 return -EINVAL;
 401         if (set && dwc->dis_u1_entry_quirk)
 402                 return -EINVAL;
 403
 404         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 405         if (set)
 406                 reg |= DWC3_DCTL_INITU1ENA;
 407         else
 408                 reg &= ~DWC3_DCTL_INITU1ENA;
 409         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 410
 411         return 0;
 412 }
 413
 414 static int dwc3_ep0_handle_u2(struct dwc3 *dwc, enum usb_device_state state,
 415                 int set)
 416 {
 417         u32 reg;
 418
 419
 420         if (state != USB_STATE_CONFIGURED)
 421                 return -EINVAL;
 422         if ((dwc->speed != DWC3_DSTS_SUPERSPEED) &&
 423                         (dwc->speed != DWC3_DSTS_SUPERSPEED_PLUS))
 424                 return -EINVAL;
 425         if (set && dwc->dis_u2_entry_quirk)
 426                 return -EINVAL;
 427
 428         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 429         if (set)
 430                 reg |= DWC3_DCTL_INITU2ENA;
 431         else
 432                 reg &= ~DWC3_DCTL_INITU2ENA;
 433         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 434
 435         return 0;
 436 }
 437
 438 static int dwc3_ep0_handle_test(struct dwc3 *dwc, enum usb_device_state state,
 439                 u32 wIndex, int set)
 440 {
 441         if ((wIndex & 0xff) != 0)
 442                 return -EINVAL;
 443         if (!set)
 444                 return -EINVAL;
 445
 446         switch (wIndex >> 8) {
 447         case USB_TEST_J:
 448         case USB_TEST_K:
 449         case USB_TEST_SE0_NAK:
 450         case USB_TEST_PACKET:
 451         case USB_TEST_FORCE_ENABLE:
 452                 dwc->test_mode_nr = wIndex >> 8;
 453                 dwc->test_mode = true;
 454                 break;
 455         default:
 456                 return -EINVAL;
 457         }
 458
 459         return 0;
 460 }
 461
 462 static int dwc3_ep0_handle_device(struct dwc3 *dwc,
 463                 struct usb_ctrlrequest *ctrl, int set)
 464 {
 465         enum usb_device_state   state;
 466         u32                     wValue;
 467         u32                     wIndex;
 468         int                     ret = 0;
 469
 470         wValue = le16_to_cpu(ctrl->wValue);
 471         wIndex = le16_to_cpu(ctrl->wIndex);
 472         state = dwc->gadget->state;
 473
 474         switch (wValue) {
 475         case USB_DEVICE_REMOTE_WAKEUP:
 476                 break;
 477         /*
 478          * 9.4.1 says only for SS, in AddressState only for
 479          * default control pipe
 480          */
 481         case USB_DEVICE_U1_ENABLE:
 482                 ret = dwc3_ep0_handle_u1(dwc, state, set);
 483                 break;
 484         case USB_DEVICE_U2_ENABLE:
 485                 ret = dwc3_ep0_handle_u2(dwc, state, set);
 486                 break;
 487         case USB_DEVICE_LTM_ENABLE:
 488                 ret = -EINVAL;
 489                 break;
 490         case USB_DEVICE_TEST_MODE:
 491                 ret = dwc3_ep0_handle_test(dwc, state, wIndex, set);
 492                 break;
 493         default:
 494                 ret = -EINVAL;
 495         }
 496
 497         return ret;
 498 }
 499
 500 static int dwc3_ep0_handle_intf(struct dwc3 *dwc,
 501                 struct usb_ctrlrequest *ctrl, int set)
 502 {
 503         u32                     wValue;
 504         int                     ret = 0;
 505
 506         wValue = le16_to_cpu(ctrl->wValue);
 507
 508         switch (wValue) {
 509         case USB_INTRF_FUNC_SUSPEND:
 510                 /*
 511                  * REVISIT: Ideally we would enable some low power mode here,
 512                  * however it's unclear what we should be doing here.
 513                  *
 514                  * For now, we're not doing anything, just making sure we return
 515                  * 0 so USB Command Verifier tests pass without any errors.
 516                  */
 517                 break;
 518         default:
 519                 ret = -EINVAL;
 520         }
 521
 522         return ret;
 523 }
 524
 525 static int dwc3_ep0_handle_endpoint(struct dwc3 *dwc,
 526                 struct usb_ctrlrequest *ctrl, int set)
 527 {
 528         struct dwc3_ep          *dep;
 529         u32                     wValue;
 530         int                     ret;
 531
 532         wValue = le16_to_cpu(ctrl->wValue);
 533
 534         switch (wValue) {
 535         case USB_ENDPOINT_HALT:
 536                 dep = dwc3_wIndex_to_dep(dwc, ctrl->wIndex);
 537                 if (!dep)
 538                         return -EINVAL;
 539
 540                 if (set == 0 && (dep->flags & DWC3_EP_WEDGE))
 541                         break;
 542
 543                 ret = __dwc3_gadget_ep_set_halt(dep, set, true);
 544                 if (ret)
 545                         return -EINVAL;
 546
 547                 /* ClearFeature(Halt) may need delayed status */
 548                 if (!set && (dep->flags & DWC3_EP_END_TRANSFER_PENDING))
 549                         return USB_GADGET_DELAYED_STATUS;
 550
 551                 break;
 552         default:
 553                 return -EINVAL;
 554         }
 555
 556         return 0;
 557 }
 558
 559 static int dwc3_ep0_handle_feature(struct dwc3 *dwc,
 560                 struct usb_ctrlrequest *ctrl, int set)
 561 {
 562         u32                     recip;
 563         int                     ret;
 564
 565         recip = ctrl->bRequestType & USB_RECIP_MASK;
 566
 567         switch (recip) {
 568         case USB_RECIP_DEVICE:
 569                 ret = dwc3_ep0_handle_device(dwc, ctrl, set);
 570                 break;
 571         case USB_RECIP_INTERFACE:
 572                 ret = dwc3_ep0_handle_intf(dwc, ctrl, set);
 573                 break;
 574         case USB_RECIP_ENDPOINT:
 575                 ret = dwc3_ep0_handle_endpoint(dwc, ctrl, set);
 576                 break;
 577         default:
 578                 ret = -EINVAL;
 579         }
 580
 581         return ret;
 582 }
 583
 584 static int dwc3_ep0_set_address(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 585 {
 586         enum usb_device_state state = dwc->gadget->state;
 587         u32 addr;
 588         u32 reg;
 589
 590         addr = le16_to_cpu(ctrl->wValue);
 591         if (addr > 127) {
 592                 dev_err(dwc->dev, "invalid device address %d\n", addr);
 593                 return -EINVAL;
 594         }
 595
 596         if (state == USB_STATE_CONFIGURED) {
 597                 dev_err(dwc->dev, "can't SetAddress() from Configured State\n");
 598                 return -EINVAL;
 599         }
 600
 601         reg = dwc3_readl(dwc->regs, DWC3_DCFG);
 602         reg &= ~(DWC3_DCFG_DEVADDR_MASK);
 603         reg |= DWC3_DCFG_DEVADDR(addr);
 604         dwc3_writel(dwc->regs, DWC3_DCFG, reg);
 605
 606         if (addr)
 607                 usb_gadget_set_state(dwc->gadget, USB_STATE_ADDRESS);
 608         else
 609                 usb_gadget_set_state(dwc->gadget, USB_STATE_DEFAULT);
 610
 611         return 0;
 612 }
 613
 614 static int dwc3_ep0_delegate_req(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 615 {
 616         int ret = -EINVAL;
 617
 618         if (dwc->async_callbacks) {
 619                 spin_unlock(&dwc->lock);
 620                 ret = dwc->gadget_driver->setup(dwc->gadget, ctrl);
 621                 spin_lock(&dwc->lock);
 622         }
 623         return ret;
 624 }
 625
 626 static int dwc3_ep0_set_config(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 627 {
 628         enum usb_device_state state = dwc->gadget->state;
 629         u32 cfg;
 630         int ret;
 631         u32 reg;
 632
 633         cfg = le16_to_cpu(ctrl->wValue);
 634
 635         switch (state) {
 636         case USB_STATE_DEFAULT:
 637                 return -EINVAL;
 638
 639         case USB_STATE_ADDRESS:
 640                 dwc3_gadget_clear_tx_fifos(dwc);
 641
 642                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 643                 /* if the cfg matches and the cfg is non zero */
 644                 if (cfg && (!ret || (ret == USB_GADGET_DELAYED_STATUS))) {
 645
 646                         /*
 647                          * only change state if set_config has already
 648                          * been processed. If gadget driver returns
 649                          * USB_GADGET_DELAYED_STATUS, we will wait
 650                          * to change the state on the next usb_ep_queue()
 651                          */
 652                         if (ret == 0)
 653                                 usb_gadget_set_state(dwc->gadget,
 654                                                 USB_STATE_CONFIGURED);
 655
 656                         /*
 657                          * Enable transition to U1/U2 state when
 658                          * nothing is pending from application.
 659                          */
 660                         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 661                         if (!dwc->dis_u1_entry_quirk)
 662                                 reg |= DWC3_DCTL_ACCEPTU1ENA;
 663                         if (!dwc->dis_u2_entry_quirk)
 664                                 reg |= DWC3_DCTL_ACCEPTU2ENA;
 665                         dwc3_writel(dwc->regs, DWC3_DCTL, reg);
 666                 }
 667                 break;
 668
 669         case USB_STATE_CONFIGURED:
 670                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 671                 if (!cfg && !ret)
 672                         usb_gadget_set_state(dwc->gadget,
 673                                         USB_STATE_ADDRESS);
 674                 break;
 675         default:
 676                 ret = -EINVAL;
 677         }
 678         return ret;
 679 }
 680
 681 static void dwc3_ep0_set_sel_cmpl(struct usb_ep *ep, struct usb_request *req)
 682 {
 683         struct dwc3_ep  *dep = to_dwc3_ep(ep);
 684         struct dwc3     *dwc = dep->dwc;
 685
 686         u32             param = 0;
 687         u32             reg;
 688
 689         struct timing {
 690                 u8      u1sel;
 691                 u8      u1pel;
 692                 __le16  u2sel;
 693                 __le16  u2pel;
 694         } __packed timing;
 695
 696         int             ret;
 697
 698         memcpy(&timing, req->buf, sizeof(timing));
 699
 700         dwc->u1sel = timing.u1sel;
 701         dwc->u1pel = timing.u1pel;
 702         dwc->u2sel = le16_to_cpu(timing.u2sel);
 703         dwc->u2pel = le16_to_cpu(timing.u2pel);
 704
 705         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 706         if (reg & DWC3_DCTL_INITU2ENA)
 707                 param = dwc->u2pel;
 708         if (reg & DWC3_DCTL_INITU1ENA)
 709                 param = dwc->u1pel;
 710
 711         /*
 712          * According to Synopsys Databook, if parameter is
 713          * greater than 125, a value of zero should be
 714          * programmed in the register.
 715          */
 716         if (param > 125)
 717                 param = 0;
 718
 719         /* now that we have the time, issue DGCMD Set Sel */
 720         ret = dwc3_send_gadget_generic_command(dwc,
 721                         DWC3_DGCMD_SET_PERIODIC_PAR, param);
 722         WARN_ON(ret < 0);
 723 }
 724
 725 static int dwc3_ep0_set_sel(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 726 {
 727         struct dwc3_ep  *dep;
 728         enum usb_device_state state = dwc->gadget->state;
 729         u16             wLength;
 730
 731         if (state == USB_STATE_DEFAULT)
 732                 return -EINVAL;
 733
 734         wLength = le16_to_cpu(ctrl->wLength);
 735
 736         if (wLength != 6) {
 737                 dev_err(dwc->dev, "Set SEL should be 6 bytes, got %d\n",
 738                                 wLength);
 739                 return -EINVAL;
 740         }
 741
 742         /*
 743          * To handle Set SEL we need to receive 6 bytes from Host. So let's
 744          * queue a usb_request for 6 bytes.
 745          *
 746          * Remember, though, this controller can't handle non-wMaxPacketSize
 747          * aligned transfers on the OUT direction, so we queue a request for
 748          * wMaxPacketSize instead.
 749          */
 750         dep = dwc->eps[0];
 751         dwc->ep0_usb_req.dep = dep;
 752         dwc->ep0_usb_req.request.length = dep->endpoint.maxpacket;
 753         dwc->ep0_usb_req.request.buf = dwc->setup_buf;
 754         dwc->ep0_usb_req.request.complete = dwc3_ep0_set_sel_cmpl;
 755
 756         return __dwc3_gadget_ep0_queue(dep, &dwc->ep0_usb_req);
 757 }
 758
 759 static int dwc3_ep0_set_isoch_delay(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 760 {
 761         u16             wLength;
 762         u16             wValue;
 763         u16             wIndex;
 764
 765         wValue = le16_to_cpu(ctrl->wValue);
 766         wLength = le16_to_cpu(ctrl->wLength);
 767         wIndex = le16_to_cpu(ctrl->wIndex);
 768
 769         if (wIndex || wLength)
 770                 return -EINVAL;
 771
 772         dwc->gadget->isoch_delay = wValue;
 773
 774         return 0;
 775 }
 776
 777 static int dwc3_ep0_std_request(struct dwc3 *dwc, struct usb_ctrlrequest *ctrl)
 778 {
 779         int ret;
 780
 781         switch (ctrl->bRequest) {
 782         case USB_REQ_GET_STATUS:
 783                 ret = dwc3_ep0_handle_status(dwc, ctrl);
 784                 break;
 785         case USB_REQ_CLEAR_FEATURE:
 786                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 0);
 787                 break;
 788         case USB_REQ_SET_FEATURE:
 789                 ret = dwc3_ep0_handle_feature(dwc, ctrl, 1);
 790                 break;
 791         case USB_REQ_SET_ADDRESS:
 792                 ret = dwc3_ep0_set_address(dwc, ctrl);
 793                 break;
 794         case USB_REQ_SET_CONFIGURATION:
 795                 ret = dwc3_ep0_set_config(dwc, ctrl);
 796                 break;
 797         case USB_REQ_SET_SEL:
 798                 ret = dwc3_ep0_set_sel(dwc, ctrl);
 799                 break;
 800         case USB_REQ_SET_ISOCH_DELAY:
 801                 ret = dwc3_ep0_set_isoch_delay(dwc, ctrl);
 802                 break;
 803         default:
 804                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 805                 break;
 806         }
 807
 808         return ret;
 809 }
 810
 811 static void dwc3_ep0_inspect_setup(struct dwc3 *dwc,
 812                 const struct dwc3_event_depevt *event)
 813 {
 814         struct usb_ctrlrequest *ctrl = (void *) dwc->ep0_trb;
 815         int ret = -EINVAL;
 816         u32 len;
 817
 818         if (!dwc->gadget_driver || !dwc->connected)
 819                 goto out;
 820
 821         trace_dwc3_ctrl_req(ctrl);
 822
 823         len = le16_to_cpu(ctrl->wLength);
 824         if (!len) {
 825                 dwc->three_stage_setup = false;
 826                 dwc->ep0_expect_in = false;
 827                 dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 828         } else {
 829                 dwc->three_stage_setup = true;
 830                 dwc->ep0_expect_in = !!(ctrl->bRequestType & USB_DIR_IN);
 831                 dwc->ep0_next_event = DWC3_EP0_NRDY_DATA;
 832         }
 833
 834         if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD)
 835                 ret = dwc3_ep0_std_request(dwc, ctrl);
 836         else
 837                 ret = dwc3_ep0_delegate_req(dwc, ctrl);
 838
 839         if (ret == USB_GADGET_DELAYED_STATUS)
 840                 dwc->delayed_status = true;
 841
 842 out:
 843         if (ret < 0)
 844                 dwc3_ep0_stall_and_restart(dwc);
 845 }
 846
 847 static void dwc3_ep0_complete_data(struct dwc3 *dwc,
 848                 const struct dwc3_event_depevt *event)
 849 {
 850         struct dwc3_request     *r;
 851         struct usb_request      *ur;
 852         struct dwc3_trb         *trb;
 853         struct dwc3_ep          *ep0;
 854         u32                     transferred = 0;
 855         u32                     status;
 856         u32                     length;
 857         u8                      epnum;
 858
 859         epnum = event->endpoint_number;
 860         ep0 = dwc->eps[0];
 861
 862         dwc->ep0_next_event = DWC3_EP0_NRDY_STATUS;
 863         trb = dwc->ep0_trb;
 864         trace_dwc3_complete_trb(ep0, trb);
 865
 866         r = next_request(&ep0->pending_list);
 867         if (!r)
 868                 return;
 869
 870         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 871         if (status == DWC3_TRBSTS_SETUP_PENDING) {
 872                 dwc->setup_packet_pending = true;
 873                 if (r)
 874                         dwc3_gadget_giveback(ep0, r, -ECONNRESET);
 875
 876                 return;
 877         }
 878
 879         ur = &r->request;
 880
 881         length = trb->size & DWC3_TRB_SIZE_MASK;
 882         transferred = ur->length - length;
 883         ur->actual += transferred;
 884
 885         if ((IS_ALIGNED(ur->length, ep0->endpoint.maxpacket) &&
 886              ur->length && ur->zero) || dwc->ep0_bounced) {
 887                 trb++;
 888                 trb->ctrl &= ~DWC3_TRB_CTRL_HWO;
 889                 trace_dwc3_complete_trb(ep0, trb);
 890
 891                 if (r->direction)
 892                         dwc->eps[1]->trb_enqueue = 0;
 893                 else
 894                         dwc->eps[0]->trb_enqueue = 0;
 895
 896                 dwc->ep0_bounced = false;
 897         }
 898
 899         if ((epnum & 1) && ur->actual < ur->length)
 900                 dwc3_ep0_stall_and_restart(dwc);
 901         else
 902                 dwc3_gadget_giveback(ep0, r, 0);
 903 }
 904
 905 static void dwc3_ep0_complete_status(struct dwc3 *dwc,
 906                 const struct dwc3_event_depevt *event)
 907 {
 908         struct dwc3_request     *r;
 909         struct dwc3_ep          *dep;
 910         struct dwc3_trb         *trb;
 911         u32                     status;
 912
 913         dep = dwc->eps[0];
 914         trb = dwc->ep0_trb;
 915
 916         trace_dwc3_complete_trb(dep, trb);
 917
 918         if (!list_empty(&dep->pending_list)) {
 919                 r = next_request(&dep->pending_list);
 920
 921                 dwc3_gadget_giveback(dep, r, 0);
 922         }
 923
 924         if (dwc->test_mode) {
 925                 int ret;
 926
 927                 ret = dwc3_gadget_set_test_mode(dwc, dwc->test_mode_nr);
 928                 if (ret < 0) {
 929                         dev_err(dwc->dev, "invalid test #%d\n",
 930                                         dwc->test_mode_nr);
 931                         dwc3_ep0_stall_and_restart(dwc);
 932                         return;
 933                 }
 934         }
 935
 936         status = DWC3_TRB_SIZE_TRBSTS(trb->size);
 937         if (status == DWC3_TRBSTS_SETUP_PENDING)
 938                 dwc->setup_packet_pending = true;
 939
 940         dwc->ep0state = EP0_SETUP_PHASE;
 941         dwc3_ep0_out_start(dwc);
 942 }
 943
 944 static void dwc3_ep0_xfer_complete(struct dwc3 *dwc,
 945                         const struct dwc3_event_depevt *event)
 946 {
 947         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
 948
 949         dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
 950         dep->resource_index = 0;
 951         dwc->setup_packet_pending = false;
 952
 953         switch (dwc->ep0state) {
 954         case EP0_SETUP_PHASE:
 955                 dwc3_ep0_inspect_setup(dwc, event);
 956                 break;
 957
 958         case EP0_DATA_PHASE:
 959                 dwc3_ep0_complete_data(dwc, event);
 960                 break;
 961
 962         case EP0_STATUS_PHASE:
 963                 dwc3_ep0_complete_status(dwc, event);
 964                 break;
 965         default:
 966                 WARN(true, "UNKNOWN ep0state %d\n", dwc->ep0state);
 967         }
 968 }
 969
 970 static void __dwc3_ep0_do_control_data(struct dwc3 *dwc,
 971                 struct dwc3_ep *dep, struct dwc3_request *req)
 972 {
 973         unsigned int            trb_length = 0;
 974         int                     ret;
 975
 976         req->direction = !!dep->number;
 977
 978         if (req->request.length == 0) {
 979                 if (!req->direction)
 980                         trb_length = dep->endpoint.maxpacket;
 981
 982                 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr, trb_length,
 983                                 DWC3_TRBCTL_CONTROL_DATA, false);
 984                 ret = dwc3_ep0_start_trans(dep);
 985         } else if (!IS_ALIGNED(req->request.length, dep->endpoint.maxpacket)
 986                         && (dep->number == 0)) {
 987                 u32     maxpacket;
 988                 u32     rem;
 989
 990                 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
 991                                 &req->request, dep->number);
 992                 if (ret)
 993                         return;
 994
 995                 maxpacket = dep->endpoint.maxpacket;
 996                 rem = req->request.length % maxpacket;
 997                 dwc->ep0_bounced = true;
 998
 999                 /* prepare normal TRB */
1000                 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1001                                          req->request.length,
1002                                          DWC3_TRBCTL_CONTROL_DATA,
1003                                          true);
1004
1005                 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
1006
1007                 /* Now prepare one extra TRB to align transfer size */
1008                 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
1009                                          maxpacket - rem,
1010                                          DWC3_TRBCTL_CONTROL_DATA,
1011                                          false);
1012                 ret = dwc3_ep0_start_trans(dep);
1013         } else if (IS_ALIGNED(req->request.length, dep->endpoint.maxpacket) &&
1014                    req->request.length && req->request.zero) {
1015
1016                 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1017                                 &req->request, dep->number);
1018                 if (ret)
1019                         return;
1020
1021                 /* prepare normal TRB */
1022                 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1023                                          req->request.length,
1024                                          DWC3_TRBCTL_CONTROL_DATA,
1025                                          true);
1026
1027                 req->trb = &dwc->ep0_trb[dep->trb_enqueue - 1];
1028
1029                 if (!req->direction)
1030                         trb_length = dep->endpoint.maxpacket;
1031
1032                 /* Now prepare one extra TRB to align transfer size */
1033                 dwc3_ep0_prepare_one_trb(dep, dwc->bounce_addr,
1034                                          trb_length, DWC3_TRBCTL_CONTROL_DATA,
1035                                          false);
1036                 ret = dwc3_ep0_start_trans(dep);
1037         } else {
1038                 ret = usb_gadget_map_request_by_dev(dwc->sysdev,
1039                                 &req->request, dep->number);
1040                 if (ret)
1041                         return;
1042
1043                 dwc3_ep0_prepare_one_trb(dep, req->request.dma,
1044                                 req->request.length, DWC3_TRBCTL_CONTROL_DATA,
1045                                 false);
1046
1047                 req->trb = &dwc->ep0_trb[dep->trb_enqueue];
1048
1049                 ret = dwc3_ep0_start_trans(dep);
1050         }
1051
1052         WARN_ON(ret < 0);
1053 }
1054
1055 static int dwc3_ep0_start_control_status(struct dwc3_ep *dep)
1056 {
1057         struct dwc3             *dwc = dep->dwc;
1058         u32                     type;
1059
1060         type = dwc->three_stage_setup ? DWC3_TRBCTL_CONTROL_STATUS3
1061                 : DWC3_TRBCTL_CONTROL_STATUS2;
1062
1063         dwc3_ep0_prepare_one_trb(dep, dwc->ep0_trb_addr, 0, type, false);
1064         return dwc3_ep0_start_trans(dep);
1065 }
1066
1067 static void __dwc3_ep0_do_control_status(struct dwc3 *dwc, struct dwc3_ep *dep)
1068 {
1069         WARN_ON(dwc3_ep0_start_control_status(dep));
1070 }
1071
1072 static void dwc3_ep0_do_control_status(struct dwc3 *dwc,
1073                 const struct dwc3_event_depevt *event)
1074 {
1075         struct dwc3_ep          *dep = dwc->eps[event->endpoint_number];
1076
1077         __dwc3_ep0_do_control_status(dwc, dep);
1078 }
1079
1080 void dwc3_ep0_send_delayed_status(struct dwc3 *dwc)
1081 {
1082         unsigned int direction = !dwc->ep0_expect_in;
1083
1084         dwc->delayed_status = false;
1085         dwc->clear_stall_protocol = 0;
1086
1087         if (dwc->ep0state != EP0_STATUS_PHASE)
1088                 return;
1089
1090         __dwc3_ep0_do_control_status(dwc, dwc->eps[direction]);
1091 }
1092
1093 void dwc3_ep0_end_control_data(struct dwc3 *dwc, struct dwc3_ep *dep)
1094 {
1095         struct dwc3_gadget_ep_cmd_params params;
1096         u32                     cmd;
1097         int                     ret;
1098
1099         /*
1100          * For status/DATA OUT stage, TRB will be queued on ep0 out
1101          * endpoint for which resource index is zero. Hence allow
1102          * queuing ENDXFER command for ep0 out endpoint.
1103          */
1104         if (!dep->resource_index && dep->number)
1105                 return;
1106
1107         cmd = DWC3_DEPCMD_ENDTRANSFER;
1108         cmd |= DWC3_DEPCMD_CMDIOC;
1109         cmd |= DWC3_DEPCMD_PARAM(dep->resource_index);
1110         memset(&params, 0, sizeof(params));
1111         ret = dwc3_send_gadget_ep_cmd(dep, cmd, &params);
1112         WARN_ON_ONCE(ret);
1113         dep->resource_index = 0;
1114 }
1115
1116 static void dwc3_ep0_xfernotready(struct dwc3 *dwc,
1117                 const struct dwc3_event_depevt *event)
1118 {
1119         switch (event->status) {
1120         case DEPEVT_STATUS_CONTROL_DATA:
1121                 /*
1122                  * We already have a DATA transfer in the controller's cache,
1123                  * if we receive a XferNotReady(DATA) we will ignore it, unless
1124                  * it's for the wrong direction.
1125                  *
1126                  * In that case, we must issue END_TRANSFER command to the Data
1127                  * Phase we already have started and issue SetStall on the
1128                  * control endpoint.
1129                  */
1130                 if (dwc->ep0_expect_in != event->endpoint_number) {
1131                         struct dwc3_ep  *dep = dwc->eps[dwc->ep0_expect_in];
1132
1133                         dev_err(dwc->dev, "unexpected direction for Data Phase\n");
1134                         dwc3_ep0_end_control_data(dwc, dep);
1135                         dwc3_ep0_stall_and_restart(dwc);
1136                         return;
1137                 }
1138
1139                 break;
1140
1141         case DEPEVT_STATUS_CONTROL_STATUS:
1142                 if (dwc->ep0_next_event != DWC3_EP0_NRDY_STATUS)
1143                         return;
1144
1145                 if (dwc->setup_packet_pending) {
1146                         dwc3_ep0_stall_and_restart(dwc);
1147                         return;
1148                 }
1149
1150                 dwc->ep0state = EP0_STATUS_PHASE;
1151
1152                 if (dwc->delayed_status) {
1153                         struct dwc3_ep *dep = dwc->eps[0];
1154
1155                         WARN_ON_ONCE(event->endpoint_number != 1);
1156                         /*
1157                          * We should handle the delay STATUS phase here if the
1158                          * request for handling delay STATUS has been queued
1159                          * into the list.
1160                          */
1161                         if (!list_empty(&dep->pending_list)) {
1162                                 dwc->delayed_status = false;
1163                                 usb_gadget_set_state(dwc->gadget,
1164                                                      USB_STATE_CONFIGURED);
1165                                 dwc3_ep0_do_control_status(dwc, event);
1166                         }
1167
1168                         return;
1169                 }
1170
1171                 dwc3_ep0_do_control_status(dwc, event);
1172         }
1173 }
1174
1175 void dwc3_ep0_interrupt(struct dwc3 *dwc,
1176                 const struct dwc3_event_depevt *event)
1177 {
1178         struct dwc3_ep  *dep = dwc->eps[event->endpoint_number];
1179         u8              cmd;
1180
1181         switch (event->endpoint_event) {
1182         case DWC3_DEPEVT_XFERCOMPLETE:
1183                 dwc3_ep0_xfer_complete(dwc, event);
1184                 break;
1185
1186         case DWC3_DEPEVT_XFERNOTREADY:
1187                 dwc3_ep0_xfernotready(dwc, event);
1188                 break;
1189
1190         case DWC3_DEPEVT_XFERINPROGRESS:
1191         case DWC3_DEPEVT_RXTXFIFOEVT:
1192         case DWC3_DEPEVT_STREAMEVT:
1193                 break;
1194         case DWC3_DEPEVT_EPCMDCMPLT:
1195                 cmd = DEPEVT_PARAMETER_CMD(event->parameters);
1196
1197                 if (cmd == DWC3_DEPCMD_ENDTRANSFER) {
1198                         dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING;
1199                         dep->flags &= ~DWC3_EP_TRANSFER_STARTED;
1200                 }
1201                 break;
1202         }
1203 }