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Merge tag 'cxl-for-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl
[linux.git] / drivers / usb / dwc3 / dwc3-qcom.c
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018, The Linux Foundation. All rights reserved.
3  *
4  * Inspired by dwc3-of-simple.c
5  */
6
7 #include <linux/acpi.h>
8 #include <linux/io.h>
9 #include <linux/of.h>
10 #include <linux/clk.h>
11 #include <linux/irq.h>
12 #include <linux/of_clk.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/extcon.h>
16 #include <linux/interconnect.h>
17 #include <linux/of_platform.h>
18 #include <linux/platform_device.h>
19 #include <linux/phy/phy.h>
20 #include <linux/pm_domain.h>
21 #include <linux/usb/of.h>
22 #include <linux/reset.h>
23 #include <linux/iopoll.h>
24 #include <linux/usb/hcd.h>
25 #include <linux/usb.h>
26 #include "core.h"
27
28 /* USB QSCRATCH Hardware registers */
29 #define QSCRATCH_HS_PHY_CTRL                    0x10
30 #define UTMI_OTG_VBUS_VALID                     BIT(20)
31 #define SW_SESSVLD_SEL                          BIT(28)
32
33 #define QSCRATCH_SS_PHY_CTRL                    0x30
34 #define LANE0_PWR_PRESENT                       BIT(24)
35
36 #define QSCRATCH_GENERAL_CFG                    0x08
37 #define PIPE_UTMI_CLK_SEL                       BIT(0)
38 #define PIPE3_PHYSTATUS_SW                      BIT(3)
39 #define PIPE_UTMI_CLK_DIS                       BIT(8)
40
41 #define PWR_EVNT_IRQ_STAT_REG                   0x58
42 #define PWR_EVNT_LPM_IN_L2_MASK                 BIT(4)
43 #define PWR_EVNT_LPM_OUT_L2_MASK                BIT(5)
44
45 #define SDM845_QSCRATCH_BASE_OFFSET             0xf8800
46 #define SDM845_QSCRATCH_SIZE                    0x400
47 #define SDM845_DWC3_CORE_SIZE                   0xcd00
48
49 /* Interconnect path bandwidths in MBps */
50 #define USB_MEMORY_AVG_HS_BW MBps_to_icc(240)
51 #define USB_MEMORY_PEAK_HS_BW MBps_to_icc(700)
52 #define USB_MEMORY_AVG_SS_BW  MBps_to_icc(1000)
53 #define USB_MEMORY_PEAK_SS_BW MBps_to_icc(2500)
54 #define APPS_USB_AVG_BW 0
55 #define APPS_USB_PEAK_BW MBps_to_icc(40)
56
57 struct dwc3_acpi_pdata {
58         u32                     qscratch_base_offset;
59         u32                     qscratch_base_size;
60         u32                     dwc3_core_base_size;
61         int                     hs_phy_irq_index;
62         int                     dp_hs_phy_irq_index;
63         int                     dm_hs_phy_irq_index;
64         int                     ss_phy_irq_index;
65         bool                    is_urs;
66 };
67
68 struct dwc3_qcom {
69         struct device           *dev;
70         void __iomem            *qscratch_base;
71         struct platform_device  *dwc3;
72         struct platform_device  *urs_usb;
73         struct clk              **clks;
74         int                     num_clocks;
75         struct reset_control    *resets;
76
77         int                     hs_phy_irq;
78         int                     dp_hs_phy_irq;
79         int                     dm_hs_phy_irq;
80         int                     ss_phy_irq;
81         enum usb_device_speed   usb2_speed;
82
83         struct extcon_dev       *edev;
84         struct extcon_dev       *host_edev;
85         struct notifier_block   vbus_nb;
86         struct notifier_block   host_nb;
87
88         const struct dwc3_acpi_pdata *acpi_pdata;
89
90         enum usb_dr_mode        mode;
91         bool                    is_suspended;
92         bool                    pm_suspended;
93         struct icc_path         *icc_path_ddr;
94         struct icc_path         *icc_path_apps;
95 };
96
97 static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
98 {
99         u32 reg;
100
101         reg = readl(base + offset);
102         reg |= val;
103         writel(reg, base + offset);
104
105         /* ensure that above write is through */
106         readl(base + offset);
107 }
108
109 static inline void dwc3_qcom_clrbits(void __iomem *base, u32 offset, u32 val)
110 {
111         u32 reg;
112
113         reg = readl(base + offset);
114         reg &= ~val;
115         writel(reg, base + offset);
116
117         /* ensure that above write is through */
118         readl(base + offset);
119 }
120
121 static void dwc3_qcom_vbus_override_enable(struct dwc3_qcom *qcom, bool enable)
122 {
123         if (enable) {
124                 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
125                                   LANE0_PWR_PRESENT);
126                 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
127                                   UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
128         } else {
129                 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
130                                   LANE0_PWR_PRESENT);
131                 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
132                                   UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
133         }
134 }
135
136 static int dwc3_qcom_vbus_notifier(struct notifier_block *nb,
137                                    unsigned long event, void *ptr)
138 {
139         struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, vbus_nb);
140
141         /* enable vbus override for device mode */
142         dwc3_qcom_vbus_override_enable(qcom, event);
143         qcom->mode = event ? USB_DR_MODE_PERIPHERAL : USB_DR_MODE_HOST;
144
145         return NOTIFY_DONE;
146 }
147
148 static int dwc3_qcom_host_notifier(struct notifier_block *nb,
149                                    unsigned long event, void *ptr)
150 {
151         struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, host_nb);
152
153         /* disable vbus override in host mode */
154         dwc3_qcom_vbus_override_enable(qcom, !event);
155         qcom->mode = event ? USB_DR_MODE_HOST : USB_DR_MODE_PERIPHERAL;
156
157         return NOTIFY_DONE;
158 }
159
160 static int dwc3_qcom_register_extcon(struct dwc3_qcom *qcom)
161 {
162         struct device           *dev = qcom->dev;
163         struct extcon_dev       *host_edev;
164         int                     ret;
165
166         if (!of_property_read_bool(dev->of_node, "extcon"))
167                 return 0;
168
169         qcom->edev = extcon_get_edev_by_phandle(dev, 0);
170         if (IS_ERR(qcom->edev))
171                 return PTR_ERR(qcom->edev);
172
173         qcom->vbus_nb.notifier_call = dwc3_qcom_vbus_notifier;
174
175         qcom->host_edev = extcon_get_edev_by_phandle(dev, 1);
176         if (IS_ERR(qcom->host_edev))
177                 qcom->host_edev = NULL;
178
179         ret = devm_extcon_register_notifier(dev, qcom->edev, EXTCON_USB,
180                                             &qcom->vbus_nb);
181         if (ret < 0) {
182                 dev_err(dev, "VBUS notifier register failed\n");
183                 return ret;
184         }
185
186         if (qcom->host_edev)
187                 host_edev = qcom->host_edev;
188         else
189                 host_edev = qcom->edev;
190
191         qcom->host_nb.notifier_call = dwc3_qcom_host_notifier;
192         ret = devm_extcon_register_notifier(dev, host_edev, EXTCON_USB_HOST,
193                                             &qcom->host_nb);
194         if (ret < 0) {
195                 dev_err(dev, "Host notifier register failed\n");
196                 return ret;
197         }
198
199         /* Update initial VBUS override based on extcon state */
200         if (extcon_get_state(qcom->edev, EXTCON_USB) ||
201             !extcon_get_state(host_edev, EXTCON_USB_HOST))
202                 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, true, qcom->edev);
203         else
204                 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, false, qcom->edev);
205
206         return 0;
207 }
208
209 static int dwc3_qcom_interconnect_enable(struct dwc3_qcom *qcom)
210 {
211         int ret;
212
213         ret = icc_enable(qcom->icc_path_ddr);
214         if (ret)
215                 return ret;
216
217         ret = icc_enable(qcom->icc_path_apps);
218         if (ret)
219                 icc_disable(qcom->icc_path_ddr);
220
221         return ret;
222 }
223
224 static int dwc3_qcom_interconnect_disable(struct dwc3_qcom *qcom)
225 {
226         int ret;
227
228         ret = icc_disable(qcom->icc_path_ddr);
229         if (ret)
230                 return ret;
231
232         ret = icc_disable(qcom->icc_path_apps);
233         if (ret)
234                 icc_enable(qcom->icc_path_ddr);
235
236         return ret;
237 }
238
239 /**
240  * dwc3_qcom_interconnect_init() - Get interconnect path handles
241  * and set bandwidth.
242  * @qcom:                       Pointer to the concerned usb core.
243  *
244  */
245 static int dwc3_qcom_interconnect_init(struct dwc3_qcom *qcom)
246 {
247         struct device *dev = qcom->dev;
248         int ret;
249
250         if (has_acpi_companion(dev))
251                 return 0;
252
253         qcom->icc_path_ddr = of_icc_get(dev, "usb-ddr");
254         if (IS_ERR(qcom->icc_path_ddr)) {
255                 dev_err(dev, "failed to get usb-ddr path: %ld\n",
256                         PTR_ERR(qcom->icc_path_ddr));
257                 return PTR_ERR(qcom->icc_path_ddr);
258         }
259
260         qcom->icc_path_apps = of_icc_get(dev, "apps-usb");
261         if (IS_ERR(qcom->icc_path_apps)) {
262                 dev_err(dev, "failed to get apps-usb path: %ld\n",
263                                 PTR_ERR(qcom->icc_path_apps));
264                 return PTR_ERR(qcom->icc_path_apps);
265         }
266
267         if (usb_get_maximum_speed(&qcom->dwc3->dev) >= USB_SPEED_SUPER ||
268                         usb_get_maximum_speed(&qcom->dwc3->dev) == USB_SPEED_UNKNOWN)
269                 ret = icc_set_bw(qcom->icc_path_ddr,
270                         USB_MEMORY_AVG_SS_BW, USB_MEMORY_PEAK_SS_BW);
271         else
272                 ret = icc_set_bw(qcom->icc_path_ddr,
273                         USB_MEMORY_AVG_HS_BW, USB_MEMORY_PEAK_HS_BW);
274
275         if (ret) {
276                 dev_err(dev, "failed to set bandwidth for usb-ddr path: %d\n", ret);
277                 return ret;
278         }
279
280         ret = icc_set_bw(qcom->icc_path_apps,
281                 APPS_USB_AVG_BW, APPS_USB_PEAK_BW);
282         if (ret) {
283                 dev_err(dev, "failed to set bandwidth for apps-usb path: %d\n", ret);
284                 return ret;
285         }
286
287         return 0;
288 }
289
290 /**
291  * dwc3_qcom_interconnect_exit() - Release interconnect path handles
292  * @qcom:                       Pointer to the concerned usb core.
293  *
294  * This function is used to release interconnect path handle.
295  */
296 static void dwc3_qcom_interconnect_exit(struct dwc3_qcom *qcom)
297 {
298         icc_put(qcom->icc_path_ddr);
299         icc_put(qcom->icc_path_apps);
300 }
301
302 static enum usb_device_speed dwc3_qcom_read_usb2_speed(struct dwc3_qcom *qcom)
303 {
304         struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
305         struct usb_hcd *hcd = platform_get_drvdata(dwc->xhci);
306         struct usb_device *udev;
307
308         /*
309          * It is possible to query the speed of all children of
310          * USB2.0 root hub via usb_hub_for_each_child(). DWC3 code
311          * currently supports only 1 port per controller. So
312          * this is sufficient.
313          */
314         udev = usb_hub_find_child(hcd->self.root_hub, 1);
315
316         if (!udev)
317                 return USB_SPEED_UNKNOWN;
318
319         return udev->speed;
320 }
321
322 static void dwc3_qcom_enable_wakeup_irq(int irq, unsigned int polarity)
323 {
324         if (!irq)
325                 return;
326
327         if (polarity)
328                 irq_set_irq_type(irq, polarity);
329
330         enable_irq(irq);
331         enable_irq_wake(irq);
332 }
333
334 static void dwc3_qcom_disable_wakeup_irq(int irq)
335 {
336         if (!irq)
337                 return;
338
339         disable_irq_wake(irq);
340         disable_irq_nosync(irq);
341 }
342
343 static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom)
344 {
345         dwc3_qcom_disable_wakeup_irq(qcom->hs_phy_irq);
346
347         if (qcom->usb2_speed == USB_SPEED_LOW) {
348                 dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq);
349         } else if ((qcom->usb2_speed == USB_SPEED_HIGH) ||
350                         (qcom->usb2_speed == USB_SPEED_FULL)) {
351                 dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq);
352         } else {
353                 dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq);
354                 dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq);
355         }
356
357         dwc3_qcom_disable_wakeup_irq(qcom->ss_phy_irq);
358 }
359
360 static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
361 {
362         dwc3_qcom_enable_wakeup_irq(qcom->hs_phy_irq, 0);
363
364         /*
365          * Configure DP/DM line interrupts based on the USB2 device attached to
366          * the root hub port. When HS/FS device is connected, configure the DP line
367          * as falling edge to detect both disconnect and remote wakeup scenarios. When
368          * LS device is connected, configure DM line as falling edge to detect both
369          * disconnect and remote wakeup. When no device is connected, configure both
370          * DP and DM lines as rising edge to detect HS/HS/LS device connect scenario.
371          */
372
373         if (qcom->usb2_speed == USB_SPEED_LOW) {
374                 dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq,
375                                                 IRQ_TYPE_EDGE_FALLING);
376         } else if ((qcom->usb2_speed == USB_SPEED_HIGH) ||
377                         (qcom->usb2_speed == USB_SPEED_FULL)) {
378                 dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq,
379                                                 IRQ_TYPE_EDGE_FALLING);
380         } else {
381                 dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq,
382                                                 IRQ_TYPE_EDGE_RISING);
383                 dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq,
384                                                 IRQ_TYPE_EDGE_RISING);
385         }
386
387         dwc3_qcom_enable_wakeup_irq(qcom->ss_phy_irq, 0);
388 }
389
390 static int dwc3_qcom_suspend(struct dwc3_qcom *qcom)
391 {
392         u32 val;
393         int i, ret;
394
395         if (qcom->is_suspended)
396                 return 0;
397
398         val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG);
399         if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
400                 dev_err(qcom->dev, "HS-PHY not in L2\n");
401
402         for (i = qcom->num_clocks - 1; i >= 0; i--)
403                 clk_disable_unprepare(qcom->clks[i]);
404
405         ret = dwc3_qcom_interconnect_disable(qcom);
406         if (ret)
407                 dev_warn(qcom->dev, "failed to disable interconnect: %d\n", ret);
408
409         if (device_may_wakeup(qcom->dev)) {
410                 qcom->usb2_speed = dwc3_qcom_read_usb2_speed(qcom);
411                 dwc3_qcom_enable_interrupts(qcom);
412         }
413
414         qcom->is_suspended = true;
415
416         return 0;
417 }
418
419 static int dwc3_qcom_resume(struct dwc3_qcom *qcom)
420 {
421         int ret;
422         int i;
423
424         if (!qcom->is_suspended)
425                 return 0;
426
427         if (device_may_wakeup(qcom->dev))
428                 dwc3_qcom_disable_interrupts(qcom);
429
430         for (i = 0; i < qcom->num_clocks; i++) {
431                 ret = clk_prepare_enable(qcom->clks[i]);
432                 if (ret < 0) {
433                         while (--i >= 0)
434                                 clk_disable_unprepare(qcom->clks[i]);
435                         return ret;
436                 }
437         }
438
439         ret = dwc3_qcom_interconnect_enable(qcom);
440         if (ret)
441                 dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret);
442
443         /* Clear existing events from PHY related to L2 in/out */
444         dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG,
445                           PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK);
446
447         qcom->is_suspended = false;
448
449         return 0;
450 }
451
452 static irqreturn_t qcom_dwc3_resume_irq(int irq, void *data)
453 {
454         struct dwc3_qcom *qcom = data;
455         struct dwc3     *dwc = platform_get_drvdata(qcom->dwc3);
456
457         /* If pm_suspended then let pm_resume take care of resuming h/w */
458         if (qcom->pm_suspended)
459                 return IRQ_HANDLED;
460
461         if (dwc->xhci)
462                 pm_runtime_resume(&dwc->xhci->dev);
463
464         return IRQ_HANDLED;
465 }
466
467 static void dwc3_qcom_select_utmi_clk(struct dwc3_qcom *qcom)
468 {
469         /* Configure dwc3 to use UTMI clock as PIPE clock not present */
470         dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
471                           PIPE_UTMI_CLK_DIS);
472
473         usleep_range(100, 1000);
474
475         dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
476                           PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW);
477
478         usleep_range(100, 1000);
479
480         dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
481                           PIPE_UTMI_CLK_DIS);
482 }
483
484 static int dwc3_qcom_get_irq(struct platform_device *pdev,
485                              const char *name, int num)
486 {
487         struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
488         struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb : pdev;
489         struct device_node *np = pdev->dev.of_node;
490         int ret;
491
492         if (np)
493                 ret = platform_get_irq_byname_optional(pdev_irq, name);
494         else
495                 ret = platform_get_irq_optional(pdev_irq, num);
496
497         return ret;
498 }
499
500 static int dwc3_qcom_setup_irq(struct platform_device *pdev)
501 {
502         struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
503         const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata;
504         int irq;
505         int ret;
506
507         irq = dwc3_qcom_get_irq(pdev, "hs_phy_irq",
508                                 pdata ? pdata->hs_phy_irq_index : -1);
509         if (irq > 0) {
510                 /* Keep wakeup interrupts disabled until suspend */
511                 irq_set_status_flags(irq, IRQ_NOAUTOEN);
512                 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
513                                         qcom_dwc3_resume_irq,
514                                         IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
515                                         "qcom_dwc3 HS", qcom);
516                 if (ret) {
517                         dev_err(qcom->dev, "hs_phy_irq failed: %d\n", ret);
518                         return ret;
519                 }
520                 qcom->hs_phy_irq = irq;
521         }
522
523         irq = dwc3_qcom_get_irq(pdev, "dp_hs_phy_irq",
524                                 pdata ? pdata->dp_hs_phy_irq_index : -1);
525         if (irq > 0) {
526                 irq_set_status_flags(irq, IRQ_NOAUTOEN);
527                 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
528                                         qcom_dwc3_resume_irq,
529                                         IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
530                                         "qcom_dwc3 DP_HS", qcom);
531                 if (ret) {
532                         dev_err(qcom->dev, "dp_hs_phy_irq failed: %d\n", ret);
533                         return ret;
534                 }
535                 qcom->dp_hs_phy_irq = irq;
536         }
537
538         irq = dwc3_qcom_get_irq(pdev, "dm_hs_phy_irq",
539                                 pdata ? pdata->dm_hs_phy_irq_index : -1);
540         if (irq > 0) {
541                 irq_set_status_flags(irq, IRQ_NOAUTOEN);
542                 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
543                                         qcom_dwc3_resume_irq,
544                                         IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
545                                         "qcom_dwc3 DM_HS", qcom);
546                 if (ret) {
547                         dev_err(qcom->dev, "dm_hs_phy_irq failed: %d\n", ret);
548                         return ret;
549                 }
550                 qcom->dm_hs_phy_irq = irq;
551         }
552
553         irq = dwc3_qcom_get_irq(pdev, "ss_phy_irq",
554                                 pdata ? pdata->ss_phy_irq_index : -1);
555         if (irq > 0) {
556                 irq_set_status_flags(irq, IRQ_NOAUTOEN);
557                 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
558                                         qcom_dwc3_resume_irq,
559                                         IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
560                                         "qcom_dwc3 SS", qcom);
561                 if (ret) {
562                         dev_err(qcom->dev, "ss_phy_irq failed: %d\n", ret);
563                         return ret;
564                 }
565                 qcom->ss_phy_irq = irq;
566         }
567
568         return 0;
569 }
570
571 static int dwc3_qcom_clk_init(struct dwc3_qcom *qcom, int count)
572 {
573         struct device           *dev = qcom->dev;
574         struct device_node      *np = dev->of_node;
575         int                     i;
576
577         if (!np || !count)
578                 return 0;
579
580         if (count < 0)
581                 return count;
582
583         qcom->num_clocks = count;
584
585         qcom->clks = devm_kcalloc(dev, qcom->num_clocks,
586                                   sizeof(struct clk *), GFP_KERNEL);
587         if (!qcom->clks)
588                 return -ENOMEM;
589
590         for (i = 0; i < qcom->num_clocks; i++) {
591                 struct clk      *clk;
592                 int             ret;
593
594                 clk = of_clk_get(np, i);
595                 if (IS_ERR(clk)) {
596                         while (--i >= 0)
597                                 clk_put(qcom->clks[i]);
598                         return PTR_ERR(clk);
599                 }
600
601                 ret = clk_prepare_enable(clk);
602                 if (ret < 0) {
603                         while (--i >= 0) {
604                                 clk_disable_unprepare(qcom->clks[i]);
605                                 clk_put(qcom->clks[i]);
606                         }
607                         clk_put(clk);
608
609                         return ret;
610                 }
611
612                 qcom->clks[i] = clk;
613         }
614
615         return 0;
616 }
617
618 static const struct property_entry dwc3_qcom_acpi_properties[] = {
619         PROPERTY_ENTRY_STRING("dr_mode", "host"),
620         {}
621 };
622
623 static const struct software_node dwc3_qcom_swnode = {
624         .properties = dwc3_qcom_acpi_properties,
625 };
626
627 static int dwc3_qcom_acpi_register_core(struct platform_device *pdev)
628 {
629         struct dwc3_qcom        *qcom = platform_get_drvdata(pdev);
630         struct device           *dev = &pdev->dev;
631         struct resource         *res, *child_res = NULL;
632         struct platform_device  *pdev_irq = qcom->urs_usb ? qcom->urs_usb :
633                                                             pdev;
634         int                     irq;
635         int                     ret;
636
637         qcom->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
638         if (!qcom->dwc3)
639                 return -ENOMEM;
640
641         qcom->dwc3->dev.parent = dev;
642         qcom->dwc3->dev.type = dev->type;
643         qcom->dwc3->dev.dma_mask = dev->dma_mask;
644         qcom->dwc3->dev.dma_parms = dev->dma_parms;
645         qcom->dwc3->dev.coherent_dma_mask = dev->coherent_dma_mask;
646
647         child_res = kcalloc(2, sizeof(*child_res), GFP_KERNEL);
648         if (!child_res) {
649                 platform_device_put(qcom->dwc3);
650                 return -ENOMEM;
651         }
652
653         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
654         if (!res) {
655                 dev_err(&pdev->dev, "failed to get memory resource\n");
656                 ret = -ENODEV;
657                 goto out;
658         }
659
660         child_res[0].flags = res->flags;
661         child_res[0].start = res->start;
662         child_res[0].end = child_res[0].start +
663                 qcom->acpi_pdata->dwc3_core_base_size;
664
665         irq = platform_get_irq(pdev_irq, 0);
666         if (irq < 0) {
667                 ret = irq;
668                 goto out;
669         }
670         child_res[1].flags = IORESOURCE_IRQ;
671         child_res[1].start = child_res[1].end = irq;
672
673         ret = platform_device_add_resources(qcom->dwc3, child_res, 2);
674         if (ret) {
675                 dev_err(&pdev->dev, "failed to add resources\n");
676                 goto out;
677         }
678
679         ret = device_add_software_node(&qcom->dwc3->dev, &dwc3_qcom_swnode);
680         if (ret < 0) {
681                 dev_err(&pdev->dev, "failed to add properties\n");
682                 goto out;
683         }
684
685         ret = platform_device_add(qcom->dwc3);
686         if (ret) {
687                 dev_err(&pdev->dev, "failed to add device\n");
688                 device_remove_software_node(&qcom->dwc3->dev);
689                 goto out;
690         }
691         kfree(child_res);
692         return 0;
693
694 out:
695         platform_device_put(qcom->dwc3);
696         kfree(child_res);
697         return ret;
698 }
699
700 static int dwc3_qcom_of_register_core(struct platform_device *pdev)
701 {
702         struct dwc3_qcom        *qcom = platform_get_drvdata(pdev);
703         struct device_node      *np = pdev->dev.of_node, *dwc3_np;
704         struct device           *dev = &pdev->dev;
705         int                     ret;
706
707         dwc3_np = of_get_compatible_child(np, "snps,dwc3");
708         if (!dwc3_np) {
709                 dev_err(dev, "failed to find dwc3 core child\n");
710                 return -ENODEV;
711         }
712
713         ret = of_platform_populate(np, NULL, NULL, dev);
714         if (ret) {
715                 dev_err(dev, "failed to register dwc3 core - %d\n", ret);
716                 goto node_put;
717         }
718
719         qcom->dwc3 = of_find_device_by_node(dwc3_np);
720         if (!qcom->dwc3) {
721                 ret = -ENODEV;
722                 dev_err(dev, "failed to get dwc3 platform device\n");
723         }
724
725 node_put:
726         of_node_put(dwc3_np);
727
728         return ret;
729 }
730
731 static struct platform_device *
732 dwc3_qcom_create_urs_usb_platdev(struct device *dev)
733 {
734         struct fwnode_handle *fwh;
735         struct acpi_device *adev;
736         char name[8];
737         int ret;
738         int id;
739
740         /* Figure out device id */
741         ret = sscanf(fwnode_get_name(dev->fwnode), "URS%d", &id);
742         if (!ret)
743                 return NULL;
744
745         /* Find the child using name */
746         snprintf(name, sizeof(name), "USB%d", id);
747         fwh = fwnode_get_named_child_node(dev->fwnode, name);
748         if (!fwh)
749                 return NULL;
750
751         adev = to_acpi_device_node(fwh);
752         if (!adev)
753                 return NULL;
754
755         return acpi_create_platform_device(adev, NULL);
756 }
757
758 static int dwc3_qcom_probe(struct platform_device *pdev)
759 {
760         struct device_node *np = pdev->dev.of_node;
761         struct device *dev = &pdev->dev;
762         struct dwc3_qcom *qcom;
763         struct resource *res, *parent_res = NULL;
764         int ret, i;
765         bool ignore_pipe_clk;
766         struct generic_pm_domain *genpd;
767
768         qcom = devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL);
769         if (!qcom)
770                 return -ENOMEM;
771
772         platform_set_drvdata(pdev, qcom);
773         qcom->dev = &pdev->dev;
774
775         genpd = pd_to_genpd(qcom->dev->pm_domain);
776
777         if (has_acpi_companion(dev)) {
778                 qcom->acpi_pdata = acpi_device_get_match_data(dev);
779                 if (!qcom->acpi_pdata) {
780                         dev_err(&pdev->dev, "no supporting ACPI device data\n");
781                         return -EINVAL;
782                 }
783         }
784
785         qcom->resets = devm_reset_control_array_get_optional_exclusive(dev);
786         if (IS_ERR(qcom->resets)) {
787                 ret = PTR_ERR(qcom->resets);
788                 dev_err(&pdev->dev, "failed to get resets, err=%d\n", ret);
789                 return ret;
790         }
791
792         ret = reset_control_assert(qcom->resets);
793         if (ret) {
794                 dev_err(&pdev->dev, "failed to assert resets, err=%d\n", ret);
795                 return ret;
796         }
797
798         usleep_range(10, 1000);
799
800         ret = reset_control_deassert(qcom->resets);
801         if (ret) {
802                 dev_err(&pdev->dev, "failed to deassert resets, err=%d\n", ret);
803                 goto reset_assert;
804         }
805
806         ret = dwc3_qcom_clk_init(qcom, of_clk_get_parent_count(np));
807         if (ret) {
808                 dev_err(dev, "failed to get clocks\n");
809                 goto reset_assert;
810         }
811
812         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
813
814         if (np) {
815                 parent_res = res;
816         } else {
817                 parent_res = kmemdup(res, sizeof(struct resource), GFP_KERNEL);
818                 if (!parent_res)
819                         return -ENOMEM;
820
821                 parent_res->start = res->start +
822                         qcom->acpi_pdata->qscratch_base_offset;
823                 parent_res->end = parent_res->start +
824                         qcom->acpi_pdata->qscratch_base_size;
825
826                 if (qcom->acpi_pdata->is_urs) {
827                         qcom->urs_usb = dwc3_qcom_create_urs_usb_platdev(dev);
828                         if (IS_ERR_OR_NULL(qcom->urs_usb)) {
829                                 dev_err(dev, "failed to create URS USB platdev\n");
830                                 if (!qcom->urs_usb)
831                                         return -ENODEV;
832                                 else
833                                         return PTR_ERR(qcom->urs_usb);
834                         }
835                 }
836         }
837
838         qcom->qscratch_base = devm_ioremap_resource(dev, parent_res);
839         if (IS_ERR(qcom->qscratch_base)) {
840                 ret = PTR_ERR(qcom->qscratch_base);
841                 goto clk_disable;
842         }
843
844         ret = dwc3_qcom_setup_irq(pdev);
845         if (ret) {
846                 dev_err(dev, "failed to setup IRQs, err=%d\n", ret);
847                 goto clk_disable;
848         }
849
850         /*
851          * Disable pipe_clk requirement if specified. Used when dwc3
852          * operates without SSPHY and only HS/FS/LS modes are supported.
853          */
854         ignore_pipe_clk = device_property_read_bool(dev,
855                                 "qcom,select-utmi-as-pipe-clk");
856         if (ignore_pipe_clk)
857                 dwc3_qcom_select_utmi_clk(qcom);
858
859         if (np)
860                 ret = dwc3_qcom_of_register_core(pdev);
861         else
862                 ret = dwc3_qcom_acpi_register_core(pdev);
863
864         if (ret) {
865                 dev_err(dev, "failed to register DWC3 Core, err=%d\n", ret);
866                 goto depopulate;
867         }
868
869         ret = dwc3_qcom_interconnect_init(qcom);
870         if (ret)
871                 goto depopulate;
872
873         qcom->mode = usb_get_dr_mode(&qcom->dwc3->dev);
874
875         /* enable vbus override for device mode */
876         if (qcom->mode == USB_DR_MODE_PERIPHERAL)
877                 dwc3_qcom_vbus_override_enable(qcom, true);
878
879         /* register extcon to override sw_vbus on Vbus change later */
880         ret = dwc3_qcom_register_extcon(qcom);
881         if (ret)
882                 goto interconnect_exit;
883
884         if (device_can_wakeup(&qcom->dwc3->dev)) {
885                 /*
886                  * Setting GENPD_FLAG_ALWAYS_ON flag takes care of keeping
887                  * genpd on in both runtime suspend and system suspend cases.
888                  */
889                 genpd->flags |= GENPD_FLAG_ALWAYS_ON;
890                 device_init_wakeup(&pdev->dev, true);
891         } else {
892                 genpd->flags |= GENPD_FLAG_RPM_ALWAYS_ON;
893         }
894
895         qcom->is_suspended = false;
896         pm_runtime_set_active(dev);
897         pm_runtime_enable(dev);
898         pm_runtime_forbid(dev);
899
900         return 0;
901
902 interconnect_exit:
903         dwc3_qcom_interconnect_exit(qcom);
904 depopulate:
905         if (np)
906                 of_platform_depopulate(&pdev->dev);
907         else
908                 platform_device_put(pdev);
909 clk_disable:
910         for (i = qcom->num_clocks - 1; i >= 0; i--) {
911                 clk_disable_unprepare(qcom->clks[i]);
912                 clk_put(qcom->clks[i]);
913         }
914 reset_assert:
915         reset_control_assert(qcom->resets);
916
917         return ret;
918 }
919
920 static int dwc3_qcom_remove(struct platform_device *pdev)
921 {
922         struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
923         struct device *dev = &pdev->dev;
924         int i;
925
926         device_remove_software_node(&qcom->dwc3->dev);
927         of_platform_depopulate(dev);
928
929         for (i = qcom->num_clocks - 1; i >= 0; i--) {
930                 clk_disable_unprepare(qcom->clks[i]);
931                 clk_put(qcom->clks[i]);
932         }
933         qcom->num_clocks = 0;
934
935         dwc3_qcom_interconnect_exit(qcom);
936         reset_control_assert(qcom->resets);
937
938         pm_runtime_allow(dev);
939         pm_runtime_disable(dev);
940
941         return 0;
942 }
943
944 static int __maybe_unused dwc3_qcom_pm_suspend(struct device *dev)
945 {
946         struct dwc3_qcom *qcom = dev_get_drvdata(dev);
947         int ret = 0;
948
949         ret = dwc3_qcom_suspend(qcom);
950         if (!ret)
951                 qcom->pm_suspended = true;
952
953         return ret;
954 }
955
956 static int __maybe_unused dwc3_qcom_pm_resume(struct device *dev)
957 {
958         struct dwc3_qcom *qcom = dev_get_drvdata(dev);
959         int ret;
960
961         ret = dwc3_qcom_resume(qcom);
962         if (!ret)
963                 qcom->pm_suspended = false;
964
965         return ret;
966 }
967
968 static int __maybe_unused dwc3_qcom_runtime_suspend(struct device *dev)
969 {
970         struct dwc3_qcom *qcom = dev_get_drvdata(dev);
971
972         return dwc3_qcom_suspend(qcom);
973 }
974
975 static int __maybe_unused dwc3_qcom_runtime_resume(struct device *dev)
976 {
977         struct dwc3_qcom *qcom = dev_get_drvdata(dev);
978
979         return dwc3_qcom_resume(qcom);
980 }
981
982 static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = {
983         SET_SYSTEM_SLEEP_PM_OPS(dwc3_qcom_pm_suspend, dwc3_qcom_pm_resume)
984         SET_RUNTIME_PM_OPS(dwc3_qcom_runtime_suspend, dwc3_qcom_runtime_resume,
985                            NULL)
986 };
987
988 static const struct of_device_id dwc3_qcom_of_match[] = {
989         { .compatible = "qcom,dwc3" },
990         { .compatible = "qcom,msm8996-dwc3" },
991         { .compatible = "qcom,msm8998-dwc3" },
992         { .compatible = "qcom,sdm660-dwc3" },
993         { .compatible = "qcom,sdm845-dwc3" },
994         { }
995 };
996 MODULE_DEVICE_TABLE(of, dwc3_qcom_of_match);
997
998 #ifdef CONFIG_ACPI
999 static const struct dwc3_acpi_pdata sdm845_acpi_pdata = {
1000         .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
1001         .qscratch_base_size = SDM845_QSCRATCH_SIZE,
1002         .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
1003         .hs_phy_irq_index = 1,
1004         .dp_hs_phy_irq_index = 4,
1005         .dm_hs_phy_irq_index = 3,
1006         .ss_phy_irq_index = 2
1007 };
1008
1009 static const struct dwc3_acpi_pdata sdm845_acpi_urs_pdata = {
1010         .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
1011         .qscratch_base_size = SDM845_QSCRATCH_SIZE,
1012         .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
1013         .hs_phy_irq_index = 1,
1014         .dp_hs_phy_irq_index = 4,
1015         .dm_hs_phy_irq_index = 3,
1016         .ss_phy_irq_index = 2,
1017         .is_urs = true,
1018 };
1019
1020 static const struct acpi_device_id dwc3_qcom_acpi_match[] = {
1021         { "QCOM2430", (unsigned long)&sdm845_acpi_pdata },
1022         { "QCOM0304", (unsigned long)&sdm845_acpi_urs_pdata },
1023         { "QCOM0497", (unsigned long)&sdm845_acpi_urs_pdata },
1024         { "QCOM04A6", (unsigned long)&sdm845_acpi_pdata },
1025         { },
1026 };
1027 MODULE_DEVICE_TABLE(acpi, dwc3_qcom_acpi_match);
1028 #endif
1029
1030 static struct platform_driver dwc3_qcom_driver = {
1031         .probe          = dwc3_qcom_probe,
1032         .remove         = dwc3_qcom_remove,
1033         .driver         = {
1034                 .name   = "dwc3-qcom",
1035                 .pm     = &dwc3_qcom_dev_pm_ops,
1036                 .of_match_table = dwc3_qcom_of_match,
1037                 .acpi_match_table = ACPI_PTR(dwc3_qcom_acpi_match),
1038         },
1039 };
1040
1041 module_platform_driver(dwc3_qcom_driver);
1042
1043 MODULE_LICENSE("GPL v2");
1044 MODULE_DESCRIPTION("DesignWare DWC3 QCOM Glue Driver");
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