1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 * Inspired by dwc3-of-simple.c
7 #include <linux/acpi.h>
10 #include <linux/clk.h>
11 #include <linux/irq.h>
12 #include <linux/of_clk.h>
13 #include <linux/module.h>
14 #include <linux/kernel.h>
15 #include <linux/extcon.h>
16 #include <linux/interconnect.h>
17 #include <linux/of_platform.h>
18 #include <linux/platform_device.h>
19 #include <linux/phy/phy.h>
20 #include <linux/pm_domain.h>
21 #include <linux/usb/of.h>
22 #include <linux/reset.h>
23 #include <linux/iopoll.h>
24 #include <linux/usb/hcd.h>
25 #include <linux/usb.h>
28 /* USB QSCRATCH Hardware registers */
29 #define QSCRATCH_HS_PHY_CTRL 0x10
30 #define UTMI_OTG_VBUS_VALID BIT(20)
31 #define SW_SESSVLD_SEL BIT(28)
33 #define QSCRATCH_SS_PHY_CTRL 0x30
34 #define LANE0_PWR_PRESENT BIT(24)
36 #define QSCRATCH_GENERAL_CFG 0x08
37 #define PIPE_UTMI_CLK_SEL BIT(0)
38 #define PIPE3_PHYSTATUS_SW BIT(3)
39 #define PIPE_UTMI_CLK_DIS BIT(8)
41 #define PWR_EVNT_IRQ_STAT_REG 0x58
42 #define PWR_EVNT_LPM_IN_L2_MASK BIT(4)
43 #define PWR_EVNT_LPM_OUT_L2_MASK BIT(5)
45 #define SDM845_QSCRATCH_BASE_OFFSET 0xf8800
46 #define SDM845_QSCRATCH_SIZE 0x400
47 #define SDM845_DWC3_CORE_SIZE 0xcd00
49 /* Interconnect path bandwidths in MBps */
50 #define USB_MEMORY_AVG_HS_BW MBps_to_icc(240)
51 #define USB_MEMORY_PEAK_HS_BW MBps_to_icc(700)
52 #define USB_MEMORY_AVG_SS_BW MBps_to_icc(1000)
53 #define USB_MEMORY_PEAK_SS_BW MBps_to_icc(2500)
54 #define APPS_USB_AVG_BW 0
55 #define APPS_USB_PEAK_BW MBps_to_icc(40)
57 struct dwc3_acpi_pdata {
58 u32 qscratch_base_offset;
59 u32 qscratch_base_size;
60 u32 dwc3_core_base_size;
62 int dp_hs_phy_irq_index;
63 int dm_hs_phy_irq_index;
70 void __iomem *qscratch_base;
71 struct platform_device *dwc3;
72 struct platform_device *urs_usb;
75 struct reset_control *resets;
81 enum usb_device_speed usb2_speed;
83 struct extcon_dev *edev;
84 struct extcon_dev *host_edev;
85 struct notifier_block vbus_nb;
86 struct notifier_block host_nb;
88 const struct dwc3_acpi_pdata *acpi_pdata;
90 enum usb_dr_mode mode;
93 struct icc_path *icc_path_ddr;
94 struct icc_path *icc_path_apps;
97 static inline void dwc3_qcom_setbits(void __iomem *base, u32 offset, u32 val)
101 reg = readl(base + offset);
103 writel(reg, base + offset);
105 /* ensure that above write is through */
106 readl(base + offset);
109 static inline void dwc3_qcom_clrbits(void __iomem *base, u32 offset, u32 val)
113 reg = readl(base + offset);
115 writel(reg, base + offset);
117 /* ensure that above write is through */
118 readl(base + offset);
121 static void dwc3_qcom_vbus_override_enable(struct dwc3_qcom *qcom, bool enable)
124 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
126 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
127 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
129 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_SS_PHY_CTRL,
131 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_HS_PHY_CTRL,
132 UTMI_OTG_VBUS_VALID | SW_SESSVLD_SEL);
136 static int dwc3_qcom_vbus_notifier(struct notifier_block *nb,
137 unsigned long event, void *ptr)
139 struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, vbus_nb);
141 /* enable vbus override for device mode */
142 dwc3_qcom_vbus_override_enable(qcom, event);
143 qcom->mode = event ? USB_DR_MODE_PERIPHERAL : USB_DR_MODE_HOST;
148 static int dwc3_qcom_host_notifier(struct notifier_block *nb,
149 unsigned long event, void *ptr)
151 struct dwc3_qcom *qcom = container_of(nb, struct dwc3_qcom, host_nb);
153 /* disable vbus override in host mode */
154 dwc3_qcom_vbus_override_enable(qcom, !event);
155 qcom->mode = event ? USB_DR_MODE_HOST : USB_DR_MODE_PERIPHERAL;
160 static int dwc3_qcom_register_extcon(struct dwc3_qcom *qcom)
162 struct device *dev = qcom->dev;
163 struct extcon_dev *host_edev;
166 if (!of_property_read_bool(dev->of_node, "extcon"))
169 qcom->edev = extcon_get_edev_by_phandle(dev, 0);
170 if (IS_ERR(qcom->edev))
171 return PTR_ERR(qcom->edev);
173 qcom->vbus_nb.notifier_call = dwc3_qcom_vbus_notifier;
175 qcom->host_edev = extcon_get_edev_by_phandle(dev, 1);
176 if (IS_ERR(qcom->host_edev))
177 qcom->host_edev = NULL;
179 ret = devm_extcon_register_notifier(dev, qcom->edev, EXTCON_USB,
182 dev_err(dev, "VBUS notifier register failed\n");
187 host_edev = qcom->host_edev;
189 host_edev = qcom->edev;
191 qcom->host_nb.notifier_call = dwc3_qcom_host_notifier;
192 ret = devm_extcon_register_notifier(dev, host_edev, EXTCON_USB_HOST,
195 dev_err(dev, "Host notifier register failed\n");
199 /* Update initial VBUS override based on extcon state */
200 if (extcon_get_state(qcom->edev, EXTCON_USB) ||
201 !extcon_get_state(host_edev, EXTCON_USB_HOST))
202 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, true, qcom->edev);
204 dwc3_qcom_vbus_notifier(&qcom->vbus_nb, false, qcom->edev);
209 static int dwc3_qcom_interconnect_enable(struct dwc3_qcom *qcom)
213 ret = icc_enable(qcom->icc_path_ddr);
217 ret = icc_enable(qcom->icc_path_apps);
219 icc_disable(qcom->icc_path_ddr);
224 static int dwc3_qcom_interconnect_disable(struct dwc3_qcom *qcom)
228 ret = icc_disable(qcom->icc_path_ddr);
232 ret = icc_disable(qcom->icc_path_apps);
234 icc_enable(qcom->icc_path_ddr);
240 * dwc3_qcom_interconnect_init() - Get interconnect path handles
242 * @qcom: Pointer to the concerned usb core.
245 static int dwc3_qcom_interconnect_init(struct dwc3_qcom *qcom)
247 struct device *dev = qcom->dev;
250 if (has_acpi_companion(dev))
253 qcom->icc_path_ddr = of_icc_get(dev, "usb-ddr");
254 if (IS_ERR(qcom->icc_path_ddr)) {
255 dev_err(dev, "failed to get usb-ddr path: %ld\n",
256 PTR_ERR(qcom->icc_path_ddr));
257 return PTR_ERR(qcom->icc_path_ddr);
260 qcom->icc_path_apps = of_icc_get(dev, "apps-usb");
261 if (IS_ERR(qcom->icc_path_apps)) {
262 dev_err(dev, "failed to get apps-usb path: %ld\n",
263 PTR_ERR(qcom->icc_path_apps));
264 return PTR_ERR(qcom->icc_path_apps);
267 if (usb_get_maximum_speed(&qcom->dwc3->dev) >= USB_SPEED_SUPER ||
268 usb_get_maximum_speed(&qcom->dwc3->dev) == USB_SPEED_UNKNOWN)
269 ret = icc_set_bw(qcom->icc_path_ddr,
270 USB_MEMORY_AVG_SS_BW, USB_MEMORY_PEAK_SS_BW);
272 ret = icc_set_bw(qcom->icc_path_ddr,
273 USB_MEMORY_AVG_HS_BW, USB_MEMORY_PEAK_HS_BW);
276 dev_err(dev, "failed to set bandwidth for usb-ddr path: %d\n", ret);
280 ret = icc_set_bw(qcom->icc_path_apps,
281 APPS_USB_AVG_BW, APPS_USB_PEAK_BW);
283 dev_err(dev, "failed to set bandwidth for apps-usb path: %d\n", ret);
291 * dwc3_qcom_interconnect_exit() - Release interconnect path handles
292 * @qcom: Pointer to the concerned usb core.
294 * This function is used to release interconnect path handle.
296 static void dwc3_qcom_interconnect_exit(struct dwc3_qcom *qcom)
298 icc_put(qcom->icc_path_ddr);
299 icc_put(qcom->icc_path_apps);
302 static enum usb_device_speed dwc3_qcom_read_usb2_speed(struct dwc3_qcom *qcom)
304 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
305 struct usb_hcd *hcd = platform_get_drvdata(dwc->xhci);
306 struct usb_device *udev;
309 * It is possible to query the speed of all children of
310 * USB2.0 root hub via usb_hub_for_each_child(). DWC3 code
311 * currently supports only 1 port per controller. So
312 * this is sufficient.
314 udev = usb_hub_find_child(hcd->self.root_hub, 1);
317 return USB_SPEED_UNKNOWN;
322 static void dwc3_qcom_enable_wakeup_irq(int irq, unsigned int polarity)
328 irq_set_irq_type(irq, polarity);
331 enable_irq_wake(irq);
334 static void dwc3_qcom_disable_wakeup_irq(int irq)
339 disable_irq_wake(irq);
340 disable_irq_nosync(irq);
343 static void dwc3_qcom_disable_interrupts(struct dwc3_qcom *qcom)
345 dwc3_qcom_disable_wakeup_irq(qcom->hs_phy_irq);
347 if (qcom->usb2_speed == USB_SPEED_LOW) {
348 dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq);
349 } else if ((qcom->usb2_speed == USB_SPEED_HIGH) ||
350 (qcom->usb2_speed == USB_SPEED_FULL)) {
351 dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq);
353 dwc3_qcom_disable_wakeup_irq(qcom->dp_hs_phy_irq);
354 dwc3_qcom_disable_wakeup_irq(qcom->dm_hs_phy_irq);
357 dwc3_qcom_disable_wakeup_irq(qcom->ss_phy_irq);
360 static void dwc3_qcom_enable_interrupts(struct dwc3_qcom *qcom)
362 dwc3_qcom_enable_wakeup_irq(qcom->hs_phy_irq, 0);
365 * Configure DP/DM line interrupts based on the USB2 device attached to
366 * the root hub port. When HS/FS device is connected, configure the DP line
367 * as falling edge to detect both disconnect and remote wakeup scenarios. When
368 * LS device is connected, configure DM line as falling edge to detect both
369 * disconnect and remote wakeup. When no device is connected, configure both
370 * DP and DM lines as rising edge to detect HS/HS/LS device connect scenario.
373 if (qcom->usb2_speed == USB_SPEED_LOW) {
374 dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq,
375 IRQ_TYPE_EDGE_FALLING);
376 } else if ((qcom->usb2_speed == USB_SPEED_HIGH) ||
377 (qcom->usb2_speed == USB_SPEED_FULL)) {
378 dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq,
379 IRQ_TYPE_EDGE_FALLING);
381 dwc3_qcom_enable_wakeup_irq(qcom->dp_hs_phy_irq,
382 IRQ_TYPE_EDGE_RISING);
383 dwc3_qcom_enable_wakeup_irq(qcom->dm_hs_phy_irq,
384 IRQ_TYPE_EDGE_RISING);
387 dwc3_qcom_enable_wakeup_irq(qcom->ss_phy_irq, 0);
390 static int dwc3_qcom_suspend(struct dwc3_qcom *qcom)
395 if (qcom->is_suspended)
398 val = readl(qcom->qscratch_base + PWR_EVNT_IRQ_STAT_REG);
399 if (!(val & PWR_EVNT_LPM_IN_L2_MASK))
400 dev_err(qcom->dev, "HS-PHY not in L2\n");
402 for (i = qcom->num_clocks - 1; i >= 0; i--)
403 clk_disable_unprepare(qcom->clks[i]);
405 ret = dwc3_qcom_interconnect_disable(qcom);
407 dev_warn(qcom->dev, "failed to disable interconnect: %d\n", ret);
409 if (device_may_wakeup(qcom->dev)) {
410 qcom->usb2_speed = dwc3_qcom_read_usb2_speed(qcom);
411 dwc3_qcom_enable_interrupts(qcom);
414 qcom->is_suspended = true;
419 static int dwc3_qcom_resume(struct dwc3_qcom *qcom)
424 if (!qcom->is_suspended)
427 if (device_may_wakeup(qcom->dev))
428 dwc3_qcom_disable_interrupts(qcom);
430 for (i = 0; i < qcom->num_clocks; i++) {
431 ret = clk_prepare_enable(qcom->clks[i]);
434 clk_disable_unprepare(qcom->clks[i]);
439 ret = dwc3_qcom_interconnect_enable(qcom);
441 dev_warn(qcom->dev, "failed to enable interconnect: %d\n", ret);
443 /* Clear existing events from PHY related to L2 in/out */
444 dwc3_qcom_setbits(qcom->qscratch_base, PWR_EVNT_IRQ_STAT_REG,
445 PWR_EVNT_LPM_IN_L2_MASK | PWR_EVNT_LPM_OUT_L2_MASK);
447 qcom->is_suspended = false;
452 static irqreturn_t qcom_dwc3_resume_irq(int irq, void *data)
454 struct dwc3_qcom *qcom = data;
455 struct dwc3 *dwc = platform_get_drvdata(qcom->dwc3);
457 /* If pm_suspended then let pm_resume take care of resuming h/w */
458 if (qcom->pm_suspended)
462 pm_runtime_resume(&dwc->xhci->dev);
467 static void dwc3_qcom_select_utmi_clk(struct dwc3_qcom *qcom)
469 /* Configure dwc3 to use UTMI clock as PIPE clock not present */
470 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
473 usleep_range(100, 1000);
475 dwc3_qcom_setbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
476 PIPE_UTMI_CLK_SEL | PIPE3_PHYSTATUS_SW);
478 usleep_range(100, 1000);
480 dwc3_qcom_clrbits(qcom->qscratch_base, QSCRATCH_GENERAL_CFG,
484 static int dwc3_qcom_get_irq(struct platform_device *pdev,
485 const char *name, int num)
487 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
488 struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb : pdev;
489 struct device_node *np = pdev->dev.of_node;
493 ret = platform_get_irq_byname_optional(pdev_irq, name);
495 ret = platform_get_irq_optional(pdev_irq, num);
500 static int dwc3_qcom_setup_irq(struct platform_device *pdev)
502 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
503 const struct dwc3_acpi_pdata *pdata = qcom->acpi_pdata;
507 irq = dwc3_qcom_get_irq(pdev, "hs_phy_irq",
508 pdata ? pdata->hs_phy_irq_index : -1);
510 /* Keep wakeup interrupts disabled until suspend */
511 irq_set_status_flags(irq, IRQ_NOAUTOEN);
512 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
513 qcom_dwc3_resume_irq,
514 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
515 "qcom_dwc3 HS", qcom);
517 dev_err(qcom->dev, "hs_phy_irq failed: %d\n", ret);
520 qcom->hs_phy_irq = irq;
523 irq = dwc3_qcom_get_irq(pdev, "dp_hs_phy_irq",
524 pdata ? pdata->dp_hs_phy_irq_index : -1);
526 irq_set_status_flags(irq, IRQ_NOAUTOEN);
527 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
528 qcom_dwc3_resume_irq,
529 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
530 "qcom_dwc3 DP_HS", qcom);
532 dev_err(qcom->dev, "dp_hs_phy_irq failed: %d\n", ret);
535 qcom->dp_hs_phy_irq = irq;
538 irq = dwc3_qcom_get_irq(pdev, "dm_hs_phy_irq",
539 pdata ? pdata->dm_hs_phy_irq_index : -1);
541 irq_set_status_flags(irq, IRQ_NOAUTOEN);
542 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
543 qcom_dwc3_resume_irq,
544 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
545 "qcom_dwc3 DM_HS", qcom);
547 dev_err(qcom->dev, "dm_hs_phy_irq failed: %d\n", ret);
550 qcom->dm_hs_phy_irq = irq;
553 irq = dwc3_qcom_get_irq(pdev, "ss_phy_irq",
554 pdata ? pdata->ss_phy_irq_index : -1);
556 irq_set_status_flags(irq, IRQ_NOAUTOEN);
557 ret = devm_request_threaded_irq(qcom->dev, irq, NULL,
558 qcom_dwc3_resume_irq,
559 IRQF_TRIGGER_HIGH | IRQF_ONESHOT,
560 "qcom_dwc3 SS", qcom);
562 dev_err(qcom->dev, "ss_phy_irq failed: %d\n", ret);
565 qcom->ss_phy_irq = irq;
571 static int dwc3_qcom_clk_init(struct dwc3_qcom *qcom, int count)
573 struct device *dev = qcom->dev;
574 struct device_node *np = dev->of_node;
583 qcom->num_clocks = count;
585 qcom->clks = devm_kcalloc(dev, qcom->num_clocks,
586 sizeof(struct clk *), GFP_KERNEL);
590 for (i = 0; i < qcom->num_clocks; i++) {
594 clk = of_clk_get(np, i);
597 clk_put(qcom->clks[i]);
601 ret = clk_prepare_enable(clk);
604 clk_disable_unprepare(qcom->clks[i]);
605 clk_put(qcom->clks[i]);
618 static const struct property_entry dwc3_qcom_acpi_properties[] = {
619 PROPERTY_ENTRY_STRING("dr_mode", "host"),
623 static const struct software_node dwc3_qcom_swnode = {
624 .properties = dwc3_qcom_acpi_properties,
627 static int dwc3_qcom_acpi_register_core(struct platform_device *pdev)
629 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
630 struct device *dev = &pdev->dev;
631 struct resource *res, *child_res = NULL;
632 struct platform_device *pdev_irq = qcom->urs_usb ? qcom->urs_usb :
637 qcom->dwc3 = platform_device_alloc("dwc3", PLATFORM_DEVID_AUTO);
641 qcom->dwc3->dev.parent = dev;
642 qcom->dwc3->dev.type = dev->type;
643 qcom->dwc3->dev.dma_mask = dev->dma_mask;
644 qcom->dwc3->dev.dma_parms = dev->dma_parms;
645 qcom->dwc3->dev.coherent_dma_mask = dev->coherent_dma_mask;
647 child_res = kcalloc(2, sizeof(*child_res), GFP_KERNEL);
649 platform_device_put(qcom->dwc3);
653 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
655 dev_err(&pdev->dev, "failed to get memory resource\n");
660 child_res[0].flags = res->flags;
661 child_res[0].start = res->start;
662 child_res[0].end = child_res[0].start +
663 qcom->acpi_pdata->dwc3_core_base_size;
665 irq = platform_get_irq(pdev_irq, 0);
670 child_res[1].flags = IORESOURCE_IRQ;
671 child_res[1].start = child_res[1].end = irq;
673 ret = platform_device_add_resources(qcom->dwc3, child_res, 2);
675 dev_err(&pdev->dev, "failed to add resources\n");
679 ret = device_add_software_node(&qcom->dwc3->dev, &dwc3_qcom_swnode);
681 dev_err(&pdev->dev, "failed to add properties\n");
685 ret = platform_device_add(qcom->dwc3);
687 dev_err(&pdev->dev, "failed to add device\n");
688 device_remove_software_node(&qcom->dwc3->dev);
695 platform_device_put(qcom->dwc3);
700 static int dwc3_qcom_of_register_core(struct platform_device *pdev)
702 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
703 struct device_node *np = pdev->dev.of_node, *dwc3_np;
704 struct device *dev = &pdev->dev;
707 dwc3_np = of_get_compatible_child(np, "snps,dwc3");
709 dev_err(dev, "failed to find dwc3 core child\n");
713 ret = of_platform_populate(np, NULL, NULL, dev);
715 dev_err(dev, "failed to register dwc3 core - %d\n", ret);
719 qcom->dwc3 = of_find_device_by_node(dwc3_np);
722 dev_err(dev, "failed to get dwc3 platform device\n");
726 of_node_put(dwc3_np);
731 static struct platform_device *
732 dwc3_qcom_create_urs_usb_platdev(struct device *dev)
734 struct fwnode_handle *fwh;
735 struct acpi_device *adev;
740 /* Figure out device id */
741 ret = sscanf(fwnode_get_name(dev->fwnode), "URS%d", &id);
745 /* Find the child using name */
746 snprintf(name, sizeof(name), "USB%d", id);
747 fwh = fwnode_get_named_child_node(dev->fwnode, name);
751 adev = to_acpi_device_node(fwh);
755 return acpi_create_platform_device(adev, NULL);
758 static int dwc3_qcom_probe(struct platform_device *pdev)
760 struct device_node *np = pdev->dev.of_node;
761 struct device *dev = &pdev->dev;
762 struct dwc3_qcom *qcom;
763 struct resource *res, *parent_res = NULL;
765 bool ignore_pipe_clk;
766 struct generic_pm_domain *genpd;
768 qcom = devm_kzalloc(&pdev->dev, sizeof(*qcom), GFP_KERNEL);
772 platform_set_drvdata(pdev, qcom);
773 qcom->dev = &pdev->dev;
775 genpd = pd_to_genpd(qcom->dev->pm_domain);
777 if (has_acpi_companion(dev)) {
778 qcom->acpi_pdata = acpi_device_get_match_data(dev);
779 if (!qcom->acpi_pdata) {
780 dev_err(&pdev->dev, "no supporting ACPI device data\n");
785 qcom->resets = devm_reset_control_array_get_optional_exclusive(dev);
786 if (IS_ERR(qcom->resets)) {
787 ret = PTR_ERR(qcom->resets);
788 dev_err(&pdev->dev, "failed to get resets, err=%d\n", ret);
792 ret = reset_control_assert(qcom->resets);
794 dev_err(&pdev->dev, "failed to assert resets, err=%d\n", ret);
798 usleep_range(10, 1000);
800 ret = reset_control_deassert(qcom->resets);
802 dev_err(&pdev->dev, "failed to deassert resets, err=%d\n", ret);
806 ret = dwc3_qcom_clk_init(qcom, of_clk_get_parent_count(np));
808 dev_err(dev, "failed to get clocks\n");
812 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
817 parent_res = kmemdup(res, sizeof(struct resource), GFP_KERNEL);
821 parent_res->start = res->start +
822 qcom->acpi_pdata->qscratch_base_offset;
823 parent_res->end = parent_res->start +
824 qcom->acpi_pdata->qscratch_base_size;
826 if (qcom->acpi_pdata->is_urs) {
827 qcom->urs_usb = dwc3_qcom_create_urs_usb_platdev(dev);
828 if (IS_ERR_OR_NULL(qcom->urs_usb)) {
829 dev_err(dev, "failed to create URS USB platdev\n");
833 return PTR_ERR(qcom->urs_usb);
838 qcom->qscratch_base = devm_ioremap_resource(dev, parent_res);
839 if (IS_ERR(qcom->qscratch_base)) {
840 ret = PTR_ERR(qcom->qscratch_base);
844 ret = dwc3_qcom_setup_irq(pdev);
846 dev_err(dev, "failed to setup IRQs, err=%d\n", ret);
851 * Disable pipe_clk requirement if specified. Used when dwc3
852 * operates without SSPHY and only HS/FS/LS modes are supported.
854 ignore_pipe_clk = device_property_read_bool(dev,
855 "qcom,select-utmi-as-pipe-clk");
857 dwc3_qcom_select_utmi_clk(qcom);
860 ret = dwc3_qcom_of_register_core(pdev);
862 ret = dwc3_qcom_acpi_register_core(pdev);
865 dev_err(dev, "failed to register DWC3 Core, err=%d\n", ret);
869 ret = dwc3_qcom_interconnect_init(qcom);
873 qcom->mode = usb_get_dr_mode(&qcom->dwc3->dev);
875 /* enable vbus override for device mode */
876 if (qcom->mode == USB_DR_MODE_PERIPHERAL)
877 dwc3_qcom_vbus_override_enable(qcom, true);
879 /* register extcon to override sw_vbus on Vbus change later */
880 ret = dwc3_qcom_register_extcon(qcom);
882 goto interconnect_exit;
884 if (device_can_wakeup(&qcom->dwc3->dev)) {
886 * Setting GENPD_FLAG_ALWAYS_ON flag takes care of keeping
887 * genpd on in both runtime suspend and system suspend cases.
889 genpd->flags |= GENPD_FLAG_ALWAYS_ON;
890 device_init_wakeup(&pdev->dev, true);
892 genpd->flags |= GENPD_FLAG_RPM_ALWAYS_ON;
895 qcom->is_suspended = false;
896 pm_runtime_set_active(dev);
897 pm_runtime_enable(dev);
898 pm_runtime_forbid(dev);
903 dwc3_qcom_interconnect_exit(qcom);
906 of_platform_depopulate(&pdev->dev);
908 platform_device_put(pdev);
910 for (i = qcom->num_clocks - 1; i >= 0; i--) {
911 clk_disable_unprepare(qcom->clks[i]);
912 clk_put(qcom->clks[i]);
915 reset_control_assert(qcom->resets);
920 static int dwc3_qcom_remove(struct platform_device *pdev)
922 struct dwc3_qcom *qcom = platform_get_drvdata(pdev);
923 struct device *dev = &pdev->dev;
926 device_remove_software_node(&qcom->dwc3->dev);
927 of_platform_depopulate(dev);
929 for (i = qcom->num_clocks - 1; i >= 0; i--) {
930 clk_disable_unprepare(qcom->clks[i]);
931 clk_put(qcom->clks[i]);
933 qcom->num_clocks = 0;
935 dwc3_qcom_interconnect_exit(qcom);
936 reset_control_assert(qcom->resets);
938 pm_runtime_allow(dev);
939 pm_runtime_disable(dev);
944 static int __maybe_unused dwc3_qcom_pm_suspend(struct device *dev)
946 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
949 ret = dwc3_qcom_suspend(qcom);
951 qcom->pm_suspended = true;
956 static int __maybe_unused dwc3_qcom_pm_resume(struct device *dev)
958 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
961 ret = dwc3_qcom_resume(qcom);
963 qcom->pm_suspended = false;
968 static int __maybe_unused dwc3_qcom_runtime_suspend(struct device *dev)
970 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
972 return dwc3_qcom_suspend(qcom);
975 static int __maybe_unused dwc3_qcom_runtime_resume(struct device *dev)
977 struct dwc3_qcom *qcom = dev_get_drvdata(dev);
979 return dwc3_qcom_resume(qcom);
982 static const struct dev_pm_ops dwc3_qcom_dev_pm_ops = {
983 SET_SYSTEM_SLEEP_PM_OPS(dwc3_qcom_pm_suspend, dwc3_qcom_pm_resume)
984 SET_RUNTIME_PM_OPS(dwc3_qcom_runtime_suspend, dwc3_qcom_runtime_resume,
988 static const struct of_device_id dwc3_qcom_of_match[] = {
989 { .compatible = "qcom,dwc3" },
990 { .compatible = "qcom,msm8996-dwc3" },
991 { .compatible = "qcom,msm8998-dwc3" },
992 { .compatible = "qcom,sdm660-dwc3" },
993 { .compatible = "qcom,sdm845-dwc3" },
996 MODULE_DEVICE_TABLE(of, dwc3_qcom_of_match);
999 static const struct dwc3_acpi_pdata sdm845_acpi_pdata = {
1000 .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
1001 .qscratch_base_size = SDM845_QSCRATCH_SIZE,
1002 .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
1003 .hs_phy_irq_index = 1,
1004 .dp_hs_phy_irq_index = 4,
1005 .dm_hs_phy_irq_index = 3,
1006 .ss_phy_irq_index = 2
1009 static const struct dwc3_acpi_pdata sdm845_acpi_urs_pdata = {
1010 .qscratch_base_offset = SDM845_QSCRATCH_BASE_OFFSET,
1011 .qscratch_base_size = SDM845_QSCRATCH_SIZE,
1012 .dwc3_core_base_size = SDM845_DWC3_CORE_SIZE,
1013 .hs_phy_irq_index = 1,
1014 .dp_hs_phy_irq_index = 4,
1015 .dm_hs_phy_irq_index = 3,
1016 .ss_phy_irq_index = 2,
1020 static const struct acpi_device_id dwc3_qcom_acpi_match[] = {
1021 { "QCOM2430", (unsigned long)&sdm845_acpi_pdata },
1022 { "QCOM0304", (unsigned long)&sdm845_acpi_urs_pdata },
1023 { "QCOM0497", (unsigned long)&sdm845_acpi_urs_pdata },
1024 { "QCOM04A6", (unsigned long)&sdm845_acpi_pdata },
1027 MODULE_DEVICE_TABLE(acpi, dwc3_qcom_acpi_match);
1030 static struct platform_driver dwc3_qcom_driver = {
1031 .probe = dwc3_qcom_probe,
1032 .remove = dwc3_qcom_remove,
1034 .name = "dwc3-qcom",
1035 .pm = &dwc3_qcom_dev_pm_ops,
1036 .of_match_table = dwc3_qcom_of_match,
1037 .acpi_match_table = ACPI_PTR(dwc3_qcom_acpi_match),
1041 module_platform_driver(dwc3_qcom_driver);
1043 MODULE_LICENSE("GPL v2");
1044 MODULE_DESCRIPTION("DesignWare DWC3 QCOM Glue Driver");