drivers/usb/dwc3/core.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * core.c - DesignWare USB3 DRD Controller Core file
   4  *
   5  * Copyright (C) 2010-2011 Texas Instruments Incorporated - https://www.ti.com
   6  *
   7  * Authors: Felipe Balbi <[email protected]>,
   8  *          Sebastian Andrzej Siewior <[email protected]>
   9  */
  10
  11 #include <linux/clk.h>
  12 #include <linux/version.h>
  13 #include <linux/module.h>
  14 #include <linux/kernel.h>
  15 #include <linux/slab.h>
  16 #include <linux/spinlock.h>
  17 #include <linux/platform_device.h>
  18 #include <linux/pm_runtime.h>
  19 #include <linux/interrupt.h>
  20 #include <linux/ioport.h>
  21 #include <linux/io.h>
  22 #include <linux/list.h>
  23 #include <linux/delay.h>
  24 #include <linux/dma-mapping.h>
  25 #include <linux/of.h>
  26 #include <linux/of_graph.h>
  27 #include <linux/acpi.h>
  28 #include <linux/pinctrl/consumer.h>
  29 #include <linux/reset.h>
  30 #include <linux/bitfield.h>
  31
  32 #include <linux/usb/ch9.h>
  33 #include <linux/usb/gadget.h>
  34 #include <linux/usb/of.h>
  35 #include <linux/usb/otg.h>
  36
  37 #include "core.h"
  38 #include "gadget.h"
  39 #include "io.h"
  40
  41 #include "debug.h"
  42
  43 #define DWC3_DEFAULT_AUTOSUSPEND_DELAY  5000 /* ms */
  44
  45 /**
  46  * dwc3_get_dr_mode - Validates and sets dr_mode
  47  * @dwc: pointer to our context structure
  48  */
  49 static int dwc3_get_dr_mode(struct dwc3 *dwc)
  50 {
  51         enum usb_dr_mode mode;
  52         struct device *dev = dwc->dev;
  53         unsigned int hw_mode;
  54
  55         if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
  56                 dwc->dr_mode = USB_DR_MODE_OTG;
  57
  58         mode = dwc->dr_mode;
  59         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
  60
  61         switch (hw_mode) {
  62         case DWC3_GHWPARAMS0_MODE_GADGET:
  63                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST)) {
  64                         dev_err(dev,
  65                                 "Controller does not support host mode.\n");
  66                         return -EINVAL;
  67                 }
  68                 mode = USB_DR_MODE_PERIPHERAL;
  69                 break;
  70         case DWC3_GHWPARAMS0_MODE_HOST:
  71                 if (IS_ENABLED(CONFIG_USB_DWC3_GADGET)) {
  72                         dev_err(dev,
  73                                 "Controller does not support device mode.\n");
  74                         return -EINVAL;
  75                 }
  76                 mode = USB_DR_MODE_HOST;
  77                 break;
  78         default:
  79                 if (IS_ENABLED(CONFIG_USB_DWC3_HOST))
  80                         mode = USB_DR_MODE_HOST;
  81                 else if (IS_ENABLED(CONFIG_USB_DWC3_GADGET))
  82                         mode = USB_DR_MODE_PERIPHERAL;
  83
  84                 /*
  85                  * DWC_usb31 and DWC_usb3 v3.30a and higher do not support OTG
  86                  * mode. If the controller supports DRD but the dr_mode is not
  87                  * specified or set to OTG, then set the mode to peripheral.
  88                  */
  89                 if (mode == USB_DR_MODE_OTG && !dwc->edev &&
  90                     (!IS_ENABLED(CONFIG_USB_ROLE_SWITCH) ||
  91                      !device_property_read_bool(dwc->dev, "usb-role-switch")) &&
  92                     !DWC3_VER_IS_PRIOR(DWC3, 330A))
  93                         mode = USB_DR_MODE_PERIPHERAL;
  94         }
  95
  96         if (mode != dwc->dr_mode) {
  97                 dev_warn(dev,
  98                          "Configuration mismatch. dr_mode forced to %s\n",
  99                          mode == USB_DR_MODE_HOST ? "host" : "gadget");
 100
 101                 dwc->dr_mode = mode;
 102         }
 103
 104         return 0;
 105 }
 106
 107 void dwc3_set_prtcap(struct dwc3 *dwc, u32 mode)
 108 {
 109         u32 reg;
 110
 111         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 112         reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
 113         reg |= DWC3_GCTL_PRTCAPDIR(mode);
 114         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 115
 116         dwc->current_dr_role = mode;
 117 }
 118
 119 static void __dwc3_set_mode(struct work_struct *work)
 120 {
 121         struct dwc3 *dwc = work_to_dwc(work);
 122         unsigned long flags;
 123         int ret;
 124         u32 reg;
 125
 126         mutex_lock(&dwc->mutex);
 127
 128         pm_runtime_get_sync(dwc->dev);
 129
 130         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_OTG)
 131                 dwc3_otg_update(dwc, 0);
 132
 133         if (!dwc->desired_dr_role)
 134                 goto out;
 135
 136         if (dwc->desired_dr_role == dwc->current_dr_role)
 137                 goto out;
 138
 139         if (dwc->desired_dr_role == DWC3_GCTL_PRTCAP_OTG && dwc->edev)
 140                 goto out;
 141
 142         switch (dwc->current_dr_role) {
 143         case DWC3_GCTL_PRTCAP_HOST:
 144                 dwc3_host_exit(dwc);
 145                 break;
 146         case DWC3_GCTL_PRTCAP_DEVICE:
 147                 dwc3_gadget_exit(dwc);
 148                 dwc3_event_buffers_cleanup(dwc);
 149                 break;
 150         case DWC3_GCTL_PRTCAP_OTG:
 151                 dwc3_otg_exit(dwc);
 152                 spin_lock_irqsave(&dwc->lock, flags);
 153                 dwc->desired_otg_role = DWC3_OTG_ROLE_IDLE;
 154                 spin_unlock_irqrestore(&dwc->lock, flags);
 155                 dwc3_otg_update(dwc, 1);
 156                 break;
 157         default:
 158                 break;
 159         }
 160
 161         /*
 162          * When current_dr_role is not set, there's no role switching.
 163          * Only perform GCTL.CoreSoftReset when there's DRD role switching.
 164          */
 165         if (dwc->current_dr_role && ((DWC3_IP_IS(DWC3) ||
 166                         DWC3_VER_IS_PRIOR(DWC31, 190A)) &&
 167                         dwc->desired_dr_role != DWC3_GCTL_PRTCAP_OTG)) {
 168                 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 169                 reg |= DWC3_GCTL_CORESOFTRESET;
 170                 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 171
 172                 /*
 173                  * Wait for internal clocks to synchronized. DWC_usb31 and
 174                  * DWC_usb32 may need at least 50ms (less for DWC_usb3). To
 175                  * keep it consistent across different IPs, let's wait up to
 176                  * 100ms before clearing GCTL.CORESOFTRESET.
 177                  */
 178                 msleep(100);
 179
 180                 reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 181                 reg &= ~DWC3_GCTL_CORESOFTRESET;
 182                 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 183         }
 184
 185         spin_lock_irqsave(&dwc->lock, flags);
 186
 187         dwc3_set_prtcap(dwc, dwc->desired_dr_role);
 188
 189         spin_unlock_irqrestore(&dwc->lock, flags);
 190
 191         switch (dwc->desired_dr_role) {
 192         case DWC3_GCTL_PRTCAP_HOST:
 193                 ret = dwc3_host_init(dwc);
 194                 if (ret) {
 195                         dev_err(dwc->dev, "failed to initialize host\n");
 196                 } else {
 197                         if (dwc->usb2_phy)
 198                                 otg_set_vbus(dwc->usb2_phy->otg, true);
 199                         phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
 200                         phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
 201                         if (dwc->dis_split_quirk) {
 202                                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
 203                                 reg |= DWC3_GUCTL3_SPLITDISABLE;
 204                                 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
 205                         }
 206                 }
 207                 break;
 208         case DWC3_GCTL_PRTCAP_DEVICE:
 209                 dwc3_core_soft_reset(dwc);
 210
 211                 dwc3_event_buffers_setup(dwc);
 212
 213                 if (dwc->usb2_phy)
 214                         otg_set_vbus(dwc->usb2_phy->otg, false);
 215                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
 216                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
 217
 218                 ret = dwc3_gadget_init(dwc);
 219                 if (ret)
 220                         dev_err(dwc->dev, "failed to initialize peripheral\n");
 221                 break;
 222         case DWC3_GCTL_PRTCAP_OTG:
 223                 dwc3_otg_init(dwc);
 224                 dwc3_otg_update(dwc, 0);
 225                 break;
 226         default:
 227                 break;
 228         }
 229
 230 out:
 231         pm_runtime_mark_last_busy(dwc->dev);
 232         pm_runtime_put_autosuspend(dwc->dev);
 233         mutex_unlock(&dwc->mutex);
 234 }
 235
 236 void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
 237 {
 238         unsigned long flags;
 239
 240         if (dwc->dr_mode != USB_DR_MODE_OTG)
 241                 return;
 242
 243         spin_lock_irqsave(&dwc->lock, flags);
 244         dwc->desired_dr_role = mode;
 245         spin_unlock_irqrestore(&dwc->lock, flags);
 246
 247         queue_work(system_freezable_wq, &dwc->drd_work);
 248 }
 249
 250 u32 dwc3_core_fifo_space(struct dwc3_ep *dep, u8 type)
 251 {
 252         struct dwc3             *dwc = dep->dwc;
 253         u32                     reg;
 254
 255         dwc3_writel(dwc->regs, DWC3_GDBGFIFOSPACE,
 256                         DWC3_GDBGFIFOSPACE_NUM(dep->number) |
 257                         DWC3_GDBGFIFOSPACE_TYPE(type));
 258
 259         reg = dwc3_readl(dwc->regs, DWC3_GDBGFIFOSPACE);
 260
 261         return DWC3_GDBGFIFOSPACE_SPACE_AVAILABLE(reg);
 262 }
 263
 264 /**
 265  * dwc3_core_soft_reset - Issues core soft reset and PHY reset
 266  * @dwc: pointer to our context structure
 267  */
 268 int dwc3_core_soft_reset(struct dwc3 *dwc)
 269 {
 270         u32             reg;
 271         int             retries = 1000;
 272
 273         /*
 274          * We're resetting only the device side because, if we're in host mode,
 275          * XHCI driver will reset the host block. If dwc3 was configured for
 276          * host-only mode, then we can return early.
 277          */
 278         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST)
 279                 return 0;
 280
 281         reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 282         reg |= DWC3_DCTL_CSFTRST;
 283         reg &= ~DWC3_DCTL_RUN_STOP;
 284         dwc3_gadget_dctl_write_safe(dwc, reg);
 285
 286         /*
 287          * For DWC_usb31 controller 1.90a and later, the DCTL.CSFRST bit
 288          * is cleared only after all the clocks are synchronized. This can
 289          * take a little more than 50ms. Set the polling rate at 20ms
 290          * for 10 times instead.
 291          */
 292         if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
 293                 retries = 10;
 294
 295         do {
 296                 reg = dwc3_readl(dwc->regs, DWC3_DCTL);
 297                 if (!(reg & DWC3_DCTL_CSFTRST))
 298                         goto done;
 299
 300                 if (DWC3_VER_IS_WITHIN(DWC31, 190A, ANY) || DWC3_IP_IS(DWC32))
 301                         msleep(20);
 302                 else
 303                         udelay(1);
 304         } while (--retries);
 305
 306         dev_warn(dwc->dev, "DWC3 controller soft reset failed.\n");
 307         return -ETIMEDOUT;
 308
 309 done:
 310         /*
 311          * For DWC_usb31 controller 1.80a and prior, once DCTL.CSFRST bit
 312          * is cleared, we must wait at least 50ms before accessing the PHY
 313          * domain (synchronization delay).
 314          */
 315         if (DWC3_VER_IS_WITHIN(DWC31, ANY, 180A))
 316                 msleep(50);
 317
 318         return 0;
 319 }
 320
 321 /*
 322  * dwc3_frame_length_adjustment - Adjusts frame length if required
 323  * @dwc3: Pointer to our controller context structure
 324  */
 325 static void dwc3_frame_length_adjustment(struct dwc3 *dwc)
 326 {
 327         u32 reg;
 328         u32 dft;
 329
 330         if (DWC3_VER_IS_PRIOR(DWC3, 250A))
 331                 return;
 332
 333         if (dwc->fladj == 0)
 334                 return;
 335
 336         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 337         dft = reg & DWC3_GFLADJ_30MHZ_MASK;
 338         if (dft != dwc->fladj) {
 339                 reg &= ~DWC3_GFLADJ_30MHZ_MASK;
 340                 reg |= DWC3_GFLADJ_30MHZ_SDBND_SEL | dwc->fladj;
 341                 dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 342         }
 343 }
 344
 345 /**
 346  * dwc3_ref_clk_period - Reference clock period configuration
 347  *              Default reference clock period depends on hardware
 348  *              configuration. For systems with reference clock that differs
 349  *              from the default, this will set clock period in DWC3_GUCTL
 350  *              register.
 351  * @dwc: Pointer to our controller context structure
 352  */
 353 static void dwc3_ref_clk_period(struct dwc3 *dwc)
 354 {
 355         unsigned long period;
 356         unsigned long fladj;
 357         unsigned long decr;
 358         unsigned long rate;
 359         u32 reg;
 360
 361         if (dwc->ref_clk) {
 362                 rate = clk_get_rate(dwc->ref_clk);
 363                 if (!rate)
 364                         return;
 365                 period = NSEC_PER_SEC / rate;
 366         } else if (dwc->ref_clk_per) {
 367                 period = dwc->ref_clk_per;
 368                 rate = NSEC_PER_SEC / period;
 369         } else {
 370                 return;
 371         }
 372
 373         reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
 374         reg &= ~DWC3_GUCTL_REFCLKPER_MASK;
 375         reg |=  FIELD_PREP(DWC3_GUCTL_REFCLKPER_MASK, period);
 376         dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
 377
 378         if (DWC3_VER_IS_PRIOR(DWC3, 250A))
 379                 return;
 380
 381         /*
 382          * The calculation below is
 383          *
 384          * 125000 * (NSEC_PER_SEC / (rate * period) - 1)
 385          *
 386          * but rearranged for fixed-point arithmetic. The division must be
 387          * 64-bit because 125000 * NSEC_PER_SEC doesn't fit in 32 bits (and
 388          * neither does rate * period).
 389          *
 390          * Note that rate * period ~= NSEC_PER_SECOND, minus the number of
 391          * nanoseconds of error caused by the truncation which happened during
 392          * the division when calculating rate or period (whichever one was
 393          * derived from the other). We first calculate the relative error, then
 394          * scale it to units of 8 ppm.
 395          */
 396         fladj = div64_u64(125000ULL * NSEC_PER_SEC, (u64)rate * period);
 397         fladj -= 125000;
 398
 399         /*
 400          * The documented 240MHz constant is scaled by 2 to get PLS1 as well.
 401          */
 402         decr = 480000000 / rate;
 403
 404         reg = dwc3_readl(dwc->regs, DWC3_GFLADJ);
 405         reg &= ~DWC3_GFLADJ_REFCLK_FLADJ_MASK
 406             &  ~DWC3_GFLADJ_240MHZDECR
 407             &  ~DWC3_GFLADJ_240MHZDECR_PLS1;
 408         reg |= FIELD_PREP(DWC3_GFLADJ_REFCLK_FLADJ_MASK, fladj)
 409             |  FIELD_PREP(DWC3_GFLADJ_240MHZDECR, decr >> 1)
 410             |  FIELD_PREP(DWC3_GFLADJ_240MHZDECR_PLS1, decr & 1);
 411         dwc3_writel(dwc->regs, DWC3_GFLADJ, reg);
 412 }
 413
 414 /**
 415  * dwc3_free_one_event_buffer - Frees one event buffer
 416  * @dwc: Pointer to our controller context structure
 417  * @evt: Pointer to event buffer to be freed
 418  */
 419 static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
 420                 struct dwc3_event_buffer *evt)
 421 {
 422         dma_free_coherent(dwc->sysdev, evt->length, evt->buf, evt->dma);
 423 }
 424
 425 /**
 426  * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
 427  * @dwc: Pointer to our controller context structure
 428  * @length: size of the event buffer
 429  *
 430  * Returns a pointer to the allocated event buffer structure on success
 431  * otherwise ERR_PTR(errno).
 432  */
 433 static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
 434                 unsigned int length)
 435 {
 436         struct dwc3_event_buffer        *evt;
 437
 438         evt = devm_kzalloc(dwc->dev, sizeof(*evt), GFP_KERNEL);
 439         if (!evt)
 440                 return ERR_PTR(-ENOMEM);
 441
 442         evt->dwc        = dwc;
 443         evt->length     = length;
 444         evt->cache      = devm_kzalloc(dwc->dev, length, GFP_KERNEL);
 445         if (!evt->cache)
 446                 return ERR_PTR(-ENOMEM);
 447
 448         evt->buf        = dma_alloc_coherent(dwc->sysdev, length,
 449                         &evt->dma, GFP_KERNEL);
 450         if (!evt->buf)
 451                 return ERR_PTR(-ENOMEM);
 452
 453         return evt;
 454 }
 455
 456 /**
 457  * dwc3_free_event_buffers - frees all allocated event buffers
 458  * @dwc: Pointer to our controller context structure
 459  */
 460 static void dwc3_free_event_buffers(struct dwc3 *dwc)
 461 {
 462         struct dwc3_event_buffer        *evt;
 463
 464         evt = dwc->ev_buf;
 465         if (evt)
 466                 dwc3_free_one_event_buffer(dwc, evt);
 467 }
 468
 469 /**
 470  * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
 471  * @dwc: pointer to our controller context structure
 472  * @length: size of event buffer
 473  *
 474  * Returns 0 on success otherwise negative errno. In the error case, dwc
 475  * may contain some buffers allocated but not all which were requested.
 476  */
 477 static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned int length)
 478 {
 479         struct dwc3_event_buffer *evt;
 480
 481         evt = dwc3_alloc_one_event_buffer(dwc, length);
 482         if (IS_ERR(evt)) {
 483                 dev_err(dwc->dev, "can't allocate event buffer\n");
 484                 return PTR_ERR(evt);
 485         }
 486         dwc->ev_buf = evt;
 487
 488         return 0;
 489 }
 490
 491 /**
 492  * dwc3_event_buffers_setup - setup our allocated event buffers
 493  * @dwc: pointer to our controller context structure
 494  *
 495  * Returns 0 on success otherwise negative errno.
 496  */
 497 int dwc3_event_buffers_setup(struct dwc3 *dwc)
 498 {
 499         struct dwc3_event_buffer        *evt;
 500
 501         evt = dwc->ev_buf;
 502         evt->lpos = 0;
 503         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0),
 504                         lower_32_bits(evt->dma));
 505         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0),
 506                         upper_32_bits(evt->dma));
 507         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0),
 508                         DWC3_GEVNTSIZ_SIZE(evt->length));
 509         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 510
 511         return 0;
 512 }
 513
 514 void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
 515 {
 516         struct dwc3_event_buffer        *evt;
 517
 518         evt = dwc->ev_buf;
 519
 520         evt->lpos = 0;
 521
 522         dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(0), 0);
 523         dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(0), 0);
 524         dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(0), DWC3_GEVNTSIZ_INTMASK
 525                         | DWC3_GEVNTSIZ_SIZE(0));
 526         dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(0), 0);
 527 }
 528
 529 static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
 530 {
 531         if (!dwc->has_hibernation)
 532                 return 0;
 533
 534         if (!dwc->nr_scratch)
 535                 return 0;
 536
 537         dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
 538                         DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
 539         if (!dwc->scratchbuf)
 540                 return -ENOMEM;
 541
 542         return 0;
 543 }
 544
 545 static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
 546 {
 547         dma_addr_t scratch_addr;
 548         u32 param;
 549         int ret;
 550
 551         if (!dwc->has_hibernation)
 552                 return 0;
 553
 554         if (!dwc->nr_scratch)
 555                 return 0;
 556
 557          /* should never fall here */
 558         if (!WARN_ON(dwc->scratchbuf))
 559                 return 0;
 560
 561         scratch_addr = dma_map_single(dwc->sysdev, dwc->scratchbuf,
 562                         dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
 563                         DMA_BIDIRECTIONAL);
 564         if (dma_mapping_error(dwc->sysdev, scratch_addr)) {
 565                 dev_err(dwc->sysdev, "failed to map scratch buffer\n");
 566                 ret = -EFAULT;
 567                 goto err0;
 568         }
 569
 570         dwc->scratch_addr = scratch_addr;
 571
 572         param = lower_32_bits(scratch_addr);
 573
 574         ret = dwc3_send_gadget_generic_command(dwc,
 575                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
 576         if (ret < 0)
 577                 goto err1;
 578
 579         param = upper_32_bits(scratch_addr);
 580
 581         ret = dwc3_send_gadget_generic_command(dwc,
 582                         DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
 583         if (ret < 0)
 584                 goto err1;
 585
 586         return 0;
 587
 588 err1:
 589         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 590                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 591
 592 err0:
 593         return ret;
 594 }
 595
 596 static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
 597 {
 598         if (!dwc->has_hibernation)
 599                 return;
 600
 601         if (!dwc->nr_scratch)
 602                 return;
 603
 604          /* should never fall here */
 605         if (!WARN_ON(dwc->scratchbuf))
 606                 return;
 607
 608         dma_unmap_single(dwc->sysdev, dwc->scratch_addr, dwc->nr_scratch *
 609                         DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
 610         kfree(dwc->scratchbuf);
 611 }
 612
 613 static void dwc3_core_num_eps(struct dwc3 *dwc)
 614 {
 615         struct dwc3_hwparams    *parms = &dwc->hwparams;
 616
 617         dwc->num_eps = DWC3_NUM_EPS(parms);
 618 }
 619
 620 static void dwc3_cache_hwparams(struct dwc3 *dwc)
 621 {
 622         struct dwc3_hwparams    *parms = &dwc->hwparams;
 623
 624         parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
 625         parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
 626         parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
 627         parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
 628         parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
 629         parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
 630         parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
 631         parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
 632         parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
 633
 634         if (DWC3_IP_IS(DWC32))
 635                 parms->hwparams9 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS9);
 636 }
 637
 638 static int dwc3_core_ulpi_init(struct dwc3 *dwc)
 639 {
 640         int intf;
 641         int ret = 0;
 642
 643         intf = DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3);
 644
 645         if (intf == DWC3_GHWPARAMS3_HSPHY_IFC_ULPI ||
 646             (intf == DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI &&
 647              dwc->hsphy_interface &&
 648              !strncmp(dwc->hsphy_interface, "ulpi", 4)))
 649                 ret = dwc3_ulpi_init(dwc);
 650
 651         return ret;
 652 }
 653
 654 /**
 655  * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
 656  * @dwc: Pointer to our controller context structure
 657  *
 658  * Returns 0 on success. The USB PHY interfaces are configured but not
 659  * initialized. The PHY interfaces and the PHYs get initialized together with
 660  * the core in dwc3_core_init.
 661  */
 662 static int dwc3_phy_setup(struct dwc3 *dwc)
 663 {
 664         unsigned int hw_mode;
 665         u32 reg;
 666
 667         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
 668
 669         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
 670
 671         /*
 672          * Make sure UX_EXIT_PX is cleared as that causes issues with some
 673          * PHYs. Also, this bit is not supposed to be used in normal operation.
 674          */
 675         reg &= ~DWC3_GUSB3PIPECTL_UX_EXIT_PX;
 676
 677         /*
 678          * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
 679          * to '0' during coreConsultant configuration. So default value
 680          * will be '0' when the core is reset. Application needs to set it
 681          * to '1' after the core initialization is completed.
 682          */
 683         if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
 684                 reg |= DWC3_GUSB3PIPECTL_SUSPHY;
 685
 686         /*
 687          * For DRD controllers, GUSB3PIPECTL.SUSPENDENABLE must be cleared after
 688          * power-on reset, and it can be set after core initialization, which is
 689          * after device soft-reset during initialization.
 690          */
 691         if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
 692                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 693
 694         if (dwc->u2ss_inp3_quirk)
 695                 reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
 696
 697         if (dwc->dis_rxdet_inp3_quirk)
 698                 reg |= DWC3_GUSB3PIPECTL_DISRXDETINP3;
 699
 700         if (dwc->req_p1p2p3_quirk)
 701                 reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
 702
 703         if (dwc->del_p1p2p3_quirk)
 704                 reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
 705
 706         if (dwc->del_phy_power_chg_quirk)
 707                 reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
 708
 709         if (dwc->lfps_filter_quirk)
 710                 reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
 711
 712         if (dwc->rx_detect_poll_quirk)
 713                 reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
 714
 715         if (dwc->tx_de_emphasis_quirk)
 716                 reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
 717
 718         if (dwc->dis_u3_susphy_quirk)
 719                 reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
 720
 721         if (dwc->dis_del_phy_power_chg_quirk)
 722                 reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
 723
 724         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
 725
 726         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
 727
 728         /* Select the HS PHY interface */
 729         switch (DWC3_GHWPARAMS3_HSPHY_IFC(dwc->hwparams.hwparams3)) {
 730         case DWC3_GHWPARAMS3_HSPHY_IFC_UTMI_ULPI:
 731                 if (dwc->hsphy_interface &&
 732                                 !strncmp(dwc->hsphy_interface, "utmi", 4)) {
 733                         reg &= ~DWC3_GUSB2PHYCFG_ULPI_UTMI;
 734                         break;
 735                 } else if (dwc->hsphy_interface &&
 736                                 !strncmp(dwc->hsphy_interface, "ulpi", 4)) {
 737                         reg |= DWC3_GUSB2PHYCFG_ULPI_UTMI;
 738                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 739                 } else {
 740                         /* Relying on default value. */
 741                         if (!(reg & DWC3_GUSB2PHYCFG_ULPI_UTMI))
 742                                 break;
 743                 }
 744                 fallthrough;
 745         case DWC3_GHWPARAMS3_HSPHY_IFC_ULPI:
 746         default:
 747                 break;
 748         }
 749
 750         switch (dwc->hsphy_mode) {
 751         case USBPHY_INTERFACE_MODE_UTMI:
 752                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 753                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 754                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
 755                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
 756                 break;
 757         case USBPHY_INTERFACE_MODE_UTMIW:
 758                 reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
 759                        DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
 760                 reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
 761                        DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
 762                 break;
 763         default:
 764                 break;
 765         }
 766
 767         /*
 768          * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
 769          * '0' during coreConsultant configuration. So default value will
 770          * be '0' when the core is reset. Application needs to set it to
 771          * '1' after the core initialization is completed.
 772          */
 773         if (!DWC3_VER_IS_WITHIN(DWC3, ANY, 194A))
 774                 reg |= DWC3_GUSB2PHYCFG_SUSPHY;
 775
 776         /*
 777          * For DRD controllers, GUSB2PHYCFG.SUSPHY must be cleared after
 778          * power-on reset, and it can be set after core initialization, which is
 779          * after device soft-reset during initialization.
 780          */
 781         if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD)
 782                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 783
 784         if (dwc->dis_u2_susphy_quirk)
 785                 reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
 786
 787         if (dwc->dis_enblslpm_quirk)
 788                 reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
 789         else
 790                 reg |= DWC3_GUSB2PHYCFG_ENBLSLPM;
 791
 792         if (dwc->dis_u2_freeclk_exists_quirk)
 793                 reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
 794
 795         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
 796
 797         return 0;
 798 }
 799
 800 static int dwc3_clk_enable(struct dwc3 *dwc)
 801 {
 802         int ret;
 803
 804         ret = clk_prepare_enable(dwc->bus_clk);
 805         if (ret)
 806                 return ret;
 807
 808         ret = clk_prepare_enable(dwc->ref_clk);
 809         if (ret)
 810                 goto disable_bus_clk;
 811
 812         ret = clk_prepare_enable(dwc->susp_clk);
 813         if (ret)
 814                 goto disable_ref_clk;
 815
 816         return 0;
 817
 818 disable_ref_clk:
 819         clk_disable_unprepare(dwc->ref_clk);
 820 disable_bus_clk:
 821         clk_disable_unprepare(dwc->bus_clk);
 822         return ret;
 823 }
 824
 825 static void dwc3_clk_disable(struct dwc3 *dwc)
 826 {
 827         clk_disable_unprepare(dwc->susp_clk);
 828         clk_disable_unprepare(dwc->ref_clk);
 829         clk_disable_unprepare(dwc->bus_clk);
 830 }
 831
 832 static void dwc3_core_exit(struct dwc3 *dwc)
 833 {
 834         dwc3_event_buffers_cleanup(dwc);
 835
 836         usb_phy_shutdown(dwc->usb2_phy);
 837         usb_phy_shutdown(dwc->usb3_phy);
 838         phy_exit(dwc->usb2_generic_phy);
 839         phy_exit(dwc->usb3_generic_phy);
 840
 841         usb_phy_set_suspend(dwc->usb2_phy, 1);
 842         usb_phy_set_suspend(dwc->usb3_phy, 1);
 843         phy_power_off(dwc->usb2_generic_phy);
 844         phy_power_off(dwc->usb3_generic_phy);
 845         dwc3_clk_disable(dwc);
 846         reset_control_assert(dwc->reset);
 847 }
 848
 849 static bool dwc3_core_is_valid(struct dwc3 *dwc)
 850 {
 851         u32 reg;
 852
 853         reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
 854         dwc->ip = DWC3_GSNPS_ID(reg);
 855
 856         /* This should read as U3 followed by revision number */
 857         if (DWC3_IP_IS(DWC3)) {
 858                 dwc->revision = reg;
 859         } else if (DWC3_IP_IS(DWC31) || DWC3_IP_IS(DWC32)) {
 860                 dwc->revision = dwc3_readl(dwc->regs, DWC3_VER_NUMBER);
 861                 dwc->version_type = dwc3_readl(dwc->regs, DWC3_VER_TYPE);
 862         } else {
 863                 return false;
 864         }
 865
 866         return true;
 867 }
 868
 869 static void dwc3_core_setup_global_control(struct dwc3 *dwc)
 870 {
 871         u32 hwparams4 = dwc->hwparams.hwparams4;
 872         u32 reg;
 873
 874         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
 875         reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
 876
 877         switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
 878         case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
 879                 /**
 880                  * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
 881                  * issue which would cause xHCI compliance tests to fail.
 882                  *
 883                  * Because of that we cannot enable clock gating on such
 884                  * configurations.
 885                  *
 886                  * Refers to:
 887                  *
 888                  * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
 889                  * SOF/ITP Mode Used
 890                  */
 891                 if ((dwc->dr_mode == USB_DR_MODE_HOST ||
 892                                 dwc->dr_mode == USB_DR_MODE_OTG) &&
 893                                 DWC3_VER_IS_WITHIN(DWC3, 210A, 250A))
 894                         reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
 895                 else
 896                         reg &= ~DWC3_GCTL_DSBLCLKGTNG;
 897                 break;
 898         case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
 899                 /* enable hibernation here */
 900                 dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
 901
 902                 /*
 903                  * REVISIT Enabling this bit so that host-mode hibernation
 904                  * will work. Device-mode hibernation is not yet implemented.
 905                  */
 906                 reg |= DWC3_GCTL_GBLHIBERNATIONEN;
 907                 break;
 908         default:
 909                 /* nothing */
 910                 break;
 911         }
 912
 913         /* check if current dwc3 is on simulation board */
 914         if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
 915                 dev_info(dwc->dev, "Running with FPGA optimizations\n");
 916                 dwc->is_fpga = true;
 917         }
 918
 919         WARN_ONCE(dwc->disable_scramble_quirk && !dwc->is_fpga,
 920                         "disable_scramble cannot be used on non-FPGA builds\n");
 921
 922         if (dwc->disable_scramble_quirk && dwc->is_fpga)
 923                 reg |= DWC3_GCTL_DISSCRAMBLE;
 924         else
 925                 reg &= ~DWC3_GCTL_DISSCRAMBLE;
 926
 927         if (dwc->u2exit_lfps_quirk)
 928                 reg |= DWC3_GCTL_U2EXIT_LFPS;
 929
 930         /*
 931          * WORKAROUND: DWC3 revisions <1.90a have a bug
 932          * where the device can fail to connect at SuperSpeed
 933          * and falls back to high-speed mode which causes
 934          * the device to enter a Connect/Disconnect loop
 935          */
 936         if (DWC3_VER_IS_PRIOR(DWC3, 190A))
 937                 reg |= DWC3_GCTL_U2RSTECN;
 938
 939         dwc3_writel(dwc->regs, DWC3_GCTL, reg);
 940 }
 941
 942 static int dwc3_core_get_phy(struct dwc3 *dwc);
 943 static int dwc3_core_ulpi_init(struct dwc3 *dwc);
 944
 945 /* set global incr burst type configuration registers */
 946 static void dwc3_set_incr_burst_type(struct dwc3 *dwc)
 947 {
 948         struct device *dev = dwc->dev;
 949         /* incrx_mode : for INCR burst type. */
 950         bool incrx_mode;
 951         /* incrx_size : for size of INCRX burst. */
 952         u32 incrx_size;
 953         u32 *vals;
 954         u32 cfg;
 955         int ntype;
 956         int ret;
 957         int i;
 958
 959         cfg = dwc3_readl(dwc->regs, DWC3_GSBUSCFG0);
 960
 961         /*
 962          * Handle property "snps,incr-burst-type-adjustment".
 963          * Get the number of value from this property:
 964          * result <= 0, means this property is not supported.
 965          * result = 1, means INCRx burst mode supported.
 966          * result > 1, means undefined length burst mode supported.
 967          */
 968         ntype = device_property_count_u32(dev, "snps,incr-burst-type-adjustment");
 969         if (ntype <= 0)
 970                 return;
 971
 972         vals = kcalloc(ntype, sizeof(u32), GFP_KERNEL);
 973         if (!vals)
 974                 return;
 975
 976         /* Get INCR burst type, and parse it */
 977         ret = device_property_read_u32_array(dev,
 978                         "snps,incr-burst-type-adjustment", vals, ntype);
 979         if (ret) {
 980                 kfree(vals);
 981                 dev_err(dev, "Error to get property\n");
 982                 return;
 983         }
 984
 985         incrx_size = *vals;
 986
 987         if (ntype > 1) {
 988                 /* INCRX (undefined length) burst mode */
 989                 incrx_mode = INCRX_UNDEF_LENGTH_BURST_MODE;
 990                 for (i = 1; i < ntype; i++) {
 991                         if (vals[i] > incrx_size)
 992                                 incrx_size = vals[i];
 993                 }
 994         } else {
 995                 /* INCRX burst mode */
 996                 incrx_mode = INCRX_BURST_MODE;
 997         }
 998
 999         kfree(vals);
1000
1001         /* Enable Undefined Length INCR Burst and Enable INCRx Burst */
1002         cfg &= ~DWC3_GSBUSCFG0_INCRBRST_MASK;
1003         if (incrx_mode)
1004                 cfg |= DWC3_GSBUSCFG0_INCRBRSTENA;
1005         switch (incrx_size) {
1006         case 256:
1007                 cfg |= DWC3_GSBUSCFG0_INCR256BRSTENA;
1008                 break;
1009         case 128:
1010                 cfg |= DWC3_GSBUSCFG0_INCR128BRSTENA;
1011                 break;
1012         case 64:
1013                 cfg |= DWC3_GSBUSCFG0_INCR64BRSTENA;
1014                 break;
1015         case 32:
1016                 cfg |= DWC3_GSBUSCFG0_INCR32BRSTENA;
1017                 break;
1018         case 16:
1019                 cfg |= DWC3_GSBUSCFG0_INCR16BRSTENA;
1020                 break;
1021         case 8:
1022                 cfg |= DWC3_GSBUSCFG0_INCR8BRSTENA;
1023                 break;
1024         case 4:
1025                 cfg |= DWC3_GSBUSCFG0_INCR4BRSTENA;
1026                 break;
1027         case 1:
1028                 break;
1029         default:
1030                 dev_err(dev, "Invalid property\n");
1031                 break;
1032         }
1033
1034         dwc3_writel(dwc->regs, DWC3_GSBUSCFG0, cfg);
1035 }
1036
1037 static void dwc3_set_power_down_clk_scale(struct dwc3 *dwc)
1038 {
1039         u32 scale;
1040         u32 reg;
1041
1042         if (!dwc->susp_clk)
1043                 return;
1044
1045         /*
1046          * The power down scale field specifies how many suspend_clk
1047          * periods fit into a 16KHz clock period. When performing
1048          * the division, round up the remainder.
1049          *
1050          * The power down scale value is calculated using the fastest
1051          * frequency of the suspend_clk. If it isn't fixed (but within
1052          * the accuracy requirement), the driver may not know the max
1053          * rate of the suspend_clk, so only update the power down scale
1054          * if the default is less than the calculated value from
1055          * clk_get_rate() or if the default is questionably high
1056          * (3x or more) to be within the requirement.
1057          */
1058         scale = DIV_ROUND_UP(clk_get_rate(dwc->susp_clk), 16000);
1059         reg = dwc3_readl(dwc->regs, DWC3_GCTL);
1060         if ((reg & DWC3_GCTL_PWRDNSCALE_MASK) < DWC3_GCTL_PWRDNSCALE(scale) ||
1061             (reg & DWC3_GCTL_PWRDNSCALE_MASK) > DWC3_GCTL_PWRDNSCALE(scale*3)) {
1062                 reg &= ~(DWC3_GCTL_PWRDNSCALE_MASK);
1063                 reg |= DWC3_GCTL_PWRDNSCALE(scale);
1064                 dwc3_writel(dwc->regs, DWC3_GCTL, reg);
1065         }
1066 }
1067
1068 /**
1069  * dwc3_core_init - Low-level initialization of DWC3 Core
1070  * @dwc: Pointer to our controller context structure
1071  *
1072  * Returns 0 on success otherwise negative errno.
1073  */
1074 static int dwc3_core_init(struct dwc3 *dwc)
1075 {
1076         unsigned int            hw_mode;
1077         u32                     reg;
1078         int                     ret;
1079
1080         hw_mode = DWC3_GHWPARAMS0_MODE(dwc->hwparams.hwparams0);
1081
1082         /*
1083          * Write Linux Version Code to our GUID register so it's easy to figure
1084          * out which kernel version a bug was found.
1085          */
1086         dwc3_writel(dwc->regs, DWC3_GUID, LINUX_VERSION_CODE);
1087
1088         ret = dwc3_phy_setup(dwc);
1089         if (ret)
1090                 goto err0;
1091
1092         if (!dwc->ulpi_ready) {
1093                 ret = dwc3_core_ulpi_init(dwc);
1094                 if (ret)
1095                         goto err0;
1096                 dwc->ulpi_ready = true;
1097         }
1098
1099         if (!dwc->phys_ready) {
1100                 ret = dwc3_core_get_phy(dwc);
1101                 if (ret)
1102                         goto err0a;
1103                 dwc->phys_ready = true;
1104         }
1105
1106         usb_phy_init(dwc->usb2_phy);
1107         usb_phy_init(dwc->usb3_phy);
1108         ret = phy_init(dwc->usb2_generic_phy);
1109         if (ret < 0)
1110                 goto err0a;
1111
1112         ret = phy_init(dwc->usb3_generic_phy);
1113         if (ret < 0) {
1114                 phy_exit(dwc->usb2_generic_phy);
1115                 goto err0a;
1116         }
1117
1118         ret = dwc3_core_soft_reset(dwc);
1119         if (ret)
1120                 goto err1;
1121
1122         if (hw_mode == DWC3_GHWPARAMS0_MODE_DRD &&
1123             !DWC3_VER_IS_WITHIN(DWC3, ANY, 194A)) {
1124                 if (!dwc->dis_u3_susphy_quirk) {
1125                         reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
1126                         reg |= DWC3_GUSB3PIPECTL_SUSPHY;
1127                         dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
1128                 }
1129
1130                 if (!dwc->dis_u2_susphy_quirk) {
1131                         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1132                         reg |= DWC3_GUSB2PHYCFG_SUSPHY;
1133                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1134                 }
1135         }
1136
1137         dwc3_core_setup_global_control(dwc);
1138         dwc3_core_num_eps(dwc);
1139
1140         ret = dwc3_setup_scratch_buffers(dwc);
1141         if (ret)
1142                 goto err1;
1143
1144         /* Set power down scale of suspend_clk */
1145         dwc3_set_power_down_clk_scale(dwc);
1146
1147         /* Adjust Frame Length */
1148         dwc3_frame_length_adjustment(dwc);
1149
1150         /* Adjust Reference Clock Period */
1151         dwc3_ref_clk_period(dwc);
1152
1153         dwc3_set_incr_burst_type(dwc);
1154
1155         usb_phy_set_suspend(dwc->usb2_phy, 0);
1156         usb_phy_set_suspend(dwc->usb3_phy, 0);
1157         ret = phy_power_on(dwc->usb2_generic_phy);
1158         if (ret < 0)
1159                 goto err2;
1160
1161         ret = phy_power_on(dwc->usb3_generic_phy);
1162         if (ret < 0)
1163                 goto err3;
1164
1165         ret = dwc3_event_buffers_setup(dwc);
1166         if (ret) {
1167                 dev_err(dwc->dev, "failed to setup event buffers\n");
1168                 goto err4;
1169         }
1170
1171         /*
1172          * ENDXFER polling is available on version 3.10a and later of
1173          * the DWC_usb3 controller. It is NOT available in the
1174          * DWC_usb31 controller.
1175          */
1176         if (DWC3_VER_IS_WITHIN(DWC3, 310A, ANY)) {
1177                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL2);
1178                 reg |= DWC3_GUCTL2_RST_ACTBITLATER;
1179                 dwc3_writel(dwc->regs, DWC3_GUCTL2, reg);
1180         }
1181
1182         if (!DWC3_VER_IS_PRIOR(DWC3, 250A)) {
1183                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL1);
1184
1185                 /*
1186                  * Enable hardware control of sending remote wakeup
1187                  * in HS when the device is in the L1 state.
1188                  */
1189                 if (!DWC3_VER_IS_PRIOR(DWC3, 290A))
1190                         reg |= DWC3_GUCTL1_DEV_L1_EXIT_BY_HW;
1191
1192                 /*
1193                  * Decouple USB 2.0 L1 & L2 events which will allow for
1194                  * gadget driver to only receive U3/L2 suspend & wakeup
1195                  * events and prevent the more frequent L1 LPM transitions
1196                  * from interrupting the driver.
1197                  */
1198                 if (!DWC3_VER_IS_PRIOR(DWC3, 300A))
1199                         reg |= DWC3_GUCTL1_DEV_DECOUPLE_L1L2_EVT;
1200
1201                 if (dwc->dis_tx_ipgap_linecheck_quirk)
1202                         reg |= DWC3_GUCTL1_TX_IPGAP_LINECHECK_DIS;
1203
1204                 if (dwc->parkmode_disable_ss_quirk)
1205                         reg |= DWC3_GUCTL1_PARKMODE_DISABLE_SS;
1206
1207                 if (DWC3_VER_IS_WITHIN(DWC3, 290A, ANY) &&
1208                     (dwc->maximum_speed == USB_SPEED_HIGH ||
1209                      dwc->maximum_speed == USB_SPEED_FULL))
1210                         reg |= DWC3_GUCTL1_DEV_FORCE_20_CLK_FOR_30_CLK;
1211
1212                 dwc3_writel(dwc->regs, DWC3_GUCTL1, reg);
1213         }
1214
1215         if (dwc->dr_mode == USB_DR_MODE_HOST ||
1216             dwc->dr_mode == USB_DR_MODE_OTG) {
1217                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL);
1218
1219                 /*
1220                  * Enable Auto retry Feature to make the controller operating in
1221                  * Host mode on seeing transaction errors(CRC errors or internal
1222                  * overrun scenerios) on IN transfers to reply to the device
1223                  * with a non-terminating retry ACK (i.e, an ACK transcation
1224                  * packet with Retry=1 & Nump != 0)
1225                  */
1226                 reg |= DWC3_GUCTL_HSTINAUTORETRY;
1227
1228                 dwc3_writel(dwc->regs, DWC3_GUCTL, reg);
1229         }
1230
1231         /*
1232          * Must config both number of packets and max burst settings to enable
1233          * RX and/or TX threshold.
1234          */
1235         if (!DWC3_IP_IS(DWC3) && dwc->dr_mode == USB_DR_MODE_HOST) {
1236                 u8 rx_thr_num = dwc->rx_thr_num_pkt_prd;
1237                 u8 rx_maxburst = dwc->rx_max_burst_prd;
1238                 u8 tx_thr_num = dwc->tx_thr_num_pkt_prd;
1239                 u8 tx_maxburst = dwc->tx_max_burst_prd;
1240
1241                 if (rx_thr_num && rx_maxburst) {
1242                         reg = dwc3_readl(dwc->regs, DWC3_GRXTHRCFG);
1243                         reg |= DWC31_RXTHRNUMPKTSEL_PRD;
1244
1245                         reg &= ~DWC31_RXTHRNUMPKT_PRD(~0);
1246                         reg |= DWC31_RXTHRNUMPKT_PRD(rx_thr_num);
1247
1248                         reg &= ~DWC31_MAXRXBURSTSIZE_PRD(~0);
1249                         reg |= DWC31_MAXRXBURSTSIZE_PRD(rx_maxburst);
1250
1251                         dwc3_writel(dwc->regs, DWC3_GRXTHRCFG, reg);
1252                 }
1253
1254                 if (tx_thr_num && tx_maxburst) {
1255                         reg = dwc3_readl(dwc->regs, DWC3_GTXTHRCFG);
1256                         reg |= DWC31_TXTHRNUMPKTSEL_PRD;
1257
1258                         reg &= ~DWC31_TXTHRNUMPKT_PRD(~0);
1259                         reg |= DWC31_TXTHRNUMPKT_PRD(tx_thr_num);
1260
1261                         reg &= ~DWC31_MAXTXBURSTSIZE_PRD(~0);
1262                         reg |= DWC31_MAXTXBURSTSIZE_PRD(tx_maxburst);
1263
1264                         dwc3_writel(dwc->regs, DWC3_GTXTHRCFG, reg);
1265                 }
1266         }
1267
1268         return 0;
1269
1270 err4:
1271         phy_power_off(dwc->usb3_generic_phy);
1272
1273 err3:
1274         phy_power_off(dwc->usb2_generic_phy);
1275
1276 err2:
1277         usb_phy_set_suspend(dwc->usb2_phy, 1);
1278         usb_phy_set_suspend(dwc->usb3_phy, 1);
1279
1280 err1:
1281         usb_phy_shutdown(dwc->usb2_phy);
1282         usb_phy_shutdown(dwc->usb3_phy);
1283         phy_exit(dwc->usb2_generic_phy);
1284         phy_exit(dwc->usb3_generic_phy);
1285
1286 err0a:
1287         dwc3_ulpi_exit(dwc);
1288
1289 err0:
1290         return ret;
1291 }
1292
1293 static int dwc3_core_get_phy(struct dwc3 *dwc)
1294 {
1295         struct device           *dev = dwc->dev;
1296         struct device_node      *node = dev->of_node;
1297         int ret;
1298
1299         if (node) {
1300                 dwc->usb2_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 0);
1301                 dwc->usb3_phy = devm_usb_get_phy_by_phandle(dev, "usb-phy", 1);
1302         } else {
1303                 dwc->usb2_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB2);
1304                 dwc->usb3_phy = devm_usb_get_phy(dev, USB_PHY_TYPE_USB3);
1305         }
1306
1307         if (IS_ERR(dwc->usb2_phy)) {
1308                 ret = PTR_ERR(dwc->usb2_phy);
1309                 if (ret == -ENXIO || ret == -ENODEV)
1310                         dwc->usb2_phy = NULL;
1311                 else
1312                         return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1313         }
1314
1315         if (IS_ERR(dwc->usb3_phy)) {
1316                 ret = PTR_ERR(dwc->usb3_phy);
1317                 if (ret == -ENXIO || ret == -ENODEV)
1318                         dwc->usb3_phy = NULL;
1319                 else
1320                         return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1321         }
1322
1323         dwc->usb2_generic_phy = devm_phy_get(dev, "usb2-phy");
1324         if (IS_ERR(dwc->usb2_generic_phy)) {
1325                 ret = PTR_ERR(dwc->usb2_generic_phy);
1326                 if (ret == -ENOSYS || ret == -ENODEV)
1327                         dwc->usb2_generic_phy = NULL;
1328                 else
1329                         return dev_err_probe(dev, ret, "no usb2 phy configured\n");
1330         }
1331
1332         dwc->usb3_generic_phy = devm_phy_get(dev, "usb3-phy");
1333         if (IS_ERR(dwc->usb3_generic_phy)) {
1334                 ret = PTR_ERR(dwc->usb3_generic_phy);
1335                 if (ret == -ENOSYS || ret == -ENODEV)
1336                         dwc->usb3_generic_phy = NULL;
1337                 else
1338                         return dev_err_probe(dev, ret, "no usb3 phy configured\n");
1339         }
1340
1341         return 0;
1342 }
1343
1344 static int dwc3_core_init_mode(struct dwc3 *dwc)
1345 {
1346         struct device *dev = dwc->dev;
1347         int ret;
1348
1349         switch (dwc->dr_mode) {
1350         case USB_DR_MODE_PERIPHERAL:
1351                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1352
1353                 if (dwc->usb2_phy)
1354                         otg_set_vbus(dwc->usb2_phy->otg, false);
1355                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_DEVICE);
1356                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_DEVICE);
1357
1358                 ret = dwc3_gadget_init(dwc);
1359                 if (ret)
1360                         return dev_err_probe(dev, ret, "failed to initialize gadget\n");
1361                 break;
1362         case USB_DR_MODE_HOST:
1363                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
1364
1365                 if (dwc->usb2_phy)
1366                         otg_set_vbus(dwc->usb2_phy->otg, true);
1367                 phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
1368                 phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
1369
1370                 ret = dwc3_host_init(dwc);
1371                 if (ret)
1372                         return dev_err_probe(dev, ret, "failed to initialize host\n");
1373                 break;
1374         case USB_DR_MODE_OTG:
1375                 INIT_WORK(&dwc->drd_work, __dwc3_set_mode);
1376                 ret = dwc3_drd_init(dwc);
1377                 if (ret)
1378                         return dev_err_probe(dev, ret, "failed to initialize dual-role\n");
1379                 break;
1380         default:
1381                 dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
1382                 return -EINVAL;
1383         }
1384
1385         return 0;
1386 }
1387
1388 static void dwc3_core_exit_mode(struct dwc3 *dwc)
1389 {
1390         switch (dwc->dr_mode) {
1391         case USB_DR_MODE_PERIPHERAL:
1392                 dwc3_gadget_exit(dwc);
1393                 break;
1394         case USB_DR_MODE_HOST:
1395                 dwc3_host_exit(dwc);
1396                 break;
1397         case USB_DR_MODE_OTG:
1398                 dwc3_drd_exit(dwc);
1399                 break;
1400         default:
1401                 /* do nothing */
1402                 break;
1403         }
1404
1405         /* de-assert DRVVBUS for HOST and OTG mode */
1406         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
1407 }
1408
1409 static void dwc3_get_properties(struct dwc3 *dwc)
1410 {
1411         struct device           *dev = dwc->dev;
1412         u8                      lpm_nyet_threshold;
1413         u8                      tx_de_emphasis;
1414         u8                      hird_threshold;
1415         u8                      rx_thr_num_pkt_prd = 0;
1416         u8                      rx_max_burst_prd = 0;
1417         u8                      tx_thr_num_pkt_prd = 0;
1418         u8                      tx_max_burst_prd = 0;
1419         u8                      tx_fifo_resize_max_num;
1420         const char              *usb_psy_name;
1421         int                     ret;
1422
1423         /* default to highest possible threshold */
1424         lpm_nyet_threshold = 0xf;
1425
1426         /* default to -3.5dB de-emphasis */
1427         tx_de_emphasis = 1;
1428
1429         /*
1430          * default to assert utmi_sleep_n and use maximum allowed HIRD
1431          * threshold value of 0b1100
1432          */
1433         hird_threshold = 12;
1434
1435         /*
1436          * default to a TXFIFO size large enough to fit 6 max packets.  This
1437          * allows for systems with larger bus latencies to have some headroom
1438          * for endpoints that have a large bMaxBurst value.
1439          */
1440         tx_fifo_resize_max_num = 6;
1441
1442         dwc->maximum_speed = usb_get_maximum_speed(dev);
1443         dwc->max_ssp_rate = usb_get_maximum_ssp_rate(dev);
1444         dwc->dr_mode = usb_get_dr_mode(dev);
1445         dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
1446
1447         dwc->sysdev_is_parent = device_property_read_bool(dev,
1448                                 "linux,sysdev_is_parent");
1449         if (dwc->sysdev_is_parent)
1450                 dwc->sysdev = dwc->dev->parent;
1451         else
1452                 dwc->sysdev = dwc->dev;
1453
1454         ret = device_property_read_string(dev, "usb-psy-name", &usb_psy_name);
1455         if (ret >= 0) {
1456                 dwc->usb_psy = power_supply_get_by_name(usb_psy_name);
1457                 if (!dwc->usb_psy)
1458                         dev_err(dev, "couldn't get usb power supply\n");
1459         }
1460
1461         dwc->has_lpm_erratum = device_property_read_bool(dev,
1462                                 "snps,has-lpm-erratum");
1463         device_property_read_u8(dev, "snps,lpm-nyet-threshold",
1464                                 &lpm_nyet_threshold);
1465         dwc->is_utmi_l1_suspend = device_property_read_bool(dev,
1466                                 "snps,is-utmi-l1-suspend");
1467         device_property_read_u8(dev, "snps,hird-threshold",
1468                                 &hird_threshold);
1469         dwc->dis_start_transfer_quirk = device_property_read_bool(dev,
1470                                 "snps,dis-start-transfer-quirk");
1471         dwc->usb3_lpm_capable = device_property_read_bool(dev,
1472                                 "snps,usb3_lpm_capable");
1473         dwc->usb2_lpm_disable = device_property_read_bool(dev,
1474                                 "snps,usb2-lpm-disable");
1475         dwc->usb2_gadget_lpm_disable = device_property_read_bool(dev,
1476                                 "snps,usb2-gadget-lpm-disable");
1477         device_property_read_u8(dev, "snps,rx-thr-num-pkt-prd",
1478                                 &rx_thr_num_pkt_prd);
1479         device_property_read_u8(dev, "snps,rx-max-burst-prd",
1480                                 &rx_max_burst_prd);
1481         device_property_read_u8(dev, "snps,tx-thr-num-pkt-prd",
1482                                 &tx_thr_num_pkt_prd);
1483         device_property_read_u8(dev, "snps,tx-max-burst-prd",
1484                                 &tx_max_burst_prd);
1485         dwc->do_fifo_resize = device_property_read_bool(dev,
1486                                                         "tx-fifo-resize");
1487         if (dwc->do_fifo_resize)
1488                 device_property_read_u8(dev, "tx-fifo-max-num",
1489                                         &tx_fifo_resize_max_num);
1490
1491         dwc->disable_scramble_quirk = device_property_read_bool(dev,
1492                                 "snps,disable_scramble_quirk");
1493         dwc->u2exit_lfps_quirk = device_property_read_bool(dev,
1494                                 "snps,u2exit_lfps_quirk");
1495         dwc->u2ss_inp3_quirk = device_property_read_bool(dev,
1496                                 "snps,u2ss_inp3_quirk");
1497         dwc->req_p1p2p3_quirk = device_property_read_bool(dev,
1498                                 "snps,req_p1p2p3_quirk");
1499         dwc->del_p1p2p3_quirk = device_property_read_bool(dev,
1500                                 "snps,del_p1p2p3_quirk");
1501         dwc->del_phy_power_chg_quirk = device_property_read_bool(dev,
1502                                 "snps,del_phy_power_chg_quirk");
1503         dwc->lfps_filter_quirk = device_property_read_bool(dev,
1504                                 "snps,lfps_filter_quirk");
1505         dwc->rx_detect_poll_quirk = device_property_read_bool(dev,
1506                                 "snps,rx_detect_poll_quirk");
1507         dwc->dis_u3_susphy_quirk = device_property_read_bool(dev,
1508                                 "snps,dis_u3_susphy_quirk");
1509         dwc->dis_u2_susphy_quirk = device_property_read_bool(dev,
1510                                 "snps,dis_u2_susphy_quirk");
1511         dwc->dis_enblslpm_quirk = device_property_read_bool(dev,
1512                                 "snps,dis_enblslpm_quirk");
1513         dwc->dis_u1_entry_quirk = device_property_read_bool(dev,
1514                                 "snps,dis-u1-entry-quirk");
1515         dwc->dis_u2_entry_quirk = device_property_read_bool(dev,
1516                                 "snps,dis-u2-entry-quirk");
1517         dwc->dis_rxdet_inp3_quirk = device_property_read_bool(dev,
1518                                 "snps,dis_rxdet_inp3_quirk");
1519         dwc->dis_u2_freeclk_exists_quirk = device_property_read_bool(dev,
1520                                 "snps,dis-u2-freeclk-exists-quirk");
1521         dwc->dis_del_phy_power_chg_quirk = device_property_read_bool(dev,
1522                                 "snps,dis-del-phy-power-chg-quirk");
1523         dwc->dis_tx_ipgap_linecheck_quirk = device_property_read_bool(dev,
1524                                 "snps,dis-tx-ipgap-linecheck-quirk");
1525         dwc->parkmode_disable_ss_quirk = device_property_read_bool(dev,
1526                                 "snps,parkmode-disable-ss-quirk");
1527
1528         dwc->tx_de_emphasis_quirk = device_property_read_bool(dev,
1529                                 "snps,tx_de_emphasis_quirk");
1530         device_property_read_u8(dev, "snps,tx_de_emphasis",
1531                                 &tx_de_emphasis);
1532         device_property_read_string(dev, "snps,hsphy_interface",
1533                                     &dwc->hsphy_interface);
1534         device_property_read_u32(dev, "snps,quirk-frame-length-adjustment",
1535                                  &dwc->fladj);
1536         device_property_read_u32(dev, "snps,ref-clock-period-ns",
1537                                  &dwc->ref_clk_per);
1538
1539         dwc->dis_metastability_quirk = device_property_read_bool(dev,
1540                                 "snps,dis_metastability_quirk");
1541
1542         dwc->dis_split_quirk = device_property_read_bool(dev,
1543                                 "snps,dis-split-quirk");
1544
1545         dwc->lpm_nyet_threshold = lpm_nyet_threshold;
1546         dwc->tx_de_emphasis = tx_de_emphasis;
1547
1548         dwc->hird_threshold = hird_threshold;
1549
1550         dwc->rx_thr_num_pkt_prd = rx_thr_num_pkt_prd;
1551         dwc->rx_max_burst_prd = rx_max_burst_prd;
1552
1553         dwc->tx_thr_num_pkt_prd = tx_thr_num_pkt_prd;
1554         dwc->tx_max_burst_prd = tx_max_burst_prd;
1555
1556         dwc->imod_interval = 0;
1557
1558         dwc->tx_fifo_resize_max_num = tx_fifo_resize_max_num;
1559 }
1560
1561 /* check whether the core supports IMOD */
1562 bool dwc3_has_imod(struct dwc3 *dwc)
1563 {
1564         return DWC3_VER_IS_WITHIN(DWC3, 300A, ANY) ||
1565                 DWC3_VER_IS_WITHIN(DWC31, 120A, ANY) ||
1566                 DWC3_IP_IS(DWC32);
1567 }
1568
1569 static void dwc3_check_params(struct dwc3 *dwc)
1570 {
1571         struct device *dev = dwc->dev;
1572         unsigned int hwparam_gen =
1573                 DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3);
1574
1575         /* Check for proper value of imod_interval */
1576         if (dwc->imod_interval && !dwc3_has_imod(dwc)) {
1577                 dev_warn(dwc->dev, "Interrupt moderation not supported\n");
1578                 dwc->imod_interval = 0;
1579         }
1580
1581         /*
1582          * Workaround for STAR 9000961433 which affects only version
1583          * 3.00a of the DWC_usb3 core. This prevents the controller
1584          * interrupt from being masked while handling events. IMOD
1585          * allows us to work around this issue. Enable it for the
1586          * affected version.
1587          */
1588         if (!dwc->imod_interval &&
1589             DWC3_VER_IS(DWC3, 300A))
1590                 dwc->imod_interval = 1;
1591
1592         /* Check the maximum_speed parameter */
1593         switch (dwc->maximum_speed) {
1594         case USB_SPEED_FULL:
1595         case USB_SPEED_HIGH:
1596                 break;
1597         case USB_SPEED_SUPER:
1598                 if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS)
1599                         dev_warn(dev, "UDC doesn't support Gen 1\n");
1600                 break;
1601         case USB_SPEED_SUPER_PLUS:
1602                 if ((DWC3_IP_IS(DWC32) &&
1603                      hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_DIS) ||
1604                     (!DWC3_IP_IS(DWC32) &&
1605                      hwparam_gen != DWC3_GHWPARAMS3_SSPHY_IFC_GEN2))
1606                         dev_warn(dev, "UDC doesn't support SSP\n");
1607                 break;
1608         default:
1609                 dev_err(dev, "invalid maximum_speed parameter %d\n",
1610                         dwc->maximum_speed);
1611                 fallthrough;
1612         case USB_SPEED_UNKNOWN:
1613                 switch (hwparam_gen) {
1614                 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1615                         dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1616                         break;
1617                 case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1618                         if (DWC3_IP_IS(DWC32))
1619                                 dwc->maximum_speed = USB_SPEED_SUPER_PLUS;
1620                         else
1621                                 dwc->maximum_speed = USB_SPEED_SUPER;
1622                         break;
1623                 case DWC3_GHWPARAMS3_SSPHY_IFC_DIS:
1624                         dwc->maximum_speed = USB_SPEED_HIGH;
1625                         break;
1626                 default:
1627                         dwc->maximum_speed = USB_SPEED_SUPER;
1628                         break;
1629                 }
1630                 break;
1631         }
1632
1633         /*
1634          * Currently the controller does not have visibility into the HW
1635          * parameter to determine the maximum number of lanes the HW supports.
1636          * If the number of lanes is not specified in the device property, then
1637          * set the default to support dual-lane for DWC_usb32 and single-lane
1638          * for DWC_usb31 for super-speed-plus.
1639          */
1640         if (dwc->maximum_speed == USB_SPEED_SUPER_PLUS) {
1641                 switch (dwc->max_ssp_rate) {
1642                 case USB_SSP_GEN_2x1:
1643                         if (hwparam_gen == DWC3_GHWPARAMS3_SSPHY_IFC_GEN1)
1644                                 dev_warn(dev, "UDC only supports Gen 1\n");
1645                         break;
1646                 case USB_SSP_GEN_1x2:
1647                 case USB_SSP_GEN_2x2:
1648                         if (DWC3_IP_IS(DWC31))
1649                                 dev_warn(dev, "UDC only supports single lane\n");
1650                         break;
1651                 case USB_SSP_GEN_UNKNOWN:
1652                 default:
1653                         switch (hwparam_gen) {
1654                         case DWC3_GHWPARAMS3_SSPHY_IFC_GEN2:
1655                                 if (DWC3_IP_IS(DWC32))
1656                                         dwc->max_ssp_rate = USB_SSP_GEN_2x2;
1657                                 else
1658                                         dwc->max_ssp_rate = USB_SSP_GEN_2x1;
1659                                 break;
1660                         case DWC3_GHWPARAMS3_SSPHY_IFC_GEN1:
1661                                 if (DWC3_IP_IS(DWC32))
1662                                         dwc->max_ssp_rate = USB_SSP_GEN_1x2;
1663                                 break;
1664                         }
1665                         break;
1666                 }
1667         }
1668 }
1669
1670 static struct extcon_dev *dwc3_get_extcon(struct dwc3 *dwc)
1671 {
1672         struct device *dev = dwc->dev;
1673         struct device_node *np_phy;
1674         struct extcon_dev *edev = NULL;
1675         const char *name;
1676
1677         if (device_property_read_bool(dev, "extcon"))
1678                 return extcon_get_edev_by_phandle(dev, 0);
1679
1680         /*
1681          * Device tree platforms should get extcon via phandle.
1682          * On ACPI platforms, we get the name from a device property.
1683          * This device property is for kernel internal use only and
1684          * is expected to be set by the glue code.
1685          */
1686         if (device_property_read_string(dev, "linux,extcon-name", &name) == 0)
1687                 return extcon_get_extcon_dev(name);
1688
1689         /*
1690          * Try to get an extcon device from the USB PHY controller's "port"
1691          * node. Check if it has the "port" node first, to avoid printing the
1692          * error message from underlying code, as it's a valid case: extcon
1693          * device (and "port" node) may be missing in case of "usb-role-switch"
1694          * or OTG mode.
1695          */
1696         np_phy = of_parse_phandle(dev->of_node, "phys", 0);
1697         if (of_graph_is_present(np_phy)) {
1698                 struct device_node *np_conn;
1699
1700                 np_conn = of_graph_get_remote_node(np_phy, -1, -1);
1701                 if (np_conn)
1702                         edev = extcon_find_edev_by_node(np_conn);
1703                 of_node_put(np_conn);
1704         }
1705         of_node_put(np_phy);
1706
1707         return edev;
1708 }
1709
1710 static int dwc3_probe(struct platform_device *pdev)
1711 {
1712         struct device           *dev = &pdev->dev;
1713         struct resource         *res, dwc_res;
1714         struct dwc3             *dwc;
1715
1716         int                     ret;
1717
1718         void __iomem            *regs;
1719
1720         dwc = devm_kzalloc(dev, sizeof(*dwc), GFP_KERNEL);
1721         if (!dwc)
1722                 return -ENOMEM;
1723
1724         dwc->dev = dev;
1725
1726         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1727         if (!res) {
1728                 dev_err(dev, "missing memory resource\n");
1729                 return -ENODEV;
1730         }
1731
1732         dwc->xhci_resources[0].start = res->start;
1733         dwc->xhci_resources[0].end = dwc->xhci_resources[0].start +
1734                                         DWC3_XHCI_REGS_END;
1735         dwc->xhci_resources[0].flags = res->flags;
1736         dwc->xhci_resources[0].name = res->name;
1737
1738         /*
1739          * Request memory region but exclude xHCI regs,
1740          * since it will be requested by the xhci-plat driver.
1741          */
1742         dwc_res = *res;
1743         dwc_res.start += DWC3_GLOBALS_REGS_START;
1744
1745         regs = devm_ioremap_resource(dev, &dwc_res);
1746         if (IS_ERR(regs))
1747                 return PTR_ERR(regs);
1748
1749         dwc->regs       = regs;
1750         dwc->regs_size  = resource_size(&dwc_res);
1751
1752         dwc3_get_properties(dwc);
1753
1754         if (!dwc->sysdev_is_parent) {
1755                 ret = dma_set_mask_and_coherent(dwc->sysdev, DMA_BIT_MASK(64));
1756                 if (ret)
1757                         return ret;
1758         }
1759
1760         dwc->reset = devm_reset_control_array_get_optional_shared(dev);
1761         if (IS_ERR(dwc->reset))
1762                 return PTR_ERR(dwc->reset);
1763
1764         if (dev->of_node) {
1765                 /*
1766                  * Clocks are optional, but new DT platforms should support all
1767                  * clocks as required by the DT-binding.
1768                  * Some devices have different clock names in legacy device trees,
1769                  * check for them to retain backwards compatibility.
1770                  */
1771                 dwc->bus_clk = devm_clk_get_optional(dev, "bus_early");
1772                 if (IS_ERR(dwc->bus_clk))
1773                         return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1774                                              "could not get bus clock\n");
1775
1776                 if (dwc->bus_clk == NULL) {
1777                         dwc->bus_clk = devm_clk_get_optional(dev, "bus_clk");
1778                         if (IS_ERR(dwc->bus_clk))
1779                                 return dev_err_probe(dev, PTR_ERR(dwc->bus_clk),
1780                                                      "could not get bus clock\n");
1781                 }
1782
1783                 dwc->ref_clk = devm_clk_get_optional(dev, "ref");
1784                 if (IS_ERR(dwc->ref_clk))
1785                         return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1786                                              "could not get ref clock\n");
1787
1788                 if (dwc->ref_clk == NULL) {
1789                         dwc->ref_clk = devm_clk_get_optional(dev, "ref_clk");
1790                         if (IS_ERR(dwc->ref_clk))
1791                                 return dev_err_probe(dev, PTR_ERR(dwc->ref_clk),
1792                                                      "could not get ref clock\n");
1793                 }
1794
1795                 dwc->susp_clk = devm_clk_get_optional(dev, "suspend");
1796                 if (IS_ERR(dwc->susp_clk))
1797                         return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1798                                              "could not get suspend clock\n");
1799
1800                 if (dwc->susp_clk == NULL) {
1801                         dwc->susp_clk = devm_clk_get_optional(dev, "suspend_clk");
1802                         if (IS_ERR(dwc->susp_clk))
1803                                 return dev_err_probe(dev, PTR_ERR(dwc->susp_clk),
1804                                                      "could not get suspend clock\n");
1805                 }
1806         }
1807
1808         ret = reset_control_deassert(dwc->reset);
1809         if (ret)
1810                 return ret;
1811
1812         ret = dwc3_clk_enable(dwc);
1813         if (ret)
1814                 goto assert_reset;
1815
1816         if (!dwc3_core_is_valid(dwc)) {
1817                 dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
1818                 ret = -ENODEV;
1819                 goto disable_clks;
1820         }
1821
1822         platform_set_drvdata(pdev, dwc);
1823         dwc3_cache_hwparams(dwc);
1824         device_init_wakeup(&pdev->dev, of_property_read_bool(dev->of_node, "wakeup-source"));
1825
1826         spin_lock_init(&dwc->lock);
1827         mutex_init(&dwc->mutex);
1828
1829         pm_runtime_set_active(dev);
1830         pm_runtime_use_autosuspend(dev);
1831         pm_runtime_set_autosuspend_delay(dev, DWC3_DEFAULT_AUTOSUSPEND_DELAY);
1832         pm_runtime_enable(dev);
1833         ret = pm_runtime_get_sync(dev);
1834         if (ret < 0)
1835                 goto err1;
1836
1837         pm_runtime_forbid(dev);
1838
1839         ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
1840         if (ret) {
1841                 dev_err(dwc->dev, "failed to allocate event buffers\n");
1842                 ret = -ENOMEM;
1843                 goto err2;
1844         }
1845
1846         dwc->edev = dwc3_get_extcon(dwc);
1847         if (IS_ERR(dwc->edev)) {
1848                 ret = PTR_ERR(dwc->edev);
1849                 dev_err_probe(dwc->dev, ret, "failed to get extcon\n");
1850                 goto err3;
1851         }
1852
1853         ret = dwc3_get_dr_mode(dwc);
1854         if (ret)
1855                 goto err3;
1856
1857         ret = dwc3_alloc_scratch_buffers(dwc);
1858         if (ret)
1859                 goto err3;
1860
1861         ret = dwc3_core_init(dwc);
1862         if (ret) {
1863                 dev_err_probe(dev, ret, "failed to initialize core\n");
1864                 goto err4;
1865         }
1866
1867         dwc3_check_params(dwc);
1868         dwc3_debugfs_init(dwc);
1869
1870         ret = dwc3_core_init_mode(dwc);
1871         if (ret)
1872                 goto err5;
1873
1874         pm_runtime_put(dev);
1875
1876         return 0;
1877
1878 err5:
1879         dwc3_debugfs_exit(dwc);
1880         dwc3_event_buffers_cleanup(dwc);
1881
1882         usb_phy_shutdown(dwc->usb2_phy);
1883         usb_phy_shutdown(dwc->usb3_phy);
1884         phy_exit(dwc->usb2_generic_phy);
1885         phy_exit(dwc->usb3_generic_phy);
1886
1887         usb_phy_set_suspend(dwc->usb2_phy, 1);
1888         usb_phy_set_suspend(dwc->usb3_phy, 1);
1889         phy_power_off(dwc->usb2_generic_phy);
1890         phy_power_off(dwc->usb3_generic_phy);
1891
1892         dwc3_ulpi_exit(dwc);
1893
1894 err4:
1895         dwc3_free_scratch_buffers(dwc);
1896
1897 err3:
1898         dwc3_free_event_buffers(dwc);
1899
1900 err2:
1901         pm_runtime_allow(&pdev->dev);
1902
1903 err1:
1904         pm_runtime_put_sync(&pdev->dev);
1905         pm_runtime_disable(&pdev->dev);
1906
1907 disable_clks:
1908         dwc3_clk_disable(dwc);
1909 assert_reset:
1910         reset_control_assert(dwc->reset);
1911
1912         if (dwc->usb_psy)
1913                 power_supply_put(dwc->usb_psy);
1914
1915         return ret;
1916 }
1917
1918 static int dwc3_remove(struct platform_device *pdev)
1919 {
1920         struct dwc3     *dwc = platform_get_drvdata(pdev);
1921
1922         pm_runtime_get_sync(&pdev->dev);
1923
1924         dwc3_core_exit_mode(dwc);
1925         dwc3_debugfs_exit(dwc);
1926
1927         dwc3_core_exit(dwc);
1928         dwc3_ulpi_exit(dwc);
1929
1930         pm_runtime_disable(&pdev->dev);
1931         pm_runtime_put_noidle(&pdev->dev);
1932         pm_runtime_set_suspended(&pdev->dev);
1933
1934         dwc3_free_event_buffers(dwc);
1935         dwc3_free_scratch_buffers(dwc);
1936
1937         if (dwc->usb_psy)
1938                 power_supply_put(dwc->usb_psy);
1939
1940         return 0;
1941 }
1942
1943 #ifdef CONFIG_PM
1944 static int dwc3_core_init_for_resume(struct dwc3 *dwc)
1945 {
1946         int ret;
1947
1948         ret = reset_control_deassert(dwc->reset);
1949         if (ret)
1950                 return ret;
1951
1952         ret = dwc3_clk_enable(dwc);
1953         if (ret)
1954                 goto assert_reset;
1955
1956         ret = dwc3_core_init(dwc);
1957         if (ret)
1958                 goto disable_clks;
1959
1960         return 0;
1961
1962 disable_clks:
1963         dwc3_clk_disable(dwc);
1964 assert_reset:
1965         reset_control_assert(dwc->reset);
1966
1967         return ret;
1968 }
1969
1970 static int dwc3_suspend_common(struct dwc3 *dwc, pm_message_t msg)
1971 {
1972         unsigned long   flags;
1973         u32 reg;
1974
1975         switch (dwc->current_dr_role) {
1976         case DWC3_GCTL_PRTCAP_DEVICE:
1977                 if (pm_runtime_suspended(dwc->dev))
1978                         break;
1979                 spin_lock_irqsave(&dwc->lock, flags);
1980                 dwc3_gadget_suspend(dwc);
1981                 spin_unlock_irqrestore(&dwc->lock, flags);
1982                 synchronize_irq(dwc->irq_gadget);
1983                 dwc3_core_exit(dwc);
1984                 break;
1985         case DWC3_GCTL_PRTCAP_HOST:
1986                 if (!PMSG_IS_AUTO(msg) && !device_can_wakeup(dwc->dev)) {
1987                         dwc3_core_exit(dwc);
1988                         break;
1989                 }
1990
1991                 /* Let controller to suspend HSPHY before PHY driver suspends */
1992                 if (dwc->dis_u2_susphy_quirk ||
1993                     dwc->dis_enblslpm_quirk) {
1994                         reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
1995                         reg |=  DWC3_GUSB2PHYCFG_ENBLSLPM |
1996                                 DWC3_GUSB2PHYCFG_SUSPHY;
1997                         dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
1998
1999                         /* Give some time for USB2 PHY to suspend */
2000                         usleep_range(5000, 6000);
2001                 }
2002
2003                 phy_pm_runtime_put_sync(dwc->usb2_generic_phy);
2004                 phy_pm_runtime_put_sync(dwc->usb3_generic_phy);
2005                 break;
2006         case DWC3_GCTL_PRTCAP_OTG:
2007                 /* do nothing during runtime_suspend */
2008                 if (PMSG_IS_AUTO(msg))
2009                         break;
2010
2011                 if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2012                         spin_lock_irqsave(&dwc->lock, flags);
2013                         dwc3_gadget_suspend(dwc);
2014                         spin_unlock_irqrestore(&dwc->lock, flags);
2015                         synchronize_irq(dwc->irq_gadget);
2016                 }
2017
2018                 dwc3_otg_exit(dwc);
2019                 dwc3_core_exit(dwc);
2020                 break;
2021         default:
2022                 /* do nothing */
2023                 break;
2024         }
2025
2026         return 0;
2027 }
2028
2029 static int dwc3_resume_common(struct dwc3 *dwc, pm_message_t msg)
2030 {
2031         unsigned long   flags;
2032         int             ret;
2033         u32             reg;
2034
2035         switch (dwc->current_dr_role) {
2036         case DWC3_GCTL_PRTCAP_DEVICE:
2037                 ret = dwc3_core_init_for_resume(dwc);
2038                 if (ret)
2039                         return ret;
2040
2041                 dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_DEVICE);
2042                 spin_lock_irqsave(&dwc->lock, flags);
2043                 dwc3_gadget_resume(dwc);
2044                 spin_unlock_irqrestore(&dwc->lock, flags);
2045                 break;
2046         case DWC3_GCTL_PRTCAP_HOST:
2047                 if (!PMSG_IS_AUTO(msg) && !device_can_wakeup(dwc->dev)) {
2048                         ret = dwc3_core_init_for_resume(dwc);
2049                         if (ret)
2050                                 return ret;
2051                         dwc3_set_prtcap(dwc, DWC3_GCTL_PRTCAP_HOST);
2052                         break;
2053                 }
2054                 /* Restore GUSB2PHYCFG bits that were modified in suspend */
2055                 reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
2056                 if (dwc->dis_u2_susphy_quirk)
2057                         reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
2058
2059                 if (dwc->dis_enblslpm_quirk)
2060                         reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
2061
2062                 dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
2063
2064                 phy_pm_runtime_get_sync(dwc->usb2_generic_phy);
2065                 phy_pm_runtime_get_sync(dwc->usb3_generic_phy);
2066                 break;
2067         case DWC3_GCTL_PRTCAP_OTG:
2068                 /* nothing to do on runtime_resume */
2069                 if (PMSG_IS_AUTO(msg))
2070                         break;
2071
2072                 ret = dwc3_core_init_for_resume(dwc);
2073                 if (ret)
2074                         return ret;
2075
2076                 dwc3_set_prtcap(dwc, dwc->current_dr_role);
2077
2078                 dwc3_otg_init(dwc);
2079                 if (dwc->current_otg_role == DWC3_OTG_ROLE_HOST) {
2080                         dwc3_otg_host_init(dwc);
2081                 } else if (dwc->current_otg_role == DWC3_OTG_ROLE_DEVICE) {
2082                         spin_lock_irqsave(&dwc->lock, flags);
2083                         dwc3_gadget_resume(dwc);
2084                         spin_unlock_irqrestore(&dwc->lock, flags);
2085                 }
2086
2087                 break;
2088         default:
2089                 /* do nothing */
2090                 break;
2091         }
2092
2093         return 0;
2094 }
2095
2096 static int dwc3_runtime_checks(struct dwc3 *dwc)
2097 {
2098         switch (dwc->current_dr_role) {
2099         case DWC3_GCTL_PRTCAP_DEVICE:
2100                 if (dwc->connected)
2101                         return -EBUSY;
2102                 break;
2103         case DWC3_GCTL_PRTCAP_HOST:
2104         default:
2105                 /* do nothing */
2106                 break;
2107         }
2108
2109         return 0;
2110 }
2111
2112 static int dwc3_runtime_suspend(struct device *dev)
2113 {
2114         struct dwc3     *dwc = dev_get_drvdata(dev);
2115         int             ret;
2116
2117         if (dwc3_runtime_checks(dwc))
2118                 return -EBUSY;
2119
2120         ret = dwc3_suspend_common(dwc, PMSG_AUTO_SUSPEND);
2121         if (ret)
2122                 return ret;
2123
2124         return 0;
2125 }
2126
2127 static int dwc3_runtime_resume(struct device *dev)
2128 {
2129         struct dwc3     *dwc = dev_get_drvdata(dev);
2130         int             ret;
2131
2132         ret = dwc3_resume_common(dwc, PMSG_AUTO_RESUME);
2133         if (ret)
2134                 return ret;
2135
2136         switch (dwc->current_dr_role) {
2137         case DWC3_GCTL_PRTCAP_DEVICE:
2138                 dwc3_gadget_process_pending_events(dwc);
2139                 break;
2140         case DWC3_GCTL_PRTCAP_HOST:
2141         default:
2142                 /* do nothing */
2143                 break;
2144         }
2145
2146         pm_runtime_mark_last_busy(dev);
2147
2148         return 0;
2149 }
2150
2151 static int dwc3_runtime_idle(struct device *dev)
2152 {
2153         struct dwc3     *dwc = dev_get_drvdata(dev);
2154
2155         switch (dwc->current_dr_role) {
2156         case DWC3_GCTL_PRTCAP_DEVICE:
2157                 if (dwc3_runtime_checks(dwc))
2158                         return -EBUSY;
2159                 break;
2160         case DWC3_GCTL_PRTCAP_HOST:
2161         default:
2162                 /* do nothing */
2163                 break;
2164         }
2165
2166         pm_runtime_mark_last_busy(dev);
2167         pm_runtime_autosuspend(dev);
2168
2169         return 0;
2170 }
2171 #endif /* CONFIG_PM */
2172
2173 #ifdef CONFIG_PM_SLEEP
2174 static int dwc3_suspend(struct device *dev)
2175 {
2176         struct dwc3     *dwc = dev_get_drvdata(dev);
2177         int             ret;
2178
2179         ret = dwc3_suspend_common(dwc, PMSG_SUSPEND);
2180         if (ret)
2181                 return ret;
2182
2183         pinctrl_pm_select_sleep_state(dev);
2184
2185         return 0;
2186 }
2187
2188 static int dwc3_resume(struct device *dev)
2189 {
2190         struct dwc3     *dwc = dev_get_drvdata(dev);
2191         int             ret;
2192
2193         pinctrl_pm_select_default_state(dev);
2194
2195         ret = dwc3_resume_common(dwc, PMSG_RESUME);
2196         if (ret)
2197                 return ret;
2198
2199         pm_runtime_disable(dev);
2200         pm_runtime_set_active(dev);
2201         pm_runtime_enable(dev);
2202
2203         return 0;
2204 }
2205
2206 static void dwc3_complete(struct device *dev)
2207 {
2208         struct dwc3     *dwc = dev_get_drvdata(dev);
2209         u32             reg;
2210
2211         if (dwc->current_dr_role == DWC3_GCTL_PRTCAP_HOST &&
2212                         dwc->dis_split_quirk) {
2213                 reg = dwc3_readl(dwc->regs, DWC3_GUCTL3);
2214                 reg |= DWC3_GUCTL3_SPLITDISABLE;
2215                 dwc3_writel(dwc->regs, DWC3_GUCTL3, reg);
2216         }
2217 }
2218 #else
2219 #define dwc3_complete NULL
2220 #endif /* CONFIG_PM_SLEEP */
2221
2222 static const struct dev_pm_ops dwc3_dev_pm_ops = {
2223         SET_SYSTEM_SLEEP_PM_OPS(dwc3_suspend, dwc3_resume)
2224         .complete = dwc3_complete,
2225         SET_RUNTIME_PM_OPS(dwc3_runtime_suspend, dwc3_runtime_resume,
2226                         dwc3_runtime_idle)
2227 };
2228
2229 #ifdef CONFIG_OF
2230 static const struct of_device_id of_dwc3_match[] = {
2231         {
2232                 .compatible = "snps,dwc3"
2233         },
2234         {
2235                 .compatible = "synopsys,dwc3"
2236         },
2237         { },
2238 };
2239 MODULE_DEVICE_TABLE(of, of_dwc3_match);
2240 #endif
2241
2242 #ifdef CONFIG_ACPI
2243
2244 #define ACPI_ID_INTEL_BSW       "808622B7"
2245
2246 static const struct acpi_device_id dwc3_acpi_match[] = {
2247         { ACPI_ID_INTEL_BSW, 0 },
2248         { },
2249 };
2250 MODULE_DEVICE_TABLE(acpi, dwc3_acpi_match);
2251 #endif
2252
2253 static struct platform_driver dwc3_driver = {
2254         .probe          = dwc3_probe,
2255         .remove         = dwc3_remove,
2256         .driver         = {
2257                 .name   = "dwc3",
2258                 .of_match_table = of_match_ptr(of_dwc3_match),
2259                 .acpi_match_table = ACPI_PTR(dwc3_acpi_match),
2260                 .pm     = &dwc3_dev_pm_ops,
2261         },
2262 };
2263
2264 module_platform_driver(dwc3_driver);
2265
2266 MODULE_ALIAS("platform:dwc3");
2267 MODULE_AUTHOR("Felipe Balbi <[email protected]>");
2268 MODULE_LICENSE("GPL v2");
2269 MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");