drivers/thermal/qcom/qcom-spmi-temp-alarm.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2011-2015, 2017, 2020, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/bitops.h>
   7 #include <linux/delay.h>
   8 #include <linux/err.h>
   9 #include <linux/iio/consumer.h>
  10 #include <linux/interrupt.h>
  11 #include <linux/module.h>
  12 #include <linux/of.h>
  13 #include <linux/of_device.h>
  14 #include <linux/platform_device.h>
  15 #include <linux/regmap.h>
  16 #include <linux/thermal.h>
  17
  18 #include "../thermal_core.h"
  19 #include "../thermal_hwmon.h"
  20
  21 #define QPNP_TM_REG_DIG_MAJOR           0x01
  22 #define QPNP_TM_REG_TYPE                0x04
  23 #define QPNP_TM_REG_SUBTYPE             0x05
  24 #define QPNP_TM_REG_STATUS              0x08
  25 #define QPNP_TM_REG_SHUTDOWN_CTRL1      0x40
  26 #define QPNP_TM_REG_ALARM_CTRL          0x46
  27
  28 #define QPNP_TM_TYPE                    0x09
  29 #define QPNP_TM_SUBTYPE_GEN1            0x08
  30 #define QPNP_TM_SUBTYPE_GEN2            0x09
  31
  32 #define STATUS_GEN1_STAGE_MASK          GENMASK(1, 0)
  33 #define STATUS_GEN2_STATE_MASK          GENMASK(6, 4)
  34 #define STATUS_GEN2_STATE_SHIFT         4
  35
  36 #define SHUTDOWN_CTRL1_OVERRIDE_S2      BIT(6)
  37 #define SHUTDOWN_CTRL1_THRESHOLD_MASK   GENMASK(1, 0)
  38
  39 #define SHUTDOWN_CTRL1_RATE_25HZ        BIT(3)
  40
  41 #define ALARM_CTRL_FORCE_ENABLE         BIT(7)
  42
  43 #define THRESH_COUNT                    4
  44 #define STAGE_COUNT                     3
  45
  46 /* Over-temperature trip point values in mC */
  47 static const long temp_map_gen1[THRESH_COUNT][STAGE_COUNT] = {
  48         { 105000, 125000, 145000 },
  49         { 110000, 130000, 150000 },
  50         { 115000, 135000, 155000 },
  51         { 120000, 140000, 160000 },
  52 };
  53
  54 static const long temp_map_gen2_v1[THRESH_COUNT][STAGE_COUNT] = {
  55         {  90000, 110000, 140000 },
  56         {  95000, 115000, 145000 },
  57         { 100000, 120000, 150000 },
  58         { 105000, 125000, 155000 },
  59 };
  60
  61 #define TEMP_THRESH_STEP                5000 /* Threshold step: 5 C */
  62
  63 #define THRESH_MIN                      0
  64 #define THRESH_MAX                      3
  65
  66 #define TEMP_STAGE_HYSTERESIS           2000
  67
  68 /* Temperature in Milli Celsius reported during stage 0 if no ADC is present */
  69 #define DEFAULT_TEMP                    37000
  70
  71 struct qpnp_tm_chip {
  72         struct regmap                   *map;
  73         struct device                   *dev;
  74         struct thermal_zone_device      *tz_dev;
  75         unsigned int                    subtype;
  76         long                            temp;
  77         unsigned int                    thresh;
  78         unsigned int                    stage;
  79         unsigned int                    prev_stage;
  80         unsigned int                    base;
  81         /* protects .thresh, .stage and chip registers */
  82         struct mutex                    lock;
  83         bool                            initialized;
  84
  85         struct iio_channel              *adc;
  86         const long                      (*temp_map)[THRESH_COUNT][STAGE_COUNT];
  87 };
  88
  89 /* This array maps from GEN2 alarm state to GEN1 alarm stage */
  90 static const unsigned int alarm_state_map[8] = {0, 1, 1, 2, 2, 3, 3, 3};
  91
  92 static int qpnp_tm_read(struct qpnp_tm_chip *chip, u16 addr, u8 *data)
  93 {
  94         unsigned int val;
  95         int ret;
  96
  97         ret = regmap_read(chip->map, chip->base + addr, &val);
  98         if (ret < 0)
  99                 return ret;
 100
 101         *data = val;
 102         return 0;
 103 }
 104
 105 static int qpnp_tm_write(struct qpnp_tm_chip *chip, u16 addr, u8 data)
 106 {
 107         return regmap_write(chip->map, chip->base + addr, data);
 108 }
 109
 110 /**
 111  * qpnp_tm_decode_temp() - return temperature in mC corresponding to the
 112  *              specified over-temperature stage
 113  * @chip:               Pointer to the qpnp_tm chip
 114  * @stage:              Over-temperature stage
 115  *
 116  * Return: temperature in mC
 117  */
 118 static long qpnp_tm_decode_temp(struct qpnp_tm_chip *chip, unsigned int stage)
 119 {
 120         if (!chip->temp_map || chip->thresh >= THRESH_COUNT || stage == 0 ||
 121             stage > STAGE_COUNT)
 122                 return 0;
 123
 124         return (*chip->temp_map)[chip->thresh][stage - 1];
 125 }
 126
 127 /**
 128  * qpnp_tm_get_temp_stage() - return over-temperature stage
 129  * @chip:               Pointer to the qpnp_tm chip
 130  *
 131  * Return: stage (GEN1) or state (GEN2) on success, or errno on failure.
 132  */
 133 static int qpnp_tm_get_temp_stage(struct qpnp_tm_chip *chip)
 134 {
 135         int ret;
 136         u8 reg = 0;
 137
 138         ret = qpnp_tm_read(chip, QPNP_TM_REG_STATUS, &reg);
 139         if (ret < 0)
 140                 return ret;
 141
 142         if (chip->subtype == QPNP_TM_SUBTYPE_GEN1)
 143                 ret = reg & STATUS_GEN1_STAGE_MASK;
 144         else
 145                 ret = (reg & STATUS_GEN2_STATE_MASK) >> STATUS_GEN2_STATE_SHIFT;
 146
 147         return ret;
 148 }
 149
 150 /*
 151  * This function updates the internal temp value based on the
 152  * current thermal stage and threshold as well as the previous stage
 153  */
 154 static int qpnp_tm_update_temp_no_adc(struct qpnp_tm_chip *chip)
 155 {
 156         unsigned int stage, stage_new, stage_old;
 157         int ret;
 158
 159         WARN_ON(!mutex_is_locked(&chip->lock));
 160
 161         ret = qpnp_tm_get_temp_stage(chip);
 162         if (ret < 0)
 163                 return ret;
 164         stage = ret;
 165
 166         if (chip->subtype == QPNP_TM_SUBTYPE_GEN1) {
 167                 stage_new = stage;
 168                 stage_old = chip->stage;
 169         } else {
 170                 stage_new = alarm_state_map[stage];
 171                 stage_old = alarm_state_map[chip->stage];
 172         }
 173
 174         if (stage_new > stage_old) {
 175                 /* increasing stage, use lower bound */
 176                 chip->temp = qpnp_tm_decode_temp(chip, stage_new)
 177                                 + TEMP_STAGE_HYSTERESIS;
 178         } else if (stage_new < stage_old) {
 179                 /* decreasing stage, use upper bound */
 180                 chip->temp = qpnp_tm_decode_temp(chip, stage_new + 1)
 181                                 - TEMP_STAGE_HYSTERESIS;
 182         }
 183
 184         chip->stage = stage;
 185
 186         return 0;
 187 }
 188
 189 static int qpnp_tm_get_temp(void *data, int *temp)
 190 {
 191         struct qpnp_tm_chip *chip = data;
 192         int ret, mili_celsius;
 193
 194         if (!temp)
 195                 return -EINVAL;
 196
 197         if (!chip->initialized) {
 198                 *temp = DEFAULT_TEMP;
 199                 return 0;
 200         }
 201
 202         if (!chip->adc) {
 203                 mutex_lock(&chip->lock);
 204                 ret = qpnp_tm_update_temp_no_adc(chip);
 205                 mutex_unlock(&chip->lock);
 206                 if (ret < 0)
 207                         return ret;
 208         } else {
 209                 ret = iio_read_channel_processed(chip->adc, &mili_celsius);
 210                 if (ret < 0)
 211                         return ret;
 212
 213                 chip->temp = mili_celsius;
 214         }
 215
 216         *temp = chip->temp;
 217
 218         return 0;
 219 }
 220
 221 static int qpnp_tm_update_critical_trip_temp(struct qpnp_tm_chip *chip,
 222                                              int temp)
 223 {
 224         long stage2_threshold_min = (*chip->temp_map)[THRESH_MIN][1];
 225         long stage2_threshold_max = (*chip->temp_map)[THRESH_MAX][1];
 226         bool disable_s2_shutdown = false;
 227         u8 reg;
 228
 229         WARN_ON(!mutex_is_locked(&chip->lock));
 230
 231         /*
 232          * Default: S2 and S3 shutdown enabled, thresholds at
 233          * lowest threshold set, monitoring at 25Hz
 234          */
 235         reg = SHUTDOWN_CTRL1_RATE_25HZ;
 236
 237         if (temp == THERMAL_TEMP_INVALID ||
 238             temp < stage2_threshold_min) {
 239                 chip->thresh = THRESH_MIN;
 240                 goto skip;
 241         }
 242
 243         if (temp <= stage2_threshold_max) {
 244                 chip->thresh = THRESH_MAX -
 245                         ((stage2_threshold_max - temp) /
 246                          TEMP_THRESH_STEP);
 247                 disable_s2_shutdown = true;
 248         } else {
 249                 chip->thresh = THRESH_MAX;
 250
 251                 if (chip->adc)
 252                         disable_s2_shutdown = true;
 253                 else
 254                         dev_warn(chip->dev,
 255                                  "No ADC is configured and critical temperature is above the maximum stage 2 threshold of 140 C! Configuring stage 2 shutdown at 140 C.\n");
 256         }
 257
 258 skip:
 259         reg |= chip->thresh;
 260         if (disable_s2_shutdown)
 261                 reg |= SHUTDOWN_CTRL1_OVERRIDE_S2;
 262
 263         return qpnp_tm_write(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, reg);
 264 }
 265
 266 static int qpnp_tm_set_trip_temp(void *data, int trip, int temp)
 267 {
 268         struct qpnp_tm_chip *chip = data;
 269         const struct thermal_trip *trip_points;
 270         int ret;
 271
 272         trip_points = of_thermal_get_trip_points(chip->tz_dev);
 273         if (!trip_points)
 274                 return -EINVAL;
 275
 276         if (trip_points[trip].type != THERMAL_TRIP_CRITICAL)
 277                 return 0;
 278
 279         mutex_lock(&chip->lock);
 280         ret = qpnp_tm_update_critical_trip_temp(chip, temp);
 281         mutex_unlock(&chip->lock);
 282
 283         return ret;
 284 }
 285
 286 static const struct thermal_zone_of_device_ops qpnp_tm_sensor_ops = {
 287         .get_temp = qpnp_tm_get_temp,
 288         .set_trip_temp = qpnp_tm_set_trip_temp,
 289 };
 290
 291 static irqreturn_t qpnp_tm_isr(int irq, void *data)
 292 {
 293         struct qpnp_tm_chip *chip = data;
 294
 295         thermal_zone_device_update(chip->tz_dev, THERMAL_EVENT_UNSPECIFIED);
 296
 297         return IRQ_HANDLED;
 298 }
 299
 300 static int qpnp_tm_get_critical_trip_temp(struct qpnp_tm_chip *chip)
 301 {
 302         int ntrips;
 303         const struct thermal_trip *trips;
 304         int i;
 305
 306         ntrips = of_thermal_get_ntrips(chip->tz_dev);
 307         if (ntrips <= 0)
 308                 return THERMAL_TEMP_INVALID;
 309
 310         trips = of_thermal_get_trip_points(chip->tz_dev);
 311         if (!trips)
 312                 return THERMAL_TEMP_INVALID;
 313
 314         for (i = 0; i < ntrips; i++) {
 315                 if (of_thermal_is_trip_valid(chip->tz_dev, i) &&
 316                     trips[i].type == THERMAL_TRIP_CRITICAL)
 317                         return trips[i].temperature;
 318         }
 319
 320         return THERMAL_TEMP_INVALID;
 321 }
 322
 323 /*
 324  * This function initializes the internal temp value based on only the
 325  * current thermal stage and threshold. Setup threshold control and
 326  * disable shutdown override.
 327  */
 328 static int qpnp_tm_init(struct qpnp_tm_chip *chip)
 329 {
 330         unsigned int stage;
 331         int ret;
 332         u8 reg = 0;
 333         int crit_temp;
 334
 335         mutex_lock(&chip->lock);
 336
 337         ret = qpnp_tm_read(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, &reg);
 338         if (ret < 0)
 339                 goto out;
 340
 341         chip->thresh = reg & SHUTDOWN_CTRL1_THRESHOLD_MASK;
 342         chip->temp = DEFAULT_TEMP;
 343
 344         ret = qpnp_tm_get_temp_stage(chip);
 345         if (ret < 0)
 346                 goto out;
 347         chip->stage = ret;
 348
 349         stage = chip->subtype == QPNP_TM_SUBTYPE_GEN1
 350                 ? chip->stage : alarm_state_map[chip->stage];
 351
 352         if (stage)
 353                 chip->temp = qpnp_tm_decode_temp(chip, stage);
 354
 355         crit_temp = qpnp_tm_get_critical_trip_temp(chip);
 356         ret = qpnp_tm_update_critical_trip_temp(chip, crit_temp);
 357         if (ret < 0)
 358                 goto out;
 359
 360         /* Enable the thermal alarm PMIC module in always-on mode. */
 361         reg = ALARM_CTRL_FORCE_ENABLE;
 362         ret = qpnp_tm_write(chip, QPNP_TM_REG_ALARM_CTRL, reg);
 363
 364         chip->initialized = true;
 365
 366 out:
 367         mutex_unlock(&chip->lock);
 368         return ret;
 369 }
 370
 371 static int qpnp_tm_probe(struct platform_device *pdev)
 372 {
 373         struct qpnp_tm_chip *chip;
 374         struct device_node *node;
 375         u8 type, subtype, dig_major;
 376         u32 res;
 377         int ret, irq;
 378
 379         node = pdev->dev.of_node;
 380
 381         chip = devm_kzalloc(&pdev->dev, sizeof(*chip), GFP_KERNEL);
 382         if (!chip)
 383                 return -ENOMEM;
 384
 385         dev_set_drvdata(&pdev->dev, chip);
 386         chip->dev = &pdev->dev;
 387
 388         mutex_init(&chip->lock);
 389
 390         chip->map = dev_get_regmap(pdev->dev.parent, NULL);
 391         if (!chip->map)
 392                 return -ENXIO;
 393
 394         ret = of_property_read_u32(node, "reg", &res);
 395         if (ret < 0)
 396                 return ret;
 397
 398         irq = platform_get_irq(pdev, 0);
 399         if (irq < 0)
 400                 return irq;
 401
 402         /* ADC based measurements are optional */
 403         chip->adc = devm_iio_channel_get(&pdev->dev, "thermal");
 404         if (IS_ERR(chip->adc)) {
 405                 ret = PTR_ERR(chip->adc);
 406                 chip->adc = NULL;
 407                 if (ret == -EPROBE_DEFER)
 408                         return ret;
 409         }
 410
 411         chip->base = res;
 412
 413         ret = qpnp_tm_read(chip, QPNP_TM_REG_TYPE, &type);
 414         if (ret < 0) {
 415                 dev_err(&pdev->dev, "could not read type\n");
 416                 return ret;
 417         }
 418
 419         ret = qpnp_tm_read(chip, QPNP_TM_REG_SUBTYPE, &subtype);
 420         if (ret < 0) {
 421                 dev_err(&pdev->dev, "could not read subtype\n");
 422                 return ret;
 423         }
 424
 425         ret = qpnp_tm_read(chip, QPNP_TM_REG_DIG_MAJOR, &dig_major);
 426         if (ret < 0) {
 427                 dev_err(&pdev->dev, "could not read dig_major\n");
 428                 return ret;
 429         }
 430
 431         if (type != QPNP_TM_TYPE || (subtype != QPNP_TM_SUBTYPE_GEN1
 432                                      && subtype != QPNP_TM_SUBTYPE_GEN2)) {
 433                 dev_err(&pdev->dev, "invalid type 0x%02x or subtype 0x%02x\n",
 434                         type, subtype);
 435                 return -ENODEV;
 436         }
 437
 438         chip->subtype = subtype;
 439         if (subtype == QPNP_TM_SUBTYPE_GEN2 && dig_major >= 1)
 440                 chip->temp_map = &temp_map_gen2_v1;
 441         else
 442                 chip->temp_map = &temp_map_gen1;
 443
 444         /*
 445          * Register the sensor before initializing the hardware to be able to
 446          * read the trip points. get_temp() returns the default temperature
 447          * before the hardware initialization is completed.
 448          */
 449         chip->tz_dev = devm_thermal_zone_of_sensor_register(
 450                 &pdev->dev, 0, chip, &qpnp_tm_sensor_ops);
 451         if (IS_ERR(chip->tz_dev)) {
 452                 dev_err(&pdev->dev, "failed to register sensor\n");
 453                 return PTR_ERR(chip->tz_dev);
 454         }
 455
 456         ret = qpnp_tm_init(chip);
 457         if (ret < 0) {
 458                 dev_err(&pdev->dev, "init failed\n");
 459                 return ret;
 460         }
 461
 462         if (devm_thermal_add_hwmon_sysfs(chip->tz_dev))
 463                 dev_warn(&pdev->dev,
 464                          "Failed to add hwmon sysfs attributes\n");
 465
 466         ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, qpnp_tm_isr,
 467                                         IRQF_ONESHOT, node->name, chip);
 468         if (ret < 0)
 469                 return ret;
 470
 471         thermal_zone_device_update(chip->tz_dev, THERMAL_EVENT_UNSPECIFIED);
 472
 473         return 0;
 474 }
 475
 476 static const struct of_device_id qpnp_tm_match_table[] = {
 477         { .compatible = "qcom,spmi-temp-alarm" },
 478         { }
 479 };
 480 MODULE_DEVICE_TABLE(of, qpnp_tm_match_table);
 481
 482 static struct platform_driver qpnp_tm_driver = {
 483         .driver = {
 484                 .name = "spmi-temp-alarm",
 485                 .of_match_table = qpnp_tm_match_table,
 486         },
 487         .probe  = qpnp_tm_probe,
 488 };
 489 module_platform_driver(qpnp_tm_driver);
 490
 491 MODULE_ALIAS("platform:spmi-temp-alarm");
 492 MODULE_DESCRIPTION("QPNP PMIC Temperature Alarm driver");
 493 MODULE_LICENSE("GPL v2");