drivers/phy/qualcomm/phy-qcom-qmp-usb.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
   4  */
   5
   6 #include <linux/clk.h>
   7 #include <linux/clk-provider.h>
   8 #include <linux/delay.h>
   9 #include <linux/err.h>
  10 #include <linux/io.h>
  11 #include <linux/iopoll.h>
  12 #include <linux/kernel.h>
  13 #include <linux/module.h>
  14 #include <linux/of.h>
  15 #include <linux/of_device.h>
  16 #include <linux/of_address.h>
  17 #include <linux/phy/phy.h>
  18 #include <linux/platform_device.h>
  19 #include <linux/regulator/consumer.h>
  20 #include <linux/reset.h>
  21 #include <linux/slab.h>
  22
  23 #include <dt-bindings/phy/phy.h>
  24
  25 #include "phy-qcom-qmp.h"
  26
  27 /* QPHY_SW_RESET bit */
  28 #define SW_RESET                                BIT(0)
  29 /* QPHY_POWER_DOWN_CONTROL */
  30 #define SW_PWRDN                                BIT(0)
  31 #define REFCLK_DRV_DSBL                         BIT(1)
  32 /* QPHY_START_CONTROL bits */
  33 #define SERDES_START                            BIT(0)
  34 #define PCS_START                               BIT(1)
  35 #define PLL_READY_GATE_EN                       BIT(3)
  36 /* QPHY_PCS_STATUS bit */
  37 #define PHYSTATUS                               BIT(6)
  38 #define PHYSTATUS_4_20                          BIT(7)
  39 /* QPHY_PCS_READY_STATUS & QPHY_COM_PCS_READY_STATUS bit */
  40 #define PCS_READY                               BIT(0)
  41
  42 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
  43 /* DP PHY soft reset */
  44 #define SW_DPPHY_RESET                          BIT(0)
  45 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */
  46 #define SW_DPPHY_RESET_MUX                      BIT(1)
  47 /* USB3 PHY soft reset */
  48 #define SW_USB3PHY_RESET                        BIT(2)
  49 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
  50 #define SW_USB3PHY_RESET_MUX                    BIT(3)
  51
  52 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
  53 #define USB3_MODE                               BIT(0) /* enables USB3 mode */
  54 #define DP_MODE                                 BIT(1) /* enables DP mode */
  55
  56 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
  57 #define ARCVR_DTCT_EN                           BIT(0)
  58 #define ALFPS_DTCT_EN                           BIT(1)
  59 #define ARCVR_DTCT_EVENT_SEL                    BIT(4)
  60
  61 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
  62 #define IRQ_CLEAR                               BIT(0)
  63
  64 /* QPHY_PCS_LFPS_RXTERM_IRQ_STATUS register bits */
  65 #define RCVR_DETECT                             BIT(0)
  66
  67 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
  68 #define CLAMP_EN                                BIT(0) /* enables i/o clamp_n */
  69
  70 #define PHY_INIT_COMPLETE_TIMEOUT               10000
  71 #define POWER_DOWN_DELAY_US_MIN                 10
  72 #define POWER_DOWN_DELAY_US_MAX                 11
  73
  74 #define MAX_PROP_NAME                           32
  75
  76 /* Define the assumed distance between lanes for underspecified device trees. */
  77 #define QMP_PHY_LEGACY_LANE_STRIDE              0x400
  78
  79 struct qmp_phy_init_tbl {
  80         unsigned int offset;
  81         unsigned int val;
  82         /*
  83          * register part of layout ?
  84          * if yes, then offset gives index in the reg-layout
  85          */
  86         bool in_layout;
  87         /*
  88          * mask of lanes for which this register is written
  89          * for cases when second lane needs different values
  90          */
  91         u8 lane_mask;
  92 };
  93
  94 #define QMP_PHY_INIT_CFG(o, v)          \
  95         {                               \
  96                 .offset = o,            \
  97                 .val = v,               \
  98                 .lane_mask = 0xff,      \
  99         }
 100
 101 #define QMP_PHY_INIT_CFG_L(o, v)        \
 102         {                               \
 103                 .offset = o,            \
 104                 .val = v,               \
 105                 .in_layout = true,      \
 106                 .lane_mask = 0xff,      \
 107         }
 108
 109 #define QMP_PHY_INIT_CFG_LANE(o, v, l)  \
 110         {                               \
 111                 .offset = o,            \
 112                 .val = v,               \
 113                 .lane_mask = l,         \
 114         }
 115
 116 /* set of registers with offsets different per-PHY */
 117 enum qphy_reg_layout {
 118         /* Common block control registers */
 119         QPHY_COM_SW_RESET,
 120         QPHY_COM_POWER_DOWN_CONTROL,
 121         QPHY_COM_START_CONTROL,
 122         QPHY_COM_PCS_READY_STATUS,
 123         /* PCS registers */
 124         QPHY_SW_RESET,
 125         QPHY_START_CTRL,
 126         QPHY_PCS_READY_STATUS,
 127         QPHY_PCS_STATUS,
 128         QPHY_PCS_AUTONOMOUS_MODE_CTRL,
 129         QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
 130         QPHY_PCS_LFPS_RXTERM_IRQ_STATUS,
 131         QPHY_PCS_POWER_DOWN_CONTROL,
 132         /* PCS_MISC registers */
 133         QPHY_PCS_MISC_TYPEC_CTRL,
 134         /* Keep last to ensure regs_layout arrays are properly initialized */
 135         QPHY_LAYOUT_SIZE
 136 };
 137
 138 static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 139         [QPHY_SW_RESET]                 = 0x00,
 140         [QPHY_START_CTRL]               = 0x08,
 141         [QPHY_PCS_STATUS]               = 0x17c,
 142         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4,
 143         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0d8,
 144         [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x178,
 145 };
 146
 147 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 148         [QPHY_SW_RESET]                 = 0x00,
 149         [QPHY_START_CTRL]               = 0x08,
 150         [QPHY_PCS_STATUS]               = 0x174,
 151         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8,
 152         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR]  = 0x0dc,
 153         [QPHY_PCS_LFPS_RXTERM_IRQ_STATUS] = 0x170,
 154 };
 155
 156 static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 157         [QPHY_SW_RESET]                 = 0x00,
 158         [QPHY_START_CTRL]               = 0x44,
 159         [QPHY_PCS_STATUS]               = 0x14,
 160         [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x40,
 161
 162         /* In PCS_USB */
 163         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x008,
 164         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x014,
 165 };
 166
 167 static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
 168         [QPHY_SW_RESET]                 = 0x00,
 169         [QPHY_PCS_POWER_DOWN_CONTROL]   = 0x04,
 170         [QPHY_START_CTRL]               = 0x08,
 171         [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8,
 172         [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc,
 173         [QPHY_PCS_STATUS]               = 0x174,
 174         [QPHY_PCS_MISC_TYPEC_CTRL]      = 0x00,
 175 };
 176
 177 static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
 178         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
 179         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 180         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 181         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 182         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 183         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 184         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 185         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 186         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 187         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
 188         /* PLL and Loop filter settings */
 189         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 190         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 191         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 192         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 193         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 194         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 195         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 196         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 197         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
 198         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
 199         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 200         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 201         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 202         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 203         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 204         /* SSC settings */
 205         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 206         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 207         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 208         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
 209         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 210         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
 211         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
 212 };
 213
 214 static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
 215         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
 216         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
 217         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
 218         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
 219         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 220         QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 221         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
 222         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 223         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
 224 };
 225
 226 static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
 227         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 228         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
 229         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 230         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 231         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 232         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 233         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
 234         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 235         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 236         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 237         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 238         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 239         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 240         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 241         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 242         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 243         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 244         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 245         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 246         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 247         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
 248         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
 249         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
 250 };
 251
 252 static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
 253         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
 254         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 255         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
 256         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
 257         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
 258         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
 259         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
 260         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
 261         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
 262         /* PLL and Loop filter settings */
 263         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
 264         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
 265         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
 266         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
 267         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
 268         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
 269         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
 270         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
 271         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
 272         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
 273         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
 274         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
 275         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
 276         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
 277         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
 278         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
 279         /* SSC settings */
 280         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
 281         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
 282         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
 283         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
 284         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
 285         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
 286         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
 287 };
 288
 289 static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
 290         QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
 291         QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
 292         QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
 293 };
 294
 295 static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
 296         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 297         QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
 298         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
 299         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
 300         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
 301         QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 302         QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 303         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
 304         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
 305         QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 306 };
 307
 308 static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
 309         /* FLL settings */
 310         QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL2, 0x03),
 311         QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL1, 0x02),
 312         QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_L, 0x09),
 313         QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_H_TOL, 0x42),
 314         QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_MAN_CODE, 0x85),
 315
 316         /* Lock Det settings */
 317         QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 318         QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 319         QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG3, 0x47),
 320         QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG2, 0x08),
 321 };
 322
 323 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = {
 324         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 325         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
 326         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
 327         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 328         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 329         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
 330         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16),
 331         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 332         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
 333         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 334         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 335         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 336         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 337         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 338         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 339         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 340         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 341         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 342         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 343         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 344         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 345         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 346         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
 347         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
 348         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
 349         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 350         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
 351         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 352         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
 353         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 354         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
 355         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 356         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
 357         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 358         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
 359         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
 360 };
 361
 362 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = {
 363         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 364         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 365         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
 366         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09),
 367         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
 368 };
 369
 370 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = {
 371         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 372         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 373         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 374         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
 375         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 376         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 377         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 378         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
 379         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 380 };
 381
 382 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = {
 383         /* FLL settings */
 384         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 385         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 386         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 387         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 388         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 389
 390         /* Lock Det settings */
 391         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 392         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 393         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 394         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 395
 396         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
 397         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
 398         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
 399         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
 400         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
 401         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
 402         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
 403         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 404         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
 405         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
 406         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
 407         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
 408         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
 409         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
 410         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
 411         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
 412         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
 413         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
 414         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
 415
 416         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
 417         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 418         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 419         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 420         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 421         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 422         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 423         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 424         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 425         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 426         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 427 };
 428
 429 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
 430         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 431         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
 432         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
 433         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 434         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
 435         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
 436         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 437         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 438         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
 439         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 440         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 441         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 442         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 443         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 444         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 445         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 446         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 447         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 448         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 449         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 450         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 451         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 452         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
 453         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
 454         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
 455         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 456         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
 457         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 458         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
 459         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 460         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
 461         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 462         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
 463         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 464         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
 465         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
 466 };
 467
 468 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
 469         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 470         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 471         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
 472         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
 473         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
 474 };
 475
 476 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
 477         QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
 478         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
 479         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 480         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
 481         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 482         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
 483         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 484         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 485         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
 486         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
 487         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 488 };
 489
 490 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
 491         /* FLL settings */
 492         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 493         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 494         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 495         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 496         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 497
 498         /* Lock Det settings */
 499         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 500         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 501         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 502         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 503
 504         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
 505         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
 506         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
 507         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
 508         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
 509         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
 510         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
 511         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 512         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
 513         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
 514         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
 515         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
 516         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
 517         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
 518         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
 519         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
 520         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
 521         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
 522         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
 523
 524         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
 525         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 526         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 527         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 528         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 529         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 530         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 531         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 532         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 533         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 534         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 535
 536         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
 537         QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
 538 };
 539
 540 static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
 541         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
 542         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
 543         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
 544         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
 545         QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
 546         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
 547         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
 548         QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
 549         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
 550         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
 551         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
 552         QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
 553         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
 554         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
 555         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
 556         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
 557         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
 558         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
 559         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
 560         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
 561         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
 562         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
 563         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
 564         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
 565         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
 566         QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
 567         QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
 568         QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
 569         QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
 570         QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
 571         QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
 572         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
 573         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
 574         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
 575         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
 576         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
 577         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
 578         QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
 579 };
 580
 581 static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
 582         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
 583         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
 584         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
 585         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
 586 };
 587
 588 static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
 589         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
 590         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 591         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
 592         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
 593         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
 594         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 595         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
 596         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
 597         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
 598         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
 599         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
 600         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
 601         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
 602         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
 603         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
 604         QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
 605         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
 606 };
 607
 608 static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
 609         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
 610         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
 611         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
 612         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
 613         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
 614         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
 615         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
 616         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
 617         QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
 618         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
 619         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
 620         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
 621         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
 622         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
 623         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
 624         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
 625         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
 626         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
 627         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
 628         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
 629         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
 630         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
 631         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
 632         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
 633         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
 634         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
 635         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
 636         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
 637         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
 638         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
 639         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 640         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 641         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
 642         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
 643         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
 644         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
 645         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
 646         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
 647 };
 648
 649 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = {
 650         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
 651         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
 652         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
 653         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
 654         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
 655         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
 656         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
 657         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
 658         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
 659         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
 660         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
 661         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
 662         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
 663         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
 664         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
 665         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
 666         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
 667         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
 668         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
 669         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
 670         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
 671         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
 672         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
 673         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
 674         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
 675         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
 676         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
 677         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
 678         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
 679         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
 680         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
 681         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
 682         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
 683         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
 684         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
 685         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
 686         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
 687         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
 688         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
 689         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
 690 };
 691
 692 static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = {
 693         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00),
 694         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00),
 695         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
 696         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
 697         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
 698 };
 699
 700 static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = {
 701         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
 702         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 703         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 704         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 705         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 706         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
 707         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
 708         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
 709         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
 710         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
 711         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
 712         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e),
 713         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 714         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 715         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 716         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 717         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 718         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 719         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
 720         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 721         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf),
 722         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf),
 723         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f),
 724         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
 725         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94),
 726         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
 727         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
 728         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
 729         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
 730         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
 731         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
 732         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 733         QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
 734         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
 735         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
 736         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
 737 };
 738
 739 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = {
 740         /* Lock Det settings */
 741         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
 742         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
 743         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
 744
 745         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
 746         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
 747         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
 748         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
 749         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
 750         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
 751         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
 752         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
 753 };
 754
 755 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = {
 756         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
 757         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
 758 };
 759
 760 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
 761         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
 762         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
 763         QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
 764         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
 765         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
 766         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
 767         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
 768         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
 769         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
 770         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
 771         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
 772         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
 773         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
 774         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
 775         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
 776         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
 777         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
 778         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
 779         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
 780         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
 781         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
 782         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
 783         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
 784         QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
 785         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
 786         QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
 787         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
 788         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
 789         QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
 790         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
 791         QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
 792         QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
 793         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
 794         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
 795         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
 796         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
 797         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
 798         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
 799         QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
 800         QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
 801 };
 802
 803 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
 804         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
 805         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
 806         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
 807         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
 808 };
 809
 810 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
 811         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
 812         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
 813         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
 814         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
 815         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
 816         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
 817         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
 818         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
 819         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
 820         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
 821         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
 822         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
 823         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
 824         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
 825         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
 826         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 827         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 828         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 829         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 830         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
 831         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
 832         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
 833         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
 834         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 835         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 836         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 837         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
 838         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
 839         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 840         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
 841         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 842         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 843         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 844         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
 845         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
 846         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
 847 };
 848
 849 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
 850         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
 851         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
 852         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
 853         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
 854         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 855         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 856         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
 857         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
 858         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
 859         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
 860         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
 861         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
 862         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
 863         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
 864 };
 865
 866 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_usb_tbl[] = {
 867         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
 868         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
 869 };
 870
 871 static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = {
 872         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60),
 873         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60),
 874         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
 875         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
 876         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
 877         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
 878         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1),
 879         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2),
 880 };
 881
 882 static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = {
 883         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
 884         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 885         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 886         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 887         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 888         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
 889         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
 890         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
 891         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
 892         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
 893         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
 894         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
 895         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 896         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 897         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 898         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 899         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 900         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
 901         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
 902         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 903         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1),
 904         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2),
 905         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1),
 906         QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2),
 907         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f),
 908         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
 909         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97),
 910         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
 911         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
 912         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
 913         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
 914         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
 915         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
 916         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 917         QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
 918         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
 919         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
 920         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10),
 921 };
 922
 923 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = {
 924         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
 925         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
 926         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
 927         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
 928         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
 929         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
 930         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
 931         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
 932         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
 933         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
 934         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
 935         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
 936 };
 937
 938 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = {
 939         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
 940         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
 941 };
 942
 943 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
 944         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
 945         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
 946         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
 947         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
 948         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
 949         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
 950 };
 951
 952 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
 953         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
 954         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
 955         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
 956         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
 957         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
 958         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
 959         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
 960         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
 961         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
 962         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
 963         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
 964         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
 965         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
 966         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
 967         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
 968         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
 969         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
 970         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
 971         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
 972         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
 973         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
 974         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
 975         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
 976         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
 977         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
 978         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
 979         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
 980         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
 981         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
 982         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
 983         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
 984         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
 985         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
 986         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
 987         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
 988         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
 989 };
 990
 991 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
 992         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
 993         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
 994         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
 995         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
 996         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
 997         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
 998         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
 999         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1000         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1001         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1002         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1003         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1004         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1005         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1006 };
1007
1008 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_usb_tbl[] = {
1009         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1010         QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1011 };
1012
1013 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
1014         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
1015         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
1016         QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
1017         QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
1018         QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
1019 };
1020
1021 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
1022         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
1023         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
1024         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
1025         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
1026         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
1027         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
1028         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
1029         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
1030         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
1031         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
1032         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
1033         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
1034         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
1035         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
1036         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
1037         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1038         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1039         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1040         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1041         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
1042         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
1043         QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
1044         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1045         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1046         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1047         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
1048         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1049         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1050         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
1051         QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1052         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1053         QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1054         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1055         QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
1056         QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
1057         QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
1058 };
1059
1060 static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
1061         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
1062         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
1063         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
1064         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1065         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
1066         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
1067         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
1068 };
1069
1070 static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
1071         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
1072         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
1073         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
1074         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
1075         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
1076         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
1077         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
1078         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
1079         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
1080         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
1081         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
1082         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1083         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1084         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
1085         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
1086         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1087         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1088         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1089         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
1090         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
1091         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1092         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1093         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1094         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1095         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1096         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
1097         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1098         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1099         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
1100         QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1101         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
1102 };
1103
1104 static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = {
1105         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00),
1106         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00),
1107         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16),
1108         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
1109         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35),
1110         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
1111         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f),
1112         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f),
1113         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12),
1114         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
1115 };
1116
1117 static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = {
1118         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
1119         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
1120         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1121         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
1122         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1123         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1124         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
1125         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1126         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1127         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
1128         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
1129         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
1130         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1131         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1132         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
1133         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1134         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
1135         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
1136         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1137         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
1138         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1139         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb),
1140         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b),
1141         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb),
1142         QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1),
1143         QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2),
1144         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
1145         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
1146         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
1147         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2),
1148         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13),
1149         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
1150         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04),
1151         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1152         QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0),
1153         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
1154         QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1155         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10),
1156 };
1157
1158 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = {
1159         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1160         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1161         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1162         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1163         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1164         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1165         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1166         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1167         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1168         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1169         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1170         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1171         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1172         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1173 };
1174
1175 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] = {
1176         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40),
1177         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00),
1178         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1179         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1180 };
1181
1182 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
1183         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
1184         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
1185         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
1186         QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1187         QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
1188         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
1189         QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
1190 };
1191
1192 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
1193         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
1194         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
1195         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
1196         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
1197         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
1198         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
1199         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
1200         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
1201         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
1202         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
1203         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
1204         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1205         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1206         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
1207         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
1208         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1209         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1210         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1211         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
1212         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
1213         QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1214         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1215         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1216         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1217         QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1218         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
1219         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1220         QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1221         QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
1222         QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1223         QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
1224 };
1225
1226 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
1227         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1228         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
1229         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
1230         QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
1231         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1232         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1233         QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
1234         QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
1235         QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
1236         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1237         QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1238         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
1239         QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
1240         QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
1241 };
1242
1243 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_usb_tbl[] = {
1244         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1245         QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1246 };
1247
1248 static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
1249         QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
1250         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
1251         QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
1252         QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
1253         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
1254         QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
1255         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
1256         QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
1257         QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
1258         QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
1259         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
1260         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
1261         QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
1262         QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
1263         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
1264         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
1265         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
1266         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
1267         QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
1268         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
1269         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
1270         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
1271         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
1272         QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
1273         QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
1274         QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
1275         QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
1276         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
1277         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
1278         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
1279         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
1280         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
1281         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
1282         QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
1283         QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
1284         QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
1285         QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
1286         QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
1287 };
1288
1289 static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
1290         QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
1291         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
1292         QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
1293         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
1294         QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
1295 };
1296
1297 static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
1298         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
1299         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00),
1300         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
1301         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
1302         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
1303         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
1304         QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
1305         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
1306         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
1307         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
1308         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
1309         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1310         QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
1311         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
1312         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
1313         QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
1314         QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
1315 };
1316
1317 static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
1318         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
1319         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
1320         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
1321         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1322         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1323         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1324         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1325         QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
1326         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1327         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1328         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1329         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1330         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1331         QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1332         QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1333         QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1334         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1335         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1336         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1337         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1338         QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
1339 };
1340
1341 struct qmp_phy;
1342
1343 /* struct qmp_phy_cfg - per-PHY initialization config */
1344 struct qmp_phy_cfg {
1345         /* phy-type - PCIE/UFS/USB */
1346         unsigned int type;
1347         /* number of lanes provided by phy */
1348         int nlanes;
1349
1350         /* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1351         const struct qmp_phy_init_tbl *serdes_tbl;
1352         int serdes_tbl_num;
1353         const struct qmp_phy_init_tbl *tx_tbl;
1354         int tx_tbl_num;
1355         const struct qmp_phy_init_tbl *rx_tbl;
1356         int rx_tbl_num;
1357         const struct qmp_phy_init_tbl *pcs_tbl;
1358         int pcs_tbl_num;
1359         const struct qmp_phy_init_tbl *pcs_usb_tbl;
1360         int pcs_usb_tbl_num;
1361
1362         /* clock ids to be requested */
1363         const char * const *clk_list;
1364         int num_clks;
1365         /* resets to be requested */
1366         const char * const *reset_list;
1367         int num_resets;
1368         /* regulators to be requested */
1369         const char * const *vreg_list;
1370         int num_vregs;
1371
1372         /* array of registers with different offsets */
1373         const unsigned int *regs;
1374
1375         unsigned int start_ctrl;
1376         unsigned int pwrdn_ctrl;
1377         /* bit offset of PHYSTATUS in QPHY_PCS_STATUS register */
1378         unsigned int phy_status;
1379
1380         /* true, if PHY needs delay after POWER_DOWN */
1381         bool has_pwrdn_delay;
1382         /* power_down delay in usec */
1383         int pwrdn_delay_min;
1384         int pwrdn_delay_max;
1385
1386         /* true, if PHY has a separate DP_COM control block */
1387         bool has_phy_dp_com_ctrl;
1388         /* true, if PHY has secondary tx/rx lanes to be configured */
1389         bool is_dual_lane_phy;
1390
1391         /* Offset from PCS to PCS_USB region */
1392         unsigned int pcs_usb_offset;
1393 };
1394
1395 /**
1396  * struct qmp_phy - per-lane phy descriptor
1397  *
1398  * @phy: generic phy
1399  * @cfg: phy specific configuration
1400  * @serdes: iomapped memory space for phy's serdes (i.e. PLL)
1401  * @tx: iomapped memory space for lane's tx
1402  * @rx: iomapped memory space for lane's rx
1403  * @pcs: iomapped memory space for lane's pcs
1404  * @tx2: iomapped memory space for second lane's tx (in dual lane PHYs)
1405  * @rx2: iomapped memory space for second lane's rx (in dual lane PHYs)
1406  * @pcs_misc: iomapped memory space for lane's pcs_misc
1407  * @pcs_usb: iomapped memory space for lane's pcs_usb
1408  * @pipe_clk: pipe clock
1409  * @index: lane index
1410  * @qmp: QMP phy to which this lane belongs
1411  * @mode: current PHY mode
1412  */
1413 struct qmp_phy {
1414         struct phy *phy;
1415         const struct qmp_phy_cfg *cfg;
1416         void __iomem *serdes;
1417         void __iomem *tx;
1418         void __iomem *rx;
1419         void __iomem *pcs;
1420         void __iomem *tx2;
1421         void __iomem *rx2;
1422         void __iomem *pcs_misc;
1423         void __iomem *pcs_usb;
1424         struct clk *pipe_clk;
1425         unsigned int index;
1426         struct qcom_qmp *qmp;
1427         enum phy_mode mode;
1428 };
1429
1430 /**
1431  * struct qcom_qmp - structure holding QMP phy block attributes
1432  *
1433  * @dev: device
1434  * @dp_com: iomapped memory space for phy's dp_com control block
1435  *
1436  * @clks: array of clocks required by phy
1437  * @resets: array of resets required by phy
1438  * @vregs: regulator supplies bulk data
1439  *
1440  * @phys: array of per-lane phy descriptors
1441  */
1442 struct qcom_qmp {
1443         struct device *dev;
1444         void __iomem *dp_com;
1445
1446         struct clk_bulk_data *clks;
1447         struct reset_control_bulk_data *resets;
1448         struct regulator_bulk_data *vregs;
1449
1450         struct qmp_phy **phys;
1451 };
1452
1453 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
1454 {
1455         u32 reg;
1456
1457         reg = readl(base + offset);
1458         reg |= val;
1459         writel(reg, base + offset);
1460
1461         /* ensure that above write is through */
1462         readl(base + offset);
1463 }
1464
1465 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
1466 {
1467         u32 reg;
1468
1469         reg = readl(base + offset);
1470         reg &= ~val;
1471         writel(reg, base + offset);
1472
1473         /* ensure that above write is through */
1474         readl(base + offset);
1475 }
1476
1477 /* list of clocks required by phy */
1478 static const char * const msm8996_phy_clk_l[] = {
1479         "aux", "cfg_ahb", "ref",
1480 };
1481
1482 static const char * const qmp_v3_phy_clk_l[] = {
1483         "aux", "cfg_ahb", "ref", "com_aux",
1484 };
1485
1486 static const char * const qmp_v4_phy_clk_l[] = {
1487         "aux", "ref_clk_src", "ref", "com_aux",
1488 };
1489
1490 /* the primary usb3 phy on sm8250 doesn't have a ref clock */
1491 static const char * const qmp_v4_sm8250_usbphy_clk_l[] = {
1492         "aux", "ref_clk_src", "com_aux"
1493 };
1494
1495 /* usb3 phy on sdx55 doesn't have com_aux clock */
1496 static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
1497         "aux", "cfg_ahb", "ref"
1498 };
1499
1500 static const char * const qcm2290_usb3phy_clk_l[] = {
1501         "cfg_ahb", "ref", "com_aux",
1502 };
1503
1504 /* list of resets */
1505 static const char * const msm8996_usb3phy_reset_l[] = {
1506         "phy", "common",
1507 };
1508
1509 static const char * const sc7180_usb3phy_reset_l[] = {
1510         "phy",
1511 };
1512
1513 static const char * const qcm2290_usb3phy_reset_l[] = {
1514         "phy_phy", "phy",
1515 };
1516
1517 /* list of regulators */
1518 static const char * const qmp_phy_vreg_l[] = {
1519         "vdda-phy", "vdda-pll",
1520 };
1521
1522 static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
1523         .type                   = PHY_TYPE_USB3,
1524         .nlanes                 = 1,
1525
1526         .serdes_tbl             = ipq8074_usb3_serdes_tbl,
1527         .serdes_tbl_num         = ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
1528         .tx_tbl                 = msm8996_usb3_tx_tbl,
1529         .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1530         .rx_tbl                 = ipq8074_usb3_rx_tbl,
1531         .rx_tbl_num             = ARRAY_SIZE(ipq8074_usb3_rx_tbl),
1532         .pcs_tbl                = ipq8074_usb3_pcs_tbl,
1533         .pcs_tbl_num            = ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
1534         .clk_list               = msm8996_phy_clk_l,
1535         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
1536         .reset_list             = msm8996_usb3phy_reset_l,
1537         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1538         .vreg_list              = qmp_phy_vreg_l,
1539         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1540         .regs                   = usb3phy_regs_layout,
1541
1542         .start_ctrl             = SERDES_START | PCS_START,
1543         .pwrdn_ctrl             = SW_PWRDN,
1544         .phy_status             = PHYSTATUS,
1545 };
1546
1547 static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
1548         .type                   = PHY_TYPE_USB3,
1549         .nlanes                 = 1,
1550
1551         .serdes_tbl             = msm8996_usb3_serdes_tbl,
1552         .serdes_tbl_num         = ARRAY_SIZE(msm8996_usb3_serdes_tbl),
1553         .tx_tbl                 = msm8996_usb3_tx_tbl,
1554         .tx_tbl_num             = ARRAY_SIZE(msm8996_usb3_tx_tbl),
1555         .rx_tbl                 = msm8996_usb3_rx_tbl,
1556         .rx_tbl_num             = ARRAY_SIZE(msm8996_usb3_rx_tbl),
1557         .pcs_tbl                = msm8996_usb3_pcs_tbl,
1558         .pcs_tbl_num            = ARRAY_SIZE(msm8996_usb3_pcs_tbl),
1559         .clk_list               = msm8996_phy_clk_l,
1560         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
1561         .reset_list             = msm8996_usb3phy_reset_l,
1562         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1563         .vreg_list              = qmp_phy_vreg_l,
1564         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1565         .regs                   = usb3phy_regs_layout,
1566
1567         .start_ctrl             = SERDES_START | PCS_START,
1568         .pwrdn_ctrl             = SW_PWRDN,
1569         .phy_status             = PHYSTATUS,
1570 };
1571
1572 static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
1573         .type                   = PHY_TYPE_USB3,
1574         .nlanes                 = 1,
1575
1576         .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
1577         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1578         .tx_tbl                 = qmp_v3_usb3_tx_tbl,
1579         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1580         .rx_tbl                 = qmp_v3_usb3_rx_tbl,
1581         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
1582         .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
1583         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
1584         .clk_list               = qmp_v3_phy_clk_l,
1585         .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
1586         .reset_list             = msm8996_usb3phy_reset_l,
1587         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1588         .vreg_list              = qmp_phy_vreg_l,
1589         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1590         .regs                   = qmp_v3_usb3phy_regs_layout,
1591
1592         .start_ctrl             = SERDES_START | PCS_START,
1593         .pwrdn_ctrl             = SW_PWRDN,
1594         .phy_status             = PHYSTATUS,
1595
1596         .has_pwrdn_delay        = true,
1597         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
1598         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
1599
1600         .has_phy_dp_com_ctrl    = true,
1601         .is_dual_lane_phy       = true,
1602 };
1603
1604 static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
1605         .type                   = PHY_TYPE_USB3,
1606         .nlanes                 = 1,
1607
1608         .serdes_tbl             = qmp_v3_usb3_serdes_tbl,
1609         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
1610         .tx_tbl                 = qmp_v3_usb3_tx_tbl,
1611         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
1612         .rx_tbl                 = qmp_v3_usb3_rx_tbl,
1613         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
1614         .pcs_tbl                = qmp_v3_usb3_pcs_tbl,
1615         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
1616         .clk_list               = qmp_v3_phy_clk_l,
1617         .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
1618         .reset_list             = sc7180_usb3phy_reset_l,
1619         .num_resets             = ARRAY_SIZE(sc7180_usb3phy_reset_l),
1620         .vreg_list              = qmp_phy_vreg_l,
1621         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1622         .regs                   = qmp_v3_usb3phy_regs_layout,
1623
1624         .start_ctrl             = SERDES_START | PCS_START,
1625         .pwrdn_ctrl             = SW_PWRDN,
1626         .phy_status             = PHYSTATUS,
1627
1628         .has_pwrdn_delay        = true,
1629         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
1630         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
1631
1632         .has_phy_dp_com_ctrl    = true,
1633         .is_dual_lane_phy       = true,
1634 };
1635
1636 static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
1637         .type                   = PHY_TYPE_USB3,
1638         .nlanes                 = 1,
1639
1640         .serdes_tbl             = qmp_v3_usb3_uniphy_serdes_tbl,
1641         .serdes_tbl_num         = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
1642         .tx_tbl                 = qmp_v3_usb3_uniphy_tx_tbl,
1643         .tx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
1644         .rx_tbl                 = qmp_v3_usb3_uniphy_rx_tbl,
1645         .rx_tbl_num             = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
1646         .pcs_tbl                = qmp_v3_usb3_uniphy_pcs_tbl,
1647         .pcs_tbl_num            = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
1648         .clk_list               = qmp_v3_phy_clk_l,
1649         .num_clks               = ARRAY_SIZE(qmp_v3_phy_clk_l),
1650         .reset_list             = msm8996_usb3phy_reset_l,
1651         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1652         .vreg_list              = qmp_phy_vreg_l,
1653         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1654         .regs                   = qmp_v3_usb3phy_regs_layout,
1655
1656         .start_ctrl             = SERDES_START | PCS_START,
1657         .pwrdn_ctrl             = SW_PWRDN,
1658         .phy_status             = PHYSTATUS,
1659
1660         .has_pwrdn_delay        = true,
1661         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
1662         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
1663 };
1664
1665 static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
1666         .type                   = PHY_TYPE_USB3,
1667         .nlanes                 = 1,
1668
1669         .serdes_tbl             = msm8998_usb3_serdes_tbl,
1670         .serdes_tbl_num         = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
1671         .tx_tbl                 = msm8998_usb3_tx_tbl,
1672         .tx_tbl_num             = ARRAY_SIZE(msm8998_usb3_tx_tbl),
1673         .rx_tbl                 = msm8998_usb3_rx_tbl,
1674         .rx_tbl_num             = ARRAY_SIZE(msm8998_usb3_rx_tbl),
1675         .pcs_tbl                = msm8998_usb3_pcs_tbl,
1676         .pcs_tbl_num            = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
1677         .clk_list               = msm8996_phy_clk_l,
1678         .num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
1679         .reset_list             = msm8996_usb3phy_reset_l,
1680         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1681         .vreg_list              = qmp_phy_vreg_l,
1682         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1683         .regs                   = qmp_v3_usb3phy_regs_layout,
1684
1685         .start_ctrl             = SERDES_START | PCS_START,
1686         .pwrdn_ctrl             = SW_PWRDN,
1687         .phy_status             = PHYSTATUS,
1688
1689         .is_dual_lane_phy       = true,
1690 };
1691
1692 static const struct qmp_phy_cfg sm8150_usb3phy_cfg = {
1693         .type                   = PHY_TYPE_USB3,
1694         .nlanes                 = 1,
1695
1696         .serdes_tbl             = sm8150_usb3_serdes_tbl,
1697         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
1698         .tx_tbl                 = sm8150_usb3_tx_tbl,
1699         .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_tx_tbl),
1700         .rx_tbl                 = sm8150_usb3_rx_tbl,
1701         .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_rx_tbl),
1702         .pcs_tbl                = sm8150_usb3_pcs_tbl,
1703         .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_pcs_tbl),
1704         .pcs_usb_tbl            = sm8150_usb3_pcs_usb_tbl,
1705         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl),
1706         .clk_list               = qmp_v4_phy_clk_l,
1707         .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
1708         .reset_list             = msm8996_usb3phy_reset_l,
1709         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1710         .vreg_list              = qmp_phy_vreg_l,
1711         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1712         .regs                   = qmp_v4_usb3phy_regs_layout,
1713         .pcs_usb_offset         = 0x300,
1714
1715         .start_ctrl             = SERDES_START | PCS_START,
1716         .pwrdn_ctrl             = SW_PWRDN,
1717         .phy_status             = PHYSTATUS,
1718
1719
1720         .has_pwrdn_delay        = true,
1721         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
1722         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
1723
1724         .has_phy_dp_com_ctrl    = true,
1725         .is_dual_lane_phy       = true,
1726 };
1727
1728 static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
1729         .type                   = PHY_TYPE_USB3,
1730         .nlanes                 = 1,
1731
1732         .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
1733         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1734         .tx_tbl                 = sm8150_usb3_uniphy_tx_tbl,
1735         .tx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
1736         .rx_tbl                 = sm8150_usb3_uniphy_rx_tbl,
1737         .rx_tbl_num             = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
1738         .pcs_tbl                = sm8150_usb3_uniphy_pcs_tbl,
1739         .pcs_tbl_num            = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
1740         .pcs_usb_tbl            = sm8150_usb3_uniphy_pcs_usb_tbl,
1741         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_usb_tbl),
1742         .clk_list               = qmp_v4_phy_clk_l,
1743         .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
1744         .reset_list             = msm8996_usb3phy_reset_l,
1745         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1746         .vreg_list              = qmp_phy_vreg_l,
1747         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1748         .regs                   = qmp_v4_usb3phy_regs_layout,
1749         .pcs_usb_offset         = 0x600,
1750
1751         .start_ctrl             = SERDES_START | PCS_START,
1752         .pwrdn_ctrl             = SW_PWRDN,
1753         .phy_status             = PHYSTATUS,
1754
1755         .has_pwrdn_delay        = true,
1756         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
1757         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
1758 };
1759
1760 static const struct qmp_phy_cfg sm8250_usb3phy_cfg = {
1761         .type                   = PHY_TYPE_USB3,
1762         .nlanes                 = 1,
1763
1764         .serdes_tbl             = sm8150_usb3_serdes_tbl,
1765         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
1766         .tx_tbl                 = sm8250_usb3_tx_tbl,
1767         .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_tx_tbl),
1768         .rx_tbl                 = sm8250_usb3_rx_tbl,
1769         .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_rx_tbl),
1770         .pcs_tbl                = sm8250_usb3_pcs_tbl,
1771         .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_pcs_tbl),
1772         .pcs_usb_tbl            = sm8250_usb3_pcs_usb_tbl,
1773         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl),
1774         .clk_list               = qmp_v4_sm8250_usbphy_clk_l,
1775         .num_clks               = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
1776         .reset_list             = msm8996_usb3phy_reset_l,
1777         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1778         .vreg_list              = qmp_phy_vreg_l,
1779         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1780         .regs                   = qmp_v4_usb3phy_regs_layout,
1781         .pcs_usb_offset         = 0x300,
1782
1783         .start_ctrl             = SERDES_START | PCS_START,
1784         .pwrdn_ctrl             = SW_PWRDN,
1785         .phy_status             = PHYSTATUS,
1786
1787         .has_pwrdn_delay        = true,
1788         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
1789         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
1790
1791         .has_phy_dp_com_ctrl    = true,
1792         .is_dual_lane_phy       = true,
1793 };
1794
1795 static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
1796         .type                   = PHY_TYPE_USB3,
1797         .nlanes                 = 1,
1798
1799         .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
1800         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1801         .tx_tbl                 = sm8250_usb3_uniphy_tx_tbl,
1802         .tx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
1803         .rx_tbl                 = sm8250_usb3_uniphy_rx_tbl,
1804         .rx_tbl_num             = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
1805         .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
1806         .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
1807         .pcs_usb_tbl            = sm8250_usb3_uniphy_pcs_usb_tbl,
1808         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl),
1809         .clk_list               = qmp_v4_phy_clk_l,
1810         .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
1811         .reset_list             = msm8996_usb3phy_reset_l,
1812         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1813         .vreg_list              = qmp_phy_vreg_l,
1814         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1815         .regs                   = qmp_v4_usb3phy_regs_layout,
1816         .pcs_usb_offset         = 0x600,
1817
1818         .start_ctrl             = SERDES_START | PCS_START,
1819         .pwrdn_ctrl             = SW_PWRDN,
1820         .phy_status             = PHYSTATUS,
1821
1822         .has_pwrdn_delay        = true,
1823         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
1824         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
1825 };
1826
1827 static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
1828         .type                   = PHY_TYPE_USB3,
1829         .nlanes                 = 1,
1830
1831         .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
1832         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1833         .tx_tbl                 = sdx55_usb3_uniphy_tx_tbl,
1834         .tx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
1835         .rx_tbl                 = sdx55_usb3_uniphy_rx_tbl,
1836         .rx_tbl_num             = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
1837         .pcs_tbl                = sm8250_usb3_uniphy_pcs_tbl,
1838         .pcs_tbl_num            = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
1839         .pcs_usb_tbl            = sm8250_usb3_uniphy_pcs_usb_tbl,
1840         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl),
1841         .clk_list               = qmp_v4_sdx55_usbphy_clk_l,
1842         .num_clks               = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
1843         .reset_list             = msm8996_usb3phy_reset_l,
1844         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1845         .vreg_list              = qmp_phy_vreg_l,
1846         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1847         .regs                   = qmp_v4_usb3phy_regs_layout,
1848         .pcs_usb_offset         = 0x600,
1849
1850         .start_ctrl             = SERDES_START | PCS_START,
1851         .pwrdn_ctrl             = SW_PWRDN,
1852         .phy_status             = PHYSTATUS,
1853
1854         .has_pwrdn_delay        = true,
1855         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
1856         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
1857 };
1858
1859 static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
1860         .type                   = PHY_TYPE_USB3,
1861         .nlanes                 = 1,
1862
1863         .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
1864         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1865         .tx_tbl                 = sdx65_usb3_uniphy_tx_tbl,
1866         .tx_tbl_num             = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
1867         .rx_tbl                 = sdx65_usb3_uniphy_rx_tbl,
1868         .rx_tbl_num             = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
1869         .pcs_tbl                = sm8350_usb3_uniphy_pcs_tbl,
1870         .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
1871         .pcs_usb_tbl            = sm8350_usb3_uniphy_pcs_usb_tbl,
1872         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl),
1873         .clk_list               = qmp_v4_sdx55_usbphy_clk_l,
1874         .num_clks               = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
1875         .reset_list             = msm8996_usb3phy_reset_l,
1876         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1877         .vreg_list              = qmp_phy_vreg_l,
1878         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1879         .regs                   = qmp_v4_usb3phy_regs_layout,
1880         .pcs_usb_offset         = 0x1000,
1881
1882         .start_ctrl             = SERDES_START | PCS_START,
1883         .pwrdn_ctrl             = SW_PWRDN,
1884         .phy_status             = PHYSTATUS,
1885
1886         .has_pwrdn_delay        = true,
1887         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
1888         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
1889 };
1890
1891 static const struct qmp_phy_cfg sm8350_usb3phy_cfg = {
1892         .type                   = PHY_TYPE_USB3,
1893         .nlanes                 = 1,
1894
1895         .serdes_tbl             = sm8150_usb3_serdes_tbl,
1896         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_serdes_tbl),
1897         .tx_tbl                 = sm8350_usb3_tx_tbl,
1898         .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_tx_tbl),
1899         .rx_tbl                 = sm8350_usb3_rx_tbl,
1900         .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_rx_tbl),
1901         .pcs_tbl                = sm8350_usb3_pcs_tbl,
1902         .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_pcs_tbl),
1903         .pcs_usb_tbl            = sm8350_usb3_pcs_usb_tbl,
1904         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl),
1905         .clk_list               = qmp_v4_sm8250_usbphy_clk_l,
1906         .num_clks               = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l),
1907         .reset_list             = msm8996_usb3phy_reset_l,
1908         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1909         .vreg_list              = qmp_phy_vreg_l,
1910         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1911         .regs                   = qmp_v4_usb3phy_regs_layout,
1912         .pcs_usb_offset         = 0x300,
1913
1914         .start_ctrl             = SERDES_START | PCS_START,
1915         .pwrdn_ctrl             = SW_PWRDN,
1916         .phy_status             = PHYSTATUS,
1917
1918         .has_pwrdn_delay        = true,
1919         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
1920         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
1921
1922         .has_phy_dp_com_ctrl    = true,
1923         .is_dual_lane_phy       = true,
1924 };
1925
1926 static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
1927         .type                   = PHY_TYPE_USB3,
1928         .nlanes                 = 1,
1929
1930         .serdes_tbl             = sm8150_usb3_uniphy_serdes_tbl,
1931         .serdes_tbl_num         = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1932         .tx_tbl                 = sm8350_usb3_uniphy_tx_tbl,
1933         .tx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
1934         .rx_tbl                 = sm8350_usb3_uniphy_rx_tbl,
1935         .rx_tbl_num             = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
1936         .pcs_tbl                = sm8350_usb3_uniphy_pcs_tbl,
1937         .pcs_tbl_num            = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
1938         .pcs_usb_tbl            = sm8350_usb3_uniphy_pcs_usb_tbl,
1939         .pcs_usb_tbl_num        = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl),
1940         .clk_list               = qmp_v4_phy_clk_l,
1941         .num_clks               = ARRAY_SIZE(qmp_v4_phy_clk_l),
1942         .reset_list             = msm8996_usb3phy_reset_l,
1943         .num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1944         .vreg_list              = qmp_phy_vreg_l,
1945         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1946         .regs                   = qmp_v4_usb3phy_regs_layout,
1947         .pcs_usb_offset         = 0x1000,
1948
1949         .start_ctrl             = SERDES_START | PCS_START,
1950         .pwrdn_ctrl             = SW_PWRDN,
1951         .phy_status             = PHYSTATUS,
1952
1953         .has_pwrdn_delay        = true,
1954         .pwrdn_delay_min        = POWER_DOWN_DELAY_US_MIN,
1955         .pwrdn_delay_max        = POWER_DOWN_DELAY_US_MAX,
1956 };
1957
1958 static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
1959         .type                   = PHY_TYPE_USB3,
1960         .nlanes                 = 1,
1961
1962         .serdes_tbl             = qcm2290_usb3_serdes_tbl,
1963         .serdes_tbl_num         = ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
1964         .tx_tbl                 = qcm2290_usb3_tx_tbl,
1965         .tx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_tx_tbl),
1966         .rx_tbl                 = qcm2290_usb3_rx_tbl,
1967         .rx_tbl_num             = ARRAY_SIZE(qcm2290_usb3_rx_tbl),
1968         .pcs_tbl                = qcm2290_usb3_pcs_tbl,
1969         .pcs_tbl_num            = ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
1970         .clk_list               = qcm2290_usb3phy_clk_l,
1971         .num_clks               = ARRAY_SIZE(qcm2290_usb3phy_clk_l),
1972         .reset_list             = qcm2290_usb3phy_reset_l,
1973         .num_resets             = ARRAY_SIZE(qcm2290_usb3phy_reset_l),
1974         .vreg_list              = qmp_phy_vreg_l,
1975         .num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1976         .regs                   = qcm2290_usb3phy_regs_layout,
1977
1978         .start_ctrl             = SERDES_START | PCS_START,
1979         .pwrdn_ctrl             = SW_PWRDN,
1980         .phy_status             = PHYSTATUS,
1981
1982         .is_dual_lane_phy       = true,
1983 };
1984
1985 static void qcom_qmp_phy_usb_configure_lane(void __iomem *base,
1986                                         const unsigned int *regs,
1987                                         const struct qmp_phy_init_tbl tbl[],
1988                                         int num,
1989                                         u8 lane_mask)
1990 {
1991         int i;
1992         const struct qmp_phy_init_tbl *t = tbl;
1993
1994         if (!t)
1995                 return;
1996
1997         for (i = 0; i < num; i++, t++) {
1998                 if (!(t->lane_mask & lane_mask))
1999                         continue;
2000
2001                 if (t->in_layout)
2002                         writel(t->val, base + regs[t->offset]);
2003                 else
2004                         writel(t->val, base + t->offset);
2005         }
2006 }
2007
2008 static void qcom_qmp_phy_usb_configure(void __iomem *base,
2009                                    const unsigned int *regs,
2010                                    const struct qmp_phy_init_tbl tbl[],
2011                                    int num)
2012 {
2013         qcom_qmp_phy_usb_configure_lane(base, regs, tbl, num, 0xff);
2014 }
2015
2016 static int qcom_qmp_phy_usb_serdes_init(struct qmp_phy *qphy)
2017 {
2018         const struct qmp_phy_cfg *cfg = qphy->cfg;
2019         void __iomem *serdes = qphy->serdes;
2020         const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
2021         int serdes_tbl_num = cfg->serdes_tbl_num;
2022
2023         qcom_qmp_phy_usb_configure(serdes, cfg->regs, serdes_tbl, serdes_tbl_num);
2024
2025         return 0;
2026 }
2027
2028 static int qcom_qmp_phy_usb_com_init(struct qmp_phy *qphy)
2029 {
2030         struct qcom_qmp *qmp = qphy->qmp;
2031         const struct qmp_phy_cfg *cfg = qphy->cfg;
2032         void __iomem *pcs = qphy->pcs;
2033         void __iomem *dp_com = qmp->dp_com;
2034         int ret;
2035
2036         /* turn on regulator supplies */
2037         ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
2038         if (ret) {
2039                 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
2040                 return ret;
2041         }
2042
2043         ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
2044         if (ret) {
2045                 dev_err(qmp->dev, "reset assert failed\n");
2046                 goto err_disable_regulators;
2047         }
2048
2049         ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
2050         if (ret) {
2051                 dev_err(qmp->dev, "reset deassert failed\n");
2052                 goto err_disable_regulators;
2053         }
2054
2055         ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
2056         if (ret)
2057                 goto err_assert_reset;
2058
2059         if (cfg->has_phy_dp_com_ctrl) {
2060                 qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL,
2061                              SW_PWRDN);
2062                 /* override hardware control for reset of qmp phy */
2063                 qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
2064                              SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
2065                              SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
2066
2067                 /* Default type-c orientation, i.e CC1 */
2068                 qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02);
2069
2070                 qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL,
2071                              USB3_MODE | DP_MODE);
2072
2073                 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */
2074                 qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL,
2075                              SW_DPPHY_RESET_MUX | SW_DPPHY_RESET |
2076                              SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET);
2077
2078                 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03);
2079                 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET);
2080         }
2081
2082         if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL])
2083                 qphy_setbits(pcs,
2084                              cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
2085                              cfg->pwrdn_ctrl);
2086         else
2087                 qphy_setbits(pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
2088                              cfg->pwrdn_ctrl);
2089
2090         return 0;
2091
2092 err_assert_reset:
2093         reset_control_bulk_assert(cfg->num_resets, qmp->resets);
2094 err_disable_regulators:
2095         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
2096
2097         return ret;
2098 }
2099
2100 static int qcom_qmp_phy_usb_com_exit(struct qmp_phy *qphy)
2101 {
2102         struct qcom_qmp *qmp = qphy->qmp;
2103         const struct qmp_phy_cfg *cfg = qphy->cfg;
2104
2105         reset_control_bulk_assert(cfg->num_resets, qmp->resets);
2106
2107         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
2108
2109         regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
2110
2111         return 0;
2112 }
2113
2114 static int qcom_qmp_phy_usb_init(struct phy *phy)
2115 {
2116         struct qmp_phy *qphy = phy_get_drvdata(phy);
2117         struct qcom_qmp *qmp = qphy->qmp;
2118         int ret;
2119         dev_vdbg(qmp->dev, "Initializing QMP phy\n");
2120
2121         ret = qcom_qmp_phy_usb_com_init(qphy);
2122         if (ret)
2123                 return ret;
2124
2125         return 0;
2126 }
2127
2128 static int qcom_qmp_phy_usb_power_on(struct phy *phy)
2129 {
2130         struct qmp_phy *qphy = phy_get_drvdata(phy);
2131         struct qcom_qmp *qmp = qphy->qmp;
2132         const struct qmp_phy_cfg *cfg = qphy->cfg;
2133         void __iomem *tx = qphy->tx;
2134         void __iomem *rx = qphy->rx;
2135         void __iomem *pcs = qphy->pcs;
2136         void __iomem *status;
2137         unsigned int mask, val, ready;
2138         int ret;
2139
2140         qcom_qmp_phy_usb_serdes_init(qphy);
2141
2142         ret = clk_prepare_enable(qphy->pipe_clk);
2143         if (ret) {
2144                 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
2145                 return ret;
2146         }
2147
2148         /* Tx, Rx, and PCS configurations */
2149         qcom_qmp_phy_usb_configure_lane(tx, cfg->regs,
2150                                     cfg->tx_tbl, cfg->tx_tbl_num, 1);
2151
2152         /* Configuration for other LANE for USB-DP combo PHY */
2153         if (cfg->is_dual_lane_phy) {
2154                 qcom_qmp_phy_usb_configure_lane(qphy->tx2, cfg->regs,
2155                                             cfg->tx_tbl, cfg->tx_tbl_num, 2);
2156         }
2157
2158         qcom_qmp_phy_usb_configure_lane(rx, cfg->regs,
2159                                     cfg->rx_tbl, cfg->rx_tbl_num, 1);
2160
2161         if (cfg->is_dual_lane_phy) {
2162                 qcom_qmp_phy_usb_configure_lane(qphy->rx2, cfg->regs,
2163                                             cfg->rx_tbl, cfg->rx_tbl_num, 2);
2164         }
2165
2166         /* Configure link rate, swing, etc. */
2167         qcom_qmp_phy_usb_configure(pcs, cfg->regs, cfg->pcs_tbl, cfg->pcs_tbl_num);
2168
2169         if (cfg->has_pwrdn_delay)
2170                 usleep_range(cfg->pwrdn_delay_min, cfg->pwrdn_delay_max);
2171
2172         /* Pull PHY out of reset state */
2173         qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
2174
2175         /* start SerDes and Phy-Coding-Sublayer */
2176         qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
2177
2178         status = pcs + cfg->regs[QPHY_PCS_STATUS];
2179         mask = cfg->phy_status;
2180         ready = 0;
2181
2182         ret = readl_poll_timeout(status, val, (val & mask) == ready, 10,
2183                                  PHY_INIT_COMPLETE_TIMEOUT);
2184         if (ret) {
2185                 dev_err(qmp->dev, "phy initialization timed-out\n");
2186                 goto err_disable_pipe_clk;
2187         }
2188
2189         return 0;
2190
2191 err_disable_pipe_clk:
2192         clk_disable_unprepare(qphy->pipe_clk);
2193
2194         return ret;
2195 }
2196
2197 static int qcom_qmp_phy_usb_power_off(struct phy *phy)
2198 {
2199         struct qmp_phy *qphy = phy_get_drvdata(phy);
2200         const struct qmp_phy_cfg *cfg = qphy->cfg;
2201
2202         clk_disable_unprepare(qphy->pipe_clk);
2203
2204         /* PHY reset */
2205         qphy_setbits(qphy->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
2206
2207         /* stop SerDes and Phy-Coding-Sublayer */
2208         qphy_clrbits(qphy->pcs, cfg->regs[QPHY_START_CTRL], cfg->start_ctrl);
2209
2210         /* Put PHY into POWER DOWN state: active low */
2211         if (cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL]) {
2212                 qphy_clrbits(qphy->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
2213                              cfg->pwrdn_ctrl);
2214         } else {
2215                 qphy_clrbits(qphy->pcs, QPHY_V2_PCS_POWER_DOWN_CONTROL,
2216                                 cfg->pwrdn_ctrl);
2217         }
2218
2219         return 0;
2220 }
2221
2222 static int qcom_qmp_phy_usb_exit(struct phy *phy)
2223 {
2224         struct qmp_phy *qphy = phy_get_drvdata(phy);
2225
2226         qcom_qmp_phy_usb_com_exit(qphy);
2227
2228         return 0;
2229 }
2230
2231 static int qcom_qmp_phy_usb_enable(struct phy *phy)
2232 {
2233         int ret;
2234
2235         ret = qcom_qmp_phy_usb_init(phy);
2236         if (ret)
2237                 return ret;
2238
2239         ret = qcom_qmp_phy_usb_power_on(phy);
2240         if (ret)
2241                 qcom_qmp_phy_usb_exit(phy);
2242
2243         return ret;
2244 }
2245
2246 static int qcom_qmp_phy_usb_disable(struct phy *phy)
2247 {
2248         int ret;
2249
2250         ret = qcom_qmp_phy_usb_power_off(phy);
2251         if (ret)
2252                 return ret;
2253         return qcom_qmp_phy_usb_exit(phy);
2254 }
2255
2256 static int qcom_qmp_phy_usb_set_mode(struct phy *phy,
2257                                  enum phy_mode mode, int submode)
2258 {
2259         struct qmp_phy *qphy = phy_get_drvdata(phy);
2260
2261         qphy->mode = mode;
2262
2263         return 0;
2264 }
2265
2266 static void qcom_qmp_phy_usb_enable_autonomous_mode(struct qmp_phy *qphy)
2267 {
2268         const struct qmp_phy_cfg *cfg = qphy->cfg;
2269         void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs;
2270         void __iomem *pcs_misc = qphy->pcs_misc;
2271         u32 intr_mask;
2272
2273         if (qphy->mode == PHY_MODE_USB_HOST_SS ||
2274             qphy->mode == PHY_MODE_USB_DEVICE_SS)
2275                 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
2276         else
2277                 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
2278
2279         /* Clear any pending interrupts status */
2280         qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2281         /* Writing 1 followed by 0 clears the interrupt */
2282         qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2283
2284         qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
2285                      ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
2286
2287         /* Enable required PHY autonomous mode interrupts */
2288         qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
2289
2290         /* Enable i/o clamp_n for autonomous mode */
2291         if (pcs_misc)
2292                 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
2293 }
2294
2295 static void qcom_qmp_phy_usb_disable_autonomous_mode(struct qmp_phy *qphy)
2296 {
2297         const struct qmp_phy_cfg *cfg = qphy->cfg;
2298         void __iomem *pcs_usb = qphy->pcs_usb ?: qphy->pcs;
2299         void __iomem *pcs_misc = qphy->pcs_misc;
2300
2301         /* Disable i/o clamp_n on resume for normal mode */
2302         if (pcs_misc)
2303                 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
2304
2305         qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
2306                      ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
2307
2308         qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2309         /* Writing 1 followed by 0 clears the interrupt */
2310         qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
2311 }
2312
2313 static int __maybe_unused qcom_qmp_phy_usb_runtime_suspend(struct device *dev)
2314 {
2315         struct qcom_qmp *qmp = dev_get_drvdata(dev);
2316         struct qmp_phy *qphy = qmp->phys[0];
2317         const struct qmp_phy_cfg *cfg = qphy->cfg;
2318
2319         dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qphy->mode);
2320
2321         /* Supported only for USB3 PHY and luckily USB3 is the first phy */
2322         if (cfg->type != PHY_TYPE_USB3)
2323                 return 0;
2324
2325         if (!qphy->phy->init_count) {
2326                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
2327                 return 0;
2328         }
2329
2330         qcom_qmp_phy_usb_enable_autonomous_mode(qphy);
2331
2332         clk_disable_unprepare(qphy->pipe_clk);
2333         clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
2334
2335         return 0;
2336 }
2337
2338 static int __maybe_unused qcom_qmp_phy_usb_runtime_resume(struct device *dev)
2339 {
2340         struct qcom_qmp *qmp = dev_get_drvdata(dev);
2341         struct qmp_phy *qphy = qmp->phys[0];
2342         const struct qmp_phy_cfg *cfg = qphy->cfg;
2343         int ret = 0;
2344
2345         dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qphy->mode);
2346
2347         /* Supported only for USB3 PHY and luckily USB3 is the first phy */
2348         if (cfg->type != PHY_TYPE_USB3)
2349                 return 0;
2350
2351         if (!qphy->phy->init_count) {
2352                 dev_vdbg(dev, "PHY not initialized, bailing out\n");
2353                 return 0;
2354         }
2355
2356         ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
2357         if (ret)
2358                 return ret;
2359
2360         ret = clk_prepare_enable(qphy->pipe_clk);
2361         if (ret) {
2362                 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
2363                 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
2364                 return ret;
2365         }
2366
2367         qcom_qmp_phy_usb_disable_autonomous_mode(qphy);
2368
2369         return 0;
2370 }
2371
2372 static int qcom_qmp_phy_usb_vreg_init(struct device *dev, const struct qmp_phy_cfg *cfg)
2373 {
2374         struct qcom_qmp *qmp = dev_get_drvdata(dev);
2375         int num = cfg->num_vregs;
2376         int i;
2377
2378         qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
2379         if (!qmp->vregs)
2380                 return -ENOMEM;
2381
2382         for (i = 0; i < num; i++)
2383                 qmp->vregs[i].supply = cfg->vreg_list[i];
2384
2385         return devm_regulator_bulk_get(dev, num, qmp->vregs);
2386 }
2387
2388 static int qcom_qmp_phy_usb_reset_init(struct device *dev, const struct qmp_phy_cfg *cfg)
2389 {
2390         struct qcom_qmp *qmp = dev_get_drvdata(dev);
2391         int i;
2392         int ret;
2393
2394         qmp->resets = devm_kcalloc(dev, cfg->num_resets,
2395                                    sizeof(*qmp->resets), GFP_KERNEL);
2396         if (!qmp->resets)
2397                 return -ENOMEM;
2398
2399         for (i = 0; i < cfg->num_resets; i++)
2400                 qmp->resets[i].id = cfg->reset_list[i];
2401
2402         ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets);
2403         if (ret)
2404                 return dev_err_probe(dev, ret, "failed to get resets\n");
2405
2406         return 0;
2407 }
2408
2409 static int qcom_qmp_phy_usb_clk_init(struct device *dev, const struct qmp_phy_cfg *cfg)
2410 {
2411         struct qcom_qmp *qmp = dev_get_drvdata(dev);
2412         int num = cfg->num_clks;
2413         int i;
2414
2415         qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
2416         if (!qmp->clks)
2417                 return -ENOMEM;
2418
2419         for (i = 0; i < num; i++)
2420                 qmp->clks[i].id = cfg->clk_list[i];
2421
2422         return devm_clk_bulk_get(dev, num, qmp->clks);
2423 }
2424
2425 static void phy_clk_release_provider(void *res)
2426 {
2427         of_clk_del_provider(res);
2428 }
2429
2430 /*
2431  * Register a fixed rate pipe clock.
2432  *
2433  * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
2434  * controls it. The <s>_pipe_clk coming out of the GCC is requested
2435  * by the PHY driver for its operations.
2436  * We register the <s>_pipe_clksrc here. The gcc driver takes care
2437  * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
2438  * Below picture shows this relationship.
2439  *
2440  *         +---------------+
2441  *         |   PHY block   |<<---------------------------------------+
2442  *         |               |                                         |
2443  *         |   +-------+   |                   +-----+               |
2444  *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
2445  *    clk  |   +-------+   |                   +-----+
2446  *         +---------------+
2447  */
2448 static int phy_pipe_clk_register(struct qcom_qmp *qmp, struct device_node *np)
2449 {
2450         struct clk_fixed_rate *fixed;
2451         struct clk_init_data init = { };
2452         int ret;
2453
2454         ret = of_property_read_string(np, "clock-output-names", &init.name);
2455         if (ret) {
2456                 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
2457                 return ret;
2458         }
2459
2460         fixed = devm_kzalloc(qmp->dev, sizeof(*fixed), GFP_KERNEL);
2461         if (!fixed)
2462                 return -ENOMEM;
2463
2464         init.ops = &clk_fixed_rate_ops;
2465
2466         /* controllers using QMP phys use 125MHz pipe clock interface */
2467         fixed->fixed_rate = 125000000;
2468         fixed->hw.init = &init;
2469
2470         ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
2471         if (ret)
2472                 return ret;
2473
2474         ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
2475         if (ret)
2476                 return ret;
2477
2478         /*
2479          * Roll a devm action because the clock provider is the child node, but
2480          * the child node is not actually a device.
2481          */
2482         return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
2483 }
2484
2485 static const struct phy_ops qcom_qmp_phy_usb_ops = {
2486         .init           = qcom_qmp_phy_usb_enable,
2487         .exit           = qcom_qmp_phy_usb_disable,
2488         .set_mode       = qcom_qmp_phy_usb_set_mode,
2489         .owner          = THIS_MODULE,
2490 };
2491
2492 static
2493 int qcom_qmp_phy_usb_create(struct device *dev, struct device_node *np, int id,
2494                         void __iomem *serdes, const struct qmp_phy_cfg *cfg)
2495 {
2496         struct qcom_qmp *qmp = dev_get_drvdata(dev);
2497         struct phy *generic_phy;
2498         struct qmp_phy *qphy;
2499         char prop_name[MAX_PROP_NAME];
2500         int ret;
2501
2502         qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL);
2503         if (!qphy)
2504                 return -ENOMEM;
2505
2506         qphy->cfg = cfg;
2507         qphy->serdes = serdes;
2508         /*
2509          * Get memory resources for each phy lane:
2510          * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
2511          * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
2512          * For single lane PHYs: pcs_misc (optional) -> 3.
2513          */
2514         qphy->tx = of_iomap(np, 0);
2515         if (!qphy->tx)
2516                 return -ENOMEM;
2517
2518         qphy->rx = of_iomap(np, 1);
2519         if (!qphy->rx)
2520                 return -ENOMEM;
2521
2522         qphy->pcs = of_iomap(np, 2);
2523         if (!qphy->pcs)
2524                 return -ENOMEM;
2525
2526         if (cfg->pcs_usb_offset)
2527                 qphy->pcs_usb = qphy->pcs + cfg->pcs_usb_offset;
2528
2529         /*
2530          * If this is a dual-lane PHY, then there should be registers for the
2531          * second lane. Some old device trees did not specify this, so fall
2532          * back to old legacy behavior of assuming they can be reached at an
2533          * offset from the first lane.
2534          */
2535         if (cfg->is_dual_lane_phy) {
2536                 qphy->tx2 = of_iomap(np, 3);
2537                 qphy->rx2 = of_iomap(np, 4);
2538                 if (!qphy->tx2 || !qphy->rx2) {
2539                         dev_warn(dev,
2540                                  "Underspecified device tree, falling back to legacy register regions\n");
2541
2542                         /* In the old version, pcs_misc is at index 3. */
2543                         qphy->pcs_misc = qphy->tx2;
2544                         qphy->tx2 = qphy->tx + QMP_PHY_LEGACY_LANE_STRIDE;
2545                         qphy->rx2 = qphy->rx + QMP_PHY_LEGACY_LANE_STRIDE;
2546
2547                 } else {
2548                         qphy->pcs_misc = of_iomap(np, 5);
2549                 }
2550
2551         } else {
2552                 qphy->pcs_misc = of_iomap(np, 3);
2553         }
2554
2555         if (!qphy->pcs_misc)
2556                 dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
2557
2558         snprintf(prop_name, sizeof(prop_name), "pipe%d", id);
2559         qphy->pipe_clk = devm_get_clk_from_child(dev, np, prop_name);
2560         if (IS_ERR(qphy->pipe_clk)) {
2561                 return dev_err_probe(dev, PTR_ERR(qphy->pipe_clk),
2562                                      "failed to get lane%d pipe clock\n", id);
2563         }
2564
2565         generic_phy = devm_phy_create(dev, np, &qcom_qmp_phy_usb_ops);
2566         if (IS_ERR(generic_phy)) {
2567                 ret = PTR_ERR(generic_phy);
2568                 dev_err(dev, "failed to create qphy %d\n", ret);
2569                 return ret;
2570         }
2571
2572         qphy->phy = generic_phy;
2573         qphy->index = id;
2574         qphy->qmp = qmp;
2575         qmp->phys[id] = qphy;
2576         phy_set_drvdata(generic_phy, qphy);
2577
2578         return 0;
2579 }
2580
2581 static const struct of_device_id qcom_qmp_phy_usb_of_match_table[] = {
2582         {
2583                 .compatible = "qcom,ipq8074-qmp-usb3-phy",
2584                 .data = &ipq8074_usb3phy_cfg,
2585         }, {
2586                 .compatible = "qcom,msm8996-qmp-usb3-phy",
2587                 .data = &msm8996_usb3phy_cfg,
2588         }, {
2589                 .compatible = "qcom,ipq6018-qmp-usb3-phy",
2590                 .data = &ipq8074_usb3phy_cfg,
2591         }, {
2592                 .compatible = "qcom,sc7180-qmp-usb3-phy",
2593                 .data = &sc7180_usb3phy_cfg,
2594         }, {
2595                 .compatible = "qcom,sc8180x-qmp-usb3-phy",
2596                 .data = &sm8150_usb3phy_cfg,
2597         }, {
2598                 .compatible = "qcom,sdm845-qmp-usb3-phy",
2599                 .data = &qmp_v3_usb3phy_cfg,
2600         }, {
2601                 .compatible = "qcom,sdm845-qmp-usb3-uni-phy",
2602                 .data = &qmp_v3_usb3_uniphy_cfg,
2603         }, {
2604                 .compatible = "qcom,msm8998-qmp-usb3-phy",
2605                 .data = &msm8998_usb3phy_cfg,
2606         }, {
2607                 .compatible = "qcom,sm8150-qmp-usb3-phy",
2608                 .data = &sm8150_usb3phy_cfg,
2609         }, {
2610                 .compatible = "qcom,sm8150-qmp-usb3-uni-phy",
2611                 .data = &sm8150_usb3_uniphy_cfg,
2612         }, {
2613                 .compatible = "qcom,sm8250-qmp-usb3-phy",
2614                 .data = &sm8250_usb3phy_cfg,
2615         }, {
2616                 .compatible = "qcom,sm8250-qmp-usb3-uni-phy",
2617                 .data = &sm8250_usb3_uniphy_cfg,
2618         }, {
2619                 .compatible = "qcom,sdx55-qmp-usb3-uni-phy",
2620                 .data = &sdx55_usb3_uniphy_cfg,
2621         }, {
2622                 .compatible = "qcom,sdx65-qmp-usb3-uni-phy",
2623                 .data = &sdx65_usb3_uniphy_cfg,
2624         }, {
2625                 .compatible = "qcom,sm8350-qmp-usb3-phy",
2626                 .data = &sm8350_usb3phy_cfg,
2627         }, {
2628                 .compatible = "qcom,sm8350-qmp-usb3-uni-phy",
2629                 .data = &sm8350_usb3_uniphy_cfg,
2630         }, {
2631                 .compatible = "qcom,sm8450-qmp-usb3-phy",
2632                 .data = &sm8350_usb3phy_cfg,
2633         }, {
2634                 .compatible = "qcom,qcm2290-qmp-usb3-phy",
2635                 .data = &qcm2290_usb3phy_cfg,
2636         },
2637         { },
2638 };
2639 MODULE_DEVICE_TABLE(of, qcom_qmp_phy_usb_of_match_table);
2640
2641 static const struct dev_pm_ops qcom_qmp_phy_usb_pm_ops = {
2642         SET_RUNTIME_PM_OPS(qcom_qmp_phy_usb_runtime_suspend,
2643                            qcom_qmp_phy_usb_runtime_resume, NULL)
2644 };
2645
2646 static int qcom_qmp_phy_usb_probe(struct platform_device *pdev)
2647 {
2648         struct qcom_qmp *qmp;
2649         struct device *dev = &pdev->dev;
2650         struct device_node *child;
2651         struct phy_provider *phy_provider;
2652         void __iomem *serdes;
2653         const struct qmp_phy_cfg *cfg = NULL;
2654         int num, id;
2655         int ret;
2656
2657         qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
2658         if (!qmp)
2659                 return -ENOMEM;
2660
2661         qmp->dev = dev;
2662         dev_set_drvdata(dev, qmp);
2663
2664         /* Get the specific init parameters of QMP phy */
2665         cfg = of_device_get_match_data(dev);
2666         if (!cfg)
2667                 return -EINVAL;
2668
2669         /* per PHY serdes; usually located at base address */
2670         serdes = devm_platform_ioremap_resource(pdev, 0);
2671         if (IS_ERR(serdes))
2672                 return PTR_ERR(serdes);
2673
2674         /* per PHY dp_com; if PHY has dp_com control block */
2675         if (cfg->has_phy_dp_com_ctrl) {
2676                 qmp->dp_com = devm_platform_ioremap_resource(pdev, 1);
2677                 if (IS_ERR(qmp->dp_com))
2678                         return PTR_ERR(qmp->dp_com);
2679         }
2680
2681         ret = qcom_qmp_phy_usb_clk_init(dev, cfg);
2682         if (ret)
2683                 return ret;
2684
2685         ret = qcom_qmp_phy_usb_reset_init(dev, cfg);
2686         if (ret)
2687                 return ret;
2688
2689         ret = qcom_qmp_phy_usb_vreg_init(dev, cfg);
2690         if (ret) {
2691                 if (ret != -EPROBE_DEFER)
2692                         dev_err(dev, "failed to get regulator supplies: %d\n",
2693                                 ret);
2694                 return ret;
2695         }
2696
2697         num = of_get_available_child_count(dev->of_node);
2698         /* do we have a rogue child node ? */
2699         if (num > 1)
2700                 return -EINVAL;
2701
2702         qmp->phys = devm_kcalloc(dev, num, sizeof(*qmp->phys), GFP_KERNEL);
2703         if (!qmp->phys)
2704                 return -ENOMEM;
2705
2706         pm_runtime_set_active(dev);
2707         pm_runtime_enable(dev);
2708         /*
2709          * Prevent runtime pm from being ON by default. Users can enable
2710          * it using power/control in sysfs.
2711          */
2712         pm_runtime_forbid(dev);
2713
2714         id = 0;
2715         for_each_available_child_of_node(dev->of_node, child) {
2716                 /* Create per-lane phy */
2717                 ret = qcom_qmp_phy_usb_create(dev, child, id, serdes, cfg);
2718                 if (ret) {
2719                         dev_err(dev, "failed to create lane%d phy, %d\n",
2720                                 id, ret);
2721                         goto err_node_put;
2722                 }
2723
2724                 /*
2725                  * Register the pipe clock provided by phy.
2726                  * See function description to see details of this pipe clock.
2727                  */
2728                 ret = phy_pipe_clk_register(qmp, child);
2729                 if (ret) {
2730                         dev_err(qmp->dev,
2731                                 "failed to register pipe clock source\n");
2732                         goto err_node_put;
2733                 }
2734
2735                 id++;
2736         }
2737
2738         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
2739         if (!IS_ERR(phy_provider))
2740                 dev_info(dev, "Registered Qcom-QMP phy\n");
2741         else
2742                 pm_runtime_disable(dev);
2743
2744         return PTR_ERR_OR_ZERO(phy_provider);
2745
2746 err_node_put:
2747         pm_runtime_disable(dev);
2748         of_node_put(child);
2749         return ret;
2750 }
2751
2752 static struct platform_driver qcom_qmp_phy_usb_driver = {
2753         .probe          = qcom_qmp_phy_usb_probe,
2754         .driver = {
2755                 .name   = "qcom-qmp-usb-phy",
2756                 .pm     = &qcom_qmp_phy_usb_pm_ops,
2757                 .of_match_table = qcom_qmp_phy_usb_of_match_table,
2758         },
2759 };
2760
2761 module_platform_driver(qcom_qmp_phy_usb_driver);
2762
2763 MODULE_AUTHOR("Vivek Gautam <[email protected]>");
2764 MODULE_DESCRIPTION("Qualcomm QMP USB PHY driver");
2765 MODULE_LICENSE("GPL v2");