1 // SPDX-License-Identifier: GPL-2.0
3 * Enable PCIe link L0s/L1 state and Clock Power Management
5 * Copyright (C) 2007 Intel
10 #include <linux/kernel.h>
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/pci.h>
14 #include <linux/pci_regs.h>
15 #include <linux/errno.h>
17 #include <linux/init.h>
18 #include <linux/slab.h>
19 #include <linux/jiffies.h>
20 #include <linux/delay.h>
23 #ifdef MODULE_PARAM_PREFIX
24 #undef MODULE_PARAM_PREFIX
26 #define MODULE_PARAM_PREFIX "pcie_aspm."
28 /* Note: those are not register definitions */
29 #define ASPM_STATE_L0S_UP (1) /* Upstream direction L0s state */
30 #define ASPM_STATE_L0S_DW (2) /* Downstream direction L0s state */
31 #define ASPM_STATE_L1 (4) /* L1 state */
32 #define ASPM_STATE_L1_1 (8) /* ASPM L1.1 state */
33 #define ASPM_STATE_L1_2 (0x10) /* ASPM L1.2 state */
34 #define ASPM_STATE_L1_1_PCIPM (0x20) /* PCI PM L1.1 state */
35 #define ASPM_STATE_L1_2_PCIPM (0x40) /* PCI PM L1.2 state */
36 #define ASPM_STATE_L1_SS_PCIPM (ASPM_STATE_L1_1_PCIPM | ASPM_STATE_L1_2_PCIPM)
37 #define ASPM_STATE_L1_2_MASK (ASPM_STATE_L1_2 | ASPM_STATE_L1_2_PCIPM)
38 #define ASPM_STATE_L1SS (ASPM_STATE_L1_1 | ASPM_STATE_L1_1_PCIPM |\
40 #define ASPM_STATE_L0S (ASPM_STATE_L0S_UP | ASPM_STATE_L0S_DW)
41 #define ASPM_STATE_ALL (ASPM_STATE_L0S | ASPM_STATE_L1 | \
44 struct pcie_link_state {
45 struct pci_dev *pdev; /* Upstream component of the Link */
46 struct pci_dev *downstream; /* Downstream component, function 0 */
47 struct pcie_link_state *root; /* pointer to the root port link */
48 struct pcie_link_state *parent; /* pointer to the parent Link state */
49 struct list_head sibling; /* node in link_list */
52 u32 aspm_support:7; /* Supported ASPM state */
53 u32 aspm_enabled:7; /* Enabled ASPM state */
54 u32 aspm_capable:7; /* Capable ASPM state with latency */
55 u32 aspm_default:7; /* Default ASPM state by BIOS */
56 u32 aspm_disable:7; /* Disabled ASPM state */
59 u32 clkpm_capable:1; /* Clock PM capable? */
60 u32 clkpm_enabled:1; /* Current Clock PM state */
61 u32 clkpm_default:1; /* Default Clock PM state by BIOS */
62 u32 clkpm_disable:1; /* Clock PM disabled */
65 static int aspm_disabled, aspm_force;
66 static bool aspm_support_enabled = true;
67 static DEFINE_MUTEX(aspm_lock);
68 static LIST_HEAD(link_list);
70 #define POLICY_DEFAULT 0 /* BIOS default setting */
71 #define POLICY_PERFORMANCE 1 /* high performance */
72 #define POLICY_POWERSAVE 2 /* high power saving */
73 #define POLICY_POWER_SUPERSAVE 3 /* possibly even more power saving */
75 #ifdef CONFIG_PCIEASPM_PERFORMANCE
76 static int aspm_policy = POLICY_PERFORMANCE;
77 #elif defined CONFIG_PCIEASPM_POWERSAVE
78 static int aspm_policy = POLICY_POWERSAVE;
79 #elif defined CONFIG_PCIEASPM_POWER_SUPERSAVE
80 static int aspm_policy = POLICY_POWER_SUPERSAVE;
82 static int aspm_policy;
85 static const char *policy_str[] = {
86 [POLICY_DEFAULT] = "default",
87 [POLICY_PERFORMANCE] = "performance",
88 [POLICY_POWERSAVE] = "powersave",
89 [POLICY_POWER_SUPERSAVE] = "powersupersave"
92 #define LINK_RETRAIN_TIMEOUT HZ
95 * The L1 PM substate capability is only implemented in function 0 in a
96 * multi function device.
98 static struct pci_dev *pci_function_0(struct pci_bus *linkbus)
100 struct pci_dev *child;
102 list_for_each_entry(child, &linkbus->devices, bus_list)
103 if (PCI_FUNC(child->devfn) == 0)
108 static int policy_to_aspm_state(struct pcie_link_state *link)
110 switch (aspm_policy) {
111 case POLICY_PERFORMANCE:
112 /* Disable ASPM and Clock PM */
114 case POLICY_POWERSAVE:
115 /* Enable ASPM L0s/L1 */
116 return (ASPM_STATE_L0S | ASPM_STATE_L1);
117 case POLICY_POWER_SUPERSAVE:
118 /* Enable Everything */
119 return ASPM_STATE_ALL;
121 return link->aspm_default;
126 static int policy_to_clkpm_state(struct pcie_link_state *link)
128 switch (aspm_policy) {
129 case POLICY_PERFORMANCE:
130 /* Disable ASPM and Clock PM */
132 case POLICY_POWERSAVE:
133 case POLICY_POWER_SUPERSAVE:
134 /* Enable Clock PM */
137 return link->clkpm_default;
142 static void pcie_set_clkpm_nocheck(struct pcie_link_state *link, int enable)
144 struct pci_dev *child;
145 struct pci_bus *linkbus = link->pdev->subordinate;
146 u32 val = enable ? PCI_EXP_LNKCTL_CLKREQ_EN : 0;
148 list_for_each_entry(child, &linkbus->devices, bus_list)
149 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
150 PCI_EXP_LNKCTL_CLKREQ_EN,
152 link->clkpm_enabled = !!enable;
155 static void pcie_set_clkpm(struct pcie_link_state *link, int enable)
158 * Don't enable Clock PM if the link is not Clock PM capable
159 * or Clock PM is disabled
161 if (!link->clkpm_capable || link->clkpm_disable)
163 /* Need nothing if the specified equals to current state */
164 if (link->clkpm_enabled == enable)
166 pcie_set_clkpm_nocheck(link, enable);
169 static void pcie_clkpm_cap_init(struct pcie_link_state *link, int blacklist)
171 int capable = 1, enabled = 1;
174 struct pci_dev *child;
175 struct pci_bus *linkbus = link->pdev->subordinate;
177 /* All functions should have the same cap and state, take the worst */
178 list_for_each_entry(child, &linkbus->devices, bus_list) {
179 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, ®32);
180 if (!(reg32 & PCI_EXP_LNKCAP_CLKPM)) {
185 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
186 if (!(reg16 & PCI_EXP_LNKCTL_CLKREQ_EN))
189 link->clkpm_enabled = enabled;
190 link->clkpm_default = enabled;
191 link->clkpm_capable = capable;
192 link->clkpm_disable = blacklist ? 1 : 0;
195 static bool pcie_retrain_link(struct pcie_link_state *link)
197 struct pci_dev *parent = link->pdev;
198 unsigned long end_jiffies;
201 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
202 reg16 |= PCI_EXP_LNKCTL_RL;
203 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
204 if (parent->clear_retrain_link) {
206 * Due to an erratum in some devices the Retrain Link bit
207 * needs to be cleared again manually to allow the link
208 * training to succeed.
210 reg16 &= ~PCI_EXP_LNKCTL_RL;
211 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
214 /* Wait for link training end. Break out after waiting for timeout */
215 end_jiffies = jiffies + LINK_RETRAIN_TIMEOUT;
217 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
218 if (!(reg16 & PCI_EXP_LNKSTA_LT))
221 } while (time_before(jiffies, end_jiffies));
222 return !(reg16 & PCI_EXP_LNKSTA_LT);
226 * pcie_aspm_configure_common_clock: check if the 2 ends of a link
227 * could use common clock. If they are, configure them to use the
228 * common clock. That will reduce the ASPM state exit latency.
230 static void pcie_aspm_configure_common_clock(struct pcie_link_state *link)
233 u16 reg16, parent_reg, child_reg[8];
234 struct pci_dev *child, *parent = link->pdev;
235 struct pci_bus *linkbus = parent->subordinate;
237 * All functions of a slot should have the same Slot Clock
238 * Configuration, so just check one function
240 child = list_entry(linkbus->devices.next, struct pci_dev, bus_list);
241 BUG_ON(!pci_is_pcie(child));
243 /* Check downstream component if bit Slot Clock Configuration is 1 */
244 pcie_capability_read_word(child, PCI_EXP_LNKSTA, ®16);
245 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
248 /* Check upstream component if bit Slot Clock Configuration is 1 */
249 pcie_capability_read_word(parent, PCI_EXP_LNKSTA, ®16);
250 if (!(reg16 & PCI_EXP_LNKSTA_SLC))
253 /* Port might be already in common clock mode */
254 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
255 if (same_clock && (reg16 & PCI_EXP_LNKCTL_CCC)) {
256 bool consistent = true;
258 list_for_each_entry(child, &linkbus->devices, bus_list) {
259 pcie_capability_read_word(child, PCI_EXP_LNKCTL,
261 if (!(reg16 & PCI_EXP_LNKCTL_CCC)) {
268 pci_info(parent, "ASPM: current common clock configuration is inconsistent, reconfiguring\n");
271 /* Configure downstream component, all functions */
272 list_for_each_entry(child, &linkbus->devices, bus_list) {
273 pcie_capability_read_word(child, PCI_EXP_LNKCTL, ®16);
274 child_reg[PCI_FUNC(child->devfn)] = reg16;
276 reg16 |= PCI_EXP_LNKCTL_CCC;
278 reg16 &= ~PCI_EXP_LNKCTL_CCC;
279 pcie_capability_write_word(child, PCI_EXP_LNKCTL, reg16);
282 /* Configure upstream component */
283 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, ®16);
286 reg16 |= PCI_EXP_LNKCTL_CCC;
288 reg16 &= ~PCI_EXP_LNKCTL_CCC;
289 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, reg16);
291 if (pcie_retrain_link(link))
294 /* Training failed. Restore common clock configurations */
295 pci_err(parent, "ASPM: Could not configure common clock\n");
296 list_for_each_entry(child, &linkbus->devices, bus_list)
297 pcie_capability_write_word(child, PCI_EXP_LNKCTL,
298 child_reg[PCI_FUNC(child->devfn)]);
299 pcie_capability_write_word(parent, PCI_EXP_LNKCTL, parent_reg);
302 /* Convert L0s latency encoding to ns */
303 static u32 calc_l0s_latency(u32 lnkcap)
305 u32 encoding = (lnkcap & PCI_EXP_LNKCAP_L0SEL) >> 12;
308 return (5 * 1000); /* > 4us */
309 return (64 << encoding);
312 /* Convert L0s acceptable latency encoding to ns */
313 static u32 calc_l0s_acceptable(u32 encoding)
317 return (64 << encoding);
320 /* Convert L1 latency encoding to ns */
321 static u32 calc_l1_latency(u32 lnkcap)
323 u32 encoding = (lnkcap & PCI_EXP_LNKCAP_L1EL) >> 15;
326 return (65 * 1000); /* > 64us */
327 return (1000 << encoding);
330 /* Convert L1 acceptable latency encoding to ns */
331 static u32 calc_l1_acceptable(u32 encoding)
335 return (1000 << encoding);
338 /* Convert L1SS T_pwr encoding to usec */
339 static u32 calc_l1ss_pwron(struct pci_dev *pdev, u32 scale, u32 val)
349 pci_err(pdev, "%s: Invalid T_PwrOn scale: %u\n", __func__, scale);
353 static void encode_l12_threshold(u32 threshold_us, u32 *scale, u32 *value)
355 u32 threshold_ns = threshold_us * 1000;
357 /* See PCIe r3.1, sec 7.33.3 and sec 6.18 */
358 if (threshold_ns < 32) {
360 *value = threshold_ns;
361 } else if (threshold_ns < 1024) {
363 *value = threshold_ns >> 5;
364 } else if (threshold_ns < 32768) {
366 *value = threshold_ns >> 10;
367 } else if (threshold_ns < 1048576) {
369 *value = threshold_ns >> 15;
370 } else if (threshold_ns < 33554432) {
372 *value = threshold_ns >> 20;
375 *value = threshold_ns >> 25;
379 static void pcie_aspm_check_latency(struct pci_dev *endpoint)
381 u32 latency, encoding, lnkcap_up, lnkcap_dw;
382 u32 l1_switch_latency = 0, latency_up_l0s;
383 u32 latency_up_l1, latency_dw_l0s, latency_dw_l1;
384 u32 acceptable_l0s, acceptable_l1;
385 struct pcie_link_state *link;
387 /* Device not in D0 doesn't need latency check */
388 if ((endpoint->current_state != PCI_D0) &&
389 (endpoint->current_state != PCI_UNKNOWN))
392 link = endpoint->bus->self->link_state;
394 /* Calculate endpoint L0s acceptable latency */
395 encoding = (endpoint->devcap & PCI_EXP_DEVCAP_L0S) >> 6;
396 acceptable_l0s = calc_l0s_acceptable(encoding);
398 /* Calculate endpoint L1 acceptable latency */
399 encoding = (endpoint->devcap & PCI_EXP_DEVCAP_L1) >> 9;
400 acceptable_l1 = calc_l1_acceptable(encoding);
403 struct pci_dev *dev = pci_function_0(link->pdev->subordinate);
405 /* Read direction exit latencies */
406 pcie_capability_read_dword(link->pdev, PCI_EXP_LNKCAP,
408 pcie_capability_read_dword(dev, PCI_EXP_LNKCAP,
410 latency_up_l0s = calc_l0s_latency(lnkcap_up);
411 latency_up_l1 = calc_l1_latency(lnkcap_up);
412 latency_dw_l0s = calc_l0s_latency(lnkcap_dw);
413 latency_dw_l1 = calc_l1_latency(lnkcap_dw);
415 /* Check upstream direction L0s latency */
416 if ((link->aspm_capable & ASPM_STATE_L0S_UP) &&
417 (latency_up_l0s > acceptable_l0s))
418 link->aspm_capable &= ~ASPM_STATE_L0S_UP;
420 /* Check downstream direction L0s latency */
421 if ((link->aspm_capable & ASPM_STATE_L0S_DW) &&
422 (latency_dw_l0s > acceptable_l0s))
423 link->aspm_capable &= ~ASPM_STATE_L0S_DW;
426 * Every switch on the path to root complex need 1
427 * more microsecond for L1. Spec doesn't mention L0s.
429 * The exit latencies for L1 substates are not advertised
430 * by a device. Since the spec also doesn't mention a way
431 * to determine max latencies introduced by enabling L1
432 * substates on the components, it is not clear how to do
433 * a L1 substate exit latency check. We assume that the
434 * L1 exit latencies advertised by a device include L1
435 * substate latencies (and hence do not do any check).
437 latency = max_t(u32, latency_up_l1, latency_dw_l1);
438 if ((link->aspm_capable & ASPM_STATE_L1) &&
439 (latency + l1_switch_latency > acceptable_l1))
440 link->aspm_capable &= ~ASPM_STATE_L1;
441 l1_switch_latency += 1000;
447 static void pci_clear_and_set_dword(struct pci_dev *pdev, int pos,
452 pci_read_config_dword(pdev, pos, &val);
455 pci_write_config_dword(pdev, pos, val);
458 /* Calculate L1.2 PM substate timing parameters */
459 static void aspm_calc_l1ss_info(struct pcie_link_state *link,
460 u32 parent_l1ss_cap, u32 child_l1ss_cap)
462 struct pci_dev *child = link->downstream, *parent = link->pdev;
463 u32 val1, val2, scale1, scale2;
464 u32 t_common_mode, t_power_on, l1_2_threshold, scale, value;
465 u32 ctl1 = 0, ctl2 = 0;
466 u32 pctl1, pctl2, cctl1, cctl2;
467 u32 pl1_2_enables, cl1_2_enables;
469 if (!(link->aspm_support & ASPM_STATE_L1_2_MASK))
472 /* Choose the greater of the two Port Common_Mode_Restore_Times */
473 val1 = (parent_l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
474 val2 = (child_l1ss_cap & PCI_L1SS_CAP_CM_RESTORE_TIME) >> 8;
475 t_common_mode = max(val1, val2);
477 /* Choose the greater of the two Port T_POWER_ON times */
478 val1 = (parent_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
479 scale1 = (parent_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
480 val2 = (child_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_VALUE) >> 19;
481 scale2 = (child_l1ss_cap & PCI_L1SS_CAP_P_PWR_ON_SCALE) >> 16;
483 if (calc_l1ss_pwron(parent, scale1, val1) >
484 calc_l1ss_pwron(child, scale2, val2)) {
485 ctl2 |= scale1 | (val1 << 3);
486 t_power_on = calc_l1ss_pwron(parent, scale1, val1);
488 ctl2 |= scale2 | (val2 << 3);
489 t_power_on = calc_l1ss_pwron(child, scale2, val2);
493 * Set LTR_L1.2_THRESHOLD to the time required to transition the
494 * Link from L0 to L1.2 and back to L0 so we enter L1.2 only if
495 * downstream devices report (via LTR) that they can tolerate at
496 * least that much latency.
498 * Based on PCIe r3.1, sec 5.5.3.3.1, Figures 5-16 and 5-17, and
499 * Table 5-11. T(POWER_OFF) is at most 2us and T(L1.2) is at
502 l1_2_threshold = 2 + 4 + t_common_mode + t_power_on;
503 encode_l12_threshold(l1_2_threshold, &scale, &value);
504 ctl1 |= t_common_mode << 8 | scale << 29 | value << 16;
506 /* Some broken devices only support dword access to L1 SS */
507 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1, &pctl1);
508 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, &pctl2);
509 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1, &cctl1);
510 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL2, &cctl2);
512 if (ctl1 == pctl1 && ctl1 == cctl1 &&
513 ctl2 == pctl2 && ctl2 == cctl2)
516 /* Disable L1.2 while updating. See PCIe r5.0, sec 5.5.4, 7.8.3.3 */
517 pl1_2_enables = pctl1 & PCI_L1SS_CTL1_L1_2_MASK;
518 cl1_2_enables = cctl1 & PCI_L1SS_CTL1_L1_2_MASK;
520 if (pl1_2_enables || cl1_2_enables) {
521 pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
522 PCI_L1SS_CTL1_L1_2_MASK, 0);
523 pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
524 PCI_L1SS_CTL1_L1_2_MASK, 0);
527 /* Program T_POWER_ON times in both ports */
528 pci_write_config_dword(parent, parent->l1ss + PCI_L1SS_CTL2, ctl2);
529 pci_write_config_dword(child, child->l1ss + PCI_L1SS_CTL2, ctl2);
531 /* Program Common_Mode_Restore_Time in upstream device */
532 pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
533 PCI_L1SS_CTL1_CM_RESTORE_TIME, ctl1);
535 /* Program LTR_L1.2_THRESHOLD time in both ports */
536 pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
537 PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
538 PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1);
539 pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
540 PCI_L1SS_CTL1_LTR_L12_TH_VALUE |
541 PCI_L1SS_CTL1_LTR_L12_TH_SCALE, ctl1);
543 if (pl1_2_enables || cl1_2_enables) {
544 pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1, 0,
546 pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1, 0,
551 static void pcie_aspm_cap_init(struct pcie_link_state *link, int blacklist)
553 struct pci_dev *child = link->downstream, *parent = link->pdev;
554 u32 parent_lnkcap, child_lnkcap;
555 u16 parent_lnkctl, child_lnkctl;
556 u32 parent_l1ss_cap, child_l1ss_cap;
557 u32 parent_l1ss_ctl1 = 0, child_l1ss_ctl1 = 0;
558 struct pci_bus *linkbus = parent->subordinate;
561 /* Set enabled/disable so that we will disable ASPM later */
562 link->aspm_enabled = ASPM_STATE_ALL;
563 link->aspm_disable = ASPM_STATE_ALL;
568 * If ASPM not supported, don't mess with the clocks and link,
571 pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, &parent_lnkcap);
572 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap);
573 if (!(parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPMS))
576 /* Configure common clock before checking latencies */
577 pcie_aspm_configure_common_clock(link);
580 * Re-read upstream/downstream components' register state after
581 * clock configuration. L0s & L1 exit latencies in the otherwise
582 * read-only Link Capabilities may change depending on common clock
583 * configuration (PCIe r5.0, sec 7.5.3.6).
585 pcie_capability_read_dword(parent, PCI_EXP_LNKCAP, &parent_lnkcap);
586 pcie_capability_read_dword(child, PCI_EXP_LNKCAP, &child_lnkcap);
587 pcie_capability_read_word(parent, PCI_EXP_LNKCTL, &parent_lnkctl);
588 pcie_capability_read_word(child, PCI_EXP_LNKCTL, &child_lnkctl);
593 * Note that we must not enable L0s in either direction on a
594 * given link unless components on both sides of the link each
597 if (parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPM_L0S)
598 link->aspm_support |= ASPM_STATE_L0S;
600 if (child_lnkctl & PCI_EXP_LNKCTL_ASPM_L0S)
601 link->aspm_enabled |= ASPM_STATE_L0S_UP;
602 if (parent_lnkctl & PCI_EXP_LNKCTL_ASPM_L0S)
603 link->aspm_enabled |= ASPM_STATE_L0S_DW;
606 if (parent_lnkcap & child_lnkcap & PCI_EXP_LNKCAP_ASPM_L1)
607 link->aspm_support |= ASPM_STATE_L1;
609 if (parent_lnkctl & child_lnkctl & PCI_EXP_LNKCTL_ASPM_L1)
610 link->aspm_enabled |= ASPM_STATE_L1;
612 /* Setup L1 substate */
613 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CAP,
615 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CAP,
618 if (!(parent_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS))
620 if (!(child_l1ss_cap & PCI_L1SS_CAP_L1_PM_SS))
624 * If we don't have LTR for the entire path from the Root Complex
625 * to this device, we can't use ASPM L1.2 because it relies on the
626 * LTR_L1.2_THRESHOLD. See PCIe r4.0, secs 5.5.4, 6.18.
628 if (!child->ltr_path)
629 child_l1ss_cap &= ~PCI_L1SS_CAP_ASPM_L1_2;
631 if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_ASPM_L1_1)
632 link->aspm_support |= ASPM_STATE_L1_1;
633 if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_ASPM_L1_2)
634 link->aspm_support |= ASPM_STATE_L1_2;
635 if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_1)
636 link->aspm_support |= ASPM_STATE_L1_1_PCIPM;
637 if (parent_l1ss_cap & child_l1ss_cap & PCI_L1SS_CAP_PCIPM_L1_2)
638 link->aspm_support |= ASPM_STATE_L1_2_PCIPM;
641 pci_read_config_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
644 pci_read_config_dword(child, child->l1ss + PCI_L1SS_CTL1,
647 if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_1)
648 link->aspm_enabled |= ASPM_STATE_L1_1;
649 if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_ASPM_L1_2)
650 link->aspm_enabled |= ASPM_STATE_L1_2;
651 if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_1)
652 link->aspm_enabled |= ASPM_STATE_L1_1_PCIPM;
653 if (parent_l1ss_ctl1 & child_l1ss_ctl1 & PCI_L1SS_CTL1_PCIPM_L1_2)
654 link->aspm_enabled |= ASPM_STATE_L1_2_PCIPM;
656 if (link->aspm_support & ASPM_STATE_L1SS)
657 aspm_calc_l1ss_info(link, parent_l1ss_cap, child_l1ss_cap);
659 /* Save default state */
660 link->aspm_default = link->aspm_enabled;
662 /* Setup initial capable state. Will be updated later */
663 link->aspm_capable = link->aspm_support;
665 /* Get and check endpoint acceptable latencies */
666 list_for_each_entry(child, &linkbus->devices, bus_list) {
667 if (pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT &&
668 pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END)
671 pcie_aspm_check_latency(child);
675 /* Configure the ASPM L1 substates */
676 static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state)
679 struct pci_dev *child = link->downstream, *parent = link->pdev;
681 enable_req = (link->aspm_enabled ^ state) & state;
684 * Here are the rules specified in the PCIe spec for enabling L1SS:
685 * - When enabling L1.x, enable bit at parent first, then at child
686 * - When disabling L1.x, disable bit at child first, then at parent
687 * - When enabling ASPM L1.x, need to disable L1
688 * (at child followed by parent).
689 * - The ASPM/PCIPM L1.2 must be disabled while programming timing
692 * To keep it simple, disable all L1SS bits first, and later enable
696 /* Disable all L1 substates */
697 pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
698 PCI_L1SS_CTL1_L1SS_MASK, 0);
699 pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
700 PCI_L1SS_CTL1_L1SS_MASK, 0);
702 * If needed, disable L1, and it gets enabled later
703 * in pcie_config_aspm_link().
705 if (enable_req & (ASPM_STATE_L1_1 | ASPM_STATE_L1_2)) {
706 pcie_capability_clear_and_set_word(child, PCI_EXP_LNKCTL,
707 PCI_EXP_LNKCTL_ASPM_L1, 0);
708 pcie_capability_clear_and_set_word(parent, PCI_EXP_LNKCTL,
709 PCI_EXP_LNKCTL_ASPM_L1, 0);
713 if (state & ASPM_STATE_L1_1)
714 val |= PCI_L1SS_CTL1_ASPM_L1_1;
715 if (state & ASPM_STATE_L1_2)
716 val |= PCI_L1SS_CTL1_ASPM_L1_2;
717 if (state & ASPM_STATE_L1_1_PCIPM)
718 val |= PCI_L1SS_CTL1_PCIPM_L1_1;
719 if (state & ASPM_STATE_L1_2_PCIPM)
720 val |= PCI_L1SS_CTL1_PCIPM_L1_2;
722 /* Enable what we need to enable */
723 pci_clear_and_set_dword(parent, parent->l1ss + PCI_L1SS_CTL1,
724 PCI_L1SS_CTL1_L1SS_MASK, val);
725 pci_clear_and_set_dword(child, child->l1ss + PCI_L1SS_CTL1,
726 PCI_L1SS_CTL1_L1SS_MASK, val);
729 static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
731 pcie_capability_clear_and_set_word(pdev, PCI_EXP_LNKCTL,
732 PCI_EXP_LNKCTL_ASPMC, val);
735 static void pcie_config_aspm_link(struct pcie_link_state *link, u32 state)
737 u32 upstream = 0, dwstream = 0;
738 struct pci_dev *child = link->downstream, *parent = link->pdev;
739 struct pci_bus *linkbus = parent->subordinate;
741 /* Enable only the states that were not explicitly disabled */
742 state &= (link->aspm_capable & ~link->aspm_disable);
744 /* Can't enable any substates if L1 is not enabled */
745 if (!(state & ASPM_STATE_L1))
746 state &= ~ASPM_STATE_L1SS;
748 /* Spec says both ports must be in D0 before enabling PCI PM substates*/
749 if (parent->current_state != PCI_D0 || child->current_state != PCI_D0) {
750 state &= ~ASPM_STATE_L1_SS_PCIPM;
751 state |= (link->aspm_enabled & ASPM_STATE_L1_SS_PCIPM);
754 /* Nothing to do if the link is already in the requested state */
755 if (link->aspm_enabled == state)
757 /* Convert ASPM state to upstream/downstream ASPM register state */
758 if (state & ASPM_STATE_L0S_UP)
759 dwstream |= PCI_EXP_LNKCTL_ASPM_L0S;
760 if (state & ASPM_STATE_L0S_DW)
761 upstream |= PCI_EXP_LNKCTL_ASPM_L0S;
762 if (state & ASPM_STATE_L1) {
763 upstream |= PCI_EXP_LNKCTL_ASPM_L1;
764 dwstream |= PCI_EXP_LNKCTL_ASPM_L1;
767 if (link->aspm_capable & ASPM_STATE_L1SS)
768 pcie_config_aspm_l1ss(link, state);
771 * Spec 2.0 suggests all functions should be configured the
772 * same setting for ASPM. Enabling ASPM L1 should be done in
773 * upstream component first and then downstream, and vice
774 * versa for disabling ASPM L1. Spec doesn't mention L0S.
776 if (state & ASPM_STATE_L1)
777 pcie_config_aspm_dev(parent, upstream);
778 list_for_each_entry(child, &linkbus->devices, bus_list)
779 pcie_config_aspm_dev(child, dwstream);
780 if (!(state & ASPM_STATE_L1))
781 pcie_config_aspm_dev(parent, upstream);
783 link->aspm_enabled = state;
786 static void pcie_config_aspm_path(struct pcie_link_state *link)
789 pcie_config_aspm_link(link, policy_to_aspm_state(link));
794 static void free_link_state(struct pcie_link_state *link)
796 link->pdev->link_state = NULL;
800 static int pcie_aspm_sanity_check(struct pci_dev *pdev)
802 struct pci_dev *child;
806 * Some functions in a slot might not all be PCIe functions,
807 * very strange. Disable ASPM for the whole slot
809 list_for_each_entry(child, &pdev->subordinate->devices, bus_list) {
810 if (!pci_is_pcie(child))
814 * If ASPM is disabled then we're not going to change
815 * the BIOS state. It's safe to continue even if it's a
823 * Disable ASPM for pre-1.1 PCIe device, we follow MS to use
824 * RBER bit to determine if a function is 1.1 version device
826 pcie_capability_read_dword(child, PCI_EXP_DEVCAP, ®32);
827 if (!(reg32 & PCI_EXP_DEVCAP_RBER) && !aspm_force) {
828 pci_info(child, "disabling ASPM on pre-1.1 PCIe device. You can enable it with 'pcie_aspm=force'\n");
835 static struct pcie_link_state *alloc_pcie_link_state(struct pci_dev *pdev)
837 struct pcie_link_state *link;
839 link = kzalloc(sizeof(*link), GFP_KERNEL);
843 INIT_LIST_HEAD(&link->sibling);
845 link->downstream = pci_function_0(pdev->subordinate);
848 * Root Ports and PCI/PCI-X to PCIe Bridges are roots of PCIe
849 * hierarchies. Note that some PCIe host implementations omit
850 * the root ports entirely, in which case a downstream port on
851 * a switch may become the root of the link state chain for all
852 * its subordinate endpoints.
854 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT ||
855 pci_pcie_type(pdev) == PCI_EXP_TYPE_PCIE_BRIDGE ||
856 !pdev->bus->parent->self) {
859 struct pcie_link_state *parent;
861 parent = pdev->bus->parent->self->link_state;
867 link->parent = parent;
868 link->root = link->parent->root;
871 list_add(&link->sibling, &link_list);
872 pdev->link_state = link;
876 static void pcie_aspm_update_sysfs_visibility(struct pci_dev *pdev)
878 struct pci_dev *child;
880 list_for_each_entry(child, &pdev->subordinate->devices, bus_list)
881 sysfs_update_group(&child->dev.kobj, &aspm_ctrl_attr_group);
885 * pcie_aspm_init_link_state: Initiate PCI express link state.
886 * It is called after the pcie and its children devices are scanned.
887 * @pdev: the root port or switch downstream port
889 void pcie_aspm_init_link_state(struct pci_dev *pdev)
891 struct pcie_link_state *link;
892 int blacklist = !!pcie_aspm_sanity_check(pdev);
894 if (!aspm_support_enabled)
897 if (pdev->link_state)
901 * We allocate pcie_link_state for the component on the upstream
902 * end of a Link, so there's nothing to do unless this device is
905 if (!pcie_downstream_port(pdev))
908 /* VIA has a strange chipset, root port is under a bridge */
909 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT &&
913 down_read(&pci_bus_sem);
914 if (list_empty(&pdev->subordinate->devices))
917 mutex_lock(&aspm_lock);
918 link = alloc_pcie_link_state(pdev);
922 * Setup initial ASPM state. Note that we need to configure
923 * upstream links also because capable state of them can be
924 * update through pcie_aspm_cap_init().
926 pcie_aspm_cap_init(link, blacklist);
928 /* Setup initial Clock PM state */
929 pcie_clkpm_cap_init(link, blacklist);
932 * At this stage drivers haven't had an opportunity to change the
933 * link policy setting. Enabling ASPM on broken hardware can cripple
934 * it even before the driver has had a chance to disable ASPM, so
935 * default to a safe level right now. If we're enabling ASPM beyond
936 * the BIOS's expectation, we'll do so once pci_enable_device() is
939 if (aspm_policy != POLICY_POWERSAVE &&
940 aspm_policy != POLICY_POWER_SUPERSAVE) {
941 pcie_config_aspm_path(link);
942 pcie_set_clkpm(link, policy_to_clkpm_state(link));
945 pcie_aspm_update_sysfs_visibility(pdev);
948 mutex_unlock(&aspm_lock);
950 up_read(&pci_bus_sem);
953 /* Recheck latencies and update aspm_capable for links under the root */
954 static void pcie_update_aspm_capable(struct pcie_link_state *root)
956 struct pcie_link_state *link;
957 BUG_ON(root->parent);
958 list_for_each_entry(link, &link_list, sibling) {
959 if (link->root != root)
961 link->aspm_capable = link->aspm_support;
963 list_for_each_entry(link, &link_list, sibling) {
964 struct pci_dev *child;
965 struct pci_bus *linkbus = link->pdev->subordinate;
966 if (link->root != root)
968 list_for_each_entry(child, &linkbus->devices, bus_list) {
969 if ((pci_pcie_type(child) != PCI_EXP_TYPE_ENDPOINT) &&
970 (pci_pcie_type(child) != PCI_EXP_TYPE_LEG_END))
972 pcie_aspm_check_latency(child);
977 /* @pdev: the endpoint device */
978 void pcie_aspm_exit_link_state(struct pci_dev *pdev)
980 struct pci_dev *parent = pdev->bus->self;
981 struct pcie_link_state *link, *root, *parent_link;
983 if (!parent || !parent->link_state)
986 down_read(&pci_bus_sem);
987 mutex_lock(&aspm_lock);
989 * All PCIe functions are in one slot, remove one function will remove
990 * the whole slot, so just wait until we are the last function left.
992 if (!list_empty(&parent->subordinate->devices))
995 link = parent->link_state;
997 parent_link = link->parent;
999 /* All functions are removed, so just disable ASPM for the link */
1000 pcie_config_aspm_link(link, 0);
1001 list_del(&link->sibling);
1002 /* Clock PM is for endpoint device */
1003 free_link_state(link);
1005 /* Recheck latencies and configure upstream links */
1007 pcie_update_aspm_capable(root);
1008 pcie_config_aspm_path(parent_link);
1011 mutex_unlock(&aspm_lock);
1012 up_read(&pci_bus_sem);
1015 void pcie_aspm_powersave_config_link(struct pci_dev *pdev)
1017 struct pcie_link_state *link = pdev->link_state;
1019 if (aspm_disabled || !link)
1022 if (aspm_policy != POLICY_POWERSAVE &&
1023 aspm_policy != POLICY_POWER_SUPERSAVE)
1026 down_read(&pci_bus_sem);
1027 mutex_lock(&aspm_lock);
1028 pcie_config_aspm_path(link);
1029 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1030 mutex_unlock(&aspm_lock);
1031 up_read(&pci_bus_sem);
1034 static struct pcie_link_state *pcie_aspm_get_link(struct pci_dev *pdev)
1036 struct pci_dev *bridge;
1038 if (!pci_is_pcie(pdev))
1041 bridge = pci_upstream_bridge(pdev);
1042 if (!bridge || !pci_is_pcie(bridge))
1045 return bridge->link_state;
1048 static int __pci_disable_link_state(struct pci_dev *pdev, int state, bool sem)
1050 struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1055 * A driver requested that ASPM be disabled on this device, but
1056 * if we don't have permission to manage ASPM (e.g., on ACPI
1057 * systems we have to observe the FADT ACPI_FADT_NO_ASPM bit and
1058 * the _OSC method), we can't honor that request. Windows has
1059 * a similar mechanism using "PciASPMOptOut", which is also
1060 * ignored in this situation.
1062 if (aspm_disabled) {
1063 pci_warn(pdev, "can't disable ASPM; OS doesn't have ASPM control\n");
1068 down_read(&pci_bus_sem);
1069 mutex_lock(&aspm_lock);
1070 if (state & PCIE_LINK_STATE_L0S)
1071 link->aspm_disable |= ASPM_STATE_L0S;
1072 if (state & PCIE_LINK_STATE_L1)
1073 /* L1 PM substates require L1 */
1074 link->aspm_disable |= ASPM_STATE_L1 | ASPM_STATE_L1SS;
1075 if (state & PCIE_LINK_STATE_L1_1)
1076 link->aspm_disable |= ASPM_STATE_L1_1;
1077 if (state & PCIE_LINK_STATE_L1_2)
1078 link->aspm_disable |= ASPM_STATE_L1_2;
1079 if (state & PCIE_LINK_STATE_L1_1_PCIPM)
1080 link->aspm_disable |= ASPM_STATE_L1_1_PCIPM;
1081 if (state & PCIE_LINK_STATE_L1_2_PCIPM)
1082 link->aspm_disable |= ASPM_STATE_L1_2_PCIPM;
1083 pcie_config_aspm_link(link, policy_to_aspm_state(link));
1085 if (state & PCIE_LINK_STATE_CLKPM)
1086 link->clkpm_disable = 1;
1087 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1088 mutex_unlock(&aspm_lock);
1090 up_read(&pci_bus_sem);
1095 int pci_disable_link_state_locked(struct pci_dev *pdev, int state)
1097 return __pci_disable_link_state(pdev, state, false);
1099 EXPORT_SYMBOL(pci_disable_link_state_locked);
1102 * pci_disable_link_state - Disable device's link state, so the link will
1103 * never enter specific states. Note that if the BIOS didn't grant ASPM
1104 * control to the OS, this does nothing because we can't touch the LNKCTL
1105 * register. Returns 0 or a negative errno.
1108 * @state: ASPM link state to disable
1110 int pci_disable_link_state(struct pci_dev *pdev, int state)
1112 return __pci_disable_link_state(pdev, state, true);
1114 EXPORT_SYMBOL(pci_disable_link_state);
1116 static int pcie_aspm_set_policy(const char *val,
1117 const struct kernel_param *kp)
1120 struct pcie_link_state *link;
1124 i = sysfs_match_string(policy_str, val);
1127 if (i == aspm_policy)
1130 down_read(&pci_bus_sem);
1131 mutex_lock(&aspm_lock);
1133 list_for_each_entry(link, &link_list, sibling) {
1134 pcie_config_aspm_link(link, policy_to_aspm_state(link));
1135 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1137 mutex_unlock(&aspm_lock);
1138 up_read(&pci_bus_sem);
1142 static int pcie_aspm_get_policy(char *buffer, const struct kernel_param *kp)
1145 for (i = 0; i < ARRAY_SIZE(policy_str); i++)
1146 if (i == aspm_policy)
1147 cnt += sprintf(buffer + cnt, "[%s] ", policy_str[i]);
1149 cnt += sprintf(buffer + cnt, "%s ", policy_str[i]);
1150 cnt += sprintf(buffer + cnt, "\n");
1154 module_param_call(policy, pcie_aspm_set_policy, pcie_aspm_get_policy,
1158 * pcie_aspm_enabled - Check if PCIe ASPM has been enabled for a device.
1159 * @pdev: Target device.
1161 * Relies on the upstream bridge's link_state being valid. The link_state
1162 * is deallocated only when the last child of the bridge (i.e., @pdev or a
1163 * sibling) is removed, and the caller should be holding a reference to
1164 * @pdev, so this should be safe.
1166 bool pcie_aspm_enabled(struct pci_dev *pdev)
1168 struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1173 return link->aspm_enabled;
1175 EXPORT_SYMBOL_GPL(pcie_aspm_enabled);
1177 static ssize_t aspm_attr_show_common(struct device *dev,
1178 struct device_attribute *attr,
1179 char *buf, u8 state)
1181 struct pci_dev *pdev = to_pci_dev(dev);
1182 struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1184 return sysfs_emit(buf, "%d\n", (link->aspm_enabled & state) ? 1 : 0);
1187 static ssize_t aspm_attr_store_common(struct device *dev,
1188 struct device_attribute *attr,
1189 const char *buf, size_t len, u8 state)
1191 struct pci_dev *pdev = to_pci_dev(dev);
1192 struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1195 if (kstrtobool(buf, &state_enable) < 0)
1198 down_read(&pci_bus_sem);
1199 mutex_lock(&aspm_lock);
1202 link->aspm_disable &= ~state;
1203 /* need to enable L1 for substates */
1204 if (state & ASPM_STATE_L1SS)
1205 link->aspm_disable &= ~ASPM_STATE_L1;
1207 link->aspm_disable |= state;
1210 pcie_config_aspm_link(link, policy_to_aspm_state(link));
1212 mutex_unlock(&aspm_lock);
1213 up_read(&pci_bus_sem);
1218 #define ASPM_ATTR(_f, _s) \
1219 static ssize_t _f##_show(struct device *dev, \
1220 struct device_attribute *attr, char *buf) \
1221 { return aspm_attr_show_common(dev, attr, buf, ASPM_STATE_##_s); } \
1223 static ssize_t _f##_store(struct device *dev, \
1224 struct device_attribute *attr, \
1225 const char *buf, size_t len) \
1226 { return aspm_attr_store_common(dev, attr, buf, len, ASPM_STATE_##_s); }
1228 ASPM_ATTR(l0s_aspm, L0S)
1229 ASPM_ATTR(l1_aspm, L1)
1230 ASPM_ATTR(l1_1_aspm, L1_1)
1231 ASPM_ATTR(l1_2_aspm, L1_2)
1232 ASPM_ATTR(l1_1_pcipm, L1_1_PCIPM)
1233 ASPM_ATTR(l1_2_pcipm, L1_2_PCIPM)
1235 static ssize_t clkpm_show(struct device *dev,
1236 struct device_attribute *attr, char *buf)
1238 struct pci_dev *pdev = to_pci_dev(dev);
1239 struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1241 return sysfs_emit(buf, "%d\n", link->clkpm_enabled);
1244 static ssize_t clkpm_store(struct device *dev,
1245 struct device_attribute *attr,
1246 const char *buf, size_t len)
1248 struct pci_dev *pdev = to_pci_dev(dev);
1249 struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1252 if (kstrtobool(buf, &state_enable) < 0)
1255 down_read(&pci_bus_sem);
1256 mutex_lock(&aspm_lock);
1258 link->clkpm_disable = !state_enable;
1259 pcie_set_clkpm(link, policy_to_clkpm_state(link));
1261 mutex_unlock(&aspm_lock);
1262 up_read(&pci_bus_sem);
1267 static DEVICE_ATTR_RW(clkpm);
1268 static DEVICE_ATTR_RW(l0s_aspm);
1269 static DEVICE_ATTR_RW(l1_aspm);
1270 static DEVICE_ATTR_RW(l1_1_aspm);
1271 static DEVICE_ATTR_RW(l1_2_aspm);
1272 static DEVICE_ATTR_RW(l1_1_pcipm);
1273 static DEVICE_ATTR_RW(l1_2_pcipm);
1275 static struct attribute *aspm_ctrl_attrs[] = {
1276 &dev_attr_clkpm.attr,
1277 &dev_attr_l0s_aspm.attr,
1278 &dev_attr_l1_aspm.attr,
1279 &dev_attr_l1_1_aspm.attr,
1280 &dev_attr_l1_2_aspm.attr,
1281 &dev_attr_l1_1_pcipm.attr,
1282 &dev_attr_l1_2_pcipm.attr,
1286 static umode_t aspm_ctrl_attrs_are_visible(struct kobject *kobj,
1287 struct attribute *a, int n)
1289 struct device *dev = kobj_to_dev(kobj);
1290 struct pci_dev *pdev = to_pci_dev(dev);
1291 struct pcie_link_state *link = pcie_aspm_get_link(pdev);
1292 static const u8 aspm_state_map[] = {
1297 ASPM_STATE_L1_1_PCIPM,
1298 ASPM_STATE_L1_2_PCIPM,
1301 if (aspm_disabled || !link)
1305 return link->clkpm_capable ? a->mode : 0;
1307 return link->aspm_capable & aspm_state_map[n - 1] ? a->mode : 0;
1310 const struct attribute_group aspm_ctrl_attr_group = {
1312 .attrs = aspm_ctrl_attrs,
1313 .is_visible = aspm_ctrl_attrs_are_visible,
1316 static int __init pcie_aspm_disable(char *str)
1318 if (!strcmp(str, "off")) {
1319 aspm_policy = POLICY_DEFAULT;
1321 aspm_support_enabled = false;
1322 printk(KERN_INFO "PCIe ASPM is disabled\n");
1323 } else if (!strcmp(str, "force")) {
1325 printk(KERN_INFO "PCIe ASPM is forcibly enabled\n");
1330 __setup("pcie_aspm=", pcie_aspm_disable);
1332 void pcie_no_aspm(void)
1335 * Disabling ASPM is intended to prevent the kernel from modifying
1336 * existing hardware state, not to clear existing state. To that end:
1337 * (a) set policy to POLICY_DEFAULT in order to avoid changing state
1338 * (b) prevent userspace from changing policy
1341 aspm_policy = POLICY_DEFAULT;
1346 bool pcie_aspm_support_enabled(void)
1348 return aspm_support_enabled;