drivers/net/phy/micrel.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * drivers/net/phy/micrel.c
   4  *
   5  * Driver for Micrel PHYs
   6  *
   7  * Author: David J. Choi
   8  *
   9  * Copyright (c) 2010-2013 Micrel, Inc.
  10  * Copyright (c) 2014 Johan Hovold <[email protected]>
  11  *
  12  * Support : Micrel Phys:
  13  *              Giga phys: ksz9021, ksz9031, ksz9131
  14  *              100/10 Phys : ksz8001, ksz8721, ksz8737, ksz8041
  15  *                         ksz8021, ksz8031, ksz8051,
  16  *                         ksz8081, ksz8091,
  17  *                         ksz8061,
  18  *              Switch : ksz8873, ksz886x
  19  *                       ksz9477
  20  */
  21
  22 #include <linux/bitfield.h>
  23 #include <linux/ethtool_netlink.h>
  24 #include <linux/kernel.h>
  25 #include <linux/module.h>
  26 #include <linux/phy.h>
  27 #include <linux/micrel_phy.h>
  28 #include <linux/of.h>
  29 #include <linux/clk.h>
  30 #include <linux/delay.h>
  31 #include <linux/ptp_clock_kernel.h>
  32 #include <linux/ptp_clock.h>
  33 #include <linux/ptp_classify.h>
  34 #include <linux/net_tstamp.h>
  35 #include <linux/gpio/consumer.h>
  36
  37 /* Operation Mode Strap Override */
  38 #define MII_KSZPHY_OMSO                         0x16
  39 #define KSZPHY_OMSO_FACTORY_TEST                BIT(15)
  40 #define KSZPHY_OMSO_B_CAST_OFF                  BIT(9)
  41 #define KSZPHY_OMSO_NAND_TREE_ON                BIT(5)
  42 #define KSZPHY_OMSO_RMII_OVERRIDE               BIT(1)
  43 #define KSZPHY_OMSO_MII_OVERRIDE                BIT(0)
  44
  45 /* general Interrupt control/status reg in vendor specific block. */
  46 #define MII_KSZPHY_INTCS                        0x1B
  47 #define KSZPHY_INTCS_JABBER                     BIT(15)
  48 #define KSZPHY_INTCS_RECEIVE_ERR                BIT(14)
  49 #define KSZPHY_INTCS_PAGE_RECEIVE               BIT(13)
  50 #define KSZPHY_INTCS_PARELLEL                   BIT(12)
  51 #define KSZPHY_INTCS_LINK_PARTNER_ACK           BIT(11)
  52 #define KSZPHY_INTCS_LINK_DOWN                  BIT(10)
  53 #define KSZPHY_INTCS_REMOTE_FAULT               BIT(9)
  54 #define KSZPHY_INTCS_LINK_UP                    BIT(8)
  55 #define KSZPHY_INTCS_ALL                        (KSZPHY_INTCS_LINK_UP |\
  56                                                 KSZPHY_INTCS_LINK_DOWN)
  57 #define KSZPHY_INTCS_LINK_DOWN_STATUS           BIT(2)
  58 #define KSZPHY_INTCS_LINK_UP_STATUS             BIT(0)
  59 #define KSZPHY_INTCS_STATUS                     (KSZPHY_INTCS_LINK_DOWN_STATUS |\
  60                                                  KSZPHY_INTCS_LINK_UP_STATUS)
  61
  62 /* LinkMD Control/Status */
  63 #define KSZ8081_LMD                             0x1d
  64 #define KSZ8081_LMD_ENABLE_TEST                 BIT(15)
  65 #define KSZ8081_LMD_STAT_NORMAL                 0
  66 #define KSZ8081_LMD_STAT_OPEN                   1
  67 #define KSZ8081_LMD_STAT_SHORT                  2
  68 #define KSZ8081_LMD_STAT_FAIL                   3
  69 #define KSZ8081_LMD_STAT_MASK                   GENMASK(14, 13)
  70 /* Short cable (<10 meter) has been detected by LinkMD */
  71 #define KSZ8081_LMD_SHORT_INDICATOR             BIT(12)
  72 #define KSZ8081_LMD_DELTA_TIME_MASK             GENMASK(8, 0)
  73
  74 #define KSZ9x31_LMD                             0x12
  75 #define KSZ9x31_LMD_VCT_EN                      BIT(15)
  76 #define KSZ9x31_LMD_VCT_DIS_TX                  BIT(14)
  77 #define KSZ9x31_LMD_VCT_PAIR(n)                 (((n) & 0x3) << 12)
  78 #define KSZ9x31_LMD_VCT_SEL_RESULT              0
  79 #define KSZ9x31_LMD_VCT_SEL_THRES_HI            BIT(10)
  80 #define KSZ9x31_LMD_VCT_SEL_THRES_LO            BIT(11)
  81 #define KSZ9x31_LMD_VCT_SEL_MASK                GENMASK(11, 10)
  82 #define KSZ9x31_LMD_VCT_ST_NORMAL               0
  83 #define KSZ9x31_LMD_VCT_ST_OPEN                 1
  84 #define KSZ9x31_LMD_VCT_ST_SHORT                2
  85 #define KSZ9x31_LMD_VCT_ST_FAIL                 3
  86 #define KSZ9x31_LMD_VCT_ST_MASK                 GENMASK(9, 8)
  87 #define KSZ9x31_LMD_VCT_DATA_REFLECTED_INVALID  BIT(7)
  88 #define KSZ9x31_LMD_VCT_DATA_SIG_WAIT_TOO_LONG  BIT(6)
  89 #define KSZ9x31_LMD_VCT_DATA_MASK100            BIT(5)
  90 #define KSZ9x31_LMD_VCT_DATA_NLP_FLP            BIT(4)
  91 #define KSZ9x31_LMD_VCT_DATA_LO_PULSE_MASK      GENMASK(3, 2)
  92 #define KSZ9x31_LMD_VCT_DATA_HI_PULSE_MASK      GENMASK(1, 0)
  93 #define KSZ9x31_LMD_VCT_DATA_MASK               GENMASK(7, 0)
  94
  95 /* Lan8814 general Interrupt control/status reg in GPHY specific block. */
  96 #define LAN8814_INTC                            0x18
  97 #define LAN8814_INTS                            0x1B
  98
  99 #define LAN8814_INT_LINK_DOWN                   BIT(2)
 100 #define LAN8814_INT_LINK_UP                     BIT(0)
 101 #define LAN8814_INT_LINK                        (LAN8814_INT_LINK_UP |\
 102                                                  LAN8814_INT_LINK_DOWN)
 103
 104 #define LAN8814_INTR_CTRL_REG                   0x34
 105 #define LAN8814_INTR_CTRL_REG_POLARITY          BIT(1)
 106 #define LAN8814_INTR_CTRL_REG_INTR_ENABLE       BIT(0)
 107
 108 /* Represents 1ppm adjustment in 2^32 format with
 109  * each nsec contains 4 clock cycles.
 110  * The value is calculated as following: (1/1000000)/((2^-32)/4)
 111  */
 112 #define LAN8814_1PPM_FORMAT                     17179
 113
 114 #define PTP_RX_MOD                              0x024F
 115 #define PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)
 116 #define PTP_RX_TIMESTAMP_EN                     0x024D
 117 #define PTP_TX_TIMESTAMP_EN                     0x028D
 118
 119 #define PTP_TIMESTAMP_EN_SYNC_                  BIT(0)
 120 #define PTP_TIMESTAMP_EN_DREQ_                  BIT(1)
 121 #define PTP_TIMESTAMP_EN_PDREQ_                 BIT(2)
 122 #define PTP_TIMESTAMP_EN_PDRES_                 BIT(3)
 123
 124 #define PTP_TX_PARSE_L2_ADDR_EN                 0x0284
 125 #define PTP_RX_PARSE_L2_ADDR_EN                 0x0244
 126
 127 #define PTP_TX_PARSE_IP_ADDR_EN                 0x0285
 128 #define PTP_RX_PARSE_IP_ADDR_EN                 0x0245
 129 #define LTC_HARD_RESET                          0x023F
 130 #define LTC_HARD_RESET_                         BIT(0)
 131
 132 #define TSU_HARD_RESET                          0x02C1
 133 #define TSU_HARD_RESET_                         BIT(0)
 134
 135 #define PTP_CMD_CTL                             0x0200
 136 #define PTP_CMD_CTL_PTP_DISABLE_                BIT(0)
 137 #define PTP_CMD_CTL_PTP_ENABLE_                 BIT(1)
 138 #define PTP_CMD_CTL_PTP_CLOCK_READ_             BIT(3)
 139 #define PTP_CMD_CTL_PTP_CLOCK_LOAD_             BIT(4)
 140 #define PTP_CMD_CTL_PTP_LTC_STEP_SEC_           BIT(5)
 141 #define PTP_CMD_CTL_PTP_LTC_STEP_NSEC_          BIT(6)
 142
 143 #define PTP_CLOCK_SET_SEC_MID                   0x0206
 144 #define PTP_CLOCK_SET_SEC_LO                    0x0207
 145 #define PTP_CLOCK_SET_NS_HI                     0x0208
 146 #define PTP_CLOCK_SET_NS_LO                     0x0209
 147
 148 #define PTP_CLOCK_READ_SEC_MID                  0x022A
 149 #define PTP_CLOCK_READ_SEC_LO                   0x022B
 150 #define PTP_CLOCK_READ_NS_HI                    0x022C
 151 #define PTP_CLOCK_READ_NS_LO                    0x022D
 152
 153 #define PTP_OPERATING_MODE                      0x0241
 154 #define PTP_OPERATING_MODE_STANDALONE_          BIT(0)
 155
 156 #define PTP_TX_MOD                              0x028F
 157 #define PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_       BIT(12)
 158 #define PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_ BIT(3)
 159
 160 #define PTP_RX_PARSE_CONFIG                     0x0242
 161 #define PTP_RX_PARSE_CONFIG_LAYER2_EN_          BIT(0)
 162 #define PTP_RX_PARSE_CONFIG_IPV4_EN_            BIT(1)
 163 #define PTP_RX_PARSE_CONFIG_IPV6_EN_            BIT(2)
 164
 165 #define PTP_TX_PARSE_CONFIG                     0x0282
 166 #define PTP_TX_PARSE_CONFIG_LAYER2_EN_          BIT(0)
 167 #define PTP_TX_PARSE_CONFIG_IPV4_EN_            BIT(1)
 168 #define PTP_TX_PARSE_CONFIG_IPV6_EN_            BIT(2)
 169
 170 #define PTP_CLOCK_RATE_ADJ_HI                   0x020C
 171 #define PTP_CLOCK_RATE_ADJ_LO                   0x020D
 172 #define PTP_CLOCK_RATE_ADJ_DIR_                 BIT(15)
 173
 174 #define PTP_LTC_STEP_ADJ_HI                     0x0212
 175 #define PTP_LTC_STEP_ADJ_LO                     0x0213
 176 #define PTP_LTC_STEP_ADJ_DIR_                   BIT(15)
 177
 178 #define LAN8814_INTR_STS_REG                    0x0033
 179 #define LAN8814_INTR_STS_REG_1588_TSU0_         BIT(0)
 180 #define LAN8814_INTR_STS_REG_1588_TSU1_         BIT(1)
 181 #define LAN8814_INTR_STS_REG_1588_TSU2_         BIT(2)
 182 #define LAN8814_INTR_STS_REG_1588_TSU3_         BIT(3)
 183
 184 #define PTP_CAP_INFO                            0x022A
 185 #define PTP_CAP_INFO_TX_TS_CNT_GET_(reg_val)    (((reg_val) & 0x0f00) >> 8)
 186 #define PTP_CAP_INFO_RX_TS_CNT_GET_(reg_val)    ((reg_val) & 0x000f)
 187
 188 #define PTP_TX_EGRESS_SEC_HI                    0x0296
 189 #define PTP_TX_EGRESS_SEC_LO                    0x0297
 190 #define PTP_TX_EGRESS_NS_HI                     0x0294
 191 #define PTP_TX_EGRESS_NS_LO                     0x0295
 192 #define PTP_TX_MSG_HEADER2                      0x0299
 193
 194 #define PTP_RX_INGRESS_SEC_HI                   0x0256
 195 #define PTP_RX_INGRESS_SEC_LO                   0x0257
 196 #define PTP_RX_INGRESS_NS_HI                    0x0254
 197 #define PTP_RX_INGRESS_NS_LO                    0x0255
 198 #define PTP_RX_MSG_HEADER2                      0x0259
 199
 200 #define PTP_TSU_INT_EN                          0x0200
 201 #define PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_      BIT(3)
 202 #define PTP_TSU_INT_EN_PTP_TX_TS_EN_            BIT(2)
 203 #define PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_      BIT(1)
 204 #define PTP_TSU_INT_EN_PTP_RX_TS_EN_            BIT(0)
 205
 206 #define PTP_TSU_INT_STS                         0x0201
 207 #define PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_    BIT(3)
 208 #define PTP_TSU_INT_STS_PTP_TX_TS_EN_           BIT(2)
 209 #define PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_    BIT(1)
 210 #define PTP_TSU_INT_STS_PTP_RX_TS_EN_           BIT(0)
 211
 212 #define LAN8814_LED_CTRL_1                      0x0
 213 #define LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_    BIT(6)
 214
 215 /* PHY Control 1 */
 216 #define MII_KSZPHY_CTRL_1                       0x1e
 217 #define KSZ8081_CTRL1_MDIX_STAT                 BIT(4)
 218
 219 /* PHY Control 2 / PHY Control (if no PHY Control 1) */
 220 #define MII_KSZPHY_CTRL_2                       0x1f
 221 #define MII_KSZPHY_CTRL                         MII_KSZPHY_CTRL_2
 222 /* bitmap of PHY register to set interrupt mode */
 223 #define KSZ8081_CTRL2_HP_MDIX                   BIT(15)
 224 #define KSZ8081_CTRL2_MDI_MDI_X_SELECT          BIT(14)
 225 #define KSZ8081_CTRL2_DISABLE_AUTO_MDIX         BIT(13)
 226 #define KSZ8081_CTRL2_FORCE_LINK                BIT(11)
 227 #define KSZ8081_CTRL2_POWER_SAVING              BIT(10)
 228 #define KSZPHY_CTRL_INT_ACTIVE_HIGH             BIT(9)
 229 #define KSZPHY_RMII_REF_CLK_SEL                 BIT(7)
 230
 231 /* Write/read to/from extended registers */
 232 #define MII_KSZPHY_EXTREG                       0x0b
 233 #define KSZPHY_EXTREG_WRITE                     0x8000
 234
 235 #define MII_KSZPHY_EXTREG_WRITE                 0x0c
 236 #define MII_KSZPHY_EXTREG_READ                  0x0d
 237
 238 /* Extended registers */
 239 #define MII_KSZPHY_CLK_CONTROL_PAD_SKEW         0x104
 240 #define MII_KSZPHY_RX_DATA_PAD_SKEW             0x105
 241 #define MII_KSZPHY_TX_DATA_PAD_SKEW             0x106
 242
 243 #define PS_TO_REG                               200
 244 #define FIFO_SIZE                               8
 245
 246 struct kszphy_hw_stat {
 247         const char *string;
 248         u8 reg;
 249         u8 bits;
 250 };
 251
 252 static struct kszphy_hw_stat kszphy_hw_stats[] = {
 253         { "phy_receive_errors", 21, 16},
 254         { "phy_idle_errors", 10, 8 },
 255 };
 256
 257 struct kszphy_type {
 258         u32 led_mode_reg;
 259         u16 interrupt_level_mask;
 260         bool has_broadcast_disable;
 261         bool has_nand_tree_disable;
 262         bool has_rmii_ref_clk_sel;
 263 };
 264
 265 /* Shared structure between the PHYs of the same package. */
 266 struct lan8814_shared_priv {
 267         struct phy_device *phydev;
 268         struct ptp_clock *ptp_clock;
 269         struct ptp_clock_info ptp_clock_info;
 270
 271         /* Reference counter to how many ports in the package are enabling the
 272          * timestamping
 273          */
 274         u8 ref;
 275
 276         /* Lock for ptp_clock and ref */
 277         struct mutex shared_lock;
 278 };
 279
 280 struct lan8814_ptp_rx_ts {
 281         struct list_head list;
 282         u32 seconds;
 283         u32 nsec;
 284         u16 seq_id;
 285 };
 286
 287 struct kszphy_ptp_priv {
 288         struct mii_timestamper mii_ts;
 289         struct phy_device *phydev;
 290
 291         struct sk_buff_head tx_queue;
 292         struct sk_buff_head rx_queue;
 293
 294         struct list_head rx_ts_list;
 295         /* Lock for Rx ts fifo */
 296         spinlock_t rx_ts_lock;
 297
 298         int hwts_tx_type;
 299         enum hwtstamp_rx_filters rx_filter;
 300         int layer;
 301         int version;
 302 };
 303
 304 struct kszphy_priv {
 305         struct kszphy_ptp_priv ptp_priv;
 306         const struct kszphy_type *type;
 307         int led_mode;
 308         u16 vct_ctrl1000;
 309         bool rmii_ref_clk_sel;
 310         bool rmii_ref_clk_sel_val;
 311         u64 stats[ARRAY_SIZE(kszphy_hw_stats)];
 312 };
 313
 314 static const struct kszphy_type lan8814_type = {
 315         .led_mode_reg           = ~LAN8814_LED_CTRL_1,
 316 };
 317
 318 static const struct kszphy_type ksz8021_type = {
 319         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 320         .has_broadcast_disable  = true,
 321         .has_nand_tree_disable  = true,
 322         .has_rmii_ref_clk_sel   = true,
 323 };
 324
 325 static const struct kszphy_type ksz8041_type = {
 326         .led_mode_reg           = MII_KSZPHY_CTRL_1,
 327 };
 328
 329 static const struct kszphy_type ksz8051_type = {
 330         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 331         .has_nand_tree_disable  = true,
 332 };
 333
 334 static const struct kszphy_type ksz8081_type = {
 335         .led_mode_reg           = MII_KSZPHY_CTRL_2,
 336         .has_broadcast_disable  = true,
 337         .has_nand_tree_disable  = true,
 338         .has_rmii_ref_clk_sel   = true,
 339 };
 340
 341 static const struct kszphy_type ks8737_type = {
 342         .interrupt_level_mask   = BIT(14),
 343 };
 344
 345 static const struct kszphy_type ksz9021_type = {
 346         .interrupt_level_mask   = BIT(14),
 347 };
 348
 349 static int kszphy_extended_write(struct phy_device *phydev,
 350                                 u32 regnum, u16 val)
 351 {
 352         phy_write(phydev, MII_KSZPHY_EXTREG, KSZPHY_EXTREG_WRITE | regnum);
 353         return phy_write(phydev, MII_KSZPHY_EXTREG_WRITE, val);
 354 }
 355
 356 static int kszphy_extended_read(struct phy_device *phydev,
 357                                 u32 regnum)
 358 {
 359         phy_write(phydev, MII_KSZPHY_EXTREG, regnum);
 360         return phy_read(phydev, MII_KSZPHY_EXTREG_READ);
 361 }
 362
 363 static int kszphy_ack_interrupt(struct phy_device *phydev)
 364 {
 365         /* bit[7..0] int status, which is a read and clear register. */
 366         int rc;
 367
 368         rc = phy_read(phydev, MII_KSZPHY_INTCS);
 369
 370         return (rc < 0) ? rc : 0;
 371 }
 372
 373 static int kszphy_config_intr(struct phy_device *phydev)
 374 {
 375         const struct kszphy_type *type = phydev->drv->driver_data;
 376         int temp, err;
 377         u16 mask;
 378
 379         if (type && type->interrupt_level_mask)
 380                 mask = type->interrupt_level_mask;
 381         else
 382                 mask = KSZPHY_CTRL_INT_ACTIVE_HIGH;
 383
 384         /* set the interrupt pin active low */
 385         temp = phy_read(phydev, MII_KSZPHY_CTRL);
 386         if (temp < 0)
 387                 return temp;
 388         temp &= ~mask;
 389         phy_write(phydev, MII_KSZPHY_CTRL, temp);
 390
 391         /* enable / disable interrupts */
 392         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
 393                 err = kszphy_ack_interrupt(phydev);
 394                 if (err)
 395                         return err;
 396
 397                 temp = KSZPHY_INTCS_ALL;
 398                 err = phy_write(phydev, MII_KSZPHY_INTCS, temp);
 399         } else {
 400                 temp = 0;
 401                 err = phy_write(phydev, MII_KSZPHY_INTCS, temp);
 402                 if (err)
 403                         return err;
 404
 405                 err = kszphy_ack_interrupt(phydev);
 406         }
 407
 408         return err;
 409 }
 410
 411 static irqreturn_t kszphy_handle_interrupt(struct phy_device *phydev)
 412 {
 413         int irq_status;
 414
 415         irq_status = phy_read(phydev, MII_KSZPHY_INTCS);
 416         if (irq_status < 0) {
 417                 phy_error(phydev);
 418                 return IRQ_NONE;
 419         }
 420
 421         if (!(irq_status & KSZPHY_INTCS_STATUS))
 422                 return IRQ_NONE;
 423
 424         phy_trigger_machine(phydev);
 425
 426         return IRQ_HANDLED;
 427 }
 428
 429 static int kszphy_rmii_clk_sel(struct phy_device *phydev, bool val)
 430 {
 431         int ctrl;
 432
 433         ctrl = phy_read(phydev, MII_KSZPHY_CTRL);
 434         if (ctrl < 0)
 435                 return ctrl;
 436
 437         if (val)
 438                 ctrl |= KSZPHY_RMII_REF_CLK_SEL;
 439         else
 440                 ctrl &= ~KSZPHY_RMII_REF_CLK_SEL;
 441
 442         return phy_write(phydev, MII_KSZPHY_CTRL, ctrl);
 443 }
 444
 445 static int kszphy_setup_led(struct phy_device *phydev, u32 reg, int val)
 446 {
 447         int rc, temp, shift;
 448
 449         switch (reg) {
 450         case MII_KSZPHY_CTRL_1:
 451                 shift = 14;
 452                 break;
 453         case MII_KSZPHY_CTRL_2:
 454                 shift = 4;
 455                 break;
 456         default:
 457                 return -EINVAL;
 458         }
 459
 460         temp = phy_read(phydev, reg);
 461         if (temp < 0) {
 462                 rc = temp;
 463                 goto out;
 464         }
 465
 466         temp &= ~(3 << shift);
 467         temp |= val << shift;
 468         rc = phy_write(phydev, reg, temp);
 469 out:
 470         if (rc < 0)
 471                 phydev_err(phydev, "failed to set led mode\n");
 472
 473         return rc;
 474 }
 475
 476 /* Disable PHY address 0 as the broadcast address, so that it can be used as a
 477  * unique (non-broadcast) address on a shared bus.
 478  */
 479 static int kszphy_broadcast_disable(struct phy_device *phydev)
 480 {
 481         int ret;
 482
 483         ret = phy_read(phydev, MII_KSZPHY_OMSO);
 484         if (ret < 0)
 485                 goto out;
 486
 487         ret = phy_write(phydev, MII_KSZPHY_OMSO, ret | KSZPHY_OMSO_B_CAST_OFF);
 488 out:
 489         if (ret)
 490                 phydev_err(phydev, "failed to disable broadcast address\n");
 491
 492         return ret;
 493 }
 494
 495 static int kszphy_nand_tree_disable(struct phy_device *phydev)
 496 {
 497         int ret;
 498
 499         ret = phy_read(phydev, MII_KSZPHY_OMSO);
 500         if (ret < 0)
 501                 goto out;
 502
 503         if (!(ret & KSZPHY_OMSO_NAND_TREE_ON))
 504                 return 0;
 505
 506         ret = phy_write(phydev, MII_KSZPHY_OMSO,
 507                         ret & ~KSZPHY_OMSO_NAND_TREE_ON);
 508 out:
 509         if (ret)
 510                 phydev_err(phydev, "failed to disable NAND tree mode\n");
 511
 512         return ret;
 513 }
 514
 515 /* Some config bits need to be set again on resume, handle them here. */
 516 static int kszphy_config_reset(struct phy_device *phydev)
 517 {
 518         struct kszphy_priv *priv = phydev->priv;
 519         int ret;
 520
 521         if (priv->rmii_ref_clk_sel) {
 522                 ret = kszphy_rmii_clk_sel(phydev, priv->rmii_ref_clk_sel_val);
 523                 if (ret) {
 524                         phydev_err(phydev,
 525                                    "failed to set rmii reference clock\n");
 526                         return ret;
 527                 }
 528         }
 529
 530         if (priv->type && priv->led_mode >= 0)
 531                 kszphy_setup_led(phydev, priv->type->led_mode_reg, priv->led_mode);
 532
 533         return 0;
 534 }
 535
 536 static int kszphy_config_init(struct phy_device *phydev)
 537 {
 538         struct kszphy_priv *priv = phydev->priv;
 539         const struct kszphy_type *type;
 540
 541         if (!priv)
 542                 return 0;
 543
 544         type = priv->type;
 545
 546         if (type && type->has_broadcast_disable)
 547                 kszphy_broadcast_disable(phydev);
 548
 549         if (type && type->has_nand_tree_disable)
 550                 kszphy_nand_tree_disable(phydev);
 551
 552         return kszphy_config_reset(phydev);
 553 }
 554
 555 static int ksz8041_fiber_mode(struct phy_device *phydev)
 556 {
 557         struct device_node *of_node = phydev->mdio.dev.of_node;
 558
 559         return of_property_read_bool(of_node, "micrel,fiber-mode");
 560 }
 561
 562 static int ksz8041_config_init(struct phy_device *phydev)
 563 {
 564         __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
 565
 566         /* Limit supported and advertised modes in fiber mode */
 567         if (ksz8041_fiber_mode(phydev)) {
 568                 phydev->dev_flags |= MICREL_PHY_FXEN;
 569                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, mask);
 570                 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, mask);
 571
 572                 linkmode_and(phydev->supported, phydev->supported, mask);
 573                 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
 574                                  phydev->supported);
 575                 linkmode_and(phydev->advertising, phydev->advertising, mask);
 576                 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT,
 577                                  phydev->advertising);
 578                 phydev->autoneg = AUTONEG_DISABLE;
 579         }
 580
 581         return kszphy_config_init(phydev);
 582 }
 583
 584 static int ksz8041_config_aneg(struct phy_device *phydev)
 585 {
 586         /* Skip auto-negotiation in fiber mode */
 587         if (phydev->dev_flags & MICREL_PHY_FXEN) {
 588                 phydev->speed = SPEED_100;
 589                 return 0;
 590         }
 591
 592         return genphy_config_aneg(phydev);
 593 }
 594
 595 static int ksz8051_ksz8795_match_phy_device(struct phy_device *phydev,
 596                                             const bool ksz_8051)
 597 {
 598         int ret;
 599
 600         if ((phydev->phy_id & MICREL_PHY_ID_MASK) != PHY_ID_KSZ8051)
 601                 return 0;
 602
 603         ret = phy_read(phydev, MII_BMSR);
 604         if (ret < 0)
 605                 return ret;
 606
 607         /* KSZ8051 PHY and KSZ8794/KSZ8795/KSZ8765 switch share the same
 608          * exact PHY ID. However, they can be told apart by the extended
 609          * capability registers presence. The KSZ8051 PHY has them while
 610          * the switch does not.
 611          */
 612         ret &= BMSR_ERCAP;
 613         if (ksz_8051)
 614                 return ret;
 615         else
 616                 return !ret;
 617 }
 618
 619 static int ksz8051_match_phy_device(struct phy_device *phydev)
 620 {
 621         return ksz8051_ksz8795_match_phy_device(phydev, true);
 622 }
 623
 624 static int ksz8081_config_init(struct phy_device *phydev)
 625 {
 626         /* KSZPHY_OMSO_FACTORY_TEST is set at de-assertion of the reset line
 627          * based on the RXER (KSZ8081RNA/RND) or TXC (KSZ8081MNX/RNB) pin. If a
 628          * pull-down is missing, the factory test mode should be cleared by
 629          * manually writing a 0.
 630          */
 631         phy_clear_bits(phydev, MII_KSZPHY_OMSO, KSZPHY_OMSO_FACTORY_TEST);
 632
 633         return kszphy_config_init(phydev);
 634 }
 635
 636 static int ksz8081_config_mdix(struct phy_device *phydev, u8 ctrl)
 637 {
 638         u16 val;
 639
 640         switch (ctrl) {
 641         case ETH_TP_MDI:
 642                 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX;
 643                 break;
 644         case ETH_TP_MDI_X:
 645                 val = KSZ8081_CTRL2_DISABLE_AUTO_MDIX |
 646                         KSZ8081_CTRL2_MDI_MDI_X_SELECT;
 647                 break;
 648         case ETH_TP_MDI_AUTO:
 649                 val = 0;
 650                 break;
 651         default:
 652                 return 0;
 653         }
 654
 655         return phy_modify(phydev, MII_KSZPHY_CTRL_2,
 656                           KSZ8081_CTRL2_HP_MDIX |
 657                           KSZ8081_CTRL2_MDI_MDI_X_SELECT |
 658                           KSZ8081_CTRL2_DISABLE_AUTO_MDIX,
 659                           KSZ8081_CTRL2_HP_MDIX | val);
 660 }
 661
 662 static int ksz8081_config_aneg(struct phy_device *phydev)
 663 {
 664         int ret;
 665
 666         ret = genphy_config_aneg(phydev);
 667         if (ret)
 668                 return ret;
 669
 670         /* The MDI-X configuration is automatically changed by the PHY after
 671          * switching from autoneg off to on. So, take MDI-X configuration under
 672          * own control and set it after autoneg configuration was done.
 673          */
 674         return ksz8081_config_mdix(phydev, phydev->mdix_ctrl);
 675 }
 676
 677 static int ksz8081_mdix_update(struct phy_device *phydev)
 678 {
 679         int ret;
 680
 681         ret = phy_read(phydev, MII_KSZPHY_CTRL_2);
 682         if (ret < 0)
 683                 return ret;
 684
 685         if (ret & KSZ8081_CTRL2_DISABLE_AUTO_MDIX) {
 686                 if (ret & KSZ8081_CTRL2_MDI_MDI_X_SELECT)
 687                         phydev->mdix_ctrl = ETH_TP_MDI_X;
 688                 else
 689                         phydev->mdix_ctrl = ETH_TP_MDI;
 690         } else {
 691                 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
 692         }
 693
 694         ret = phy_read(phydev, MII_KSZPHY_CTRL_1);
 695         if (ret < 0)
 696                 return ret;
 697
 698         if (ret & KSZ8081_CTRL1_MDIX_STAT)
 699                 phydev->mdix = ETH_TP_MDI;
 700         else
 701                 phydev->mdix = ETH_TP_MDI_X;
 702
 703         return 0;
 704 }
 705
 706 static int ksz8081_read_status(struct phy_device *phydev)
 707 {
 708         int ret;
 709
 710         ret = ksz8081_mdix_update(phydev);
 711         if (ret < 0)
 712                 return ret;
 713
 714         return genphy_read_status(phydev);
 715 }
 716
 717 static int ksz8061_config_init(struct phy_device *phydev)
 718 {
 719         int ret;
 720
 721         ret = phy_write_mmd(phydev, MDIO_MMD_PMAPMD, MDIO_DEVID1, 0xB61A);
 722         if (ret)
 723                 return ret;
 724
 725         return kszphy_config_init(phydev);
 726 }
 727
 728 static int ksz8795_match_phy_device(struct phy_device *phydev)
 729 {
 730         return ksz8051_ksz8795_match_phy_device(phydev, false);
 731 }
 732
 733 static int ksz9021_load_values_from_of(struct phy_device *phydev,
 734                                        const struct device_node *of_node,
 735                                        u16 reg,
 736                                        const char *field1, const char *field2,
 737                                        const char *field3, const char *field4)
 738 {
 739         int val1 = -1;
 740         int val2 = -2;
 741         int val3 = -3;
 742         int val4 = -4;
 743         int newval;
 744         int matches = 0;
 745
 746         if (!of_property_read_u32(of_node, field1, &val1))
 747                 matches++;
 748
 749         if (!of_property_read_u32(of_node, field2, &val2))
 750                 matches++;
 751
 752         if (!of_property_read_u32(of_node, field3, &val3))
 753                 matches++;
 754
 755         if (!of_property_read_u32(of_node, field4, &val4))
 756                 matches++;
 757
 758         if (!matches)
 759                 return 0;
 760
 761         if (matches < 4)
 762                 newval = kszphy_extended_read(phydev, reg);
 763         else
 764                 newval = 0;
 765
 766         if (val1 != -1)
 767                 newval = ((newval & 0xfff0) | ((val1 / PS_TO_REG) & 0xf) << 0);
 768
 769         if (val2 != -2)
 770                 newval = ((newval & 0xff0f) | ((val2 / PS_TO_REG) & 0xf) << 4);
 771
 772         if (val3 != -3)
 773                 newval = ((newval & 0xf0ff) | ((val3 / PS_TO_REG) & 0xf) << 8);
 774
 775         if (val4 != -4)
 776                 newval = ((newval & 0x0fff) | ((val4 / PS_TO_REG) & 0xf) << 12);
 777
 778         return kszphy_extended_write(phydev, reg, newval);
 779 }
 780
 781 static int ksz9021_config_init(struct phy_device *phydev)
 782 {
 783         const struct device_node *of_node;
 784         const struct device *dev_walker;
 785
 786         /* The Micrel driver has a deprecated option to place phy OF
 787          * properties in the MAC node. Walk up the tree of devices to
 788          * find a device with an OF node.
 789          */
 790         dev_walker = &phydev->mdio.dev;
 791         do {
 792                 of_node = dev_walker->of_node;
 793                 dev_walker = dev_walker->parent;
 794
 795         } while (!of_node && dev_walker);
 796
 797         if (of_node) {
 798                 ksz9021_load_values_from_of(phydev, of_node,
 799                                     MII_KSZPHY_CLK_CONTROL_PAD_SKEW,
 800                                     "txen-skew-ps", "txc-skew-ps",
 801                                     "rxdv-skew-ps", "rxc-skew-ps");
 802                 ksz9021_load_values_from_of(phydev, of_node,
 803                                     MII_KSZPHY_RX_DATA_PAD_SKEW,
 804                                     "rxd0-skew-ps", "rxd1-skew-ps",
 805                                     "rxd2-skew-ps", "rxd3-skew-ps");
 806                 ksz9021_load_values_from_of(phydev, of_node,
 807                                     MII_KSZPHY_TX_DATA_PAD_SKEW,
 808                                     "txd0-skew-ps", "txd1-skew-ps",
 809                                     "txd2-skew-ps", "txd3-skew-ps");
 810         }
 811         return 0;
 812 }
 813
 814 #define KSZ9031_PS_TO_REG               60
 815
 816 /* Extended registers */
 817 /* MMD Address 0x0 */
 818 #define MII_KSZ9031RN_FLP_BURST_TX_LO   3
 819 #define MII_KSZ9031RN_FLP_BURST_TX_HI   4
 820
 821 /* MMD Address 0x2 */
 822 #define MII_KSZ9031RN_CONTROL_PAD_SKEW  4
 823 #define MII_KSZ9031RN_RX_CTL_M          GENMASK(7, 4)
 824 #define MII_KSZ9031RN_TX_CTL_M          GENMASK(3, 0)
 825
 826 #define MII_KSZ9031RN_RX_DATA_PAD_SKEW  5
 827 #define MII_KSZ9031RN_RXD3              GENMASK(15, 12)
 828 #define MII_KSZ9031RN_RXD2              GENMASK(11, 8)
 829 #define MII_KSZ9031RN_RXD1              GENMASK(7, 4)
 830 #define MII_KSZ9031RN_RXD0              GENMASK(3, 0)
 831
 832 #define MII_KSZ9031RN_TX_DATA_PAD_SKEW  6
 833 #define MII_KSZ9031RN_TXD3              GENMASK(15, 12)
 834 #define MII_KSZ9031RN_TXD2              GENMASK(11, 8)
 835 #define MII_KSZ9031RN_TXD1              GENMASK(7, 4)
 836 #define MII_KSZ9031RN_TXD0              GENMASK(3, 0)
 837
 838 #define MII_KSZ9031RN_CLK_PAD_SKEW      8
 839 #define MII_KSZ9031RN_GTX_CLK           GENMASK(9, 5)
 840 #define MII_KSZ9031RN_RX_CLK            GENMASK(4, 0)
 841
 842 /* KSZ9031 has internal RGMII_IDRX = 1.2ns and RGMII_IDTX = 0ns. To
 843  * provide different RGMII options we need to configure delay offset
 844  * for each pad relative to build in delay.
 845  */
 846 /* keep rx as "No delay adjustment" and set rx_clk to +0.60ns to get delays of
 847  * 1.80ns
 848  */
 849 #define RX_ID                           0x7
 850 #define RX_CLK_ID                       0x19
 851
 852 /* set rx to +0.30ns and rx_clk to -0.90ns to compensate the
 853  * internal 1.2ns delay.
 854  */
 855 #define RX_ND                           0xc
 856 #define RX_CLK_ND                       0x0
 857
 858 /* set tx to -0.42ns and tx_clk to +0.96ns to get 1.38ns delay */
 859 #define TX_ID                           0x0
 860 #define TX_CLK_ID                       0x1f
 861
 862 /* set tx and tx_clk to "No delay adjustment" to keep 0ns
 863  * dealy
 864  */
 865 #define TX_ND                           0x7
 866 #define TX_CLK_ND                       0xf
 867
 868 /* MMD Address 0x1C */
 869 #define MII_KSZ9031RN_EDPD              0x23
 870 #define MII_KSZ9031RN_EDPD_ENABLE       BIT(0)
 871
 872 static int ksz9031_of_load_skew_values(struct phy_device *phydev,
 873                                        const struct device_node *of_node,
 874                                        u16 reg, size_t field_sz,
 875                                        const char *field[], u8 numfields,
 876                                        bool *update)
 877 {
 878         int val[4] = {-1, -2, -3, -4};
 879         int matches = 0;
 880         u16 mask;
 881         u16 maxval;
 882         u16 newval;
 883         int i;
 884
 885         for (i = 0; i < numfields; i++)
 886                 if (!of_property_read_u32(of_node, field[i], val + i))
 887                         matches++;
 888
 889         if (!matches)
 890                 return 0;
 891
 892         *update |= true;
 893
 894         if (matches < numfields)
 895                 newval = phy_read_mmd(phydev, 2, reg);
 896         else
 897                 newval = 0;
 898
 899         maxval = (field_sz == 4) ? 0xf : 0x1f;
 900         for (i = 0; i < numfields; i++)
 901                 if (val[i] != -(i + 1)) {
 902                         mask = 0xffff;
 903                         mask ^= maxval << (field_sz * i);
 904                         newval = (newval & mask) |
 905                                 (((val[i] / KSZ9031_PS_TO_REG) & maxval)
 906                                         << (field_sz * i));
 907                 }
 908
 909         return phy_write_mmd(phydev, 2, reg, newval);
 910 }
 911
 912 /* Center KSZ9031RNX FLP timing at 16ms. */
 913 static int ksz9031_center_flp_timing(struct phy_device *phydev)
 914 {
 915         int result;
 916
 917         result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_HI,
 918                                0x0006);
 919         if (result)
 920                 return result;
 921
 922         result = phy_write_mmd(phydev, 0, MII_KSZ9031RN_FLP_BURST_TX_LO,
 923                                0x1A80);
 924         if (result)
 925                 return result;
 926
 927         return genphy_restart_aneg(phydev);
 928 }
 929
 930 /* Enable energy-detect power-down mode */
 931 static int ksz9031_enable_edpd(struct phy_device *phydev)
 932 {
 933         int reg;
 934
 935         reg = phy_read_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD);
 936         if (reg < 0)
 937                 return reg;
 938         return phy_write_mmd(phydev, 0x1C, MII_KSZ9031RN_EDPD,
 939                              reg | MII_KSZ9031RN_EDPD_ENABLE);
 940 }
 941
 942 static int ksz9031_config_rgmii_delay(struct phy_device *phydev)
 943 {
 944         u16 rx, tx, rx_clk, tx_clk;
 945         int ret;
 946
 947         switch (phydev->interface) {
 948         case PHY_INTERFACE_MODE_RGMII:
 949                 tx = TX_ND;
 950                 tx_clk = TX_CLK_ND;
 951                 rx = RX_ND;
 952                 rx_clk = RX_CLK_ND;
 953                 break;
 954         case PHY_INTERFACE_MODE_RGMII_ID:
 955                 tx = TX_ID;
 956                 tx_clk = TX_CLK_ID;
 957                 rx = RX_ID;
 958                 rx_clk = RX_CLK_ID;
 959                 break;
 960         case PHY_INTERFACE_MODE_RGMII_RXID:
 961                 tx = TX_ND;
 962                 tx_clk = TX_CLK_ND;
 963                 rx = RX_ID;
 964                 rx_clk = RX_CLK_ID;
 965                 break;
 966         case PHY_INTERFACE_MODE_RGMII_TXID:
 967                 tx = TX_ID;
 968                 tx_clk = TX_CLK_ID;
 969                 rx = RX_ND;
 970                 rx_clk = RX_CLK_ND;
 971                 break;
 972         default:
 973                 return 0;
 974         }
 975
 976         ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_CONTROL_PAD_SKEW,
 977                             FIELD_PREP(MII_KSZ9031RN_RX_CTL_M, rx) |
 978                             FIELD_PREP(MII_KSZ9031RN_TX_CTL_M, tx));
 979         if (ret < 0)
 980                 return ret;
 981
 982         ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_RX_DATA_PAD_SKEW,
 983                             FIELD_PREP(MII_KSZ9031RN_RXD3, rx) |
 984                             FIELD_PREP(MII_KSZ9031RN_RXD2, rx) |
 985                             FIELD_PREP(MII_KSZ9031RN_RXD1, rx) |
 986                             FIELD_PREP(MII_KSZ9031RN_RXD0, rx));
 987         if (ret < 0)
 988                 return ret;
 989
 990         ret = phy_write_mmd(phydev, 2, MII_KSZ9031RN_TX_DATA_PAD_SKEW,
 991                             FIELD_PREP(MII_KSZ9031RN_TXD3, tx) |
 992                             FIELD_PREP(MII_KSZ9031RN_TXD2, tx) |
 993                             FIELD_PREP(MII_KSZ9031RN_TXD1, tx) |
 994                             FIELD_PREP(MII_KSZ9031RN_TXD0, tx));
 995         if (ret < 0)
 996                 return ret;
 997
 998         return phy_write_mmd(phydev, 2, MII_KSZ9031RN_CLK_PAD_SKEW,
 999                              FIELD_PREP(MII_KSZ9031RN_GTX_CLK, tx_clk) |
1000                              FIELD_PREP(MII_KSZ9031RN_RX_CLK, rx_clk));
1001 }
1002
1003 static int ksz9031_config_init(struct phy_device *phydev)
1004 {
1005         const struct device_node *of_node;
1006         static const char *clk_skews[2] = {"rxc-skew-ps", "txc-skew-ps"};
1007         static const char *rx_data_skews[4] = {
1008                 "rxd0-skew-ps", "rxd1-skew-ps",
1009                 "rxd2-skew-ps", "rxd3-skew-ps"
1010         };
1011         static const char *tx_data_skews[4] = {
1012                 "txd0-skew-ps", "txd1-skew-ps",
1013                 "txd2-skew-ps", "txd3-skew-ps"
1014         };
1015         static const char *control_skews[2] = {"txen-skew-ps", "rxdv-skew-ps"};
1016         const struct device *dev_walker;
1017         int result;
1018
1019         result = ksz9031_enable_edpd(phydev);
1020         if (result < 0)
1021                 return result;
1022
1023         /* The Micrel driver has a deprecated option to place phy OF
1024          * properties in the MAC node. Walk up the tree of devices to
1025          * find a device with an OF node.
1026          */
1027         dev_walker = &phydev->mdio.dev;
1028         do {
1029                 of_node = dev_walker->of_node;
1030                 dev_walker = dev_walker->parent;
1031         } while (!of_node && dev_walker);
1032
1033         if (of_node) {
1034                 bool update = false;
1035
1036                 if (phy_interface_is_rgmii(phydev)) {
1037                         result = ksz9031_config_rgmii_delay(phydev);
1038                         if (result < 0)
1039                                 return result;
1040                 }
1041
1042                 ksz9031_of_load_skew_values(phydev, of_node,
1043                                 MII_KSZ9031RN_CLK_PAD_SKEW, 5,
1044                                 clk_skews, 2, &update);
1045
1046                 ksz9031_of_load_skew_values(phydev, of_node,
1047                                 MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
1048                                 control_skews, 2, &update);
1049
1050                 ksz9031_of_load_skew_values(phydev, of_node,
1051                                 MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
1052                                 rx_data_skews, 4, &update);
1053
1054                 ksz9031_of_load_skew_values(phydev, of_node,
1055                                 MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
1056                                 tx_data_skews, 4, &update);
1057
1058                 if (update && !phy_interface_is_rgmii(phydev))
1059                         phydev_warn(phydev,
1060                                     "*-skew-ps values should be used only with RGMII PHY modes\n");
1061
1062                 /* Silicon Errata Sheet (DS80000691D or DS80000692D):
1063                  * When the device links in the 1000BASE-T slave mode only,
1064                  * the optional 125MHz reference output clock (CLK125_NDO)
1065                  * has wide duty cycle variation.
1066                  *
1067                  * The optional CLK125_NDO clock does not meet the RGMII
1068                  * 45/55 percent (min/max) duty cycle requirement and therefore
1069                  * cannot be used directly by the MAC side for clocking
1070                  * applications that have setup/hold time requirements on
1071                  * rising and falling clock edges.
1072                  *
1073                  * Workaround:
1074                  * Force the phy to be the master to receive a stable clock
1075                  * which meets the duty cycle requirement.
1076                  */
1077                 if (of_property_read_bool(of_node, "micrel,force-master")) {
1078                         result = phy_read(phydev, MII_CTRL1000);
1079                         if (result < 0)
1080                                 goto err_force_master;
1081
1082                         /* enable master mode, config & prefer master */
1083                         result |= CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER;
1084                         result = phy_write(phydev, MII_CTRL1000, result);
1085                         if (result < 0)
1086                                 goto err_force_master;
1087                 }
1088         }
1089
1090         return ksz9031_center_flp_timing(phydev);
1091
1092 err_force_master:
1093         phydev_err(phydev, "failed to force the phy to master mode\n");
1094         return result;
1095 }
1096
1097 #define KSZ9131_SKEW_5BIT_MAX   2400
1098 #define KSZ9131_SKEW_4BIT_MAX   800
1099 #define KSZ9131_OFFSET          700
1100 #define KSZ9131_STEP            100
1101
1102 static int ksz9131_of_load_skew_values(struct phy_device *phydev,
1103                                        struct device_node *of_node,
1104                                        u16 reg, size_t field_sz,
1105                                        char *field[], u8 numfields)
1106 {
1107         int val[4] = {-(1 + KSZ9131_OFFSET), -(2 + KSZ9131_OFFSET),
1108                       -(3 + KSZ9131_OFFSET), -(4 + KSZ9131_OFFSET)};
1109         int skewval, skewmax = 0;
1110         int matches = 0;
1111         u16 maxval;
1112         u16 newval;
1113         u16 mask;
1114         int i;
1115
1116         /* psec properties in dts should mean x pico seconds */
1117         if (field_sz == 5)
1118                 skewmax = KSZ9131_SKEW_5BIT_MAX;
1119         else
1120                 skewmax = KSZ9131_SKEW_4BIT_MAX;
1121
1122         for (i = 0; i < numfields; i++)
1123                 if (!of_property_read_s32(of_node, field[i], &skewval)) {
1124                         if (skewval < -KSZ9131_OFFSET)
1125                                 skewval = -KSZ9131_OFFSET;
1126                         else if (skewval > skewmax)
1127                                 skewval = skewmax;
1128
1129                         val[i] = skewval + KSZ9131_OFFSET;
1130                         matches++;
1131                 }
1132
1133         if (!matches)
1134                 return 0;
1135
1136         if (matches < numfields)
1137                 newval = phy_read_mmd(phydev, 2, reg);
1138         else
1139                 newval = 0;
1140
1141         maxval = (field_sz == 4) ? 0xf : 0x1f;
1142         for (i = 0; i < numfields; i++)
1143                 if (val[i] != -(i + 1 + KSZ9131_OFFSET)) {
1144                         mask = 0xffff;
1145                         mask ^= maxval << (field_sz * i);
1146                         newval = (newval & mask) |
1147                                 (((val[i] / KSZ9131_STEP) & maxval)
1148                                         << (field_sz * i));
1149                 }
1150
1151         return phy_write_mmd(phydev, 2, reg, newval);
1152 }
1153
1154 #define KSZ9131RN_MMD_COMMON_CTRL_REG   2
1155 #define KSZ9131RN_RXC_DLL_CTRL          76
1156 #define KSZ9131RN_TXC_DLL_CTRL          77
1157 #define KSZ9131RN_DLL_CTRL_BYPASS       BIT_MASK(12)
1158 #define KSZ9131RN_DLL_ENABLE_DELAY      0
1159 #define KSZ9131RN_DLL_DISABLE_DELAY     BIT(12)
1160
1161 static int ksz9131_config_rgmii_delay(struct phy_device *phydev)
1162 {
1163         u16 rxcdll_val, txcdll_val;
1164         int ret;
1165
1166         switch (phydev->interface) {
1167         case PHY_INTERFACE_MODE_RGMII:
1168                 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
1169                 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
1170                 break;
1171         case PHY_INTERFACE_MODE_RGMII_ID:
1172                 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1173                 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1174                 break;
1175         case PHY_INTERFACE_MODE_RGMII_RXID:
1176                 rxcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1177                 txcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
1178                 break;
1179         case PHY_INTERFACE_MODE_RGMII_TXID:
1180                 rxcdll_val = KSZ9131RN_DLL_DISABLE_DELAY;
1181                 txcdll_val = KSZ9131RN_DLL_ENABLE_DELAY;
1182                 break;
1183         default:
1184                 return 0;
1185         }
1186
1187         ret = phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1188                              KSZ9131RN_RXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
1189                              rxcdll_val);
1190         if (ret < 0)
1191                 return ret;
1192
1193         return phy_modify_mmd(phydev, KSZ9131RN_MMD_COMMON_CTRL_REG,
1194                               KSZ9131RN_TXC_DLL_CTRL, KSZ9131RN_DLL_CTRL_BYPASS,
1195                               txcdll_val);
1196 }
1197
1198 /* Silicon Errata DS80000693B
1199  *
1200  * When LEDs are configured in Individual Mode, LED1 is ON in a no-link
1201  * condition. Workaround is to set register 0x1e, bit 9, this way LED1 behaves
1202  * according to the datasheet (off if there is no link).
1203  */
1204 static int ksz9131_led_errata(struct phy_device *phydev)
1205 {
1206         int reg;
1207
1208         reg = phy_read_mmd(phydev, 2, 0);
1209         if (reg < 0)
1210                 return reg;
1211
1212         if (!(reg & BIT(4)))
1213                 return 0;
1214
1215         return phy_set_bits(phydev, 0x1e, BIT(9));
1216 }
1217
1218 static int ksz9131_config_init(struct phy_device *phydev)
1219 {
1220         struct device_node *of_node;
1221         char *clk_skews[2] = {"rxc-skew-psec", "txc-skew-psec"};
1222         char *rx_data_skews[4] = {
1223                 "rxd0-skew-psec", "rxd1-skew-psec",
1224                 "rxd2-skew-psec", "rxd3-skew-psec"
1225         };
1226         char *tx_data_skews[4] = {
1227                 "txd0-skew-psec", "txd1-skew-psec",
1228                 "txd2-skew-psec", "txd3-skew-psec"
1229         };
1230         char *control_skews[2] = {"txen-skew-psec", "rxdv-skew-psec"};
1231         const struct device *dev_walker;
1232         int ret;
1233
1234         dev_walker = &phydev->mdio.dev;
1235         do {
1236                 of_node = dev_walker->of_node;
1237                 dev_walker = dev_walker->parent;
1238         } while (!of_node && dev_walker);
1239
1240         if (!of_node)
1241                 return 0;
1242
1243         if (phy_interface_is_rgmii(phydev)) {
1244                 ret = ksz9131_config_rgmii_delay(phydev);
1245                 if (ret < 0)
1246                         return ret;
1247         }
1248
1249         ret = ksz9131_of_load_skew_values(phydev, of_node,
1250                                           MII_KSZ9031RN_CLK_PAD_SKEW, 5,
1251                                           clk_skews, 2);
1252         if (ret < 0)
1253                 return ret;
1254
1255         ret = ksz9131_of_load_skew_values(phydev, of_node,
1256                                           MII_KSZ9031RN_CONTROL_PAD_SKEW, 4,
1257                                           control_skews, 2);
1258         if (ret < 0)
1259                 return ret;
1260
1261         ret = ksz9131_of_load_skew_values(phydev, of_node,
1262                                           MII_KSZ9031RN_RX_DATA_PAD_SKEW, 4,
1263                                           rx_data_skews, 4);
1264         if (ret < 0)
1265                 return ret;
1266
1267         ret = ksz9131_of_load_skew_values(phydev, of_node,
1268                                           MII_KSZ9031RN_TX_DATA_PAD_SKEW, 4,
1269                                           tx_data_skews, 4);
1270         if (ret < 0)
1271                 return ret;
1272
1273         ret = ksz9131_led_errata(phydev);
1274         if (ret < 0)
1275                 return ret;
1276
1277         return 0;
1278 }
1279
1280 #define KSZ8873MLL_GLOBAL_CONTROL_4     0x06
1281 #define KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX      BIT(6)
1282 #define KSZ8873MLL_GLOBAL_CONTROL_4_SPEED       BIT(4)
1283 static int ksz8873mll_read_status(struct phy_device *phydev)
1284 {
1285         int regval;
1286
1287         /* dummy read */
1288         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1289
1290         regval = phy_read(phydev, KSZ8873MLL_GLOBAL_CONTROL_4);
1291
1292         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_DUPLEX)
1293                 phydev->duplex = DUPLEX_HALF;
1294         else
1295                 phydev->duplex = DUPLEX_FULL;
1296
1297         if (regval & KSZ8873MLL_GLOBAL_CONTROL_4_SPEED)
1298                 phydev->speed = SPEED_10;
1299         else
1300                 phydev->speed = SPEED_100;
1301
1302         phydev->link = 1;
1303         phydev->pause = phydev->asym_pause = 0;
1304
1305         return 0;
1306 }
1307
1308 static int ksz9031_get_features(struct phy_device *phydev)
1309 {
1310         int ret;
1311
1312         ret = genphy_read_abilities(phydev);
1313         if (ret < 0)
1314                 return ret;
1315
1316         /* Silicon Errata Sheet (DS80000691D or DS80000692D):
1317          * Whenever the device's Asymmetric Pause capability is set to 1,
1318          * link-up may fail after a link-up to link-down transition.
1319          *
1320          * The Errata Sheet is for ksz9031, but ksz9021 has the same issue
1321          *
1322          * Workaround:
1323          * Do not enable the Asymmetric Pause capability bit.
1324          */
1325         linkmode_clear_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, phydev->supported);
1326
1327         /* We force setting the Pause capability as the core will force the
1328          * Asymmetric Pause capability to 1 otherwise.
1329          */
1330         linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, phydev->supported);
1331
1332         return 0;
1333 }
1334
1335 static int ksz9031_read_status(struct phy_device *phydev)
1336 {
1337         int err;
1338         int regval;
1339
1340         err = genphy_read_status(phydev);
1341         if (err)
1342                 return err;
1343
1344         /* Make sure the PHY is not broken. Read idle error count,
1345          * and reset the PHY if it is maxed out.
1346          */
1347         regval = phy_read(phydev, MII_STAT1000);
1348         if ((regval & 0xFF) == 0xFF) {
1349                 phy_init_hw(phydev);
1350                 phydev->link = 0;
1351                 if (phydev->drv->config_intr && phy_interrupt_is_valid(phydev))
1352                         phydev->drv->config_intr(phydev);
1353                 return genphy_config_aneg(phydev);
1354         }
1355
1356         return 0;
1357 }
1358
1359 static int ksz9x31_cable_test_start(struct phy_device *phydev)
1360 {
1361         struct kszphy_priv *priv = phydev->priv;
1362         int ret;
1363
1364         /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1365          * Prior to running the cable diagnostics, Auto-negotiation should
1366          * be disabled, full duplex set and the link speed set to 1000Mbps
1367          * via the Basic Control Register.
1368          */
1369         ret = phy_modify(phydev, MII_BMCR,
1370                          BMCR_SPEED1000 | BMCR_FULLDPLX |
1371                          BMCR_ANENABLE | BMCR_SPEED100,
1372                          BMCR_SPEED1000 | BMCR_FULLDPLX);
1373         if (ret)
1374                 return ret;
1375
1376         /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1377          * The Master-Slave configuration should be set to Slave by writing
1378          * a value of 0x1000 to the Auto-Negotiation Master Slave Control
1379          * Register.
1380          */
1381         ret = phy_read(phydev, MII_CTRL1000);
1382         if (ret < 0)
1383                 return ret;
1384
1385         /* Cache these bits, they need to be restored once LinkMD finishes. */
1386         priv->vct_ctrl1000 = ret & (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
1387         ret &= ~(CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER);
1388         ret |= CTL1000_ENABLE_MASTER;
1389
1390         return phy_write(phydev, MII_CTRL1000, ret);
1391 }
1392
1393 static int ksz9x31_cable_test_result_trans(u16 status)
1394 {
1395         switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) {
1396         case KSZ9x31_LMD_VCT_ST_NORMAL:
1397                 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1398         case KSZ9x31_LMD_VCT_ST_OPEN:
1399                 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1400         case KSZ9x31_LMD_VCT_ST_SHORT:
1401                 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1402         case KSZ9x31_LMD_VCT_ST_FAIL:
1403                 fallthrough;
1404         default:
1405                 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1406         }
1407 }
1408
1409 static bool ksz9x31_cable_test_failed(u16 status)
1410 {
1411         int stat = FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status);
1412
1413         return stat == KSZ9x31_LMD_VCT_ST_FAIL;
1414 }
1415
1416 static bool ksz9x31_cable_test_fault_length_valid(u16 status)
1417 {
1418         switch (FIELD_GET(KSZ9x31_LMD_VCT_ST_MASK, status)) {
1419         case KSZ9x31_LMD_VCT_ST_OPEN:
1420                 fallthrough;
1421         case KSZ9x31_LMD_VCT_ST_SHORT:
1422                 return true;
1423         }
1424         return false;
1425 }
1426
1427 static int ksz9x31_cable_test_fault_length(struct phy_device *phydev, u16 stat)
1428 {
1429         int dt = FIELD_GET(KSZ9x31_LMD_VCT_DATA_MASK, stat);
1430
1431         /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1432          *
1433          * distance to fault = (VCT_DATA - 22) * 4 / cable propagation velocity
1434          */
1435         if ((phydev->phy_id & MICREL_PHY_ID_MASK) == PHY_ID_KSZ9131)
1436                 dt = clamp(dt - 22, 0, 255);
1437
1438         return (dt * 400) / 10;
1439 }
1440
1441 static int ksz9x31_cable_test_wait_for_completion(struct phy_device *phydev)
1442 {
1443         int val, ret;
1444
1445         ret = phy_read_poll_timeout(phydev, KSZ9x31_LMD, val,
1446                                     !(val & KSZ9x31_LMD_VCT_EN),
1447                                     30000, 100000, true);
1448
1449         return ret < 0 ? ret : 0;
1450 }
1451
1452 static int ksz9x31_cable_test_get_pair(int pair)
1453 {
1454         static const int ethtool_pair[] = {
1455                 ETHTOOL_A_CABLE_PAIR_A,
1456                 ETHTOOL_A_CABLE_PAIR_B,
1457                 ETHTOOL_A_CABLE_PAIR_C,
1458                 ETHTOOL_A_CABLE_PAIR_D,
1459         };
1460
1461         return ethtool_pair[pair];
1462 }
1463
1464 static int ksz9x31_cable_test_one_pair(struct phy_device *phydev, int pair)
1465 {
1466         int ret, val;
1467
1468         /* KSZ9131RNX, DS00002841B-page 38, 4.14 LinkMD (R) Cable Diagnostic
1469          * To test each individual cable pair, set the cable pair in the Cable
1470          * Diagnostics Test Pair (VCT_PAIR[1:0]) field of the LinkMD Cable
1471          * Diagnostic Register, along with setting the Cable Diagnostics Test
1472          * Enable (VCT_EN) bit. The Cable Diagnostics Test Enable (VCT_EN) bit
1473          * will self clear when the test is concluded.
1474          */
1475         ret = phy_write(phydev, KSZ9x31_LMD,
1476                         KSZ9x31_LMD_VCT_EN | KSZ9x31_LMD_VCT_PAIR(pair));
1477         if (ret)
1478                 return ret;
1479
1480         ret = ksz9x31_cable_test_wait_for_completion(phydev);
1481         if (ret)
1482                 return ret;
1483
1484         val = phy_read(phydev, KSZ9x31_LMD);
1485         if (val < 0)
1486                 return val;
1487
1488         if (ksz9x31_cable_test_failed(val))
1489                 return -EAGAIN;
1490
1491         ret = ethnl_cable_test_result(phydev,
1492                                       ksz9x31_cable_test_get_pair(pair),
1493                                       ksz9x31_cable_test_result_trans(val));
1494         if (ret)
1495                 return ret;
1496
1497         if (!ksz9x31_cable_test_fault_length_valid(val))
1498                 return 0;
1499
1500         return ethnl_cable_test_fault_length(phydev,
1501                                              ksz9x31_cable_test_get_pair(pair),
1502                                              ksz9x31_cable_test_fault_length(phydev, val));
1503 }
1504
1505 static int ksz9x31_cable_test_get_status(struct phy_device *phydev,
1506                                          bool *finished)
1507 {
1508         struct kszphy_priv *priv = phydev->priv;
1509         unsigned long pair_mask = 0xf;
1510         int retries = 20;
1511         int pair, ret, rv;
1512
1513         *finished = false;
1514
1515         /* Try harder if link partner is active */
1516         while (pair_mask && retries--) {
1517                 for_each_set_bit(pair, &pair_mask, 4) {
1518                         ret = ksz9x31_cable_test_one_pair(phydev, pair);
1519                         if (ret == -EAGAIN)
1520                                 continue;
1521                         if (ret < 0)
1522                                 return ret;
1523                         clear_bit(pair, &pair_mask);
1524                 }
1525                 /* If link partner is in autonegotiation mode it will send 2ms
1526                  * of FLPs with at least 6ms of silence.
1527                  * Add 2ms sleep to have better chances to hit this silence.
1528                  */
1529                 if (pair_mask)
1530                         usleep_range(2000, 3000);
1531         }
1532
1533         /* Report remaining unfinished pair result as unknown. */
1534         for_each_set_bit(pair, &pair_mask, 4) {
1535                 ret = ethnl_cable_test_result(phydev,
1536                                               ksz9x31_cable_test_get_pair(pair),
1537                                               ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC);
1538         }
1539
1540         *finished = true;
1541
1542         /* Restore cached bits from before LinkMD got started. */
1543         rv = phy_modify(phydev, MII_CTRL1000,
1544                         CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER,
1545                         priv->vct_ctrl1000);
1546         if (rv)
1547                 return rv;
1548
1549         return ret;
1550 }
1551
1552 static int ksz8873mll_config_aneg(struct phy_device *phydev)
1553 {
1554         return 0;
1555 }
1556
1557 static int ksz886x_config_mdix(struct phy_device *phydev, u8 ctrl)
1558 {
1559         u16 val;
1560
1561         switch (ctrl) {
1562         case ETH_TP_MDI:
1563                 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX;
1564                 break;
1565         case ETH_TP_MDI_X:
1566                 /* Note: The naming of the bit KSZ886X_BMCR_FORCE_MDI is bit
1567                  * counter intuitive, the "-X" in "1 = Force MDI" in the data
1568                  * sheet seems to be missing:
1569                  * 1 = Force MDI (sic!) (transmit on RX+/RX- pins)
1570                  * 0 = Normal operation (transmit on TX+/TX- pins)
1571                  */
1572                 val = KSZ886X_BMCR_DISABLE_AUTO_MDIX | KSZ886X_BMCR_FORCE_MDI;
1573                 break;
1574         case ETH_TP_MDI_AUTO:
1575                 val = 0;
1576                 break;
1577         default:
1578                 return 0;
1579         }
1580
1581         return phy_modify(phydev, MII_BMCR,
1582                           KSZ886X_BMCR_HP_MDIX | KSZ886X_BMCR_FORCE_MDI |
1583                           KSZ886X_BMCR_DISABLE_AUTO_MDIX,
1584                           KSZ886X_BMCR_HP_MDIX | val);
1585 }
1586
1587 static int ksz886x_config_aneg(struct phy_device *phydev)
1588 {
1589         int ret;
1590
1591         ret = genphy_config_aneg(phydev);
1592         if (ret)
1593                 return ret;
1594
1595         /* The MDI-X configuration is automatically changed by the PHY after
1596          * switching from autoneg off to on. So, take MDI-X configuration under
1597          * own control and set it after autoneg configuration was done.
1598          */
1599         return ksz886x_config_mdix(phydev, phydev->mdix_ctrl);
1600 }
1601
1602 static int ksz886x_mdix_update(struct phy_device *phydev)
1603 {
1604         int ret;
1605
1606         ret = phy_read(phydev, MII_BMCR);
1607         if (ret < 0)
1608                 return ret;
1609
1610         if (ret & KSZ886X_BMCR_DISABLE_AUTO_MDIX) {
1611                 if (ret & KSZ886X_BMCR_FORCE_MDI)
1612                         phydev->mdix_ctrl = ETH_TP_MDI_X;
1613                 else
1614                         phydev->mdix_ctrl = ETH_TP_MDI;
1615         } else {
1616                 phydev->mdix_ctrl = ETH_TP_MDI_AUTO;
1617         }
1618
1619         ret = phy_read(phydev, MII_KSZPHY_CTRL);
1620         if (ret < 0)
1621                 return ret;
1622
1623         /* Same reverse logic as KSZ886X_BMCR_FORCE_MDI */
1624         if (ret & KSZ886X_CTRL_MDIX_STAT)
1625                 phydev->mdix = ETH_TP_MDI_X;
1626         else
1627                 phydev->mdix = ETH_TP_MDI;
1628
1629         return 0;
1630 }
1631
1632 static int ksz886x_read_status(struct phy_device *phydev)
1633 {
1634         int ret;
1635
1636         ret = ksz886x_mdix_update(phydev);
1637         if (ret < 0)
1638                 return ret;
1639
1640         return genphy_read_status(phydev);
1641 }
1642
1643 static int kszphy_get_sset_count(struct phy_device *phydev)
1644 {
1645         return ARRAY_SIZE(kszphy_hw_stats);
1646 }
1647
1648 static void kszphy_get_strings(struct phy_device *phydev, u8 *data)
1649 {
1650         int i;
1651
1652         for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++) {
1653                 strlcpy(data + i * ETH_GSTRING_LEN,
1654                         kszphy_hw_stats[i].string, ETH_GSTRING_LEN);
1655         }
1656 }
1657
1658 static u64 kszphy_get_stat(struct phy_device *phydev, int i)
1659 {
1660         struct kszphy_hw_stat stat = kszphy_hw_stats[i];
1661         struct kszphy_priv *priv = phydev->priv;
1662         int val;
1663         u64 ret;
1664
1665         val = phy_read(phydev, stat.reg);
1666         if (val < 0) {
1667                 ret = U64_MAX;
1668         } else {
1669                 val = val & ((1 << stat.bits) - 1);
1670                 priv->stats[i] += val;
1671                 ret = priv->stats[i];
1672         }
1673
1674         return ret;
1675 }
1676
1677 static void kszphy_get_stats(struct phy_device *phydev,
1678                              struct ethtool_stats *stats, u64 *data)
1679 {
1680         int i;
1681
1682         for (i = 0; i < ARRAY_SIZE(kszphy_hw_stats); i++)
1683                 data[i] = kszphy_get_stat(phydev, i);
1684 }
1685
1686 static int kszphy_suspend(struct phy_device *phydev)
1687 {
1688         /* Disable PHY Interrupts */
1689         if (phy_interrupt_is_valid(phydev)) {
1690                 phydev->interrupts = PHY_INTERRUPT_DISABLED;
1691                 if (phydev->drv->config_intr)
1692                         phydev->drv->config_intr(phydev);
1693         }
1694
1695         return genphy_suspend(phydev);
1696 }
1697
1698 static void kszphy_parse_led_mode(struct phy_device *phydev)
1699 {
1700         const struct kszphy_type *type = phydev->drv->driver_data;
1701         const struct device_node *np = phydev->mdio.dev.of_node;
1702         struct kszphy_priv *priv = phydev->priv;
1703         int ret;
1704
1705         if (type && type->led_mode_reg) {
1706                 ret = of_property_read_u32(np, "micrel,led-mode",
1707                                            &priv->led_mode);
1708
1709                 if (ret)
1710                         priv->led_mode = -1;
1711
1712                 if (priv->led_mode > 3) {
1713                         phydev_err(phydev, "invalid led mode: 0x%02x\n",
1714                                    priv->led_mode);
1715                         priv->led_mode = -1;
1716                 }
1717         } else {
1718                 priv->led_mode = -1;
1719         }
1720 }
1721
1722 static int kszphy_resume(struct phy_device *phydev)
1723 {
1724         int ret;
1725
1726         genphy_resume(phydev);
1727
1728         /* After switching from power-down to normal mode, an internal global
1729          * reset is automatically generated. Wait a minimum of 1 ms before
1730          * read/write access to the PHY registers.
1731          */
1732         usleep_range(1000, 2000);
1733
1734         ret = kszphy_config_reset(phydev);
1735         if (ret)
1736                 return ret;
1737
1738         /* Enable PHY Interrupts */
1739         if (phy_interrupt_is_valid(phydev)) {
1740                 phydev->interrupts = PHY_INTERRUPT_ENABLED;
1741                 if (phydev->drv->config_intr)
1742                         phydev->drv->config_intr(phydev);
1743         }
1744
1745         return 0;
1746 }
1747
1748 static int kszphy_probe(struct phy_device *phydev)
1749 {
1750         const struct kszphy_type *type = phydev->drv->driver_data;
1751         const struct device_node *np = phydev->mdio.dev.of_node;
1752         struct kszphy_priv *priv;
1753         struct clk *clk;
1754
1755         priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
1756         if (!priv)
1757                 return -ENOMEM;
1758
1759         phydev->priv = priv;
1760
1761         priv->type = type;
1762
1763         kszphy_parse_led_mode(phydev);
1764
1765         clk = devm_clk_get(&phydev->mdio.dev, "rmii-ref");
1766         /* NOTE: clk may be NULL if building without CONFIG_HAVE_CLK */
1767         if (!IS_ERR_OR_NULL(clk)) {
1768                 unsigned long rate = clk_get_rate(clk);
1769                 bool rmii_ref_clk_sel_25_mhz;
1770
1771                 if (type)
1772                         priv->rmii_ref_clk_sel = type->has_rmii_ref_clk_sel;
1773                 rmii_ref_clk_sel_25_mhz = of_property_read_bool(np,
1774                                 "micrel,rmii-reference-clock-select-25-mhz");
1775
1776                 if (rate > 24500000 && rate < 25500000) {
1777                         priv->rmii_ref_clk_sel_val = rmii_ref_clk_sel_25_mhz;
1778                 } else if (rate > 49500000 && rate < 50500000) {
1779                         priv->rmii_ref_clk_sel_val = !rmii_ref_clk_sel_25_mhz;
1780                 } else {
1781                         phydev_err(phydev, "Clock rate out of range: %ld\n",
1782                                    rate);
1783                         return -EINVAL;
1784                 }
1785         }
1786
1787         if (ksz8041_fiber_mode(phydev))
1788                 phydev->port = PORT_FIBRE;
1789
1790         /* Support legacy board-file configuration */
1791         if (phydev->dev_flags & MICREL_PHY_50MHZ_CLK) {
1792                 priv->rmii_ref_clk_sel = true;
1793                 priv->rmii_ref_clk_sel_val = true;
1794         }
1795
1796         return 0;
1797 }
1798
1799 static int ksz886x_cable_test_start(struct phy_device *phydev)
1800 {
1801         if (phydev->dev_flags & MICREL_KSZ8_P1_ERRATA)
1802                 return -EOPNOTSUPP;
1803
1804         /* If autoneg is enabled, we won't be able to test cross pair
1805          * short. In this case, the PHY will "detect" a link and
1806          * confuse the internal state machine - disable auto neg here.
1807          * If autoneg is disabled, we should set the speed to 10mbit.
1808          */
1809         return phy_clear_bits(phydev, MII_BMCR, BMCR_ANENABLE | BMCR_SPEED100);
1810 }
1811
1812 static int ksz886x_cable_test_result_trans(u16 status)
1813 {
1814         switch (FIELD_GET(KSZ8081_LMD_STAT_MASK, status)) {
1815         case KSZ8081_LMD_STAT_NORMAL:
1816                 return ETHTOOL_A_CABLE_RESULT_CODE_OK;
1817         case KSZ8081_LMD_STAT_SHORT:
1818                 return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
1819         case KSZ8081_LMD_STAT_OPEN:
1820                 return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
1821         case KSZ8081_LMD_STAT_FAIL:
1822                 fallthrough;
1823         default:
1824                 return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
1825         }
1826 }
1827
1828 static bool ksz886x_cable_test_failed(u16 status)
1829 {
1830         return FIELD_GET(KSZ8081_LMD_STAT_MASK, status) ==
1831                 KSZ8081_LMD_STAT_FAIL;
1832 }
1833
1834 static bool ksz886x_cable_test_fault_length_valid(u16 status)
1835 {
1836         switch (FIELD_GET(KSZ8081_LMD_STAT_MASK, status)) {
1837         case KSZ8081_LMD_STAT_OPEN:
1838                 fallthrough;
1839         case KSZ8081_LMD_STAT_SHORT:
1840                 return true;
1841         }
1842         return false;
1843 }
1844
1845 static int ksz886x_cable_test_fault_length(u16 status)
1846 {
1847         int dt;
1848
1849         /* According to the data sheet the distance to the fault is
1850          * DELTA_TIME * 0.4 meters.
1851          */
1852         dt = FIELD_GET(KSZ8081_LMD_DELTA_TIME_MASK, status);
1853
1854         return (dt * 400) / 10;
1855 }
1856
1857 static int ksz886x_cable_test_wait_for_completion(struct phy_device *phydev)
1858 {
1859         int val, ret;
1860
1861         ret = phy_read_poll_timeout(phydev, KSZ8081_LMD, val,
1862                                     !(val & KSZ8081_LMD_ENABLE_TEST),
1863                                     30000, 100000, true);
1864
1865         return ret < 0 ? ret : 0;
1866 }
1867
1868 static int ksz886x_cable_test_one_pair(struct phy_device *phydev, int pair)
1869 {
1870         static const int ethtool_pair[] = {
1871                 ETHTOOL_A_CABLE_PAIR_A,
1872                 ETHTOOL_A_CABLE_PAIR_B,
1873         };
1874         int ret, val, mdix;
1875
1876         /* There is no way to choice the pair, like we do one ksz9031.
1877          * We can workaround this limitation by using the MDI-X functionality.
1878          */
1879         if (pair == 0)
1880                 mdix = ETH_TP_MDI;
1881         else
1882                 mdix = ETH_TP_MDI_X;
1883
1884         switch (phydev->phy_id & MICREL_PHY_ID_MASK) {
1885         case PHY_ID_KSZ8081:
1886                 ret = ksz8081_config_mdix(phydev, mdix);
1887                 break;
1888         case PHY_ID_KSZ886X:
1889                 ret = ksz886x_config_mdix(phydev, mdix);
1890                 break;
1891         default:
1892                 ret = -ENODEV;
1893         }
1894
1895         if (ret)
1896                 return ret;
1897
1898         /* Now we are ready to fire. This command will send a 100ns pulse
1899          * to the pair.
1900          */
1901         ret = phy_write(phydev, KSZ8081_LMD, KSZ8081_LMD_ENABLE_TEST);
1902         if (ret)
1903                 return ret;
1904
1905         ret = ksz886x_cable_test_wait_for_completion(phydev);
1906         if (ret)
1907                 return ret;
1908
1909         val = phy_read(phydev, KSZ8081_LMD);
1910         if (val < 0)
1911                 return val;
1912
1913         if (ksz886x_cable_test_failed(val))
1914                 return -EAGAIN;
1915
1916         ret = ethnl_cable_test_result(phydev, ethtool_pair[pair],
1917                                       ksz886x_cable_test_result_trans(val));
1918         if (ret)
1919                 return ret;
1920
1921         if (!ksz886x_cable_test_fault_length_valid(val))
1922                 return 0;
1923
1924         return ethnl_cable_test_fault_length(phydev, ethtool_pair[pair],
1925                                              ksz886x_cable_test_fault_length(val));
1926 }
1927
1928 static int ksz886x_cable_test_get_status(struct phy_device *phydev,
1929                                          bool *finished)
1930 {
1931         unsigned long pair_mask = 0x3;
1932         int retries = 20;
1933         int pair, ret;
1934
1935         *finished = false;
1936
1937         /* Try harder if link partner is active */
1938         while (pair_mask && retries--) {
1939                 for_each_set_bit(pair, &pair_mask, 4) {
1940                         ret = ksz886x_cable_test_one_pair(phydev, pair);
1941                         if (ret == -EAGAIN)
1942                                 continue;
1943                         if (ret < 0)
1944                                 return ret;
1945                         clear_bit(pair, &pair_mask);
1946                 }
1947                 /* If link partner is in autonegotiation mode it will send 2ms
1948                  * of FLPs with at least 6ms of silence.
1949                  * Add 2ms sleep to have better chances to hit this silence.
1950                  */
1951                 if (pair_mask)
1952                         msleep(2);
1953         }
1954
1955         *finished = true;
1956
1957         return ret;
1958 }
1959
1960 #define LAN_EXT_PAGE_ACCESS_CONTROL                     0x16
1961 #define LAN_EXT_PAGE_ACCESS_ADDRESS_DATA                0x17
1962 #define LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC                0x4000
1963
1964 #define LAN8814_QSGMII_SOFT_RESET                       0x43
1965 #define LAN8814_QSGMII_SOFT_RESET_BIT                   BIT(0)
1966 #define LAN8814_QSGMII_PCS1G_ANEG_CONFIG                0x13
1967 #define LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA       BIT(3)
1968 #define LAN8814_ALIGN_SWAP                              0x4a
1969 #define LAN8814_ALIGN_TX_A_B_SWAP                       0x1
1970 #define LAN8814_ALIGN_TX_A_B_SWAP_MASK                  GENMASK(2, 0)
1971
1972 #define LAN8804_ALIGN_SWAP                              0x4a
1973 #define LAN8804_ALIGN_TX_A_B_SWAP                       0x1
1974 #define LAN8804_ALIGN_TX_A_B_SWAP_MASK                  GENMASK(2, 0)
1975 #define LAN8814_CLOCK_MANAGEMENT                        0xd
1976 #define LAN8814_LINK_QUALITY                            0x8e
1977
1978 static int lanphy_read_page_reg(struct phy_device *phydev, int page, u32 addr)
1979 {
1980         int data;
1981
1982         phy_lock_mdio_bus(phydev);
1983         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
1984         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
1985         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
1986                     (page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC));
1987         data = __phy_read(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA);
1988         phy_unlock_mdio_bus(phydev);
1989
1990         return data;
1991 }
1992
1993 static int lanphy_write_page_reg(struct phy_device *phydev, int page, u16 addr,
1994                                  u16 val)
1995 {
1996         phy_lock_mdio_bus(phydev);
1997         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL, page);
1998         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, addr);
1999         __phy_write(phydev, LAN_EXT_PAGE_ACCESS_CONTROL,
2000                     page | LAN_EXT_PAGE_ACCESS_CTRL_EP_FUNC);
2001
2002         val = __phy_write(phydev, LAN_EXT_PAGE_ACCESS_ADDRESS_DATA, val);
2003         if (val != 0)
2004                 phydev_err(phydev, "Error: phy_write has returned error %d\n",
2005                            val);
2006         phy_unlock_mdio_bus(phydev);
2007         return val;
2008 }
2009
2010 static int lan8814_config_ts_intr(struct phy_device *phydev, bool enable)
2011 {
2012         u16 val = 0;
2013
2014         if (enable)
2015                 val = PTP_TSU_INT_EN_PTP_TX_TS_EN_ |
2016                       PTP_TSU_INT_EN_PTP_TX_TS_OVRFL_EN_ |
2017                       PTP_TSU_INT_EN_PTP_RX_TS_EN_ |
2018                       PTP_TSU_INT_EN_PTP_RX_TS_OVRFL_EN_;
2019
2020         return lanphy_write_page_reg(phydev, 5, PTP_TSU_INT_EN, val);
2021 }
2022
2023 static void lan8814_ptp_rx_ts_get(struct phy_device *phydev,
2024                                   u32 *seconds, u32 *nano_seconds, u16 *seq_id)
2025 {
2026         *seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_HI);
2027         *seconds = (*seconds << 16) |
2028                    lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_SEC_LO);
2029
2030         *nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_HI);
2031         *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2032                         lanphy_read_page_reg(phydev, 5, PTP_RX_INGRESS_NS_LO);
2033
2034         *seq_id = lanphy_read_page_reg(phydev, 5, PTP_RX_MSG_HEADER2);
2035 }
2036
2037 static void lan8814_ptp_tx_ts_get(struct phy_device *phydev,
2038                                   u32 *seconds, u32 *nano_seconds, u16 *seq_id)
2039 {
2040         *seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_HI);
2041         *seconds = *seconds << 16 |
2042                    lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_SEC_LO);
2043
2044         *nano_seconds = lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_HI);
2045         *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2046                         lanphy_read_page_reg(phydev, 5, PTP_TX_EGRESS_NS_LO);
2047
2048         *seq_id = lanphy_read_page_reg(phydev, 5, PTP_TX_MSG_HEADER2);
2049 }
2050
2051 static int lan8814_ts_info(struct mii_timestamper *mii_ts, struct ethtool_ts_info *info)
2052 {
2053         struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2054         struct phy_device *phydev = ptp_priv->phydev;
2055         struct lan8814_shared_priv *shared = phydev->shared->priv;
2056
2057         info->so_timestamping = SOF_TIMESTAMPING_TX_HARDWARE |
2058                                 SOF_TIMESTAMPING_RX_HARDWARE |
2059                                 SOF_TIMESTAMPING_RAW_HARDWARE;
2060
2061         info->phc_index = ptp_clock_index(shared->ptp_clock);
2062
2063         info->tx_types =
2064                 (1 << HWTSTAMP_TX_OFF) |
2065                 (1 << HWTSTAMP_TX_ON) |
2066                 (1 << HWTSTAMP_TX_ONESTEP_SYNC);
2067
2068         info->rx_filters =
2069                 (1 << HWTSTAMP_FILTER_NONE) |
2070                 (1 << HWTSTAMP_FILTER_PTP_V1_L4_EVENT) |
2071                 (1 << HWTSTAMP_FILTER_PTP_V2_L4_EVENT) |
2072                 (1 << HWTSTAMP_FILTER_PTP_V2_L2_EVENT) |
2073                 (1 << HWTSTAMP_FILTER_PTP_V2_EVENT);
2074
2075         return 0;
2076 }
2077
2078 static void lan8814_flush_fifo(struct phy_device *phydev, bool egress)
2079 {
2080         int i;
2081
2082         for (i = 0; i < FIFO_SIZE; ++i)
2083                 lanphy_read_page_reg(phydev, 5,
2084                                      egress ? PTP_TX_MSG_HEADER2 : PTP_RX_MSG_HEADER2);
2085
2086         /* Read to clear overflow status bit */
2087         lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
2088 }
2089
2090 static int lan8814_hwtstamp(struct mii_timestamper *mii_ts, struct ifreq *ifr)
2091 {
2092         struct kszphy_ptp_priv *ptp_priv =
2093                           container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2094         struct phy_device *phydev = ptp_priv->phydev;
2095         struct lan8814_shared_priv *shared = phydev->shared->priv;
2096         struct lan8814_ptp_rx_ts *rx_ts, *tmp;
2097         struct hwtstamp_config config;
2098         int txcfg = 0, rxcfg = 0;
2099         int pkt_ts_enable;
2100
2101         if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
2102                 return -EFAULT;
2103
2104         ptp_priv->hwts_tx_type = config.tx_type;
2105         ptp_priv->rx_filter = config.rx_filter;
2106
2107         switch (config.rx_filter) {
2108         case HWTSTAMP_FILTER_NONE:
2109                 ptp_priv->layer = 0;
2110                 ptp_priv->version = 0;
2111                 break;
2112         case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
2113         case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
2114         case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
2115                 ptp_priv->layer = PTP_CLASS_L4;
2116                 ptp_priv->version = PTP_CLASS_V2;
2117                 break;
2118         case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
2119         case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
2120         case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
2121                 ptp_priv->layer = PTP_CLASS_L2;
2122                 ptp_priv->version = PTP_CLASS_V2;
2123                 break;
2124         case HWTSTAMP_FILTER_PTP_V2_EVENT:
2125         case HWTSTAMP_FILTER_PTP_V2_SYNC:
2126         case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
2127                 ptp_priv->layer = PTP_CLASS_L4 | PTP_CLASS_L2;
2128                 ptp_priv->version = PTP_CLASS_V2;
2129                 break;
2130         default:
2131                 return -ERANGE;
2132         }
2133
2134         if (ptp_priv->layer & PTP_CLASS_L2) {
2135                 rxcfg = PTP_RX_PARSE_CONFIG_LAYER2_EN_;
2136                 txcfg = PTP_TX_PARSE_CONFIG_LAYER2_EN_;
2137         } else if (ptp_priv->layer & PTP_CLASS_L4) {
2138                 rxcfg |= PTP_RX_PARSE_CONFIG_IPV4_EN_ | PTP_RX_PARSE_CONFIG_IPV6_EN_;
2139                 txcfg |= PTP_TX_PARSE_CONFIG_IPV4_EN_ | PTP_TX_PARSE_CONFIG_IPV6_EN_;
2140         }
2141         lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_PARSE_CONFIG, rxcfg);
2142         lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_PARSE_CONFIG, txcfg);
2143
2144         pkt_ts_enable = PTP_TIMESTAMP_EN_SYNC_ | PTP_TIMESTAMP_EN_DREQ_ |
2145                         PTP_TIMESTAMP_EN_PDREQ_ | PTP_TIMESTAMP_EN_PDRES_;
2146         lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_RX_TIMESTAMP_EN, pkt_ts_enable);
2147         lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_TIMESTAMP_EN, pkt_ts_enable);
2148
2149         if (ptp_priv->hwts_tx_type == HWTSTAMP_TX_ONESTEP_SYNC)
2150                 lanphy_write_page_reg(ptp_priv->phydev, 5, PTP_TX_MOD,
2151                                       PTP_TX_MOD_TX_PTP_SYNC_TS_INSERT_);
2152
2153         if (config.rx_filter != HWTSTAMP_FILTER_NONE)
2154                 lan8814_config_ts_intr(ptp_priv->phydev, true);
2155         else
2156                 lan8814_config_ts_intr(ptp_priv->phydev, false);
2157
2158         mutex_lock(&shared->shared_lock);
2159         if (config.rx_filter != HWTSTAMP_FILTER_NONE)
2160                 shared->ref++;
2161         else
2162                 shared->ref--;
2163
2164         if (shared->ref)
2165                 lanphy_write_page_reg(ptp_priv->phydev, 4, PTP_CMD_CTL,
2166                                       PTP_CMD_CTL_PTP_ENABLE_);
2167         else
2168                 lanphy_write_page_reg(ptp_priv->phydev, 4, PTP_CMD_CTL,
2169                                       PTP_CMD_CTL_PTP_DISABLE_);
2170         mutex_unlock(&shared->shared_lock);
2171
2172         /* In case of multiple starts and stops, these needs to be cleared */
2173         list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {
2174                 list_del(&rx_ts->list);
2175                 kfree(rx_ts);
2176         }
2177         skb_queue_purge(&ptp_priv->rx_queue);
2178         skb_queue_purge(&ptp_priv->tx_queue);
2179
2180         lan8814_flush_fifo(ptp_priv->phydev, false);
2181         lan8814_flush_fifo(ptp_priv->phydev, true);
2182
2183         return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ? -EFAULT : 0;
2184 }
2185
2186 static void lan8814_txtstamp(struct mii_timestamper *mii_ts,
2187                              struct sk_buff *skb, int type)
2188 {
2189         struct kszphy_ptp_priv *ptp_priv = container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2190
2191         switch (ptp_priv->hwts_tx_type) {
2192         case HWTSTAMP_TX_ONESTEP_SYNC:
2193                 if (ptp_msg_is_sync(skb, type)) {
2194                         kfree_skb(skb);
2195                         return;
2196                 }
2197                 fallthrough;
2198         case HWTSTAMP_TX_ON:
2199                 skb_shinfo(skb)->tx_flags |= SKBTX_IN_PROGRESS;
2200                 skb_queue_tail(&ptp_priv->tx_queue, skb);
2201                 break;
2202         case HWTSTAMP_TX_OFF:
2203         default:
2204                 kfree_skb(skb);
2205                 break;
2206         }
2207 }
2208
2209 static void lan8814_get_sig_rx(struct sk_buff *skb, u16 *sig)
2210 {
2211         struct ptp_header *ptp_header;
2212         u32 type;
2213
2214         skb_push(skb, ETH_HLEN);
2215         type = ptp_classify_raw(skb);
2216         ptp_header = ptp_parse_header(skb, type);
2217         skb_pull_inline(skb, ETH_HLEN);
2218
2219         *sig = (__force u16)(ntohs(ptp_header->sequence_id));
2220 }
2221
2222 static bool lan8814_match_rx_ts(struct kszphy_ptp_priv *ptp_priv,
2223                                 struct sk_buff *skb)
2224 {
2225         struct skb_shared_hwtstamps *shhwtstamps;
2226         struct lan8814_ptp_rx_ts *rx_ts, *tmp;
2227         unsigned long flags;
2228         bool ret = false;
2229         u16 skb_sig;
2230
2231         lan8814_get_sig_rx(skb, &skb_sig);
2232
2233         /* Iterate over all RX timestamps and match it with the received skbs */
2234         spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);
2235         list_for_each_entry_safe(rx_ts, tmp, &ptp_priv->rx_ts_list, list) {
2236                 /* Check if we found the signature we were looking for. */
2237                 if (memcmp(&skb_sig, &rx_ts->seq_id, sizeof(rx_ts->seq_id)))
2238                         continue;
2239
2240                 shhwtstamps = skb_hwtstamps(skb);
2241                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2242                 shhwtstamps->hwtstamp = ktime_set(rx_ts->seconds,
2243                                                   rx_ts->nsec);
2244                 list_del(&rx_ts->list);
2245                 kfree(rx_ts);
2246
2247                 ret = true;
2248                 break;
2249         }
2250         spin_unlock_irqrestore(&ptp_priv->rx_ts_lock, flags);
2251
2252         if (ret)
2253                 netif_rx(skb);
2254         return ret;
2255 }
2256
2257 static bool lan8814_rxtstamp(struct mii_timestamper *mii_ts, struct sk_buff *skb, int type)
2258 {
2259         struct kszphy_ptp_priv *ptp_priv =
2260                         container_of(mii_ts, struct kszphy_ptp_priv, mii_ts);
2261
2262         if (ptp_priv->rx_filter == HWTSTAMP_FILTER_NONE ||
2263             type == PTP_CLASS_NONE)
2264                 return false;
2265
2266         if ((type & ptp_priv->version) == 0 || (type & ptp_priv->layer) == 0)
2267                 return false;
2268
2269         /* If we failed to match then add it to the queue for when the timestamp
2270          * will come
2271          */
2272         if (!lan8814_match_rx_ts(ptp_priv, skb))
2273                 skb_queue_tail(&ptp_priv->rx_queue, skb);
2274
2275         return true;
2276 }
2277
2278 static void lan8814_ptp_clock_set(struct phy_device *phydev,
2279                                   u32 seconds, u32 nano_seconds)
2280 {
2281         u32 sec_low, sec_high, nsec_low, nsec_high;
2282
2283         sec_low = seconds & 0xffff;
2284         sec_high = (seconds >> 16) & 0xffff;
2285         nsec_low = nano_seconds & 0xffff;
2286         nsec_high = (nano_seconds >> 16) & 0x3fff;
2287
2288         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_LO, sec_low);
2289         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_SEC_MID, sec_high);
2290         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_LO, nsec_low);
2291         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_SET_NS_HI, nsec_high);
2292
2293         lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_LOAD_);
2294 }
2295
2296 static void lan8814_ptp_clock_get(struct phy_device *phydev,
2297                                   u32 *seconds, u32 *nano_seconds)
2298 {
2299         lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL, PTP_CMD_CTL_PTP_CLOCK_READ_);
2300
2301         *seconds = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_MID);
2302         *seconds = (*seconds << 16) |
2303                    lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_SEC_LO);
2304
2305         *nano_seconds = lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_HI);
2306         *nano_seconds = ((*nano_seconds & 0x3fff) << 16) |
2307                         lanphy_read_page_reg(phydev, 4, PTP_CLOCK_READ_NS_LO);
2308 }
2309
2310 static int lan8814_ptpci_gettime64(struct ptp_clock_info *ptpci,
2311                                    struct timespec64 *ts)
2312 {
2313         struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2314                                                           ptp_clock_info);
2315         struct phy_device *phydev = shared->phydev;
2316         u32 nano_seconds;
2317         u32 seconds;
2318
2319         mutex_lock(&shared->shared_lock);
2320         lan8814_ptp_clock_get(phydev, &seconds, &nano_seconds);
2321         mutex_unlock(&shared->shared_lock);
2322         ts->tv_sec = seconds;
2323         ts->tv_nsec = nano_seconds;
2324
2325         return 0;
2326 }
2327
2328 static int lan8814_ptpci_settime64(struct ptp_clock_info *ptpci,
2329                                    const struct timespec64 *ts)
2330 {
2331         struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2332                                                           ptp_clock_info);
2333         struct phy_device *phydev = shared->phydev;
2334
2335         mutex_lock(&shared->shared_lock);
2336         lan8814_ptp_clock_set(phydev, ts->tv_sec, ts->tv_nsec);
2337         mutex_unlock(&shared->shared_lock);
2338
2339         return 0;
2340 }
2341
2342 static void lan8814_ptp_clock_step(struct phy_device *phydev,
2343                                    s64 time_step_ns)
2344 {
2345         u32 nano_seconds_step;
2346         u64 abs_time_step_ns;
2347         u32 unsigned_seconds;
2348         u32 nano_seconds;
2349         u32 remainder;
2350         s32 seconds;
2351
2352         if (time_step_ns >  15000000000LL) {
2353                 /* convert to clock set */
2354                 lan8814_ptp_clock_get(phydev, &unsigned_seconds, &nano_seconds);
2355                 unsigned_seconds += div_u64_rem(time_step_ns, 1000000000LL,
2356                                                 &remainder);
2357                 nano_seconds += remainder;
2358                 if (nano_seconds >= 1000000000) {
2359                         unsigned_seconds++;
2360                         nano_seconds -= 1000000000;
2361                 }
2362                 lan8814_ptp_clock_set(phydev, unsigned_seconds, nano_seconds);
2363                 return;
2364         } else if (time_step_ns < -15000000000LL) {
2365                 /* convert to clock set */
2366                 time_step_ns = -time_step_ns;
2367
2368                 lan8814_ptp_clock_get(phydev, &unsigned_seconds, &nano_seconds);
2369                 unsigned_seconds -= div_u64_rem(time_step_ns, 1000000000LL,
2370                                                 &remainder);
2371                 nano_seconds_step = remainder;
2372                 if (nano_seconds < nano_seconds_step) {
2373                         unsigned_seconds--;
2374                         nano_seconds += 1000000000;
2375                 }
2376                 nano_seconds -= nano_seconds_step;
2377                 lan8814_ptp_clock_set(phydev, unsigned_seconds,
2378                                       nano_seconds);
2379                 return;
2380         }
2381
2382         /* do clock step */
2383         if (time_step_ns >= 0) {
2384                 abs_time_step_ns = (u64)time_step_ns;
2385                 seconds = (s32)div_u64_rem(abs_time_step_ns, 1000000000,
2386                                            &remainder);
2387                 nano_seconds = remainder;
2388         } else {
2389                 abs_time_step_ns = (u64)(-time_step_ns);
2390                 seconds = -((s32)div_u64_rem(abs_time_step_ns, 1000000000,
2391                             &remainder));
2392                 nano_seconds = remainder;
2393                 if (nano_seconds > 0) {
2394                         /* subtracting nano seconds is not allowed
2395                          * convert to subtracting from seconds,
2396                          * and adding to nanoseconds
2397                          */
2398                         seconds--;
2399                         nano_seconds = (1000000000 - nano_seconds);
2400                 }
2401         }
2402
2403         if (nano_seconds > 0) {
2404                 /* add 8 ns to cover the likely normal increment */
2405                 nano_seconds += 8;
2406         }
2407
2408         if (nano_seconds >= 1000000000) {
2409                 /* carry into seconds */
2410                 seconds++;
2411                 nano_seconds -= 1000000000;
2412         }
2413
2414         while (seconds) {
2415                 if (seconds > 0) {
2416                         u32 adjustment_value = (u32)seconds;
2417                         u16 adjustment_value_lo, adjustment_value_hi;
2418
2419                         if (adjustment_value > 0xF)
2420                                 adjustment_value = 0xF;
2421
2422                         adjustment_value_lo = adjustment_value & 0xffff;
2423                         adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
2424
2425                         lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2426                                               adjustment_value_lo);
2427                         lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2428                                               PTP_LTC_STEP_ADJ_DIR_ |
2429                                               adjustment_value_hi);
2430                         seconds -= ((s32)adjustment_value);
2431                 } else {
2432                         u32 adjustment_value = (u32)(-seconds);
2433                         u16 adjustment_value_lo, adjustment_value_hi;
2434
2435                         if (adjustment_value > 0xF)
2436                                 adjustment_value = 0xF;
2437
2438                         adjustment_value_lo = adjustment_value & 0xffff;
2439                         adjustment_value_hi = (adjustment_value >> 16) & 0x3fff;
2440
2441                         lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2442                                               adjustment_value_lo);
2443                         lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2444                                               adjustment_value_hi);
2445                         seconds += ((s32)adjustment_value);
2446                 }
2447                 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,
2448                                       PTP_CMD_CTL_PTP_LTC_STEP_SEC_);
2449         }
2450         if (nano_seconds) {
2451                 u16 nano_seconds_lo;
2452                 u16 nano_seconds_hi;
2453
2454                 nano_seconds_lo = nano_seconds & 0xffff;
2455                 nano_seconds_hi = (nano_seconds >> 16) & 0x3fff;
2456
2457                 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_LO,
2458                                       nano_seconds_lo);
2459                 lanphy_write_page_reg(phydev, 4, PTP_LTC_STEP_ADJ_HI,
2460                                       PTP_LTC_STEP_ADJ_DIR_ |
2461                                       nano_seconds_hi);
2462                 lanphy_write_page_reg(phydev, 4, PTP_CMD_CTL,
2463                                       PTP_CMD_CTL_PTP_LTC_STEP_NSEC_);
2464         }
2465 }
2466
2467 static int lan8814_ptpci_adjtime(struct ptp_clock_info *ptpci, s64 delta)
2468 {
2469         struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2470                                                           ptp_clock_info);
2471         struct phy_device *phydev = shared->phydev;
2472
2473         mutex_lock(&shared->shared_lock);
2474         lan8814_ptp_clock_step(phydev, delta);
2475         mutex_unlock(&shared->shared_lock);
2476
2477         return 0;
2478 }
2479
2480 static int lan8814_ptpci_adjfine(struct ptp_clock_info *ptpci, long scaled_ppm)
2481 {
2482         struct lan8814_shared_priv *shared = container_of(ptpci, struct lan8814_shared_priv,
2483                                                           ptp_clock_info);
2484         struct phy_device *phydev = shared->phydev;
2485         u16 kszphy_rate_adj_lo, kszphy_rate_adj_hi;
2486         bool positive = true;
2487         u32 kszphy_rate_adj;
2488
2489         if (scaled_ppm < 0) {
2490                 scaled_ppm = -scaled_ppm;
2491                 positive = false;
2492         }
2493
2494         kszphy_rate_adj = LAN8814_1PPM_FORMAT * (scaled_ppm >> 16);
2495         kszphy_rate_adj += (LAN8814_1PPM_FORMAT * (0xffff & scaled_ppm)) >> 16;
2496
2497         kszphy_rate_adj_lo = kszphy_rate_adj & 0xffff;
2498         kszphy_rate_adj_hi = (kszphy_rate_adj >> 16) & 0x3fff;
2499
2500         if (positive)
2501                 kszphy_rate_adj_hi |= PTP_CLOCK_RATE_ADJ_DIR_;
2502
2503         mutex_lock(&shared->shared_lock);
2504         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_HI, kszphy_rate_adj_hi);
2505         lanphy_write_page_reg(phydev, 4, PTP_CLOCK_RATE_ADJ_LO, kszphy_rate_adj_lo);
2506         mutex_unlock(&shared->shared_lock);
2507
2508         return 0;
2509 }
2510
2511 static void lan8814_get_sig_tx(struct sk_buff *skb, u16 *sig)
2512 {
2513         struct ptp_header *ptp_header;
2514         u32 type;
2515
2516         type = ptp_classify_raw(skb);
2517         ptp_header = ptp_parse_header(skb, type);
2518
2519         *sig = (__force u16)(ntohs(ptp_header->sequence_id));
2520 }
2521
2522 static void lan8814_dequeue_tx_skb(struct kszphy_ptp_priv *ptp_priv)
2523 {
2524         struct phy_device *phydev = ptp_priv->phydev;
2525         struct skb_shared_hwtstamps shhwtstamps;
2526         struct sk_buff *skb, *skb_tmp;
2527         unsigned long flags;
2528         u32 seconds, nsec;
2529         bool ret = false;
2530         u16 skb_sig;
2531         u16 seq_id;
2532
2533         lan8814_ptp_tx_ts_get(phydev, &seconds, &nsec, &seq_id);
2534
2535         spin_lock_irqsave(&ptp_priv->tx_queue.lock, flags);
2536         skb_queue_walk_safe(&ptp_priv->tx_queue, skb, skb_tmp) {
2537                 lan8814_get_sig_tx(skb, &skb_sig);
2538
2539                 if (memcmp(&skb_sig, &seq_id, sizeof(seq_id)))
2540                         continue;
2541
2542                 __skb_unlink(skb, &ptp_priv->tx_queue);
2543                 ret = true;
2544                 break;
2545         }
2546         spin_unlock_irqrestore(&ptp_priv->tx_queue.lock, flags);
2547
2548         if (ret) {
2549                 memset(&shhwtstamps, 0, sizeof(shhwtstamps));
2550                 shhwtstamps.hwtstamp = ktime_set(seconds, nsec);
2551                 skb_complete_tx_timestamp(skb, &shhwtstamps);
2552         }
2553 }
2554
2555 static void lan8814_get_tx_ts(struct kszphy_ptp_priv *ptp_priv)
2556 {
2557         struct phy_device *phydev = ptp_priv->phydev;
2558         u32 reg;
2559
2560         do {
2561                 lan8814_dequeue_tx_skb(ptp_priv);
2562
2563                 /* If other timestamps are available in the FIFO,
2564                  * process them.
2565                  */
2566                 reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
2567         } while (PTP_CAP_INFO_TX_TS_CNT_GET_(reg) > 0);
2568 }
2569
2570 static bool lan8814_match_skb(struct kszphy_ptp_priv *ptp_priv,
2571                               struct lan8814_ptp_rx_ts *rx_ts)
2572 {
2573         struct skb_shared_hwtstamps *shhwtstamps;
2574         struct sk_buff *skb, *skb_tmp;
2575         unsigned long flags;
2576         bool ret = false;
2577         u16 skb_sig;
2578
2579         spin_lock_irqsave(&ptp_priv->rx_queue.lock, flags);
2580         skb_queue_walk_safe(&ptp_priv->rx_queue, skb, skb_tmp) {
2581                 lan8814_get_sig_rx(skb, &skb_sig);
2582
2583                 if (memcmp(&skb_sig, &rx_ts->seq_id, sizeof(rx_ts->seq_id)))
2584                         continue;
2585
2586                 __skb_unlink(skb, &ptp_priv->rx_queue);
2587
2588                 ret = true;
2589                 break;
2590         }
2591         spin_unlock_irqrestore(&ptp_priv->rx_queue.lock, flags);
2592
2593         if (ret) {
2594                 shhwtstamps = skb_hwtstamps(skb);
2595                 memset(shhwtstamps, 0, sizeof(*shhwtstamps));
2596                 shhwtstamps->hwtstamp = ktime_set(rx_ts->seconds, rx_ts->nsec);
2597                 netif_rx(skb);
2598         }
2599
2600         return ret;
2601 }
2602
2603 static void lan8814_get_rx_ts(struct kszphy_ptp_priv *ptp_priv)
2604 {
2605         struct phy_device *phydev = ptp_priv->phydev;
2606         struct lan8814_ptp_rx_ts *rx_ts;
2607         unsigned long flags;
2608         u32 reg;
2609
2610         do {
2611                 rx_ts = kzalloc(sizeof(*rx_ts), GFP_KERNEL);
2612                 if (!rx_ts)
2613                         return;
2614
2615                 lan8814_ptp_rx_ts_get(phydev, &rx_ts->seconds, &rx_ts->nsec,
2616                                       &rx_ts->seq_id);
2617
2618                 /* If we failed to match the skb add it to the queue for when
2619                  * the frame will come
2620                  */
2621                 if (!lan8814_match_skb(ptp_priv, rx_ts)) {
2622                         spin_lock_irqsave(&ptp_priv->rx_ts_lock, flags);
2623                         list_add(&rx_ts->list, &ptp_priv->rx_ts_list);
2624                         spin_unlock_irqrestore(&ptp_priv->rx_ts_lock, flags);
2625                 } else {
2626                         kfree(rx_ts);
2627                 }
2628
2629                 /* If other timestamps are available in the FIFO,
2630                  * process them.
2631                  */
2632                 reg = lanphy_read_page_reg(phydev, 5, PTP_CAP_INFO);
2633         } while (PTP_CAP_INFO_RX_TS_CNT_GET_(reg) > 0);
2634 }
2635
2636 static void lan8814_handle_ptp_interrupt(struct phy_device *phydev)
2637 {
2638         struct kszphy_priv *priv = phydev->priv;
2639         struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
2640         u16 status;
2641
2642         status = lanphy_read_page_reg(phydev, 5, PTP_TSU_INT_STS);
2643         if (status & PTP_TSU_INT_STS_PTP_TX_TS_EN_)
2644                 lan8814_get_tx_ts(ptp_priv);
2645
2646         if (status & PTP_TSU_INT_STS_PTP_RX_TS_EN_)
2647                 lan8814_get_rx_ts(ptp_priv);
2648
2649         if (status & PTP_TSU_INT_STS_PTP_TX_TS_OVRFL_INT_) {
2650                 lan8814_flush_fifo(phydev, true);
2651                 skb_queue_purge(&ptp_priv->tx_queue);
2652         }
2653
2654         if (status & PTP_TSU_INT_STS_PTP_RX_TS_OVRFL_INT_) {
2655                 lan8814_flush_fifo(phydev, false);
2656                 skb_queue_purge(&ptp_priv->rx_queue);
2657         }
2658 }
2659
2660 static int lan8804_config_init(struct phy_device *phydev)
2661 {
2662         int val;
2663
2664         /* MDI-X setting for swap A,B transmit */
2665         val = lanphy_read_page_reg(phydev, 2, LAN8804_ALIGN_SWAP);
2666         val &= ~LAN8804_ALIGN_TX_A_B_SWAP_MASK;
2667         val |= LAN8804_ALIGN_TX_A_B_SWAP;
2668         lanphy_write_page_reg(phydev, 2, LAN8804_ALIGN_SWAP, val);
2669
2670         /* Make sure that the PHY will not stop generating the clock when the
2671          * link partner goes down
2672          */
2673         lanphy_write_page_reg(phydev, 31, LAN8814_CLOCK_MANAGEMENT, 0x27e);
2674         lanphy_read_page_reg(phydev, 1, LAN8814_LINK_QUALITY);
2675
2676         return 0;
2677 }
2678
2679 static irqreturn_t lan8814_handle_interrupt(struct phy_device *phydev)
2680 {
2681         int irq_status, tsu_irq_status;
2682
2683         irq_status = phy_read(phydev, LAN8814_INTS);
2684         if (irq_status > 0 && (irq_status & LAN8814_INT_LINK))
2685                 phy_trigger_machine(phydev);
2686
2687         if (irq_status < 0) {
2688                 phy_error(phydev);
2689                 return IRQ_NONE;
2690         }
2691
2692         while (1) {
2693                 tsu_irq_status = lanphy_read_page_reg(phydev, 4,
2694                                                       LAN8814_INTR_STS_REG);
2695
2696                 if (tsu_irq_status > 0 &&
2697                     (tsu_irq_status & (LAN8814_INTR_STS_REG_1588_TSU0_ |
2698                                        LAN8814_INTR_STS_REG_1588_TSU1_ |
2699                                        LAN8814_INTR_STS_REG_1588_TSU2_ |
2700                                        LAN8814_INTR_STS_REG_1588_TSU3_)))
2701                         lan8814_handle_ptp_interrupt(phydev);
2702                 else
2703                         break;
2704         }
2705         return IRQ_HANDLED;
2706 }
2707
2708 static int lan8814_ack_interrupt(struct phy_device *phydev)
2709 {
2710         /* bit[12..0] int status, which is a read and clear register. */
2711         int rc;
2712
2713         rc = phy_read(phydev, LAN8814_INTS);
2714
2715         return (rc < 0) ? rc : 0;
2716 }
2717
2718 static int lan8814_config_intr(struct phy_device *phydev)
2719 {
2720         int err;
2721
2722         lanphy_write_page_reg(phydev, 4, LAN8814_INTR_CTRL_REG,
2723                               LAN8814_INTR_CTRL_REG_POLARITY |
2724                               LAN8814_INTR_CTRL_REG_INTR_ENABLE);
2725
2726         /* enable / disable interrupts */
2727         if (phydev->interrupts == PHY_INTERRUPT_ENABLED) {
2728                 err = lan8814_ack_interrupt(phydev);
2729                 if (err)
2730                         return err;
2731
2732                 err =  phy_write(phydev, LAN8814_INTC, LAN8814_INT_LINK);
2733         } else {
2734                 err =  phy_write(phydev, LAN8814_INTC, 0);
2735                 if (err)
2736                         return err;
2737
2738                 err = lan8814_ack_interrupt(phydev);
2739         }
2740
2741         return err;
2742 }
2743
2744 static void lan8814_ptp_init(struct phy_device *phydev)
2745 {
2746         struct kszphy_priv *priv = phydev->priv;
2747         struct kszphy_ptp_priv *ptp_priv = &priv->ptp_priv;
2748         u32 temp;
2749
2750         if (!IS_ENABLED(CONFIG_PTP_1588_CLOCK) ||
2751             !IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))
2752                 return;
2753
2754         lanphy_write_page_reg(phydev, 5, TSU_HARD_RESET, TSU_HARD_RESET_);
2755
2756         temp = lanphy_read_page_reg(phydev, 5, PTP_TX_MOD);
2757         temp |= PTP_TX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;
2758         lanphy_write_page_reg(phydev, 5, PTP_TX_MOD, temp);
2759
2760         temp = lanphy_read_page_reg(phydev, 5, PTP_RX_MOD);
2761         temp |= PTP_RX_MOD_BAD_UDPV4_CHKSUM_FORCE_FCS_DIS_;
2762         lanphy_write_page_reg(phydev, 5, PTP_RX_MOD, temp);
2763
2764         lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_CONFIG, 0);
2765         lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_CONFIG, 0);
2766
2767         /* Removing default registers configs related to L2 and IP */
2768         lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_L2_ADDR_EN, 0);
2769         lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_L2_ADDR_EN, 0);
2770         lanphy_write_page_reg(phydev, 5, PTP_TX_PARSE_IP_ADDR_EN, 0);
2771         lanphy_write_page_reg(phydev, 5, PTP_RX_PARSE_IP_ADDR_EN, 0);
2772
2773         skb_queue_head_init(&ptp_priv->tx_queue);
2774         skb_queue_head_init(&ptp_priv->rx_queue);
2775         INIT_LIST_HEAD(&ptp_priv->rx_ts_list);
2776         spin_lock_init(&ptp_priv->rx_ts_lock);
2777
2778         ptp_priv->phydev = phydev;
2779
2780         ptp_priv->mii_ts.rxtstamp = lan8814_rxtstamp;
2781         ptp_priv->mii_ts.txtstamp = lan8814_txtstamp;
2782         ptp_priv->mii_ts.hwtstamp = lan8814_hwtstamp;
2783         ptp_priv->mii_ts.ts_info  = lan8814_ts_info;
2784
2785         phydev->mii_ts = &ptp_priv->mii_ts;
2786 }
2787
2788 static int lan8814_ptp_probe_once(struct phy_device *phydev)
2789 {
2790         struct lan8814_shared_priv *shared = phydev->shared->priv;
2791
2792         if (!IS_ENABLED(CONFIG_PTP_1588_CLOCK) ||
2793             !IS_ENABLED(CONFIG_NETWORK_PHY_TIMESTAMPING))
2794                 return 0;
2795
2796         /* Initialise shared lock for clock*/
2797         mutex_init(&shared->shared_lock);
2798
2799         shared->ptp_clock_info.owner = THIS_MODULE;
2800         snprintf(shared->ptp_clock_info.name, 30, "%s", phydev->drv->name);
2801         shared->ptp_clock_info.max_adj = 31249999;
2802         shared->ptp_clock_info.n_alarm = 0;
2803         shared->ptp_clock_info.n_ext_ts = 0;
2804         shared->ptp_clock_info.n_pins = 0;
2805         shared->ptp_clock_info.pps = 0;
2806         shared->ptp_clock_info.pin_config = NULL;
2807         shared->ptp_clock_info.adjfine = lan8814_ptpci_adjfine;
2808         shared->ptp_clock_info.adjtime = lan8814_ptpci_adjtime;
2809         shared->ptp_clock_info.gettime64 = lan8814_ptpci_gettime64;
2810         shared->ptp_clock_info.settime64 = lan8814_ptpci_settime64;
2811         shared->ptp_clock_info.getcrosststamp = NULL;
2812
2813         shared->ptp_clock = ptp_clock_register(&shared->ptp_clock_info,
2814                                                &phydev->mdio.dev);
2815         if (IS_ERR_OR_NULL(shared->ptp_clock)) {
2816                 phydev_err(phydev, "ptp_clock_register failed %lu\n",
2817                            PTR_ERR(shared->ptp_clock));
2818                 return -EINVAL;
2819         }
2820
2821         phydev_dbg(phydev, "successfully registered ptp clock\n");
2822
2823         shared->phydev = phydev;
2824
2825         /* The EP.4 is shared between all the PHYs in the package and also it
2826          * can be accessed by any of the PHYs
2827          */
2828         lanphy_write_page_reg(phydev, 4, LTC_HARD_RESET, LTC_HARD_RESET_);
2829         lanphy_write_page_reg(phydev, 4, PTP_OPERATING_MODE,
2830                               PTP_OPERATING_MODE_STANDALONE_);
2831
2832         return 0;
2833 }
2834
2835 static void lan8814_setup_led(struct phy_device *phydev, int val)
2836 {
2837         int temp;
2838
2839         temp = lanphy_read_page_reg(phydev, 5, LAN8814_LED_CTRL_1);
2840
2841         if (val)
2842                 temp |= LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_;
2843         else
2844                 temp &= ~LAN8814_LED_CTRL_1_KSZ9031_LED_MODE_;
2845
2846         lanphy_write_page_reg(phydev, 5, LAN8814_LED_CTRL_1, temp);
2847 }
2848
2849 static int lan8814_config_init(struct phy_device *phydev)
2850 {
2851         struct kszphy_priv *lan8814 = phydev->priv;
2852         int val;
2853
2854         /* Reset the PHY */
2855         val = lanphy_read_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET);
2856         val |= LAN8814_QSGMII_SOFT_RESET_BIT;
2857         lanphy_write_page_reg(phydev, 4, LAN8814_QSGMII_SOFT_RESET, val);
2858
2859         /* Disable ANEG with QSGMII PCS Host side */
2860         val = lanphy_read_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG);
2861         val &= ~LAN8814_QSGMII_PCS1G_ANEG_CONFIG_ANEG_ENA;
2862         lanphy_write_page_reg(phydev, 5, LAN8814_QSGMII_PCS1G_ANEG_CONFIG, val);
2863
2864         /* MDI-X setting for swap A,B transmit */
2865         val = lanphy_read_page_reg(phydev, 2, LAN8814_ALIGN_SWAP);
2866         val &= ~LAN8814_ALIGN_TX_A_B_SWAP_MASK;
2867         val |= LAN8814_ALIGN_TX_A_B_SWAP;
2868         lanphy_write_page_reg(phydev, 2, LAN8814_ALIGN_SWAP, val);
2869
2870         if (lan8814->led_mode >= 0)
2871                 lan8814_setup_led(phydev, lan8814->led_mode);
2872
2873         return 0;
2874 }
2875
2876 static int lan8814_release_coma_mode(struct phy_device *phydev)
2877 {
2878         struct gpio_desc *gpiod;
2879
2880         gpiod = devm_gpiod_get_optional(&phydev->mdio.dev, "coma-mode",
2881                                         GPIOD_OUT_HIGH_OPEN_DRAIN);
2882         if (IS_ERR(gpiod))
2883                 return PTR_ERR(gpiod);
2884
2885         gpiod_set_consumer_name(gpiod, "LAN8814 coma mode");
2886         gpiod_set_value_cansleep(gpiod, 0);
2887
2888         return 0;
2889 }
2890
2891 static int lan8814_probe(struct phy_device *phydev)
2892 {
2893         const struct kszphy_type *type = phydev->drv->driver_data;
2894         struct kszphy_priv *priv;
2895         u16 addr;
2896         int err;
2897
2898         priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL);
2899         if (!priv)
2900                 return -ENOMEM;
2901
2902         phydev->priv = priv;
2903
2904         priv->type = type;
2905
2906         kszphy_parse_led_mode(phydev);
2907
2908         /* Strap-in value for PHY address, below register read gives starting
2909          * phy address value
2910          */
2911         addr = lanphy_read_page_reg(phydev, 4, 0) & 0x1F;
2912         devm_phy_package_join(&phydev->mdio.dev, phydev,
2913                               addr, sizeof(struct lan8814_shared_priv));
2914
2915         if (phy_package_init_once(phydev)) {
2916                 err = lan8814_release_coma_mode(phydev);
2917                 if (err)
2918                         return err;
2919
2920                 err = lan8814_ptp_probe_once(phydev);
2921                 if (err)
2922                         return err;
2923         }
2924
2925         lan8814_ptp_init(phydev);
2926
2927         return 0;
2928 }
2929
2930 static struct phy_driver ksphy_driver[] = {
2931 {
2932         .phy_id         = PHY_ID_KS8737,
2933         .phy_id_mask    = MICREL_PHY_ID_MASK,
2934         .name           = "Micrel KS8737",
2935         /* PHY_BASIC_FEATURES */
2936         .driver_data    = &ks8737_type,
2937         .probe          = kszphy_probe,
2938         .config_init    = kszphy_config_init,
2939         .config_intr    = kszphy_config_intr,
2940         .handle_interrupt = kszphy_handle_interrupt,
2941         .suspend        = kszphy_suspend,
2942         .resume         = kszphy_resume,
2943 }, {
2944         .phy_id         = PHY_ID_KSZ8021,
2945         .phy_id_mask    = 0x00ffffff,
2946         .name           = "Micrel KSZ8021 or KSZ8031",
2947         /* PHY_BASIC_FEATURES */
2948         .driver_data    = &ksz8021_type,
2949         .probe          = kszphy_probe,
2950         .config_init    = kszphy_config_init,
2951         .config_intr    = kszphy_config_intr,
2952         .handle_interrupt = kszphy_handle_interrupt,
2953         .get_sset_count = kszphy_get_sset_count,
2954         .get_strings    = kszphy_get_strings,
2955         .get_stats      = kszphy_get_stats,
2956         .suspend        = kszphy_suspend,
2957         .resume         = kszphy_resume,
2958 }, {
2959         .phy_id         = PHY_ID_KSZ8031,
2960         .phy_id_mask    = 0x00ffffff,
2961         .name           = "Micrel KSZ8031",
2962         /* PHY_BASIC_FEATURES */
2963         .driver_data    = &ksz8021_type,
2964         .probe          = kszphy_probe,
2965         .config_init    = kszphy_config_init,
2966         .config_intr    = kszphy_config_intr,
2967         .handle_interrupt = kszphy_handle_interrupt,
2968         .get_sset_count = kszphy_get_sset_count,
2969         .get_strings    = kszphy_get_strings,
2970         .get_stats      = kszphy_get_stats,
2971         .suspend        = kszphy_suspend,
2972         .resume         = kszphy_resume,
2973 }, {
2974         .phy_id         = PHY_ID_KSZ8041,
2975         .phy_id_mask    = MICREL_PHY_ID_MASK,
2976         .name           = "Micrel KSZ8041",
2977         /* PHY_BASIC_FEATURES */
2978         .driver_data    = &ksz8041_type,
2979         .probe          = kszphy_probe,
2980         .config_init    = ksz8041_config_init,
2981         .config_aneg    = ksz8041_config_aneg,
2982         .config_intr    = kszphy_config_intr,
2983         .handle_interrupt = kszphy_handle_interrupt,
2984         .get_sset_count = kszphy_get_sset_count,
2985         .get_strings    = kszphy_get_strings,
2986         .get_stats      = kszphy_get_stats,
2987         /* No suspend/resume callbacks because of errata DS80000700A,
2988          * receiver error following software power down.
2989          */
2990 }, {
2991         .phy_id         = PHY_ID_KSZ8041RNLI,
2992         .phy_id_mask    = MICREL_PHY_ID_MASK,
2993         .name           = "Micrel KSZ8041RNLI",
2994         /* PHY_BASIC_FEATURES */
2995         .driver_data    = &ksz8041_type,
2996         .probe          = kszphy_probe,
2997         .config_init    = kszphy_config_init,
2998         .config_intr    = kszphy_config_intr,
2999         .handle_interrupt = kszphy_handle_interrupt,
3000         .get_sset_count = kszphy_get_sset_count,
3001         .get_strings    = kszphy_get_strings,
3002         .get_stats      = kszphy_get_stats,
3003         .suspend        = kszphy_suspend,
3004         .resume         = kszphy_resume,
3005 }, {
3006         .name           = "Micrel KSZ8051",
3007         /* PHY_BASIC_FEATURES */
3008         .driver_data    = &ksz8051_type,
3009         .probe          = kszphy_probe,
3010         .config_init    = kszphy_config_init,
3011         .config_intr    = kszphy_config_intr,
3012         .handle_interrupt = kszphy_handle_interrupt,
3013         .get_sset_count = kszphy_get_sset_count,
3014         .get_strings    = kszphy_get_strings,
3015         .get_stats      = kszphy_get_stats,
3016         .match_phy_device = ksz8051_match_phy_device,
3017         .suspend        = kszphy_suspend,
3018         .resume         = kszphy_resume,
3019 }, {
3020         .phy_id         = PHY_ID_KSZ8001,
3021         .name           = "Micrel KSZ8001 or KS8721",
3022         .phy_id_mask    = 0x00fffffc,
3023         /* PHY_BASIC_FEATURES */
3024         .driver_data    = &ksz8041_type,
3025         .probe          = kszphy_probe,
3026         .config_init    = kszphy_config_init,
3027         .config_intr    = kszphy_config_intr,
3028         .handle_interrupt = kszphy_handle_interrupt,
3029         .get_sset_count = kszphy_get_sset_count,
3030         .get_strings    = kszphy_get_strings,
3031         .get_stats      = kszphy_get_stats,
3032         .suspend        = kszphy_suspend,
3033         .resume         = kszphy_resume,
3034 }, {
3035         .phy_id         = PHY_ID_KSZ8081,
3036         .name           = "Micrel KSZ8081 or KSZ8091",
3037         .phy_id_mask    = MICREL_PHY_ID_MASK,
3038         .flags          = PHY_POLL_CABLE_TEST,
3039         /* PHY_BASIC_FEATURES */
3040         .driver_data    = &ksz8081_type,
3041         .probe          = kszphy_probe,
3042         .config_init    = ksz8081_config_init,
3043         .soft_reset     = genphy_soft_reset,
3044         .config_aneg    = ksz8081_config_aneg,
3045         .read_status    = ksz8081_read_status,
3046         .config_intr    = kszphy_config_intr,
3047         .handle_interrupt = kszphy_handle_interrupt,
3048         .get_sset_count = kszphy_get_sset_count,
3049         .get_strings    = kszphy_get_strings,
3050         .get_stats      = kszphy_get_stats,
3051         .suspend        = kszphy_suspend,
3052         .resume         = kszphy_resume,
3053         .cable_test_start       = ksz886x_cable_test_start,
3054         .cable_test_get_status  = ksz886x_cable_test_get_status,
3055 }, {
3056         .phy_id         = PHY_ID_KSZ8061,
3057         .name           = "Micrel KSZ8061",
3058         .phy_id_mask    = MICREL_PHY_ID_MASK,
3059         /* PHY_BASIC_FEATURES */
3060         .probe          = kszphy_probe,
3061         .config_init    = ksz8061_config_init,
3062         .config_intr    = kszphy_config_intr,
3063         .handle_interrupt = kszphy_handle_interrupt,
3064         .suspend        = kszphy_suspend,
3065         .resume         = kszphy_resume,
3066 }, {
3067         .phy_id         = PHY_ID_KSZ9021,
3068         .phy_id_mask    = 0x000ffffe,
3069         .name           = "Micrel KSZ9021 Gigabit PHY",
3070         /* PHY_GBIT_FEATURES */
3071         .driver_data    = &ksz9021_type,
3072         .probe          = kszphy_probe,
3073         .get_features   = ksz9031_get_features,
3074         .config_init    = ksz9021_config_init,
3075         .config_intr    = kszphy_config_intr,
3076         .handle_interrupt = kszphy_handle_interrupt,
3077         .get_sset_count = kszphy_get_sset_count,
3078         .get_strings    = kszphy_get_strings,
3079         .get_stats      = kszphy_get_stats,
3080         .suspend        = kszphy_suspend,
3081         .resume         = kszphy_resume,
3082         .read_mmd       = genphy_read_mmd_unsupported,
3083         .write_mmd      = genphy_write_mmd_unsupported,
3084 }, {
3085         .phy_id         = PHY_ID_KSZ9031,
3086         .phy_id_mask    = MICREL_PHY_ID_MASK,
3087         .name           = "Micrel KSZ9031 Gigabit PHY",
3088         .flags          = PHY_POLL_CABLE_TEST,
3089         .driver_data    = &ksz9021_type,
3090         .probe          = kszphy_probe,
3091         .get_features   = ksz9031_get_features,
3092         .config_init    = ksz9031_config_init,
3093         .soft_reset     = genphy_soft_reset,
3094         .read_status    = ksz9031_read_status,
3095         .config_intr    = kszphy_config_intr,
3096         .handle_interrupt = kszphy_handle_interrupt,
3097         .get_sset_count = kszphy_get_sset_count,
3098         .get_strings    = kszphy_get_strings,
3099         .get_stats      = kszphy_get_stats,
3100         .suspend        = kszphy_suspend,
3101         .resume         = kszphy_resume,
3102         .cable_test_start       = ksz9x31_cable_test_start,
3103         .cable_test_get_status  = ksz9x31_cable_test_get_status,
3104 }, {
3105         .phy_id         = PHY_ID_LAN8814,
3106         .phy_id_mask    = MICREL_PHY_ID_MASK,
3107         .name           = "Microchip INDY Gigabit Quad PHY",
3108         .config_init    = lan8814_config_init,
3109         .driver_data    = &lan8814_type,
3110         .probe          = lan8814_probe,
3111         .soft_reset     = genphy_soft_reset,
3112         .read_status    = ksz9031_read_status,
3113         .get_sset_count = kszphy_get_sset_count,
3114         .get_strings    = kszphy_get_strings,
3115         .get_stats      = kszphy_get_stats,
3116         .suspend        = genphy_suspend,
3117         .resume         = kszphy_resume,
3118         .config_intr    = lan8814_config_intr,
3119         .handle_interrupt = lan8814_handle_interrupt,
3120 }, {
3121         .phy_id         = PHY_ID_LAN8804,
3122         .phy_id_mask    = MICREL_PHY_ID_MASK,
3123         .name           = "Microchip LAN966X Gigabit PHY",
3124         .config_init    = lan8804_config_init,
3125         .driver_data    = &ksz9021_type,
3126         .probe          = kszphy_probe,
3127         .soft_reset     = genphy_soft_reset,
3128         .read_status    = ksz9031_read_status,
3129         .get_sset_count = kszphy_get_sset_count,
3130         .get_strings    = kszphy_get_strings,
3131         .get_stats      = kszphy_get_stats,
3132         .suspend        = genphy_suspend,
3133         .resume         = kszphy_resume,
3134 }, {
3135         .phy_id         = PHY_ID_KSZ9131,
3136         .phy_id_mask    = MICREL_PHY_ID_MASK,
3137         .name           = "Microchip KSZ9131 Gigabit PHY",
3138         /* PHY_GBIT_FEATURES */
3139         .flags          = PHY_POLL_CABLE_TEST,
3140         .driver_data    = &ksz9021_type,
3141         .probe          = kszphy_probe,
3142         .config_init    = ksz9131_config_init,
3143         .config_intr    = kszphy_config_intr,
3144         .handle_interrupt = kszphy_handle_interrupt,
3145         .get_sset_count = kszphy_get_sset_count,
3146         .get_strings    = kszphy_get_strings,
3147         .get_stats      = kszphy_get_stats,
3148         .suspend        = kszphy_suspend,
3149         .resume         = kszphy_resume,
3150         .cable_test_start       = ksz9x31_cable_test_start,
3151         .cable_test_get_status  = ksz9x31_cable_test_get_status,
3152 }, {
3153         .phy_id         = PHY_ID_KSZ8873MLL,
3154         .phy_id_mask    = MICREL_PHY_ID_MASK,
3155         .name           = "Micrel KSZ8873MLL Switch",
3156         /* PHY_BASIC_FEATURES */
3157         .config_init    = kszphy_config_init,
3158         .config_aneg    = ksz8873mll_config_aneg,
3159         .read_status    = ksz8873mll_read_status,
3160         .suspend        = genphy_suspend,
3161         .resume         = genphy_resume,
3162 }, {
3163         .phy_id         = PHY_ID_KSZ886X,
3164         .phy_id_mask    = MICREL_PHY_ID_MASK,
3165         .name           = "Micrel KSZ8851 Ethernet MAC or KSZ886X Switch",
3166         /* PHY_BASIC_FEATURES */
3167         .flags          = PHY_POLL_CABLE_TEST,
3168         .config_init    = kszphy_config_init,
3169         .config_aneg    = ksz886x_config_aneg,
3170         .read_status    = ksz886x_read_status,
3171         .suspend        = genphy_suspend,
3172         .resume         = genphy_resume,
3173         .cable_test_start       = ksz886x_cable_test_start,
3174         .cable_test_get_status  = ksz886x_cable_test_get_status,
3175 }, {
3176         .name           = "Micrel KSZ87XX Switch",
3177         /* PHY_BASIC_FEATURES */
3178         .config_init    = kszphy_config_init,
3179         .match_phy_device = ksz8795_match_phy_device,
3180         .suspend        = genphy_suspend,
3181         .resume         = genphy_resume,
3182 }, {
3183         .phy_id         = PHY_ID_KSZ9477,
3184         .phy_id_mask    = MICREL_PHY_ID_MASK,
3185         .name           = "Microchip KSZ9477",
3186         /* PHY_GBIT_FEATURES */
3187         .config_init    = kszphy_config_init,
3188         .suspend        = genphy_suspend,
3189         .resume         = genphy_resume,
3190 } };
3191
3192 module_phy_driver(ksphy_driver);
3193
3194 MODULE_DESCRIPTION("Micrel PHY driver");
3195 MODULE_AUTHOR("David J. Choi");
3196 MODULE_LICENSE("GPL");
3197
3198 static struct mdio_device_id __maybe_unused micrel_tbl[] = {
3199         { PHY_ID_KSZ9021, 0x000ffffe },
3200         { PHY_ID_KSZ9031, MICREL_PHY_ID_MASK },
3201         { PHY_ID_KSZ9131, MICREL_PHY_ID_MASK },
3202         { PHY_ID_KSZ8001, 0x00fffffc },
3203         { PHY_ID_KS8737, MICREL_PHY_ID_MASK },
3204         { PHY_ID_KSZ8021, 0x00ffffff },
3205         { PHY_ID_KSZ8031, 0x00ffffff },
3206         { PHY_ID_KSZ8041, MICREL_PHY_ID_MASK },
3207         { PHY_ID_KSZ8051, MICREL_PHY_ID_MASK },
3208         { PHY_ID_KSZ8061, MICREL_PHY_ID_MASK },
3209         { PHY_ID_KSZ8081, MICREL_PHY_ID_MASK },
3210         { PHY_ID_KSZ8873MLL, MICREL_PHY_ID_MASK },
3211         { PHY_ID_KSZ886X, MICREL_PHY_ID_MASK },
3212         { PHY_ID_LAN8814, MICREL_PHY_ID_MASK },
3213         { PHY_ID_LAN8804, MICREL_PHY_ID_MASK },
3214         { }
3215 };
3216
3217 MODULE_DEVICE_TABLE(mdio, micrel_tbl);