1 // SPDX-License-Identifier: GPL-2.0-only
3 * Cadence MACB/GEM Ethernet Controller driver
5 * Copyright (C) 2004-2006 Atmel Corporation
8 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10 #include <linux/clk-provider.h>
11 #include <linux/crc32.h>
12 #include <linux/module.h>
13 #include <linux/moduleparam.h>
14 #include <linux/kernel.h>
15 #include <linux/types.h>
16 #include <linux/circ_buf.h>
17 #include <linux/slab.h>
18 #include <linux/init.h>
20 #include <linux/gpio.h>
21 #include <linux/gpio/consumer.h>
22 #include <linux/interrupt.h>
23 #include <linux/netdevice.h>
24 #include <linux/etherdevice.h>
25 #include <linux/dma-mapping.h>
26 #include <linux/platform_device.h>
27 #include <linux/phylink.h>
29 #include <linux/of_device.h>
30 #include <linux/of_gpio.h>
31 #include <linux/of_mdio.h>
32 #include <linux/of_net.h>
34 #include <linux/udp.h>
35 #include <linux/tcp.h>
36 #include <linux/iopoll.h>
37 #include <linux/phy/phy.h>
38 #include <linux/pm_runtime.h>
39 #include <linux/ptp_classify.h>
40 #include <linux/reset.h>
43 /* This structure is only used for MACB on SiFive FU540 devices */
44 struct sifive_fu540_macb_mgmt {
50 #define MACB_RX_BUFFER_SIZE 128
51 #define RX_BUFFER_MULTIPLE 64 /* bytes */
53 #define DEFAULT_RX_RING_SIZE 512 /* must be power of 2 */
54 #define MIN_RX_RING_SIZE 64
55 #define MAX_RX_RING_SIZE 8192
56 #define RX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
59 #define DEFAULT_TX_RING_SIZE 512 /* must be power of 2 */
60 #define MIN_TX_RING_SIZE 64
61 #define MAX_TX_RING_SIZE 4096
62 #define TX_RING_BYTES(bp) (macb_dma_desc_get_size(bp) \
65 /* level of occupied TX descriptors under which we wake up TX process */
66 #define MACB_TX_WAKEUP_THRESH(bp) (3 * (bp)->tx_ring_size / 4)
68 #define MACB_RX_INT_FLAGS (MACB_BIT(RCOMP) | MACB_BIT(ISR_ROVR))
69 #define MACB_TX_ERR_FLAGS (MACB_BIT(ISR_TUND) \
72 #define MACB_TX_INT_FLAGS (MACB_TX_ERR_FLAGS | MACB_BIT(TCOMP) \
75 /* Max length of transmit frame must be a multiple of 8 bytes */
76 #define MACB_TX_LEN_ALIGN 8
77 #define MACB_MAX_TX_LEN ((unsigned int)((1 << MACB_TX_FRMLEN_SIZE) - 1) & ~((unsigned int)(MACB_TX_LEN_ALIGN - 1)))
78 /* Limit maximum TX length as per Cadence TSO errata. This is to avoid a
79 * false amba_error in TX path from the DMA assuming there is not enough
80 * space in the SRAM (16KB) even when there is.
82 #define GEM_MAX_TX_LEN (unsigned int)(0x3FC0)
84 #define GEM_MTU_MIN_SIZE ETH_MIN_MTU
85 #define MACB_NETIF_LSO NETIF_F_TSO
87 #define MACB_WOL_HAS_MAGIC_PACKET (0x1 << 0)
88 #define MACB_WOL_ENABLED (0x1 << 1)
90 #define HS_SPEED_10000M 4
91 #define MACB_SERDES_RATE_10G 1
93 /* Graceful stop timeouts in us. We should allow up to
94 * 1 frame time (10 Mbits/s, full-duplex, ignoring collisions)
96 #define MACB_HALT_TIMEOUT 1230
98 #define MACB_PM_TIMEOUT 100 /* ms */
100 #define MACB_MDIO_TIMEOUT 1000000 /* in usecs */
102 /* DMA buffer descriptor might be different size
103 * depends on hardware configuration:
105 * 1. dma address width 32 bits:
106 * word 1: 32 bit address of Data Buffer
109 * 2. dma address width 64 bits:
110 * word 1: 32 bit address of Data Buffer
112 * word 3: upper 32 bit address of Data Buffer
115 * 3. dma address width 32 bits with hardware timestamping:
116 * word 1: 32 bit address of Data Buffer
118 * word 3: timestamp word 1
119 * word 4: timestamp word 2
121 * 4. dma address width 64 bits with hardware timestamping:
122 * word 1: 32 bit address of Data Buffer
124 * word 3: upper 32 bit address of Data Buffer
126 * word 5: timestamp word 1
127 * word 6: timestamp word 2
129 static unsigned int macb_dma_desc_get_size(struct macb *bp)
132 unsigned int desc_size;
134 switch (bp->hw_dma_cap) {
136 desc_size = sizeof(struct macb_dma_desc)
137 + sizeof(struct macb_dma_desc_64);
140 desc_size = sizeof(struct macb_dma_desc)
141 + sizeof(struct macb_dma_desc_ptp);
143 case HW_DMA_CAP_64B_PTP:
144 desc_size = sizeof(struct macb_dma_desc)
145 + sizeof(struct macb_dma_desc_64)
146 + sizeof(struct macb_dma_desc_ptp);
149 desc_size = sizeof(struct macb_dma_desc);
153 return sizeof(struct macb_dma_desc);
156 static unsigned int macb_adj_dma_desc_idx(struct macb *bp, unsigned int desc_idx)
159 switch (bp->hw_dma_cap) {
164 case HW_DMA_CAP_64B_PTP:
174 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
175 static struct macb_dma_desc_64 *macb_64b_desc(struct macb *bp, struct macb_dma_desc *desc)
177 return (struct macb_dma_desc_64 *)((void *)desc
178 + sizeof(struct macb_dma_desc));
182 /* Ring buffer accessors */
183 static unsigned int macb_tx_ring_wrap(struct macb *bp, unsigned int index)
185 return index & (bp->tx_ring_size - 1);
188 static struct macb_dma_desc *macb_tx_desc(struct macb_queue *queue,
191 index = macb_tx_ring_wrap(queue->bp, index);
192 index = macb_adj_dma_desc_idx(queue->bp, index);
193 return &queue->tx_ring[index];
196 static struct macb_tx_skb *macb_tx_skb(struct macb_queue *queue,
199 return &queue->tx_skb[macb_tx_ring_wrap(queue->bp, index)];
202 static dma_addr_t macb_tx_dma(struct macb_queue *queue, unsigned int index)
206 offset = macb_tx_ring_wrap(queue->bp, index) *
207 macb_dma_desc_get_size(queue->bp);
209 return queue->tx_ring_dma + offset;
212 static unsigned int macb_rx_ring_wrap(struct macb *bp, unsigned int index)
214 return index & (bp->rx_ring_size - 1);
217 static struct macb_dma_desc *macb_rx_desc(struct macb_queue *queue, unsigned int index)
219 index = macb_rx_ring_wrap(queue->bp, index);
220 index = macb_adj_dma_desc_idx(queue->bp, index);
221 return &queue->rx_ring[index];
224 static void *macb_rx_buffer(struct macb_queue *queue, unsigned int index)
226 return queue->rx_buffers + queue->bp->rx_buffer_size *
227 macb_rx_ring_wrap(queue->bp, index);
231 static u32 hw_readl_native(struct macb *bp, int offset)
233 return __raw_readl(bp->regs + offset);
236 static void hw_writel_native(struct macb *bp, int offset, u32 value)
238 __raw_writel(value, bp->regs + offset);
241 static u32 hw_readl(struct macb *bp, int offset)
243 return readl_relaxed(bp->regs + offset);
246 static void hw_writel(struct macb *bp, int offset, u32 value)
248 writel_relaxed(value, bp->regs + offset);
251 /* Find the CPU endianness by using the loopback bit of NCR register. When the
252 * CPU is in big endian we need to program swapped mode for management
255 static bool hw_is_native_io(void __iomem *addr)
257 u32 value = MACB_BIT(LLB);
259 __raw_writel(value, addr + MACB_NCR);
260 value = __raw_readl(addr + MACB_NCR);
262 /* Write 0 back to disable everything */
263 __raw_writel(0, addr + MACB_NCR);
265 return value == MACB_BIT(LLB);
268 static bool hw_is_gem(void __iomem *addr, bool native_io)
273 id = __raw_readl(addr + MACB_MID);
275 id = readl_relaxed(addr + MACB_MID);
277 return MACB_BFEXT(IDNUM, id) >= 0x2;
280 static void macb_set_hwaddr(struct macb *bp)
285 bottom = cpu_to_le32(*((u32 *)bp->dev->dev_addr));
286 macb_or_gem_writel(bp, SA1B, bottom);
287 top = cpu_to_le16(*((u16 *)(bp->dev->dev_addr + 4)));
288 macb_or_gem_writel(bp, SA1T, top);
290 /* Clear unused address register sets */
291 macb_or_gem_writel(bp, SA2B, 0);
292 macb_or_gem_writel(bp, SA2T, 0);
293 macb_or_gem_writel(bp, SA3B, 0);
294 macb_or_gem_writel(bp, SA3T, 0);
295 macb_or_gem_writel(bp, SA4B, 0);
296 macb_or_gem_writel(bp, SA4T, 0);
299 static void macb_get_hwaddr(struct macb *bp)
306 /* Check all 4 address register for valid address */
307 for (i = 0; i < 4; i++) {
308 bottom = macb_or_gem_readl(bp, SA1B + i * 8);
309 top = macb_or_gem_readl(bp, SA1T + i * 8);
311 addr[0] = bottom & 0xff;
312 addr[1] = (bottom >> 8) & 0xff;
313 addr[2] = (bottom >> 16) & 0xff;
314 addr[3] = (bottom >> 24) & 0xff;
315 addr[4] = top & 0xff;
316 addr[5] = (top >> 8) & 0xff;
318 if (is_valid_ether_addr(addr)) {
319 eth_hw_addr_set(bp->dev, addr);
324 dev_info(&bp->pdev->dev, "invalid hw address, using random\n");
325 eth_hw_addr_random(bp->dev);
328 static int macb_mdio_wait_for_idle(struct macb *bp)
332 return readx_poll_timeout(MACB_READ_NSR, bp, val, val & MACB_BIT(IDLE),
333 1, MACB_MDIO_TIMEOUT);
336 static int macb_mdio_read(struct mii_bus *bus, int mii_id, int regnum)
338 struct macb *bp = bus->priv;
341 status = pm_runtime_resume_and_get(&bp->pdev->dev);
345 status = macb_mdio_wait_for_idle(bp);
349 if (regnum & MII_ADDR_C45) {
350 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
351 | MACB_BF(RW, MACB_MAN_C45_ADDR)
352 | MACB_BF(PHYA, mii_id)
353 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
354 | MACB_BF(DATA, regnum & 0xFFFF)
355 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
357 status = macb_mdio_wait_for_idle(bp);
361 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
362 | MACB_BF(RW, MACB_MAN_C45_READ)
363 | MACB_BF(PHYA, mii_id)
364 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
365 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
367 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
368 | MACB_BF(RW, MACB_MAN_C22_READ)
369 | MACB_BF(PHYA, mii_id)
370 | MACB_BF(REGA, regnum)
371 | MACB_BF(CODE, MACB_MAN_C22_CODE)));
374 status = macb_mdio_wait_for_idle(bp);
378 status = MACB_BFEXT(DATA, macb_readl(bp, MAN));
381 pm_runtime_mark_last_busy(&bp->pdev->dev);
382 pm_runtime_put_autosuspend(&bp->pdev->dev);
387 static int macb_mdio_write(struct mii_bus *bus, int mii_id, int regnum,
390 struct macb *bp = bus->priv;
393 status = pm_runtime_resume_and_get(&bp->pdev->dev);
397 status = macb_mdio_wait_for_idle(bp);
399 goto mdio_write_exit;
401 if (regnum & MII_ADDR_C45) {
402 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
403 | MACB_BF(RW, MACB_MAN_C45_ADDR)
404 | MACB_BF(PHYA, mii_id)
405 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
406 | MACB_BF(DATA, regnum & 0xFFFF)
407 | MACB_BF(CODE, MACB_MAN_C45_CODE)));
409 status = macb_mdio_wait_for_idle(bp);
411 goto mdio_write_exit;
413 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C45_SOF)
414 | MACB_BF(RW, MACB_MAN_C45_WRITE)
415 | MACB_BF(PHYA, mii_id)
416 | MACB_BF(REGA, (regnum >> 16) & 0x1F)
417 | MACB_BF(CODE, MACB_MAN_C45_CODE)
418 | MACB_BF(DATA, value)));
420 macb_writel(bp, MAN, (MACB_BF(SOF, MACB_MAN_C22_SOF)
421 | MACB_BF(RW, MACB_MAN_C22_WRITE)
422 | MACB_BF(PHYA, mii_id)
423 | MACB_BF(REGA, regnum)
424 | MACB_BF(CODE, MACB_MAN_C22_CODE)
425 | MACB_BF(DATA, value)));
428 status = macb_mdio_wait_for_idle(bp);
430 goto mdio_write_exit;
433 pm_runtime_mark_last_busy(&bp->pdev->dev);
434 pm_runtime_put_autosuspend(&bp->pdev->dev);
439 static void macb_init_buffers(struct macb *bp)
441 struct macb_queue *queue;
444 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
445 queue_writel(queue, RBQP, lower_32_bits(queue->rx_ring_dma));
446 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
447 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
448 queue_writel(queue, RBQPH,
449 upper_32_bits(queue->rx_ring_dma));
451 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
452 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
453 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
454 queue_writel(queue, TBQPH,
455 upper_32_bits(queue->tx_ring_dma));
461 * macb_set_tx_clk() - Set a clock to a new frequency
462 * @bp: pointer to struct macb
463 * @speed: New frequency in Hz
465 static void macb_set_tx_clk(struct macb *bp, int speed)
467 long ferr, rate, rate_rounded;
469 if (!bp->tx_clk || (bp->caps & MACB_CAPS_CLK_HW_CHG))
472 /* In case of MII the PHY is the clock master */
473 if (bp->phy_interface == PHY_INTERFACE_MODE_MII)
490 rate_rounded = clk_round_rate(bp->tx_clk, rate);
491 if (rate_rounded < 0)
494 /* RGMII allows 50 ppm frequency error. Test and warn if this limit
497 ferr = abs(rate_rounded - rate);
498 ferr = DIV_ROUND_UP(ferr, rate / 100000);
501 "unable to generate target frequency: %ld Hz\n",
504 if (clk_set_rate(bp->tx_clk, rate_rounded))
505 netdev_err(bp->dev, "adjusting tx_clk failed.\n");
508 static void macb_usx_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode,
509 phy_interface_t interface, int speed,
512 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs);
515 config = gem_readl(bp, USX_CONTROL);
516 config = GEM_BFINS(SERDES_RATE, MACB_SERDES_RATE_10G, config);
517 config = GEM_BFINS(USX_CTRL_SPEED, HS_SPEED_10000M, config);
518 config &= ~(GEM_BIT(TX_SCR_BYPASS) | GEM_BIT(RX_SCR_BYPASS));
519 config |= GEM_BIT(TX_EN);
520 gem_writel(bp, USX_CONTROL, config);
523 static void macb_usx_pcs_get_state(struct phylink_pcs *pcs,
524 struct phylink_link_state *state)
526 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs);
529 state->speed = SPEED_10000;
531 state->an_complete = 1;
533 val = gem_readl(bp, USX_STATUS);
534 state->link = !!(val & GEM_BIT(USX_BLOCK_LOCK));
535 val = gem_readl(bp, NCFGR);
536 if (val & GEM_BIT(PAE))
537 state->pause = MLO_PAUSE_RX;
540 static int macb_usx_pcs_config(struct phylink_pcs *pcs,
542 phy_interface_t interface,
543 const unsigned long *advertising,
544 bool permit_pause_to_mac)
546 struct macb *bp = container_of(pcs, struct macb, phylink_usx_pcs);
548 gem_writel(bp, USX_CONTROL, gem_readl(bp, USX_CONTROL) |
554 static void macb_pcs_get_state(struct phylink_pcs *pcs,
555 struct phylink_link_state *state)
560 static void macb_pcs_an_restart(struct phylink_pcs *pcs)
565 static int macb_pcs_config(struct phylink_pcs *pcs,
567 phy_interface_t interface,
568 const unsigned long *advertising,
569 bool permit_pause_to_mac)
574 static const struct phylink_pcs_ops macb_phylink_usx_pcs_ops = {
575 .pcs_get_state = macb_usx_pcs_get_state,
576 .pcs_config = macb_usx_pcs_config,
577 .pcs_link_up = macb_usx_pcs_link_up,
580 static const struct phylink_pcs_ops macb_phylink_pcs_ops = {
581 .pcs_get_state = macb_pcs_get_state,
582 .pcs_an_restart = macb_pcs_an_restart,
583 .pcs_config = macb_pcs_config,
586 static void macb_mac_config(struct phylink_config *config, unsigned int mode,
587 const struct phylink_link_state *state)
589 struct net_device *ndev = to_net_dev(config->dev);
590 struct macb *bp = netdev_priv(ndev);
595 spin_lock_irqsave(&bp->lock, flags);
597 old_ctrl = ctrl = macb_or_gem_readl(bp, NCFGR);
598 old_ncr = ncr = macb_or_gem_readl(bp, NCR);
600 if (bp->caps & MACB_CAPS_MACB_IS_EMAC) {
601 if (state->interface == PHY_INTERFACE_MODE_RMII)
602 ctrl |= MACB_BIT(RM9200_RMII);
603 } else if (macb_is_gem(bp)) {
604 ctrl &= ~(GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL));
605 ncr &= ~GEM_BIT(ENABLE_HS_MAC);
607 if (state->interface == PHY_INTERFACE_MODE_SGMII) {
608 ctrl |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
609 } else if (state->interface == PHY_INTERFACE_MODE_10GBASER) {
610 ctrl |= GEM_BIT(PCSSEL);
611 ncr |= GEM_BIT(ENABLE_HS_MAC);
612 } else if (bp->caps & MACB_CAPS_MIIONRGMII &&
613 bp->phy_interface == PHY_INTERFACE_MODE_MII) {
614 ncr |= MACB_BIT(MIIONRGMII);
618 /* Apply the new configuration, if any */
620 macb_or_gem_writel(bp, NCFGR, ctrl);
623 macb_or_gem_writel(bp, NCR, ncr);
625 /* Disable AN for SGMII fixed link configuration, enable otherwise.
626 * Must be written after PCSSEL is set in NCFGR,
627 * otherwise writes will not take effect.
629 if (macb_is_gem(bp) && state->interface == PHY_INTERFACE_MODE_SGMII) {
630 u32 pcsctrl, old_pcsctrl;
632 old_pcsctrl = gem_readl(bp, PCSCNTRL);
633 if (mode == MLO_AN_FIXED)
634 pcsctrl = old_pcsctrl & ~GEM_BIT(PCSAUTONEG);
636 pcsctrl = old_pcsctrl | GEM_BIT(PCSAUTONEG);
637 if (old_pcsctrl != pcsctrl)
638 gem_writel(bp, PCSCNTRL, pcsctrl);
641 spin_unlock_irqrestore(&bp->lock, flags);
644 static void macb_mac_link_down(struct phylink_config *config, unsigned int mode,
645 phy_interface_t interface)
647 struct net_device *ndev = to_net_dev(config->dev);
648 struct macb *bp = netdev_priv(ndev);
649 struct macb_queue *queue;
653 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC))
654 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
655 queue_writel(queue, IDR,
656 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
658 /* Disable Rx and Tx */
659 ctrl = macb_readl(bp, NCR) & ~(MACB_BIT(RE) | MACB_BIT(TE));
660 macb_writel(bp, NCR, ctrl);
662 netif_tx_stop_all_queues(ndev);
665 static void macb_mac_link_up(struct phylink_config *config,
666 struct phy_device *phy,
667 unsigned int mode, phy_interface_t interface,
668 int speed, int duplex,
669 bool tx_pause, bool rx_pause)
671 struct net_device *ndev = to_net_dev(config->dev);
672 struct macb *bp = netdev_priv(ndev);
673 struct macb_queue *queue;
678 spin_lock_irqsave(&bp->lock, flags);
680 ctrl = macb_or_gem_readl(bp, NCFGR);
682 ctrl &= ~(MACB_BIT(SPD) | MACB_BIT(FD));
684 if (speed == SPEED_100)
685 ctrl |= MACB_BIT(SPD);
688 ctrl |= MACB_BIT(FD);
690 if (!(bp->caps & MACB_CAPS_MACB_IS_EMAC)) {
691 ctrl &= ~MACB_BIT(PAE);
692 if (macb_is_gem(bp)) {
693 ctrl &= ~GEM_BIT(GBE);
695 if (speed == SPEED_1000)
696 ctrl |= GEM_BIT(GBE);
700 ctrl |= MACB_BIT(PAE);
702 macb_set_tx_clk(bp, speed);
704 /* Initialize rings & buffers as clearing MACB_BIT(TE) in link down
705 * cleared the pipeline and control registers.
707 bp->macbgem_ops.mog_init_rings(bp);
708 macb_init_buffers(bp);
710 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
711 queue_writel(queue, IER,
712 bp->rx_intr_mask | MACB_TX_INT_FLAGS | MACB_BIT(HRESP));
715 macb_or_gem_writel(bp, NCFGR, ctrl);
717 if (bp->phy_interface == PHY_INTERFACE_MODE_10GBASER)
718 gem_writel(bp, HS_MAC_CONFIG, GEM_BFINS(HS_MAC_SPEED, HS_SPEED_10000M,
719 gem_readl(bp, HS_MAC_CONFIG)));
721 spin_unlock_irqrestore(&bp->lock, flags);
723 /* Enable Rx and Tx */
724 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(RE) | MACB_BIT(TE));
726 netif_tx_wake_all_queues(ndev);
729 static struct phylink_pcs *macb_mac_select_pcs(struct phylink_config *config,
730 phy_interface_t interface)
732 struct net_device *ndev = to_net_dev(config->dev);
733 struct macb *bp = netdev_priv(ndev);
735 if (interface == PHY_INTERFACE_MODE_10GBASER)
736 return &bp->phylink_usx_pcs;
737 else if (interface == PHY_INTERFACE_MODE_SGMII)
738 return &bp->phylink_sgmii_pcs;
743 static const struct phylink_mac_ops macb_phylink_ops = {
744 .validate = phylink_generic_validate,
745 .mac_select_pcs = macb_mac_select_pcs,
746 .mac_config = macb_mac_config,
747 .mac_link_down = macb_mac_link_down,
748 .mac_link_up = macb_mac_link_up,
751 static bool macb_phy_handle_exists(struct device_node *dn)
753 dn = of_parse_phandle(dn, "phy-handle", 0);
758 static int macb_phylink_connect(struct macb *bp)
760 struct device_node *dn = bp->pdev->dev.of_node;
761 struct net_device *dev = bp->dev;
762 struct phy_device *phydev;
766 ret = phylink_of_phy_connect(bp->phylink, dn, 0);
768 if (!dn || (ret && !macb_phy_handle_exists(dn))) {
769 phydev = phy_find_first(bp->mii_bus);
771 netdev_err(dev, "no PHY found\n");
775 /* attach the mac to the phy */
776 ret = phylink_connect_phy(bp->phylink, phydev);
780 netdev_err(dev, "Could not attach PHY (%d)\n", ret);
784 phylink_start(bp->phylink);
789 static void macb_get_pcs_fixed_state(struct phylink_config *config,
790 struct phylink_link_state *state)
792 struct net_device *ndev = to_net_dev(config->dev);
793 struct macb *bp = netdev_priv(ndev);
795 state->link = (macb_readl(bp, NSR) & MACB_BIT(NSR_LINK)) != 0;
798 /* based on au1000_eth. c*/
799 static int macb_mii_probe(struct net_device *dev)
801 struct macb *bp = netdev_priv(dev);
803 bp->phylink_sgmii_pcs.ops = &macb_phylink_pcs_ops;
804 bp->phylink_usx_pcs.ops = &macb_phylink_usx_pcs_ops;
806 bp->phylink_config.dev = &dev->dev;
807 bp->phylink_config.type = PHYLINK_NETDEV;
809 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {
810 bp->phylink_config.poll_fixed_state = true;
811 bp->phylink_config.get_fixed_state = macb_get_pcs_fixed_state;
814 bp->phylink_config.mac_capabilities = MAC_ASYM_PAUSE |
817 __set_bit(PHY_INTERFACE_MODE_MII,
818 bp->phylink_config.supported_interfaces);
819 __set_bit(PHY_INTERFACE_MODE_RMII,
820 bp->phylink_config.supported_interfaces);
822 /* Determine what modes are supported */
823 if (macb_is_gem(bp) && (bp->caps & MACB_CAPS_GIGABIT_MODE_AVAILABLE)) {
824 bp->phylink_config.mac_capabilities |= MAC_1000FD;
825 if (!(bp->caps & MACB_CAPS_NO_GIGABIT_HALF))
826 bp->phylink_config.mac_capabilities |= MAC_1000HD;
828 __set_bit(PHY_INTERFACE_MODE_GMII,
829 bp->phylink_config.supported_interfaces);
830 phy_interface_set_rgmii(bp->phylink_config.supported_interfaces);
832 if (bp->caps & MACB_CAPS_PCS)
833 __set_bit(PHY_INTERFACE_MODE_SGMII,
834 bp->phylink_config.supported_interfaces);
836 if (bp->caps & MACB_CAPS_HIGH_SPEED) {
837 __set_bit(PHY_INTERFACE_MODE_10GBASER,
838 bp->phylink_config.supported_interfaces);
839 bp->phylink_config.mac_capabilities |= MAC_10000FD;
843 bp->phylink = phylink_create(&bp->phylink_config, bp->pdev->dev.fwnode,
844 bp->phy_interface, &macb_phylink_ops);
845 if (IS_ERR(bp->phylink)) {
846 netdev_err(dev, "Could not create a phylink instance (%ld)\n",
847 PTR_ERR(bp->phylink));
848 return PTR_ERR(bp->phylink);
854 static int macb_mdiobus_register(struct macb *bp)
856 struct device_node *child, *np = bp->pdev->dev.of_node;
858 /* If we have a child named mdio, probe it instead of looking for PHYs
859 * directly under the MAC node
861 child = of_get_child_by_name(np, "mdio");
863 int ret = of_mdiobus_register(bp->mii_bus, child);
869 if (of_phy_is_fixed_link(np))
870 return mdiobus_register(bp->mii_bus);
872 /* Only create the PHY from the device tree if at least one PHY is
873 * described. Otherwise scan the entire MDIO bus. We do this to support
874 * old device tree that did not follow the best practices and did not
875 * describe their network PHYs.
877 for_each_available_child_of_node(np, child)
878 if (of_mdiobus_child_is_phy(child)) {
879 /* The loop increments the child refcount,
880 * decrement it before returning.
884 return of_mdiobus_register(bp->mii_bus, np);
887 return mdiobus_register(bp->mii_bus);
890 static int macb_mii_init(struct macb *bp)
894 /* Enable management port */
895 macb_writel(bp, NCR, MACB_BIT(MPE));
897 bp->mii_bus = mdiobus_alloc();
903 bp->mii_bus->name = "MACB_mii_bus";
904 bp->mii_bus->read = &macb_mdio_read;
905 bp->mii_bus->write = &macb_mdio_write;
906 snprintf(bp->mii_bus->id, MII_BUS_ID_SIZE, "%s-%x",
907 bp->pdev->name, bp->pdev->id);
908 bp->mii_bus->priv = bp;
909 bp->mii_bus->parent = &bp->pdev->dev;
911 dev_set_drvdata(&bp->dev->dev, bp->mii_bus);
913 err = macb_mdiobus_register(bp);
915 goto err_out_free_mdiobus;
917 err = macb_mii_probe(bp->dev);
919 goto err_out_unregister_bus;
923 err_out_unregister_bus:
924 mdiobus_unregister(bp->mii_bus);
925 err_out_free_mdiobus:
926 mdiobus_free(bp->mii_bus);
931 static void macb_update_stats(struct macb *bp)
933 u32 *p = &bp->hw_stats.macb.rx_pause_frames;
934 u32 *end = &bp->hw_stats.macb.tx_pause_frames + 1;
935 int offset = MACB_PFR;
937 WARN_ON((unsigned long)(end - p - 1) != (MACB_TPF - MACB_PFR) / 4);
939 for (; p < end; p++, offset += 4)
940 *p += bp->macb_reg_readl(bp, offset);
943 static int macb_halt_tx(struct macb *bp)
945 unsigned long halt_time, timeout;
948 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(THALT));
950 timeout = jiffies + usecs_to_jiffies(MACB_HALT_TIMEOUT);
953 status = macb_readl(bp, TSR);
954 if (!(status & MACB_BIT(TGO)))
958 } while (time_before(halt_time, timeout));
963 static void macb_tx_unmap(struct macb *bp, struct macb_tx_skb *tx_skb, int budget)
965 if (tx_skb->mapping) {
966 if (tx_skb->mapped_as_page)
967 dma_unmap_page(&bp->pdev->dev, tx_skb->mapping,
968 tx_skb->size, DMA_TO_DEVICE);
970 dma_unmap_single(&bp->pdev->dev, tx_skb->mapping,
971 tx_skb->size, DMA_TO_DEVICE);
976 napi_consume_skb(tx_skb->skb, budget);
981 static void macb_set_addr(struct macb *bp, struct macb_dma_desc *desc, dma_addr_t addr)
983 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
984 struct macb_dma_desc_64 *desc_64;
986 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
987 desc_64 = macb_64b_desc(bp, desc);
988 desc_64->addrh = upper_32_bits(addr);
989 /* The low bits of RX address contain the RX_USED bit, clearing
990 * of which allows packet RX. Make sure the high bits are also
991 * visible to HW at that point.
996 desc->addr = lower_32_bits(addr);
999 static dma_addr_t macb_get_addr(struct macb *bp, struct macb_dma_desc *desc)
1001 dma_addr_t addr = 0;
1002 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1003 struct macb_dma_desc_64 *desc_64;
1005 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
1006 desc_64 = macb_64b_desc(bp, desc);
1007 addr = ((u64)(desc_64->addrh) << 32);
1010 addr |= MACB_BF(RX_WADDR, MACB_BFEXT(RX_WADDR, desc->addr));
1014 static void macb_tx_error_task(struct work_struct *work)
1016 struct macb_queue *queue = container_of(work, struct macb_queue,
1018 struct macb *bp = queue->bp;
1019 struct macb_tx_skb *tx_skb;
1020 struct macb_dma_desc *desc;
1021 struct sk_buff *skb;
1023 unsigned long flags;
1025 netdev_vdbg(bp->dev, "macb_tx_error_task: q = %u, t = %u, h = %u\n",
1026 (unsigned int)(queue - bp->queues),
1027 queue->tx_tail, queue->tx_head);
1029 /* Prevent the queue NAPI TX poll from running, as it calls
1030 * macb_tx_complete(), which in turn may call netif_wake_subqueue().
1031 * As explained below, we have to halt the transmission before updating
1032 * TBQP registers so we call netif_tx_stop_all_queues() to notify the
1033 * network engine about the macb/gem being halted.
1035 napi_disable(&queue->napi_tx);
1036 spin_lock_irqsave(&bp->lock, flags);
1038 /* Make sure nobody is trying to queue up new packets */
1039 netif_tx_stop_all_queues(bp->dev);
1041 /* Stop transmission now
1042 * (in case we have just queued new packets)
1043 * macb/gem must be halted to write TBQP register
1045 if (macb_halt_tx(bp))
1046 /* Just complain for now, reinitializing TX path can be good */
1047 netdev_err(bp->dev, "BUG: halt tx timed out\n");
1049 /* Treat frames in TX queue including the ones that caused the error.
1050 * Free transmit buffers in upper layer.
1052 for (tail = queue->tx_tail; tail != queue->tx_head; tail++) {
1055 desc = macb_tx_desc(queue, tail);
1057 tx_skb = macb_tx_skb(queue, tail);
1060 if (ctrl & MACB_BIT(TX_USED)) {
1061 /* skb is set for the last buffer of the frame */
1063 macb_tx_unmap(bp, tx_skb, 0);
1065 tx_skb = macb_tx_skb(queue, tail);
1069 /* ctrl still refers to the first buffer descriptor
1070 * since it's the only one written back by the hardware
1072 if (!(ctrl & MACB_BIT(TX_BUF_EXHAUSTED))) {
1073 netdev_vdbg(bp->dev, "txerr skb %u (data %p) TX complete\n",
1074 macb_tx_ring_wrap(bp, tail),
1076 bp->dev->stats.tx_packets++;
1077 queue->stats.tx_packets++;
1078 bp->dev->stats.tx_bytes += skb->len;
1079 queue->stats.tx_bytes += skb->len;
1082 /* "Buffers exhausted mid-frame" errors may only happen
1083 * if the driver is buggy, so complain loudly about
1084 * those. Statistics are updated by hardware.
1086 if (ctrl & MACB_BIT(TX_BUF_EXHAUSTED))
1088 "BUG: TX buffers exhausted mid-frame\n");
1090 desc->ctrl = ctrl | MACB_BIT(TX_USED);
1093 macb_tx_unmap(bp, tx_skb, 0);
1096 /* Set end of TX queue */
1097 desc = macb_tx_desc(queue, 0);
1098 macb_set_addr(bp, desc, 0);
1099 desc->ctrl = MACB_BIT(TX_USED);
1101 /* Make descriptor updates visible to hardware */
1104 /* Reinitialize the TX desc queue */
1105 queue_writel(queue, TBQP, lower_32_bits(queue->tx_ring_dma));
1106 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
1107 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
1108 queue_writel(queue, TBQPH, upper_32_bits(queue->tx_ring_dma));
1110 /* Make TX ring reflect state of hardware */
1114 /* Housework before enabling TX IRQ */
1115 macb_writel(bp, TSR, macb_readl(bp, TSR));
1116 queue_writel(queue, IER, MACB_TX_INT_FLAGS);
1118 /* Now we are ready to start transmission again */
1119 netif_tx_start_all_queues(bp->dev);
1120 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1122 spin_unlock_irqrestore(&bp->lock, flags);
1123 napi_enable(&queue->napi_tx);
1126 static bool ptp_one_step_sync(struct sk_buff *skb)
1128 struct ptp_header *hdr;
1129 unsigned int ptp_class;
1132 /* No need to parse packet if PTP TS is not involved */
1133 if (likely(!(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP)))
1136 /* Identify and return whether PTP one step sync is being processed */
1137 ptp_class = ptp_classify_raw(skb);
1138 if (ptp_class == PTP_CLASS_NONE)
1141 hdr = ptp_parse_header(skb, ptp_class);
1145 if (hdr->flag_field[0] & PTP_FLAG_TWOSTEP)
1148 msgtype = ptp_get_msgtype(hdr, ptp_class);
1149 if (msgtype == PTP_MSGTYPE_SYNC)
1156 static int macb_tx_complete(struct macb_queue *queue, int budget)
1158 struct macb *bp = queue->bp;
1159 u16 queue_index = queue - bp->queues;
1164 spin_lock(&queue->tx_ptr_lock);
1165 head = queue->tx_head;
1166 for (tail = queue->tx_tail; tail != head && packets < budget; tail++) {
1167 struct macb_tx_skb *tx_skb;
1168 struct sk_buff *skb;
1169 struct macb_dma_desc *desc;
1172 desc = macb_tx_desc(queue, tail);
1174 /* Make hw descriptor updates visible to CPU */
1179 /* TX_USED bit is only set by hardware on the very first buffer
1180 * descriptor of the transmitted frame.
1182 if (!(ctrl & MACB_BIT(TX_USED)))
1185 /* Process all buffers of the current transmitted frame */
1187 tx_skb = macb_tx_skb(queue, tail);
1190 /* First, update TX stats if needed */
1192 if (unlikely(skb_shinfo(skb)->tx_flags & SKBTX_HW_TSTAMP) &&
1193 !ptp_one_step_sync(skb) &&
1194 gem_ptp_do_txstamp(queue, skb, desc) == 0) {
1195 /* skb now belongs to timestamp buffer
1196 * and will be removed later
1200 netdev_vdbg(bp->dev, "skb %u (data %p) TX complete\n",
1201 macb_tx_ring_wrap(bp, tail),
1203 bp->dev->stats.tx_packets++;
1204 queue->stats.tx_packets++;
1205 bp->dev->stats.tx_bytes += skb->len;
1206 queue->stats.tx_bytes += skb->len;
1210 /* Now we can safely release resources */
1211 macb_tx_unmap(bp, tx_skb, budget);
1213 /* skb is set only for the last buffer of the frame.
1214 * WARNING: at this point skb has been freed by
1222 queue->tx_tail = tail;
1223 if (__netif_subqueue_stopped(bp->dev, queue_index) &&
1224 CIRC_CNT(queue->tx_head, queue->tx_tail,
1225 bp->tx_ring_size) <= MACB_TX_WAKEUP_THRESH(bp))
1226 netif_wake_subqueue(bp->dev, queue_index);
1227 spin_unlock(&queue->tx_ptr_lock);
1232 static void gem_rx_refill(struct macb_queue *queue)
1235 struct sk_buff *skb;
1237 struct macb *bp = queue->bp;
1238 struct macb_dma_desc *desc;
1240 while (CIRC_SPACE(queue->rx_prepared_head, queue->rx_tail,
1241 bp->rx_ring_size) > 0) {
1242 entry = macb_rx_ring_wrap(bp, queue->rx_prepared_head);
1244 /* Make hw descriptor updates visible to CPU */
1247 desc = macb_rx_desc(queue, entry);
1249 if (!queue->rx_skbuff[entry]) {
1250 /* allocate sk_buff for this free entry in ring */
1251 skb = netdev_alloc_skb(bp->dev, bp->rx_buffer_size);
1252 if (unlikely(!skb)) {
1254 "Unable to allocate sk_buff\n");
1258 /* now fill corresponding descriptor entry */
1259 paddr = dma_map_single(&bp->pdev->dev, skb->data,
1262 if (dma_mapping_error(&bp->pdev->dev, paddr)) {
1267 queue->rx_skbuff[entry] = skb;
1269 if (entry == bp->rx_ring_size - 1)
1270 paddr |= MACB_BIT(RX_WRAP);
1272 /* Setting addr clears RX_USED and allows reception,
1273 * make sure ctrl is cleared first to avoid a race.
1276 macb_set_addr(bp, desc, paddr);
1278 /* properly align Ethernet header */
1279 skb_reserve(skb, NET_IP_ALIGN);
1283 desc->addr &= ~MACB_BIT(RX_USED);
1285 queue->rx_prepared_head++;
1288 /* Make descriptor updates visible to hardware */
1291 netdev_vdbg(bp->dev, "rx ring: queue: %p, prepared head %d, tail %d\n",
1292 queue, queue->rx_prepared_head, queue->rx_tail);
1295 /* Mark DMA descriptors from begin up to and not including end as unused */
1296 static void discard_partial_frame(struct macb_queue *queue, unsigned int begin,
1301 for (frag = begin; frag != end; frag++) {
1302 struct macb_dma_desc *desc = macb_rx_desc(queue, frag);
1304 desc->addr &= ~MACB_BIT(RX_USED);
1307 /* Make descriptor updates visible to hardware */
1310 /* When this happens, the hardware stats registers for
1311 * whatever caused this is updated, so we don't have to record
1316 static int gem_rx(struct macb_queue *queue, struct napi_struct *napi,
1319 struct macb *bp = queue->bp;
1322 struct sk_buff *skb;
1323 struct macb_dma_desc *desc;
1326 while (count < budget) {
1331 entry = macb_rx_ring_wrap(bp, queue->rx_tail);
1332 desc = macb_rx_desc(queue, entry);
1334 /* Make hw descriptor updates visible to CPU */
1337 rxused = (desc->addr & MACB_BIT(RX_USED)) ? true : false;
1338 addr = macb_get_addr(bp, desc);
1343 /* Ensure ctrl is at least as up-to-date as rxused */
1351 if (!(ctrl & MACB_BIT(RX_SOF) && ctrl & MACB_BIT(RX_EOF))) {
1353 "not whole frame pointed by descriptor\n");
1354 bp->dev->stats.rx_dropped++;
1355 queue->stats.rx_dropped++;
1358 skb = queue->rx_skbuff[entry];
1359 if (unlikely(!skb)) {
1361 "inconsistent Rx descriptor chain\n");
1362 bp->dev->stats.rx_dropped++;
1363 queue->stats.rx_dropped++;
1366 /* now everything is ready for receiving packet */
1367 queue->rx_skbuff[entry] = NULL;
1368 len = ctrl & bp->rx_frm_len_mask;
1370 netdev_vdbg(bp->dev, "gem_rx %u (len %u)\n", entry, len);
1373 dma_unmap_single(&bp->pdev->dev, addr,
1374 bp->rx_buffer_size, DMA_FROM_DEVICE);
1376 skb->protocol = eth_type_trans(skb, bp->dev);
1377 skb_checksum_none_assert(skb);
1378 if (bp->dev->features & NETIF_F_RXCSUM &&
1379 !(bp->dev->flags & IFF_PROMISC) &&
1380 GEM_BFEXT(RX_CSUM, ctrl) & GEM_RX_CSUM_CHECKED_MASK)
1381 skb->ip_summed = CHECKSUM_UNNECESSARY;
1383 bp->dev->stats.rx_packets++;
1384 queue->stats.rx_packets++;
1385 bp->dev->stats.rx_bytes += skb->len;
1386 queue->stats.rx_bytes += skb->len;
1388 gem_ptp_do_rxstamp(bp, skb, desc);
1390 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
1391 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1392 skb->len, skb->csum);
1393 print_hex_dump(KERN_DEBUG, " mac: ", DUMP_PREFIX_ADDRESS, 16, 1,
1394 skb_mac_header(skb), 16, true);
1395 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_ADDRESS, 16, 1,
1396 skb->data, 32, true);
1399 napi_gro_receive(napi, skb);
1402 gem_rx_refill(queue);
1407 static int macb_rx_frame(struct macb_queue *queue, struct napi_struct *napi,
1408 unsigned int first_frag, unsigned int last_frag)
1412 unsigned int offset;
1413 struct sk_buff *skb;
1414 struct macb_dma_desc *desc;
1415 struct macb *bp = queue->bp;
1417 desc = macb_rx_desc(queue, last_frag);
1418 len = desc->ctrl & bp->rx_frm_len_mask;
1420 netdev_vdbg(bp->dev, "macb_rx_frame frags %u - %u (len %u)\n",
1421 macb_rx_ring_wrap(bp, first_frag),
1422 macb_rx_ring_wrap(bp, last_frag), len);
1424 /* The ethernet header starts NET_IP_ALIGN bytes into the
1425 * first buffer. Since the header is 14 bytes, this makes the
1426 * payload word-aligned.
1428 * Instead of calling skb_reserve(NET_IP_ALIGN), we just copy
1429 * the two padding bytes into the skb so that we avoid hitting
1430 * the slowpath in memcpy(), and pull them off afterwards.
1432 skb = netdev_alloc_skb(bp->dev, len + NET_IP_ALIGN);
1434 bp->dev->stats.rx_dropped++;
1435 for (frag = first_frag; ; frag++) {
1436 desc = macb_rx_desc(queue, frag);
1437 desc->addr &= ~MACB_BIT(RX_USED);
1438 if (frag == last_frag)
1442 /* Make descriptor updates visible to hardware */
1449 len += NET_IP_ALIGN;
1450 skb_checksum_none_assert(skb);
1453 for (frag = first_frag; ; frag++) {
1454 unsigned int frag_len = bp->rx_buffer_size;
1456 if (offset + frag_len > len) {
1457 if (unlikely(frag != last_frag)) {
1458 dev_kfree_skb_any(skb);
1461 frag_len = len - offset;
1463 skb_copy_to_linear_data_offset(skb, offset,
1464 macb_rx_buffer(queue, frag),
1466 offset += bp->rx_buffer_size;
1467 desc = macb_rx_desc(queue, frag);
1468 desc->addr &= ~MACB_BIT(RX_USED);
1470 if (frag == last_frag)
1474 /* Make descriptor updates visible to hardware */
1477 __skb_pull(skb, NET_IP_ALIGN);
1478 skb->protocol = eth_type_trans(skb, bp->dev);
1480 bp->dev->stats.rx_packets++;
1481 bp->dev->stats.rx_bytes += skb->len;
1482 netdev_vdbg(bp->dev, "received skb of length %u, csum: %08x\n",
1483 skb->len, skb->csum);
1484 napi_gro_receive(napi, skb);
1489 static inline void macb_init_rx_ring(struct macb_queue *queue)
1491 struct macb *bp = queue->bp;
1493 struct macb_dma_desc *desc = NULL;
1496 addr = queue->rx_buffers_dma;
1497 for (i = 0; i < bp->rx_ring_size; i++) {
1498 desc = macb_rx_desc(queue, i);
1499 macb_set_addr(bp, desc, addr);
1501 addr += bp->rx_buffer_size;
1503 desc->addr |= MACB_BIT(RX_WRAP);
1507 static int macb_rx(struct macb_queue *queue, struct napi_struct *napi,
1510 struct macb *bp = queue->bp;
1511 bool reset_rx_queue = false;
1514 int first_frag = -1;
1516 for (tail = queue->rx_tail; budget > 0; tail++) {
1517 struct macb_dma_desc *desc = macb_rx_desc(queue, tail);
1520 /* Make hw descriptor updates visible to CPU */
1523 if (!(desc->addr & MACB_BIT(RX_USED)))
1526 /* Ensure ctrl is at least as up-to-date as addr */
1531 if (ctrl & MACB_BIT(RX_SOF)) {
1532 if (first_frag != -1)
1533 discard_partial_frame(queue, first_frag, tail);
1537 if (ctrl & MACB_BIT(RX_EOF)) {
1540 if (unlikely(first_frag == -1)) {
1541 reset_rx_queue = true;
1545 dropped = macb_rx_frame(queue, napi, first_frag, tail);
1547 if (unlikely(dropped < 0)) {
1548 reset_rx_queue = true;
1558 if (unlikely(reset_rx_queue)) {
1559 unsigned long flags;
1562 netdev_err(bp->dev, "RX queue corruption: reset it\n");
1564 spin_lock_irqsave(&bp->lock, flags);
1566 ctrl = macb_readl(bp, NCR);
1567 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1569 macb_init_rx_ring(queue);
1570 queue_writel(queue, RBQP, queue->rx_ring_dma);
1572 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1574 spin_unlock_irqrestore(&bp->lock, flags);
1578 if (first_frag != -1)
1579 queue->rx_tail = first_frag;
1581 queue->rx_tail = tail;
1586 static bool macb_rx_pending(struct macb_queue *queue)
1588 struct macb *bp = queue->bp;
1590 struct macb_dma_desc *desc;
1592 entry = macb_rx_ring_wrap(bp, queue->rx_tail);
1593 desc = macb_rx_desc(queue, entry);
1595 /* Make hw descriptor updates visible to CPU */
1598 return (desc->addr & MACB_BIT(RX_USED)) != 0;
1601 static int macb_rx_poll(struct napi_struct *napi, int budget)
1603 struct macb_queue *queue = container_of(napi, struct macb_queue, napi_rx);
1604 struct macb *bp = queue->bp;
1607 work_done = bp->macbgem_ops.mog_rx(queue, napi, budget);
1609 netdev_vdbg(bp->dev, "RX poll: queue = %u, work_done = %d, budget = %d\n",
1610 (unsigned int)(queue - bp->queues), work_done, budget);
1612 if (work_done < budget && napi_complete_done(napi, work_done)) {
1613 queue_writel(queue, IER, bp->rx_intr_mask);
1615 /* Packet completions only seem to propagate to raise
1616 * interrupts when interrupts are enabled at the time, so if
1617 * packets were received while interrupts were disabled,
1618 * they will not cause another interrupt to be generated when
1619 * interrupts are re-enabled.
1620 * Check for this case here to avoid losing a wakeup. This can
1621 * potentially race with the interrupt handler doing the same
1622 * actions if an interrupt is raised just after enabling them,
1623 * but this should be harmless.
1625 if (macb_rx_pending(queue)) {
1626 queue_writel(queue, IDR, bp->rx_intr_mask);
1627 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1628 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1629 netdev_vdbg(bp->dev, "poll: packets pending, reschedule\n");
1630 napi_schedule(napi);
1634 /* TODO: Handle errors */
1639 static void macb_tx_restart(struct macb_queue *queue)
1641 struct macb *bp = queue->bp;
1642 unsigned int head_idx, tbqp;
1644 spin_lock(&queue->tx_ptr_lock);
1646 if (queue->tx_head == queue->tx_tail)
1647 goto out_tx_ptr_unlock;
1649 tbqp = queue_readl(queue, TBQP) / macb_dma_desc_get_size(bp);
1650 tbqp = macb_adj_dma_desc_idx(bp, macb_tx_ring_wrap(bp, tbqp));
1651 head_idx = macb_adj_dma_desc_idx(bp, macb_tx_ring_wrap(bp, queue->tx_head));
1653 if (tbqp == head_idx)
1654 goto out_tx_ptr_unlock;
1656 spin_lock_irq(&bp->lock);
1657 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
1658 spin_unlock_irq(&bp->lock);
1661 spin_unlock(&queue->tx_ptr_lock);
1664 static bool macb_tx_complete_pending(struct macb_queue *queue)
1666 bool retval = false;
1668 spin_lock(&queue->tx_ptr_lock);
1669 if (queue->tx_head != queue->tx_tail) {
1670 /* Make hw descriptor updates visible to CPU */
1673 if (macb_tx_desc(queue, queue->tx_tail)->ctrl & MACB_BIT(TX_USED))
1676 spin_unlock(&queue->tx_ptr_lock);
1680 static int macb_tx_poll(struct napi_struct *napi, int budget)
1682 struct macb_queue *queue = container_of(napi, struct macb_queue, napi_tx);
1683 struct macb *bp = queue->bp;
1686 work_done = macb_tx_complete(queue, budget);
1688 rmb(); // ensure txubr_pending is up to date
1689 if (queue->txubr_pending) {
1690 queue->txubr_pending = false;
1691 netdev_vdbg(bp->dev, "poll: tx restart\n");
1692 macb_tx_restart(queue);
1695 netdev_vdbg(bp->dev, "TX poll: queue = %u, work_done = %d, budget = %d\n",
1696 (unsigned int)(queue - bp->queues), work_done, budget);
1698 if (work_done < budget && napi_complete_done(napi, work_done)) {
1699 queue_writel(queue, IER, MACB_BIT(TCOMP));
1701 /* Packet completions only seem to propagate to raise
1702 * interrupts when interrupts are enabled at the time, so if
1703 * packets were sent while interrupts were disabled,
1704 * they will not cause another interrupt to be generated when
1705 * interrupts are re-enabled.
1706 * Check for this case here to avoid losing a wakeup. This can
1707 * potentially race with the interrupt handler doing the same
1708 * actions if an interrupt is raised just after enabling them,
1709 * but this should be harmless.
1711 if (macb_tx_complete_pending(queue)) {
1712 queue_writel(queue, IDR, MACB_BIT(TCOMP));
1713 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1714 queue_writel(queue, ISR, MACB_BIT(TCOMP));
1715 netdev_vdbg(bp->dev, "TX poll: packets pending, reschedule\n");
1716 napi_schedule(napi);
1723 static void macb_hresp_error_task(struct tasklet_struct *t)
1725 struct macb *bp = from_tasklet(bp, t, hresp_err_tasklet);
1726 struct net_device *dev = bp->dev;
1727 struct macb_queue *queue;
1731 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
1732 queue_writel(queue, IDR, bp->rx_intr_mask |
1736 ctrl = macb_readl(bp, NCR);
1737 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
1738 macb_writel(bp, NCR, ctrl);
1740 netif_tx_stop_all_queues(dev);
1741 netif_carrier_off(dev);
1743 bp->macbgem_ops.mog_init_rings(bp);
1745 /* Initialize TX and RX buffers */
1746 macb_init_buffers(bp);
1748 /* Enable interrupts */
1749 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1750 queue_writel(queue, IER,
1755 ctrl |= MACB_BIT(RE) | MACB_BIT(TE);
1756 macb_writel(bp, NCR, ctrl);
1758 netif_carrier_on(dev);
1759 netif_tx_start_all_queues(dev);
1762 static irqreturn_t macb_wol_interrupt(int irq, void *dev_id)
1764 struct macb_queue *queue = dev_id;
1765 struct macb *bp = queue->bp;
1768 status = queue_readl(queue, ISR);
1770 if (unlikely(!status))
1773 spin_lock(&bp->lock);
1775 if (status & MACB_BIT(WOL)) {
1776 queue_writel(queue, IDR, MACB_BIT(WOL));
1777 macb_writel(bp, WOL, 0);
1778 netdev_vdbg(bp->dev, "MACB WoL: queue = %u, isr = 0x%08lx\n",
1779 (unsigned int)(queue - bp->queues),
1780 (unsigned long)status);
1781 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1782 queue_writel(queue, ISR, MACB_BIT(WOL));
1783 pm_wakeup_event(&bp->pdev->dev, 0);
1786 spin_unlock(&bp->lock);
1791 static irqreturn_t gem_wol_interrupt(int irq, void *dev_id)
1793 struct macb_queue *queue = dev_id;
1794 struct macb *bp = queue->bp;
1797 status = queue_readl(queue, ISR);
1799 if (unlikely(!status))
1802 spin_lock(&bp->lock);
1804 if (status & GEM_BIT(WOL)) {
1805 queue_writel(queue, IDR, GEM_BIT(WOL));
1806 gem_writel(bp, WOL, 0);
1807 netdev_vdbg(bp->dev, "GEM WoL: queue = %u, isr = 0x%08lx\n",
1808 (unsigned int)(queue - bp->queues),
1809 (unsigned long)status);
1810 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1811 queue_writel(queue, ISR, GEM_BIT(WOL));
1812 pm_wakeup_event(&bp->pdev->dev, 0);
1815 spin_unlock(&bp->lock);
1820 static irqreturn_t macb_interrupt(int irq, void *dev_id)
1822 struct macb_queue *queue = dev_id;
1823 struct macb *bp = queue->bp;
1824 struct net_device *dev = bp->dev;
1827 status = queue_readl(queue, ISR);
1829 if (unlikely(!status))
1832 spin_lock(&bp->lock);
1835 /* close possible race with dev_close */
1836 if (unlikely(!netif_running(dev))) {
1837 queue_writel(queue, IDR, -1);
1838 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1839 queue_writel(queue, ISR, -1);
1843 netdev_vdbg(bp->dev, "queue = %u, isr = 0x%08lx\n",
1844 (unsigned int)(queue - bp->queues),
1845 (unsigned long)status);
1847 if (status & bp->rx_intr_mask) {
1848 /* There's no point taking any more interrupts
1849 * until we have processed the buffers. The
1850 * scheduling call may fail if the poll routine
1851 * is already scheduled, so disable interrupts
1854 queue_writel(queue, IDR, bp->rx_intr_mask);
1855 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1856 queue_writel(queue, ISR, MACB_BIT(RCOMP));
1858 if (napi_schedule_prep(&queue->napi_rx)) {
1859 netdev_vdbg(bp->dev, "scheduling RX softirq\n");
1860 __napi_schedule(&queue->napi_rx);
1864 if (status & (MACB_BIT(TCOMP) |
1866 queue_writel(queue, IDR, MACB_BIT(TCOMP));
1867 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1868 queue_writel(queue, ISR, MACB_BIT(TCOMP) |
1871 if (status & MACB_BIT(TXUBR)) {
1872 queue->txubr_pending = true;
1873 wmb(); // ensure softirq can see update
1876 if (napi_schedule_prep(&queue->napi_tx)) {
1877 netdev_vdbg(bp->dev, "scheduling TX softirq\n");
1878 __napi_schedule(&queue->napi_tx);
1882 if (unlikely(status & (MACB_TX_ERR_FLAGS))) {
1883 queue_writel(queue, IDR, MACB_TX_INT_FLAGS);
1884 schedule_work(&queue->tx_error_task);
1886 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1887 queue_writel(queue, ISR, MACB_TX_ERR_FLAGS);
1892 /* Link change detection isn't possible with RMII, so we'll
1893 * add that if/when we get our hands on a full-blown MII PHY.
1896 /* There is a hardware issue under heavy load where DMA can
1897 * stop, this causes endless "used buffer descriptor read"
1898 * interrupts but it can be cleared by re-enabling RX. See
1899 * the at91rm9200 manual, section 41.3.1 or the Zynq manual
1900 * section 16.7.4 for details. RXUBR is only enabled for
1901 * these two versions.
1903 if (status & MACB_BIT(RXUBR)) {
1904 ctrl = macb_readl(bp, NCR);
1905 macb_writel(bp, NCR, ctrl & ~MACB_BIT(RE));
1907 macb_writel(bp, NCR, ctrl | MACB_BIT(RE));
1909 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1910 queue_writel(queue, ISR, MACB_BIT(RXUBR));
1913 if (status & MACB_BIT(ISR_ROVR)) {
1914 /* We missed at least one packet */
1915 if (macb_is_gem(bp))
1916 bp->hw_stats.gem.rx_overruns++;
1918 bp->hw_stats.macb.rx_overruns++;
1920 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1921 queue_writel(queue, ISR, MACB_BIT(ISR_ROVR));
1924 if (status & MACB_BIT(HRESP)) {
1925 tasklet_schedule(&bp->hresp_err_tasklet);
1926 netdev_err(dev, "DMA bus error: HRESP not OK\n");
1928 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
1929 queue_writel(queue, ISR, MACB_BIT(HRESP));
1931 status = queue_readl(queue, ISR);
1934 spin_unlock(&bp->lock);
1939 #ifdef CONFIG_NET_POLL_CONTROLLER
1940 /* Polling receive - used by netconsole and other diagnostic tools
1941 * to allow network i/o with interrupts disabled.
1943 static void macb_poll_controller(struct net_device *dev)
1945 struct macb *bp = netdev_priv(dev);
1946 struct macb_queue *queue;
1947 unsigned long flags;
1950 local_irq_save(flags);
1951 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
1952 macb_interrupt(dev->irq, queue);
1953 local_irq_restore(flags);
1957 static unsigned int macb_tx_map(struct macb *bp,
1958 struct macb_queue *queue,
1959 struct sk_buff *skb,
1960 unsigned int hdrlen)
1963 unsigned int len, entry, i, tx_head = queue->tx_head;
1964 struct macb_tx_skb *tx_skb = NULL;
1965 struct macb_dma_desc *desc;
1966 unsigned int offset, size, count = 0;
1967 unsigned int f, nr_frags = skb_shinfo(skb)->nr_frags;
1968 unsigned int eof = 1, mss_mfs = 0;
1969 u32 ctrl, lso_ctrl = 0, seq_ctrl = 0;
1972 if (skb_shinfo(skb)->gso_size != 0) {
1973 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
1975 lso_ctrl = MACB_LSO_UFO_ENABLE;
1978 lso_ctrl = MACB_LSO_TSO_ENABLE;
1981 /* First, map non-paged data */
1982 len = skb_headlen(skb);
1984 /* first buffer length */
1989 entry = macb_tx_ring_wrap(bp, tx_head);
1990 tx_skb = &queue->tx_skb[entry];
1992 mapping = dma_map_single(&bp->pdev->dev,
1994 size, DMA_TO_DEVICE);
1995 if (dma_mapping_error(&bp->pdev->dev, mapping))
1998 /* Save info to properly release resources */
2000 tx_skb->mapping = mapping;
2001 tx_skb->size = size;
2002 tx_skb->mapped_as_page = false;
2009 size = min(len, bp->max_tx_length);
2012 /* Then, map paged data from fragments */
2013 for (f = 0; f < nr_frags; f++) {
2014 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
2016 len = skb_frag_size(frag);
2019 size = min(len, bp->max_tx_length);
2020 entry = macb_tx_ring_wrap(bp, tx_head);
2021 tx_skb = &queue->tx_skb[entry];
2023 mapping = skb_frag_dma_map(&bp->pdev->dev, frag,
2024 offset, size, DMA_TO_DEVICE);
2025 if (dma_mapping_error(&bp->pdev->dev, mapping))
2028 /* Save info to properly release resources */
2030 tx_skb->mapping = mapping;
2031 tx_skb->size = size;
2032 tx_skb->mapped_as_page = true;
2041 /* Should never happen */
2042 if (unlikely(!tx_skb)) {
2043 netdev_err(bp->dev, "BUG! empty skb!\n");
2047 /* This is the last buffer of the frame: save socket buffer */
2050 /* Update TX ring: update buffer descriptors in reverse order
2051 * to avoid race condition
2054 /* Set 'TX_USED' bit in buffer descriptor at tx_head position
2055 * to set the end of TX queue
2058 entry = macb_tx_ring_wrap(bp, i);
2059 ctrl = MACB_BIT(TX_USED);
2060 desc = macb_tx_desc(queue, entry);
2064 if (lso_ctrl == MACB_LSO_UFO_ENABLE)
2065 /* include header and FCS in value given to h/w */
2066 mss_mfs = skb_shinfo(skb)->gso_size +
2067 skb_transport_offset(skb) +
2070 mss_mfs = skb_shinfo(skb)->gso_size;
2071 /* TCP Sequence Number Source Select
2072 * can be set only for TSO
2080 entry = macb_tx_ring_wrap(bp, i);
2081 tx_skb = &queue->tx_skb[entry];
2082 desc = macb_tx_desc(queue, entry);
2084 ctrl = (u32)tx_skb->size;
2086 ctrl |= MACB_BIT(TX_LAST);
2089 if (unlikely(entry == (bp->tx_ring_size - 1)))
2090 ctrl |= MACB_BIT(TX_WRAP);
2092 /* First descriptor is header descriptor */
2093 if (i == queue->tx_head) {
2094 ctrl |= MACB_BF(TX_LSO, lso_ctrl);
2095 ctrl |= MACB_BF(TX_TCP_SEQ_SRC, seq_ctrl);
2096 if ((bp->dev->features & NETIF_F_HW_CSUM) &&
2097 skb->ip_summed != CHECKSUM_PARTIAL && !lso_ctrl &&
2098 !ptp_one_step_sync(skb))
2099 ctrl |= MACB_BIT(TX_NOCRC);
2101 /* Only set MSS/MFS on payload descriptors
2102 * (second or later descriptor)
2104 ctrl |= MACB_BF(MSS_MFS, mss_mfs);
2106 /* Set TX buffer descriptor */
2107 macb_set_addr(bp, desc, tx_skb->mapping);
2108 /* desc->addr must be visible to hardware before clearing
2109 * 'TX_USED' bit in desc->ctrl.
2113 } while (i != queue->tx_head);
2115 queue->tx_head = tx_head;
2120 netdev_err(bp->dev, "TX DMA map failed\n");
2122 for (i = queue->tx_head; i != tx_head; i++) {
2123 tx_skb = macb_tx_skb(queue, i);
2125 macb_tx_unmap(bp, tx_skb, 0);
2131 static netdev_features_t macb_features_check(struct sk_buff *skb,
2132 struct net_device *dev,
2133 netdev_features_t features)
2135 unsigned int nr_frags, f;
2136 unsigned int hdrlen;
2138 /* Validate LSO compatibility */
2140 /* there is only one buffer or protocol is not UDP */
2141 if (!skb_is_nonlinear(skb) || (ip_hdr(skb)->protocol != IPPROTO_UDP))
2144 /* length of header */
2145 hdrlen = skb_transport_offset(skb);
2148 * When software supplies two or more payload buffers all payload buffers
2149 * apart from the last must be a multiple of 8 bytes in size.
2151 if (!IS_ALIGNED(skb_headlen(skb) - hdrlen, MACB_TX_LEN_ALIGN))
2152 return features & ~MACB_NETIF_LSO;
2154 nr_frags = skb_shinfo(skb)->nr_frags;
2155 /* No need to check last fragment */
2157 for (f = 0; f < nr_frags; f++) {
2158 const skb_frag_t *frag = &skb_shinfo(skb)->frags[f];
2160 if (!IS_ALIGNED(skb_frag_size(frag), MACB_TX_LEN_ALIGN))
2161 return features & ~MACB_NETIF_LSO;
2166 static inline int macb_clear_csum(struct sk_buff *skb)
2168 /* no change for packets without checksum offloading */
2169 if (skb->ip_summed != CHECKSUM_PARTIAL)
2172 /* make sure we can modify the header */
2173 if (unlikely(skb_cow_head(skb, 0)))
2176 /* initialize checksum field
2177 * This is required - at least for Zynq, which otherwise calculates
2178 * wrong UDP header checksums for UDP packets with UDP data len <=2
2180 *(__sum16 *)(skb_checksum_start(skb) + skb->csum_offset) = 0;
2184 static int macb_pad_and_fcs(struct sk_buff **skb, struct net_device *ndev)
2186 bool cloned = skb_cloned(*skb) || skb_header_cloned(*skb) ||
2187 skb_is_nonlinear(*skb);
2188 int padlen = ETH_ZLEN - (*skb)->len;
2189 int headroom = skb_headroom(*skb);
2190 int tailroom = skb_tailroom(*skb);
2191 struct sk_buff *nskb;
2194 if (!(ndev->features & NETIF_F_HW_CSUM) ||
2195 !((*skb)->ip_summed != CHECKSUM_PARTIAL) ||
2196 skb_shinfo(*skb)->gso_size || ptp_one_step_sync(*skb))
2200 /* FCS could be appeded to tailroom. */
2201 if (tailroom >= ETH_FCS_LEN)
2203 /* FCS could be appeded by moving data to headroom. */
2204 else if (!cloned && headroom + tailroom >= ETH_FCS_LEN)
2206 /* No room for FCS, need to reallocate skb. */
2208 padlen = ETH_FCS_LEN;
2210 /* Add room for FCS. */
2211 padlen += ETH_FCS_LEN;
2214 if (!cloned && headroom + tailroom >= padlen) {
2215 (*skb)->data = memmove((*skb)->head, (*skb)->data, (*skb)->len);
2216 skb_set_tail_pointer(*skb, (*skb)->len);
2218 nskb = skb_copy_expand(*skb, 0, padlen, GFP_ATOMIC);
2222 dev_consume_skb_any(*skb);
2226 if (padlen > ETH_FCS_LEN)
2227 skb_put_zero(*skb, padlen - ETH_FCS_LEN);
2230 /* set FCS to packet */
2231 fcs = crc32_le(~0, (*skb)->data, (*skb)->len);
2234 skb_put_u8(*skb, fcs & 0xff);
2235 skb_put_u8(*skb, (fcs >> 8) & 0xff);
2236 skb_put_u8(*skb, (fcs >> 16) & 0xff);
2237 skb_put_u8(*skb, (fcs >> 24) & 0xff);
2242 static netdev_tx_t macb_start_xmit(struct sk_buff *skb, struct net_device *dev)
2244 u16 queue_index = skb_get_queue_mapping(skb);
2245 struct macb *bp = netdev_priv(dev);
2246 struct macb_queue *queue = &bp->queues[queue_index];
2247 unsigned int desc_cnt, nr_frags, frag_size, f;
2248 unsigned int hdrlen;
2250 netdev_tx_t ret = NETDEV_TX_OK;
2252 if (macb_clear_csum(skb)) {
2253 dev_kfree_skb_any(skb);
2257 if (macb_pad_and_fcs(&skb, dev)) {
2258 dev_kfree_skb_any(skb);
2262 is_lso = (skb_shinfo(skb)->gso_size != 0);
2265 /* length of headers */
2266 if (ip_hdr(skb)->protocol == IPPROTO_UDP)
2267 /* only queue eth + ip headers separately for UDP */
2268 hdrlen = skb_transport_offset(skb);
2270 hdrlen = skb_tcp_all_headers(skb);
2271 if (skb_headlen(skb) < hdrlen) {
2272 netdev_err(bp->dev, "Error - LSO headers fragmented!!!\n");
2273 /* if this is required, would need to copy to single buffer */
2274 return NETDEV_TX_BUSY;
2277 hdrlen = min(skb_headlen(skb), bp->max_tx_length);
2279 #if defined(DEBUG) && defined(VERBOSE_DEBUG)
2280 netdev_vdbg(bp->dev,
2281 "start_xmit: queue %hu len %u head %p data %p tail %p end %p\n",
2282 queue_index, skb->len, skb->head, skb->data,
2283 skb_tail_pointer(skb), skb_end_pointer(skb));
2284 print_hex_dump(KERN_DEBUG, "data: ", DUMP_PREFIX_OFFSET, 16, 1,
2285 skb->data, 16, true);
2288 /* Count how many TX buffer descriptors are needed to send this
2289 * socket buffer: skb fragments of jumbo frames may need to be
2290 * split into many buffer descriptors.
2292 if (is_lso && (skb_headlen(skb) > hdrlen))
2293 /* extra header descriptor if also payload in first buffer */
2294 desc_cnt = DIV_ROUND_UP((skb_headlen(skb) - hdrlen), bp->max_tx_length) + 1;
2296 desc_cnt = DIV_ROUND_UP(skb_headlen(skb), bp->max_tx_length);
2297 nr_frags = skb_shinfo(skb)->nr_frags;
2298 for (f = 0; f < nr_frags; f++) {
2299 frag_size = skb_frag_size(&skb_shinfo(skb)->frags[f]);
2300 desc_cnt += DIV_ROUND_UP(frag_size, bp->max_tx_length);
2303 spin_lock_bh(&queue->tx_ptr_lock);
2305 /* This is a hard error, log it. */
2306 if (CIRC_SPACE(queue->tx_head, queue->tx_tail,
2307 bp->tx_ring_size) < desc_cnt) {
2308 netif_stop_subqueue(dev, queue_index);
2309 netdev_dbg(bp->dev, "tx_head = %u, tx_tail = %u\n",
2310 queue->tx_head, queue->tx_tail);
2311 ret = NETDEV_TX_BUSY;
2315 /* Map socket buffer for DMA transfer */
2316 if (!macb_tx_map(bp, queue, skb, hdrlen)) {
2317 dev_kfree_skb_any(skb);
2321 /* Make newly initialized descriptor visible to hardware */
2323 skb_tx_timestamp(skb);
2325 spin_lock_irq(&bp->lock);
2326 macb_writel(bp, NCR, macb_readl(bp, NCR) | MACB_BIT(TSTART));
2327 spin_unlock_irq(&bp->lock);
2329 if (CIRC_SPACE(queue->tx_head, queue->tx_tail, bp->tx_ring_size) < 1)
2330 netif_stop_subqueue(dev, queue_index);
2333 spin_unlock_bh(&queue->tx_ptr_lock);
2338 static void macb_init_rx_buffer_size(struct macb *bp, size_t size)
2340 if (!macb_is_gem(bp)) {
2341 bp->rx_buffer_size = MACB_RX_BUFFER_SIZE;
2343 bp->rx_buffer_size = size;
2345 if (bp->rx_buffer_size % RX_BUFFER_MULTIPLE) {
2347 "RX buffer must be multiple of %d bytes, expanding\n",
2348 RX_BUFFER_MULTIPLE);
2349 bp->rx_buffer_size =
2350 roundup(bp->rx_buffer_size, RX_BUFFER_MULTIPLE);
2354 netdev_dbg(bp->dev, "mtu [%u] rx_buffer_size [%zu]\n",
2355 bp->dev->mtu, bp->rx_buffer_size);
2358 static void gem_free_rx_buffers(struct macb *bp)
2360 struct sk_buff *skb;
2361 struct macb_dma_desc *desc;
2362 struct macb_queue *queue;
2367 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2368 if (!queue->rx_skbuff)
2371 for (i = 0; i < bp->rx_ring_size; i++) {
2372 skb = queue->rx_skbuff[i];
2377 desc = macb_rx_desc(queue, i);
2378 addr = macb_get_addr(bp, desc);
2380 dma_unmap_single(&bp->pdev->dev, addr, bp->rx_buffer_size,
2382 dev_kfree_skb_any(skb);
2386 kfree(queue->rx_skbuff);
2387 queue->rx_skbuff = NULL;
2391 static void macb_free_rx_buffers(struct macb *bp)
2393 struct macb_queue *queue = &bp->queues[0];
2395 if (queue->rx_buffers) {
2396 dma_free_coherent(&bp->pdev->dev,
2397 bp->rx_ring_size * bp->rx_buffer_size,
2398 queue->rx_buffers, queue->rx_buffers_dma);
2399 queue->rx_buffers = NULL;
2403 static void macb_free_consistent(struct macb *bp)
2405 struct macb_queue *queue;
2409 bp->macbgem_ops.mog_free_rx_buffers(bp);
2411 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2412 kfree(queue->tx_skb);
2413 queue->tx_skb = NULL;
2414 if (queue->tx_ring) {
2415 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2416 dma_free_coherent(&bp->pdev->dev, size,
2417 queue->tx_ring, queue->tx_ring_dma);
2418 queue->tx_ring = NULL;
2420 if (queue->rx_ring) {
2421 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2422 dma_free_coherent(&bp->pdev->dev, size,
2423 queue->rx_ring, queue->rx_ring_dma);
2424 queue->rx_ring = NULL;
2429 static int gem_alloc_rx_buffers(struct macb *bp)
2431 struct macb_queue *queue;
2435 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2436 size = bp->rx_ring_size * sizeof(struct sk_buff *);
2437 queue->rx_skbuff = kzalloc(size, GFP_KERNEL);
2438 if (!queue->rx_skbuff)
2442 "Allocated %d RX struct sk_buff entries at %p\n",
2443 bp->rx_ring_size, queue->rx_skbuff);
2448 static int macb_alloc_rx_buffers(struct macb *bp)
2450 struct macb_queue *queue = &bp->queues[0];
2453 size = bp->rx_ring_size * bp->rx_buffer_size;
2454 queue->rx_buffers = dma_alloc_coherent(&bp->pdev->dev, size,
2455 &queue->rx_buffers_dma, GFP_KERNEL);
2456 if (!queue->rx_buffers)
2460 "Allocated RX buffers of %d bytes at %08lx (mapped %p)\n",
2461 size, (unsigned long)queue->rx_buffers_dma, queue->rx_buffers);
2465 static int macb_alloc_consistent(struct macb *bp)
2467 struct macb_queue *queue;
2471 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2472 size = TX_RING_BYTES(bp) + bp->tx_bd_rd_prefetch;
2473 queue->tx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2474 &queue->tx_ring_dma,
2476 if (!queue->tx_ring)
2479 "Allocated TX ring for queue %u of %d bytes at %08lx (mapped %p)\n",
2480 q, size, (unsigned long)queue->tx_ring_dma,
2483 size = bp->tx_ring_size * sizeof(struct macb_tx_skb);
2484 queue->tx_skb = kmalloc(size, GFP_KERNEL);
2488 size = RX_RING_BYTES(bp) + bp->rx_bd_rd_prefetch;
2489 queue->rx_ring = dma_alloc_coherent(&bp->pdev->dev, size,
2490 &queue->rx_ring_dma, GFP_KERNEL);
2491 if (!queue->rx_ring)
2494 "Allocated RX ring of %d bytes at %08lx (mapped %p)\n",
2495 size, (unsigned long)queue->rx_ring_dma, queue->rx_ring);
2497 if (bp->macbgem_ops.mog_alloc_rx_buffers(bp))
2503 macb_free_consistent(bp);
2507 static void gem_init_rings(struct macb *bp)
2509 struct macb_queue *queue;
2510 struct macb_dma_desc *desc = NULL;
2514 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2515 for (i = 0; i < bp->tx_ring_size; i++) {
2516 desc = macb_tx_desc(queue, i);
2517 macb_set_addr(bp, desc, 0);
2518 desc->ctrl = MACB_BIT(TX_USED);
2520 desc->ctrl |= MACB_BIT(TX_WRAP);
2525 queue->rx_prepared_head = 0;
2527 gem_rx_refill(queue);
2532 static void macb_init_rings(struct macb *bp)
2535 struct macb_dma_desc *desc = NULL;
2537 macb_init_rx_ring(&bp->queues[0]);
2539 for (i = 0; i < bp->tx_ring_size; i++) {
2540 desc = macb_tx_desc(&bp->queues[0], i);
2541 macb_set_addr(bp, desc, 0);
2542 desc->ctrl = MACB_BIT(TX_USED);
2544 bp->queues[0].tx_head = 0;
2545 bp->queues[0].tx_tail = 0;
2546 desc->ctrl |= MACB_BIT(TX_WRAP);
2549 static void macb_reset_hw(struct macb *bp)
2551 struct macb_queue *queue;
2553 u32 ctrl = macb_readl(bp, NCR);
2555 /* Disable RX and TX (XXX: Should we halt the transmission
2558 ctrl &= ~(MACB_BIT(RE) | MACB_BIT(TE));
2560 /* Clear the stats registers (XXX: Update stats first?) */
2561 ctrl |= MACB_BIT(CLRSTAT);
2563 macb_writel(bp, NCR, ctrl);
2565 /* Clear all status flags */
2566 macb_writel(bp, TSR, -1);
2567 macb_writel(bp, RSR, -1);
2569 /* Disable all interrupts */
2570 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2571 queue_writel(queue, IDR, -1);
2572 queue_readl(queue, ISR);
2573 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
2574 queue_writel(queue, ISR, -1);
2578 static u32 gem_mdc_clk_div(struct macb *bp)
2581 unsigned long pclk_hz = clk_get_rate(bp->pclk);
2583 if (pclk_hz <= 20000000)
2584 config = GEM_BF(CLK, GEM_CLK_DIV8);
2585 else if (pclk_hz <= 40000000)
2586 config = GEM_BF(CLK, GEM_CLK_DIV16);
2587 else if (pclk_hz <= 80000000)
2588 config = GEM_BF(CLK, GEM_CLK_DIV32);
2589 else if (pclk_hz <= 120000000)
2590 config = GEM_BF(CLK, GEM_CLK_DIV48);
2591 else if (pclk_hz <= 160000000)
2592 config = GEM_BF(CLK, GEM_CLK_DIV64);
2594 config = GEM_BF(CLK, GEM_CLK_DIV96);
2599 static u32 macb_mdc_clk_div(struct macb *bp)
2602 unsigned long pclk_hz;
2604 if (macb_is_gem(bp))
2605 return gem_mdc_clk_div(bp);
2607 pclk_hz = clk_get_rate(bp->pclk);
2608 if (pclk_hz <= 20000000)
2609 config = MACB_BF(CLK, MACB_CLK_DIV8);
2610 else if (pclk_hz <= 40000000)
2611 config = MACB_BF(CLK, MACB_CLK_DIV16);
2612 else if (pclk_hz <= 80000000)
2613 config = MACB_BF(CLK, MACB_CLK_DIV32);
2615 config = MACB_BF(CLK, MACB_CLK_DIV64);
2620 /* Get the DMA bus width field of the network configuration register that we
2621 * should program. We find the width from decoding the design configuration
2622 * register to find the maximum supported data bus width.
2624 static u32 macb_dbw(struct macb *bp)
2626 if (!macb_is_gem(bp))
2629 switch (GEM_BFEXT(DBWDEF, gem_readl(bp, DCFG1))) {
2631 return GEM_BF(DBW, GEM_DBW128);
2633 return GEM_BF(DBW, GEM_DBW64);
2636 return GEM_BF(DBW, GEM_DBW32);
2640 /* Configure the receive DMA engine
2641 * - use the correct receive buffer size
2642 * - set best burst length for DMA operations
2643 * (if not supported by FIFO, it will fallback to default)
2644 * - set both rx/tx packet buffers to full memory size
2645 * These are configurable parameters for GEM.
2647 static void macb_configure_dma(struct macb *bp)
2649 struct macb_queue *queue;
2654 buffer_size = bp->rx_buffer_size / RX_BUFFER_MULTIPLE;
2655 if (macb_is_gem(bp)) {
2656 dmacfg = gem_readl(bp, DMACFG) & ~GEM_BF(RXBS, -1L);
2657 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2659 queue_writel(queue, RBQS, buffer_size);
2661 dmacfg |= GEM_BF(RXBS, buffer_size);
2663 if (bp->dma_burst_length)
2664 dmacfg = GEM_BFINS(FBLDO, bp->dma_burst_length, dmacfg);
2665 dmacfg |= GEM_BIT(TXPBMS) | GEM_BF(RXBMS, -1L);
2666 dmacfg &= ~GEM_BIT(ENDIA_PKT);
2669 dmacfg &= ~GEM_BIT(ENDIA_DESC);
2671 dmacfg |= GEM_BIT(ENDIA_DESC); /* CPU in big endian */
2673 if (bp->dev->features & NETIF_F_HW_CSUM)
2674 dmacfg |= GEM_BIT(TXCOEN);
2676 dmacfg &= ~GEM_BIT(TXCOEN);
2678 dmacfg &= ~GEM_BIT(ADDR64);
2679 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
2680 if (bp->hw_dma_cap & HW_DMA_CAP_64B)
2681 dmacfg |= GEM_BIT(ADDR64);
2683 #ifdef CONFIG_MACB_USE_HWSTAMP
2684 if (bp->hw_dma_cap & HW_DMA_CAP_PTP)
2685 dmacfg |= GEM_BIT(RXEXT) | GEM_BIT(TXEXT);
2687 netdev_dbg(bp->dev, "Cadence configure DMA with 0x%08x\n",
2689 gem_writel(bp, DMACFG, dmacfg);
2693 static void macb_init_hw(struct macb *bp)
2698 macb_set_hwaddr(bp);
2700 config = macb_mdc_clk_div(bp);
2701 config |= MACB_BF(RBOF, NET_IP_ALIGN); /* Make eth data aligned */
2702 config |= MACB_BIT(DRFCS); /* Discard Rx FCS */
2703 if (bp->caps & MACB_CAPS_JUMBO)
2704 config |= MACB_BIT(JFRAME); /* Enable jumbo frames */
2706 config |= MACB_BIT(BIG); /* Receive oversized frames */
2707 if (bp->dev->flags & IFF_PROMISC)
2708 config |= MACB_BIT(CAF); /* Copy All Frames */
2709 else if (macb_is_gem(bp) && bp->dev->features & NETIF_F_RXCSUM)
2710 config |= GEM_BIT(RXCOEN);
2711 if (!(bp->dev->flags & IFF_BROADCAST))
2712 config |= MACB_BIT(NBC); /* No BroadCast */
2713 config |= macb_dbw(bp);
2714 macb_writel(bp, NCFGR, config);
2715 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
2716 gem_writel(bp, JML, bp->jumbo_max_len);
2717 bp->rx_frm_len_mask = MACB_RX_FRMLEN_MASK;
2718 if (bp->caps & MACB_CAPS_JUMBO)
2719 bp->rx_frm_len_mask = MACB_RX_JFRMLEN_MASK;
2721 macb_configure_dma(bp);
2724 /* The hash address register is 64 bits long and takes up two
2725 * locations in the memory map. The least significant bits are stored
2726 * in EMAC_HSL and the most significant bits in EMAC_HSH.
2728 * The unicast hash enable and the multicast hash enable bits in the
2729 * network configuration register enable the reception of hash matched
2730 * frames. The destination address is reduced to a 6 bit index into
2731 * the 64 bit hash register using the following hash function. The
2732 * hash function is an exclusive or of every sixth bit of the
2733 * destination address.
2735 * hi[5] = da[5] ^ da[11] ^ da[17] ^ da[23] ^ da[29] ^ da[35] ^ da[41] ^ da[47]
2736 * hi[4] = da[4] ^ da[10] ^ da[16] ^ da[22] ^ da[28] ^ da[34] ^ da[40] ^ da[46]
2737 * hi[3] = da[3] ^ da[09] ^ da[15] ^ da[21] ^ da[27] ^ da[33] ^ da[39] ^ da[45]
2738 * hi[2] = da[2] ^ da[08] ^ da[14] ^ da[20] ^ da[26] ^ da[32] ^ da[38] ^ da[44]
2739 * hi[1] = da[1] ^ da[07] ^ da[13] ^ da[19] ^ da[25] ^ da[31] ^ da[37] ^ da[43]
2740 * hi[0] = da[0] ^ da[06] ^ da[12] ^ da[18] ^ da[24] ^ da[30] ^ da[36] ^ da[42]
2742 * da[0] represents the least significant bit of the first byte
2743 * received, that is, the multicast/unicast indicator, and da[47]
2744 * represents the most significant bit of the last byte received. If
2745 * the hash index, hi[n], points to a bit that is set in the hash
2746 * register then the frame will be matched according to whether the
2747 * frame is multicast or unicast. A multicast match will be signalled
2748 * if the multicast hash enable bit is set, da[0] is 1 and the hash
2749 * index points to a bit set in the hash register. A unicast match
2750 * will be signalled if the unicast hash enable bit is set, da[0] is 0
2751 * and the hash index points to a bit set in the hash register. To
2752 * receive all multicast frames, the hash register should be set with
2753 * all ones and the multicast hash enable bit should be set in the
2754 * network configuration register.
2757 static inline int hash_bit_value(int bitnr, __u8 *addr)
2759 if (addr[bitnr / 8] & (1 << (bitnr % 8)))
2764 /* Return the hash index value for the specified address. */
2765 static int hash_get_index(__u8 *addr)
2770 for (j = 0; j < 6; j++) {
2771 for (i = 0, bitval = 0; i < 8; i++)
2772 bitval ^= hash_bit_value(i * 6 + j, addr);
2774 hash_index |= (bitval << j);
2780 /* Add multicast addresses to the internal multicast-hash table. */
2781 static void macb_sethashtable(struct net_device *dev)
2783 struct netdev_hw_addr *ha;
2784 unsigned long mc_filter[2];
2786 struct macb *bp = netdev_priv(dev);
2791 netdev_for_each_mc_addr(ha, dev) {
2792 bitnr = hash_get_index(ha->addr);
2793 mc_filter[bitnr >> 5] |= 1 << (bitnr & 31);
2796 macb_or_gem_writel(bp, HRB, mc_filter[0]);
2797 macb_or_gem_writel(bp, HRT, mc_filter[1]);
2800 /* Enable/Disable promiscuous and multicast modes. */
2801 static void macb_set_rx_mode(struct net_device *dev)
2804 struct macb *bp = netdev_priv(dev);
2806 cfg = macb_readl(bp, NCFGR);
2808 if (dev->flags & IFF_PROMISC) {
2809 /* Enable promiscuous mode */
2810 cfg |= MACB_BIT(CAF);
2812 /* Disable RX checksum offload */
2813 if (macb_is_gem(bp))
2814 cfg &= ~GEM_BIT(RXCOEN);
2816 /* Disable promiscuous mode */
2817 cfg &= ~MACB_BIT(CAF);
2819 /* Enable RX checksum offload only if requested */
2820 if (macb_is_gem(bp) && dev->features & NETIF_F_RXCSUM)
2821 cfg |= GEM_BIT(RXCOEN);
2824 if (dev->flags & IFF_ALLMULTI) {
2825 /* Enable all multicast mode */
2826 macb_or_gem_writel(bp, HRB, -1);
2827 macb_or_gem_writel(bp, HRT, -1);
2828 cfg |= MACB_BIT(NCFGR_MTI);
2829 } else if (!netdev_mc_empty(dev)) {
2830 /* Enable specific multicasts */
2831 macb_sethashtable(dev);
2832 cfg |= MACB_BIT(NCFGR_MTI);
2833 } else if (dev->flags & (~IFF_ALLMULTI)) {
2834 /* Disable all multicast mode */
2835 macb_or_gem_writel(bp, HRB, 0);
2836 macb_or_gem_writel(bp, HRT, 0);
2837 cfg &= ~MACB_BIT(NCFGR_MTI);
2840 macb_writel(bp, NCFGR, cfg);
2843 static int macb_open(struct net_device *dev)
2845 size_t bufsz = dev->mtu + ETH_HLEN + ETH_FCS_LEN + NET_IP_ALIGN;
2846 struct macb *bp = netdev_priv(dev);
2847 struct macb_queue *queue;
2851 netdev_dbg(bp->dev, "open\n");
2853 err = pm_runtime_resume_and_get(&bp->pdev->dev);
2857 /* RX buffers initialization */
2858 macb_init_rx_buffer_size(bp, bufsz);
2860 err = macb_alloc_consistent(bp);
2862 netdev_err(dev, "Unable to allocate DMA memory (error %d)\n",
2867 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2868 napi_enable(&queue->napi_rx);
2869 napi_enable(&queue->napi_tx);
2874 err = phy_power_on(bp->sgmii_phy);
2878 err = macb_phylink_connect(bp);
2882 netif_tx_start_all_queues(dev);
2885 bp->ptp_info->ptp_init(dev);
2890 phy_power_off(bp->sgmii_phy);
2894 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2895 napi_disable(&queue->napi_rx);
2896 napi_disable(&queue->napi_tx);
2898 macb_free_consistent(bp);
2900 pm_runtime_put_sync(&bp->pdev->dev);
2904 static int macb_close(struct net_device *dev)
2906 struct macb *bp = netdev_priv(dev);
2907 struct macb_queue *queue;
2908 unsigned long flags;
2911 netif_tx_stop_all_queues(dev);
2913 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
2914 napi_disable(&queue->napi_rx);
2915 napi_disable(&queue->napi_tx);
2918 phylink_stop(bp->phylink);
2919 phylink_disconnect_phy(bp->phylink);
2921 phy_power_off(bp->sgmii_phy);
2923 spin_lock_irqsave(&bp->lock, flags);
2925 netif_carrier_off(dev);
2926 spin_unlock_irqrestore(&bp->lock, flags);
2928 macb_free_consistent(bp);
2931 bp->ptp_info->ptp_remove(dev);
2933 pm_runtime_put(&bp->pdev->dev);
2938 static int macb_change_mtu(struct net_device *dev, int new_mtu)
2940 if (netif_running(dev))
2948 static void gem_update_stats(struct macb *bp)
2950 struct macb_queue *queue;
2951 unsigned int i, q, idx;
2952 unsigned long *stat;
2954 u32 *p = &bp->hw_stats.gem.tx_octets_31_0;
2956 for (i = 0; i < GEM_STATS_LEN; ++i, ++p) {
2957 u32 offset = gem_statistics[i].offset;
2958 u64 val = bp->macb_reg_readl(bp, offset);
2960 bp->ethtool_stats[i] += val;
2963 if (offset == GEM_OCTTXL || offset == GEM_OCTRXL) {
2964 /* Add GEM_OCTTXH, GEM_OCTRXH */
2965 val = bp->macb_reg_readl(bp, offset + 4);
2966 bp->ethtool_stats[i] += ((u64)val) << 32;
2971 idx = GEM_STATS_LEN;
2972 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue)
2973 for (i = 0, stat = &queue->stats.first; i < QUEUE_STATS_LEN; ++i, ++stat)
2974 bp->ethtool_stats[idx++] = *stat;
2977 static struct net_device_stats *gem_get_stats(struct macb *bp)
2979 struct gem_stats *hwstat = &bp->hw_stats.gem;
2980 struct net_device_stats *nstat = &bp->dev->stats;
2982 if (!netif_running(bp->dev))
2985 gem_update_stats(bp);
2987 nstat->rx_errors = (hwstat->rx_frame_check_sequence_errors +
2988 hwstat->rx_alignment_errors +
2989 hwstat->rx_resource_errors +
2990 hwstat->rx_overruns +
2991 hwstat->rx_oversize_frames +
2992 hwstat->rx_jabbers +
2993 hwstat->rx_undersized_frames +
2994 hwstat->rx_length_field_frame_errors);
2995 nstat->tx_errors = (hwstat->tx_late_collisions +
2996 hwstat->tx_excessive_collisions +
2997 hwstat->tx_underrun +
2998 hwstat->tx_carrier_sense_errors);
2999 nstat->multicast = hwstat->rx_multicast_frames;
3000 nstat->collisions = (hwstat->tx_single_collision_frames +
3001 hwstat->tx_multiple_collision_frames +
3002 hwstat->tx_excessive_collisions);
3003 nstat->rx_length_errors = (hwstat->rx_oversize_frames +
3004 hwstat->rx_jabbers +
3005 hwstat->rx_undersized_frames +
3006 hwstat->rx_length_field_frame_errors);
3007 nstat->rx_over_errors = hwstat->rx_resource_errors;
3008 nstat->rx_crc_errors = hwstat->rx_frame_check_sequence_errors;
3009 nstat->rx_frame_errors = hwstat->rx_alignment_errors;
3010 nstat->rx_fifo_errors = hwstat->rx_overruns;
3011 nstat->tx_aborted_errors = hwstat->tx_excessive_collisions;
3012 nstat->tx_carrier_errors = hwstat->tx_carrier_sense_errors;
3013 nstat->tx_fifo_errors = hwstat->tx_underrun;
3018 static void gem_get_ethtool_stats(struct net_device *dev,
3019 struct ethtool_stats *stats, u64 *data)
3023 bp = netdev_priv(dev);
3024 gem_update_stats(bp);
3025 memcpy(data, &bp->ethtool_stats, sizeof(u64)
3026 * (GEM_STATS_LEN + QUEUE_STATS_LEN * MACB_MAX_QUEUES));
3029 static int gem_get_sset_count(struct net_device *dev, int sset)
3031 struct macb *bp = netdev_priv(dev);
3035 return GEM_STATS_LEN + bp->num_queues * QUEUE_STATS_LEN;
3041 static void gem_get_ethtool_strings(struct net_device *dev, u32 sset, u8 *p)
3043 char stat_string[ETH_GSTRING_LEN];
3044 struct macb *bp = netdev_priv(dev);
3045 struct macb_queue *queue;
3051 for (i = 0; i < GEM_STATS_LEN; i++, p += ETH_GSTRING_LEN)
3052 memcpy(p, gem_statistics[i].stat_string,
3055 for (q = 0, queue = bp->queues; q < bp->num_queues; ++q, ++queue) {
3056 for (i = 0; i < QUEUE_STATS_LEN; i++, p += ETH_GSTRING_LEN) {
3057 snprintf(stat_string, ETH_GSTRING_LEN, "q%d_%s",
3058 q, queue_statistics[i].stat_string);
3059 memcpy(p, stat_string, ETH_GSTRING_LEN);
3066 static struct net_device_stats *macb_get_stats(struct net_device *dev)
3068 struct macb *bp = netdev_priv(dev);
3069 struct net_device_stats *nstat = &bp->dev->stats;
3070 struct macb_stats *hwstat = &bp->hw_stats.macb;
3072 if (macb_is_gem(bp))
3073 return gem_get_stats(bp);
3075 /* read stats from hardware */
3076 macb_update_stats(bp);
3078 /* Convert HW stats into netdevice stats */
3079 nstat->rx_errors = (hwstat->rx_fcs_errors +
3080 hwstat->rx_align_errors +
3081 hwstat->rx_resource_errors +
3082 hwstat->rx_overruns +
3083 hwstat->rx_oversize_pkts +
3084 hwstat->rx_jabbers +
3085 hwstat->rx_undersize_pkts +
3086 hwstat->rx_length_mismatch);
3087 nstat->tx_errors = (hwstat->tx_late_cols +
3088 hwstat->tx_excessive_cols +
3089 hwstat->tx_underruns +
3090 hwstat->tx_carrier_errors +
3091 hwstat->sqe_test_errors);
3092 nstat->collisions = (hwstat->tx_single_cols +
3093 hwstat->tx_multiple_cols +
3094 hwstat->tx_excessive_cols);
3095 nstat->rx_length_errors = (hwstat->rx_oversize_pkts +
3096 hwstat->rx_jabbers +
3097 hwstat->rx_undersize_pkts +
3098 hwstat->rx_length_mismatch);
3099 nstat->rx_over_errors = hwstat->rx_resource_errors +
3100 hwstat->rx_overruns;
3101 nstat->rx_crc_errors = hwstat->rx_fcs_errors;
3102 nstat->rx_frame_errors = hwstat->rx_align_errors;
3103 nstat->rx_fifo_errors = hwstat->rx_overruns;
3104 /* XXX: What does "missed" mean? */
3105 nstat->tx_aborted_errors = hwstat->tx_excessive_cols;
3106 nstat->tx_carrier_errors = hwstat->tx_carrier_errors;
3107 nstat->tx_fifo_errors = hwstat->tx_underruns;
3108 /* Don't know about heartbeat or window errors... */
3113 static int macb_get_regs_len(struct net_device *netdev)
3115 return MACB_GREGS_NBR * sizeof(u32);
3118 static void macb_get_regs(struct net_device *dev, struct ethtool_regs *regs,
3121 struct macb *bp = netdev_priv(dev);
3122 unsigned int tail, head;
3125 regs->version = (macb_readl(bp, MID) & ((1 << MACB_REV_SIZE) - 1))
3126 | MACB_GREGS_VERSION;
3128 tail = macb_tx_ring_wrap(bp, bp->queues[0].tx_tail);
3129 head = macb_tx_ring_wrap(bp, bp->queues[0].tx_head);
3131 regs_buff[0] = macb_readl(bp, NCR);
3132 regs_buff[1] = macb_or_gem_readl(bp, NCFGR);
3133 regs_buff[2] = macb_readl(bp, NSR);
3134 regs_buff[3] = macb_readl(bp, TSR);
3135 regs_buff[4] = macb_readl(bp, RBQP);
3136 regs_buff[5] = macb_readl(bp, TBQP);
3137 regs_buff[6] = macb_readl(bp, RSR);
3138 regs_buff[7] = macb_readl(bp, IMR);
3140 regs_buff[8] = tail;
3141 regs_buff[9] = head;
3142 regs_buff[10] = macb_tx_dma(&bp->queues[0], tail);
3143 regs_buff[11] = macb_tx_dma(&bp->queues[0], head);
3145 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
3146 regs_buff[12] = macb_or_gem_readl(bp, USRIO);
3147 if (macb_is_gem(bp))
3148 regs_buff[13] = gem_readl(bp, DMACFG);
3151 static void macb_get_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
3153 struct macb *bp = netdev_priv(netdev);
3155 if (bp->wol & MACB_WOL_HAS_MAGIC_PACKET) {
3156 phylink_ethtool_get_wol(bp->phylink, wol);
3157 wol->supported |= WAKE_MAGIC;
3159 if (bp->wol & MACB_WOL_ENABLED)
3160 wol->wolopts |= WAKE_MAGIC;
3164 static int macb_set_wol(struct net_device *netdev, struct ethtool_wolinfo *wol)
3166 struct macb *bp = netdev_priv(netdev);
3169 /* Pass the order to phylink layer */
3170 ret = phylink_ethtool_set_wol(bp->phylink, wol);
3171 /* Don't manage WoL on MAC if handled by the PHY
3172 * or if there's a failure in talking to the PHY
3174 if (!ret || ret != -EOPNOTSUPP)
3177 if (!(bp->wol & MACB_WOL_HAS_MAGIC_PACKET) ||
3178 (wol->wolopts & ~WAKE_MAGIC))
3181 if (wol->wolopts & WAKE_MAGIC)
3182 bp->wol |= MACB_WOL_ENABLED;
3184 bp->wol &= ~MACB_WOL_ENABLED;
3186 device_set_wakeup_enable(&bp->pdev->dev, bp->wol & MACB_WOL_ENABLED);
3191 static int macb_get_link_ksettings(struct net_device *netdev,
3192 struct ethtool_link_ksettings *kset)
3194 struct macb *bp = netdev_priv(netdev);
3196 return phylink_ethtool_ksettings_get(bp->phylink, kset);
3199 static int macb_set_link_ksettings(struct net_device *netdev,
3200 const struct ethtool_link_ksettings *kset)
3202 struct macb *bp = netdev_priv(netdev);
3204 return phylink_ethtool_ksettings_set(bp->phylink, kset);
3207 static void macb_get_ringparam(struct net_device *netdev,
3208 struct ethtool_ringparam *ring,
3209 struct kernel_ethtool_ringparam *kernel_ring,
3210 struct netlink_ext_ack *extack)
3212 struct macb *bp = netdev_priv(netdev);
3214 ring->rx_max_pending = MAX_RX_RING_SIZE;
3215 ring->tx_max_pending = MAX_TX_RING_SIZE;
3217 ring->rx_pending = bp->rx_ring_size;
3218 ring->tx_pending = bp->tx_ring_size;
3221 static int macb_set_ringparam(struct net_device *netdev,
3222 struct ethtool_ringparam *ring,
3223 struct kernel_ethtool_ringparam *kernel_ring,
3224 struct netlink_ext_ack *extack)
3226 struct macb *bp = netdev_priv(netdev);
3227 u32 new_rx_size, new_tx_size;
3228 unsigned int reset = 0;
3230 if ((ring->rx_mini_pending) || (ring->rx_jumbo_pending))
3233 new_rx_size = clamp_t(u32, ring->rx_pending,
3234 MIN_RX_RING_SIZE, MAX_RX_RING_SIZE);
3235 new_rx_size = roundup_pow_of_two(new_rx_size);
3237 new_tx_size = clamp_t(u32, ring->tx_pending,
3238 MIN_TX_RING_SIZE, MAX_TX_RING_SIZE);
3239 new_tx_size = roundup_pow_of_two(new_tx_size);
3241 if ((new_tx_size == bp->tx_ring_size) &&
3242 (new_rx_size == bp->rx_ring_size)) {
3247 if (netif_running(bp->dev)) {
3249 macb_close(bp->dev);
3252 bp->rx_ring_size = new_rx_size;
3253 bp->tx_ring_size = new_tx_size;
3261 #ifdef CONFIG_MACB_USE_HWSTAMP
3262 static unsigned int gem_get_tsu_rate(struct macb *bp)
3264 struct clk *tsu_clk;
3265 unsigned int tsu_rate;
3267 tsu_clk = devm_clk_get(&bp->pdev->dev, "tsu_clk");
3268 if (!IS_ERR(tsu_clk))
3269 tsu_rate = clk_get_rate(tsu_clk);
3270 /* try pclk instead */
3271 else if (!IS_ERR(bp->pclk)) {
3273 tsu_rate = clk_get_rate(tsu_clk);
3279 static s32 gem_get_ptp_max_adj(void)
3284 static int gem_get_ts_info(struct net_device *dev,
3285 struct ethtool_ts_info *info)
3287 struct macb *bp = netdev_priv(dev);
3289 if ((bp->hw_dma_cap & HW_DMA_CAP_PTP) == 0) {
3290 ethtool_op_get_ts_info(dev, info);
3294 info->so_timestamping =
3295 SOF_TIMESTAMPING_TX_SOFTWARE |
3296 SOF_TIMESTAMPING_RX_SOFTWARE |
3297 SOF_TIMESTAMPING_SOFTWARE |
3298 SOF_TIMESTAMPING_TX_HARDWARE |
3299 SOF_TIMESTAMPING_RX_HARDWARE |
3300 SOF_TIMESTAMPING_RAW_HARDWARE;
3302 (1 << HWTSTAMP_TX_ONESTEP_SYNC) |
3303 (1 << HWTSTAMP_TX_OFF) |
3304 (1 << HWTSTAMP_TX_ON);
3306 (1 << HWTSTAMP_FILTER_NONE) |
3307 (1 << HWTSTAMP_FILTER_ALL);
3309 info->phc_index = bp->ptp_clock ? ptp_clock_index(bp->ptp_clock) : -1;
3314 static struct macb_ptp_info gem_ptp_info = {
3315 .ptp_init = gem_ptp_init,
3316 .ptp_remove = gem_ptp_remove,
3317 .get_ptp_max_adj = gem_get_ptp_max_adj,
3318 .get_tsu_rate = gem_get_tsu_rate,
3319 .get_ts_info = gem_get_ts_info,
3320 .get_hwtst = gem_get_hwtst,
3321 .set_hwtst = gem_set_hwtst,
3325 static int macb_get_ts_info(struct net_device *netdev,
3326 struct ethtool_ts_info *info)
3328 struct macb *bp = netdev_priv(netdev);
3331 return bp->ptp_info->get_ts_info(netdev, info);
3333 return ethtool_op_get_ts_info(netdev, info);
3336 static void gem_enable_flow_filters(struct macb *bp, bool enable)
3338 struct net_device *netdev = bp->dev;
3339 struct ethtool_rx_fs_item *item;
3343 if (!(netdev->features & NETIF_F_NTUPLE))
3346 num_t2_scr = GEM_BFEXT(T2SCR, gem_readl(bp, DCFG8));
3348 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3349 struct ethtool_rx_flow_spec *fs = &item->fs;
3350 struct ethtool_tcpip4_spec *tp4sp_m;
3352 if (fs->location >= num_t2_scr)
3355 t2_scr = gem_readl_n(bp, SCRT2, fs->location);
3357 /* enable/disable screener regs for the flow entry */
3358 t2_scr = GEM_BFINS(ETHTEN, enable, t2_scr);
3360 /* only enable fields with no masking */
3361 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3363 if (enable && (tp4sp_m->ip4src == 0xFFFFFFFF))
3364 t2_scr = GEM_BFINS(CMPAEN, 1, t2_scr);
3366 t2_scr = GEM_BFINS(CMPAEN, 0, t2_scr);
3368 if (enable && (tp4sp_m->ip4dst == 0xFFFFFFFF))
3369 t2_scr = GEM_BFINS(CMPBEN, 1, t2_scr);
3371 t2_scr = GEM_BFINS(CMPBEN, 0, t2_scr);
3373 if (enable && ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)))
3374 t2_scr = GEM_BFINS(CMPCEN, 1, t2_scr);
3376 t2_scr = GEM_BFINS(CMPCEN, 0, t2_scr);
3378 gem_writel_n(bp, SCRT2, fs->location, t2_scr);
3382 static void gem_prog_cmp_regs(struct macb *bp, struct ethtool_rx_flow_spec *fs)
3384 struct ethtool_tcpip4_spec *tp4sp_v, *tp4sp_m;
3385 uint16_t index = fs->location;
3391 if (!macb_is_gem(bp))
3394 tp4sp_v = &(fs->h_u.tcp_ip4_spec);
3395 tp4sp_m = &(fs->m_u.tcp_ip4_spec);
3397 /* ignore field if any masking set */
3398 if (tp4sp_m->ip4src == 0xFFFFFFFF) {
3399 /* 1st compare reg - IP source address */
3402 w0 = tp4sp_v->ip4src;
3403 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3404 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3405 w1 = GEM_BFINS(T2OFST, ETYPE_SRCIP_OFFSET, w1);
3406 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w0);
3407 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4SRC_CMP(index)), w1);
3411 /* ignore field if any masking set */
3412 if (tp4sp_m->ip4dst == 0xFFFFFFFF) {
3413 /* 2nd compare reg - IP destination address */
3416 w0 = tp4sp_v->ip4dst;
3417 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3418 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_ETYPE, w1);
3419 w1 = GEM_BFINS(T2OFST, ETYPE_DSTIP_OFFSET, w1);
3420 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_IP4DST_CMP(index)), w0);
3421 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_IP4DST_CMP(index)), w1);
3425 /* ignore both port fields if masking set in both */
3426 if ((tp4sp_m->psrc == 0xFFFF) || (tp4sp_m->pdst == 0xFFFF)) {
3427 /* 3rd compare reg - source port, destination port */
3430 w1 = GEM_BFINS(T2CMPOFST, GEM_T2COMPOFST_IPHDR, w1);
3431 if (tp4sp_m->psrc == tp4sp_m->pdst) {
3432 w0 = GEM_BFINS(T2MASK, tp4sp_v->psrc, w0);
3433 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3434 w1 = GEM_BFINS(T2DISMSK, 1, w1); /* 32-bit compare */
3435 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3437 /* only one port definition */
3438 w1 = GEM_BFINS(T2DISMSK, 0, w1); /* 16-bit compare */
3439 w0 = GEM_BFINS(T2MASK, 0xFFFF, w0);
3440 if (tp4sp_m->psrc == 0xFFFF) { /* src port */
3441 w0 = GEM_BFINS(T2CMP, tp4sp_v->psrc, w0);
3442 w1 = GEM_BFINS(T2OFST, IPHDR_SRCPORT_OFFSET, w1);
3443 } else { /* dst port */
3444 w0 = GEM_BFINS(T2CMP, tp4sp_v->pdst, w0);
3445 w1 = GEM_BFINS(T2OFST, IPHDR_DSTPORT_OFFSET, w1);
3448 gem_writel_n(bp, T2CMPW0, T2CMP_OFST(GEM_PORT_CMP(index)), w0);
3449 gem_writel_n(bp, T2CMPW1, T2CMP_OFST(GEM_PORT_CMP(index)), w1);
3454 t2_scr = GEM_BFINS(QUEUE, (fs->ring_cookie) & 0xFF, t2_scr);
3455 t2_scr = GEM_BFINS(ETHT2IDX, SCRT2_ETHT, t2_scr);
3457 t2_scr = GEM_BFINS(CMPA, GEM_IP4SRC_CMP(index), t2_scr);
3459 t2_scr = GEM_BFINS(CMPB, GEM_IP4DST_CMP(index), t2_scr);
3461 t2_scr = GEM_BFINS(CMPC, GEM_PORT_CMP(index), t2_scr);
3462 gem_writel_n(bp, SCRT2, index, t2_scr);
3465 static int gem_add_flow_filter(struct net_device *netdev,
3466 struct ethtool_rxnfc *cmd)
3468 struct macb *bp = netdev_priv(netdev);
3469 struct ethtool_rx_flow_spec *fs = &cmd->fs;
3470 struct ethtool_rx_fs_item *item, *newfs;
3471 unsigned long flags;
3475 newfs = kmalloc(sizeof(*newfs), GFP_KERNEL);
3478 memcpy(&newfs->fs, fs, sizeof(newfs->fs));
3481 "Adding flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3482 fs->flow_type, (int)fs->ring_cookie, fs->location,
3483 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3484 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3485 be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc),
3486 be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst));
3488 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3490 /* find correct place to add in list */
3491 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3492 if (item->fs.location > newfs->fs.location) {
3493 list_add_tail(&newfs->list, &item->list);
3496 } else if (item->fs.location == fs->location) {
3497 netdev_err(netdev, "Rule not added: location %d not free!\n",
3504 list_add_tail(&newfs->list, &bp->rx_fs_list.list);
3506 gem_prog_cmp_regs(bp, fs);
3507 bp->rx_fs_list.count++;
3508 /* enable filtering if NTUPLE on */
3509 gem_enable_flow_filters(bp, 1);
3511 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3515 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3520 static int gem_del_flow_filter(struct net_device *netdev,
3521 struct ethtool_rxnfc *cmd)
3523 struct macb *bp = netdev_priv(netdev);
3524 struct ethtool_rx_fs_item *item;
3525 struct ethtool_rx_flow_spec *fs;
3526 unsigned long flags;
3528 spin_lock_irqsave(&bp->rx_fs_lock, flags);
3530 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3531 if (item->fs.location == cmd->fs.location) {
3532 /* disable screener regs for the flow entry */
3535 "Deleting flow filter entry,type=%u,queue=%u,loc=%u,src=%08X,dst=%08X,ps=%u,pd=%u\n",
3536 fs->flow_type, (int)fs->ring_cookie, fs->location,
3537 htonl(fs->h_u.tcp_ip4_spec.ip4src),
3538 htonl(fs->h_u.tcp_ip4_spec.ip4dst),
3539 be16_to_cpu(fs->h_u.tcp_ip4_spec.psrc),
3540 be16_to_cpu(fs->h_u.tcp_ip4_spec.pdst));
3542 gem_writel_n(bp, SCRT2, fs->location, 0);
3544 list_del(&item->list);
3545 bp->rx_fs_list.count--;
3546 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3552 spin_unlock_irqrestore(&bp->rx_fs_lock, flags);
3556 static int gem_get_flow_entry(struct net_device *netdev,
3557 struct ethtool_rxnfc *cmd)
3559 struct macb *bp = netdev_priv(netdev);
3560 struct ethtool_rx_fs_item *item;
3562 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3563 if (item->fs.location == cmd->fs.location) {
3564 memcpy(&cmd->fs, &item->fs, sizeof(cmd->fs));
3571 static int gem_get_all_flow_entries(struct net_device *netdev,
3572 struct ethtool_rxnfc *cmd, u32 *rule_locs)
3574 struct macb *bp = netdev_priv(netdev);
3575 struct ethtool_rx_fs_item *item;
3578 list_for_each_entry(item, &bp->rx_fs_list.list, list) {
3579 if (cnt == cmd->rule_cnt)
3581 rule_locs[cnt] = item->fs.location;
3584 cmd->data = bp->max_tuples;
3585 cmd->rule_cnt = cnt;
3590 static int gem_get_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd,
3593 struct macb *bp = netdev_priv(netdev);
3597 case ETHTOOL_GRXRINGS:
3598 cmd->data = bp->num_queues;
3600 case ETHTOOL_GRXCLSRLCNT:
3601 cmd->rule_cnt = bp->rx_fs_list.count;
3603 case ETHTOOL_GRXCLSRULE:
3604 ret = gem_get_flow_entry(netdev, cmd);
3606 case ETHTOOL_GRXCLSRLALL:
3607 ret = gem_get_all_flow_entries(netdev, cmd, rule_locs);
3611 "Command parameter %d is not supported\n", cmd->cmd);
3618 static int gem_set_rxnfc(struct net_device *netdev, struct ethtool_rxnfc *cmd)
3620 struct macb *bp = netdev_priv(netdev);
3624 case ETHTOOL_SRXCLSRLINS:
3625 if ((cmd->fs.location >= bp->max_tuples)
3626 || (cmd->fs.ring_cookie >= bp->num_queues)) {
3630 ret = gem_add_flow_filter(netdev, cmd);
3632 case ETHTOOL_SRXCLSRLDEL:
3633 ret = gem_del_flow_filter(netdev, cmd);
3637 "Command parameter %d is not supported\n", cmd->cmd);
3644 static const struct ethtool_ops macb_ethtool_ops = {
3645 .get_regs_len = macb_get_regs_len,
3646 .get_regs = macb_get_regs,
3647 .get_link = ethtool_op_get_link,
3648 .get_ts_info = ethtool_op_get_ts_info,
3649 .get_wol = macb_get_wol,
3650 .set_wol = macb_set_wol,
3651 .get_link_ksettings = macb_get_link_ksettings,
3652 .set_link_ksettings = macb_set_link_ksettings,
3653 .get_ringparam = macb_get_ringparam,
3654 .set_ringparam = macb_set_ringparam,
3657 static const struct ethtool_ops gem_ethtool_ops = {
3658 .get_regs_len = macb_get_regs_len,
3659 .get_regs = macb_get_regs,
3660 .get_wol = macb_get_wol,
3661 .set_wol = macb_set_wol,
3662 .get_link = ethtool_op_get_link,
3663 .get_ts_info = macb_get_ts_info,
3664 .get_ethtool_stats = gem_get_ethtool_stats,
3665 .get_strings = gem_get_ethtool_strings,
3666 .get_sset_count = gem_get_sset_count,
3667 .get_link_ksettings = macb_get_link_ksettings,
3668 .set_link_ksettings = macb_set_link_ksettings,
3669 .get_ringparam = macb_get_ringparam,
3670 .set_ringparam = macb_set_ringparam,
3671 .get_rxnfc = gem_get_rxnfc,
3672 .set_rxnfc = gem_set_rxnfc,
3675 static int macb_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3677 struct macb *bp = netdev_priv(dev);
3679 if (!netif_running(dev))
3685 return bp->ptp_info->set_hwtst(dev, rq, cmd);
3687 return bp->ptp_info->get_hwtst(dev, rq);
3691 return phylink_mii_ioctl(bp->phylink, rq, cmd);
3694 static inline void macb_set_txcsum_feature(struct macb *bp,
3695 netdev_features_t features)
3699 if (!macb_is_gem(bp))
3702 val = gem_readl(bp, DMACFG);
3703 if (features & NETIF_F_HW_CSUM)
3704 val |= GEM_BIT(TXCOEN);
3706 val &= ~GEM_BIT(TXCOEN);
3708 gem_writel(bp, DMACFG, val);
3711 static inline void macb_set_rxcsum_feature(struct macb *bp,
3712 netdev_features_t features)
3714 struct net_device *netdev = bp->dev;
3717 if (!macb_is_gem(bp))
3720 val = gem_readl(bp, NCFGR);
3721 if ((features & NETIF_F_RXCSUM) && !(netdev->flags & IFF_PROMISC))
3722 val |= GEM_BIT(RXCOEN);
3724 val &= ~GEM_BIT(RXCOEN);
3726 gem_writel(bp, NCFGR, val);
3729 static inline void macb_set_rxflow_feature(struct macb *bp,
3730 netdev_features_t features)
3732 if (!macb_is_gem(bp))
3735 gem_enable_flow_filters(bp, !!(features & NETIF_F_NTUPLE));
3738 static int macb_set_features(struct net_device *netdev,
3739 netdev_features_t features)
3741 struct macb *bp = netdev_priv(netdev);
3742 netdev_features_t changed = features ^ netdev->features;
3744 /* TX checksum offload */
3745 if (changed & NETIF_F_HW_CSUM)
3746 macb_set_txcsum_feature(bp, features);
3748 /* RX checksum offload */
3749 if (changed & NETIF_F_RXCSUM)
3750 macb_set_rxcsum_feature(bp, features);
3752 /* RX Flow Filters */
3753 if (changed & NETIF_F_NTUPLE)
3754 macb_set_rxflow_feature(bp, features);
3759 static void macb_restore_features(struct macb *bp)
3761 struct net_device *netdev = bp->dev;
3762 netdev_features_t features = netdev->features;
3763 struct ethtool_rx_fs_item *item;
3765 /* TX checksum offload */
3766 macb_set_txcsum_feature(bp, features);
3768 /* RX checksum offload */
3769 macb_set_rxcsum_feature(bp, features);
3771 /* RX Flow Filters */
3772 list_for_each_entry(item, &bp->rx_fs_list.list, list)
3773 gem_prog_cmp_regs(bp, &item->fs);
3775 macb_set_rxflow_feature(bp, features);
3778 static const struct net_device_ops macb_netdev_ops = {
3779 .ndo_open = macb_open,
3780 .ndo_stop = macb_close,
3781 .ndo_start_xmit = macb_start_xmit,
3782 .ndo_set_rx_mode = macb_set_rx_mode,
3783 .ndo_get_stats = macb_get_stats,
3784 .ndo_eth_ioctl = macb_ioctl,
3785 .ndo_validate_addr = eth_validate_addr,
3786 .ndo_change_mtu = macb_change_mtu,
3787 .ndo_set_mac_address = eth_mac_addr,
3788 #ifdef CONFIG_NET_POLL_CONTROLLER
3789 .ndo_poll_controller = macb_poll_controller,
3791 .ndo_set_features = macb_set_features,
3792 .ndo_features_check = macb_features_check,
3795 /* Configure peripheral capabilities according to device tree
3796 * and integration options used
3798 static void macb_configure_caps(struct macb *bp,
3799 const struct macb_config *dt_conf)
3804 bp->caps = dt_conf->caps;
3806 if (hw_is_gem(bp->regs, bp->native_io)) {
3807 bp->caps |= MACB_CAPS_MACB_IS_GEM;
3809 dcfg = gem_readl(bp, DCFG1);
3810 if (GEM_BFEXT(IRQCOR, dcfg) == 0)
3811 bp->caps |= MACB_CAPS_ISR_CLEAR_ON_WRITE;
3812 if (GEM_BFEXT(NO_PCS, dcfg) == 0)
3813 bp->caps |= MACB_CAPS_PCS;
3814 dcfg = gem_readl(bp, DCFG12);
3815 if (GEM_BFEXT(HIGH_SPEED, dcfg) == 1)
3816 bp->caps |= MACB_CAPS_HIGH_SPEED;
3817 dcfg = gem_readl(bp, DCFG2);
3818 if ((dcfg & (GEM_BIT(RX_PKT_BUFF) | GEM_BIT(TX_PKT_BUFF))) == 0)
3819 bp->caps |= MACB_CAPS_FIFO_MODE;
3820 #ifdef CONFIG_MACB_USE_HWSTAMP
3821 if (gem_has_ptp(bp)) {
3822 if (!GEM_BFEXT(TSU, gem_readl(bp, DCFG5)))
3823 dev_err(&bp->pdev->dev,
3824 "GEM doesn't support hardware ptp.\n");
3826 bp->hw_dma_cap |= HW_DMA_CAP_PTP;
3827 bp->ptp_info = &gem_ptp_info;
3833 dev_dbg(&bp->pdev->dev, "Cadence caps 0x%08x\n", bp->caps);
3836 static void macb_probe_queues(void __iomem *mem,
3838 unsigned int *queue_mask,
3839 unsigned int *num_queues)
3844 /* is it macb or gem ?
3846 * We need to read directly from the hardware here because
3847 * we are early in the probe process and don't have the
3848 * MACB_CAPS_MACB_IS_GEM flag positioned
3850 if (!hw_is_gem(mem, native_io))
3853 /* bit 0 is never set but queue 0 always exists */
3854 *queue_mask |= readl_relaxed(mem + GEM_DCFG6) & 0xff;
3855 *num_queues = hweight32(*queue_mask);
3858 static void macb_clks_disable(struct clk *pclk, struct clk *hclk, struct clk *tx_clk,
3859 struct clk *rx_clk, struct clk *tsu_clk)
3861 struct clk_bulk_data clks[] = {
3862 { .clk = tsu_clk, },
3869 clk_bulk_disable_unprepare(ARRAY_SIZE(clks), clks);
3872 static int macb_clk_init(struct platform_device *pdev, struct clk **pclk,
3873 struct clk **hclk, struct clk **tx_clk,
3874 struct clk **rx_clk, struct clk **tsu_clk)
3876 struct macb_platform_data *pdata;
3879 pdata = dev_get_platdata(&pdev->dev);
3881 *pclk = pdata->pclk;
3882 *hclk = pdata->hclk;
3884 *pclk = devm_clk_get(&pdev->dev, "pclk");
3885 *hclk = devm_clk_get(&pdev->dev, "hclk");
3888 if (IS_ERR_OR_NULL(*pclk))
3889 return dev_err_probe(&pdev->dev,
3890 IS_ERR(*pclk) ? PTR_ERR(*pclk) : -ENODEV,
3891 "failed to get pclk\n");
3893 if (IS_ERR_OR_NULL(*hclk))
3894 return dev_err_probe(&pdev->dev,
3895 IS_ERR(*hclk) ? PTR_ERR(*hclk) : -ENODEV,
3896 "failed to get hclk\n");
3898 *tx_clk = devm_clk_get_optional(&pdev->dev, "tx_clk");
3899 if (IS_ERR(*tx_clk))
3900 return PTR_ERR(*tx_clk);
3902 *rx_clk = devm_clk_get_optional(&pdev->dev, "rx_clk");
3903 if (IS_ERR(*rx_clk))
3904 return PTR_ERR(*rx_clk);
3906 *tsu_clk = devm_clk_get_optional(&pdev->dev, "tsu_clk");
3907 if (IS_ERR(*tsu_clk))
3908 return PTR_ERR(*tsu_clk);
3910 err = clk_prepare_enable(*pclk);
3912 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
3916 err = clk_prepare_enable(*hclk);
3918 dev_err(&pdev->dev, "failed to enable hclk (%d)\n", err);
3919 goto err_disable_pclk;
3922 err = clk_prepare_enable(*tx_clk);
3924 dev_err(&pdev->dev, "failed to enable tx_clk (%d)\n", err);
3925 goto err_disable_hclk;
3928 err = clk_prepare_enable(*rx_clk);
3930 dev_err(&pdev->dev, "failed to enable rx_clk (%d)\n", err);
3931 goto err_disable_txclk;
3934 err = clk_prepare_enable(*tsu_clk);
3936 dev_err(&pdev->dev, "failed to enable tsu_clk (%d)\n", err);
3937 goto err_disable_rxclk;
3943 clk_disable_unprepare(*rx_clk);
3946 clk_disable_unprepare(*tx_clk);
3949 clk_disable_unprepare(*hclk);
3952 clk_disable_unprepare(*pclk);
3957 static int macb_init(struct platform_device *pdev)
3959 struct net_device *dev = platform_get_drvdata(pdev);
3960 unsigned int hw_q, q;
3961 struct macb *bp = netdev_priv(dev);
3962 struct macb_queue *queue;
3966 bp->tx_ring_size = DEFAULT_TX_RING_SIZE;
3967 bp->rx_ring_size = DEFAULT_RX_RING_SIZE;
3969 /* set the queue register mapping once for all: queue0 has a special
3970 * register mapping but we don't want to test the queue index then
3971 * compute the corresponding register offset at run time.
3973 for (hw_q = 0, q = 0; hw_q < MACB_MAX_QUEUES; ++hw_q) {
3974 if (!(bp->queue_mask & (1 << hw_q)))
3977 queue = &bp->queues[q];
3979 spin_lock_init(&queue->tx_ptr_lock);
3980 netif_napi_add(dev, &queue->napi_rx, macb_rx_poll, NAPI_POLL_WEIGHT);
3981 netif_napi_add(dev, &queue->napi_tx, macb_tx_poll, NAPI_POLL_WEIGHT);
3983 queue->ISR = GEM_ISR(hw_q - 1);
3984 queue->IER = GEM_IER(hw_q - 1);
3985 queue->IDR = GEM_IDR(hw_q - 1);
3986 queue->IMR = GEM_IMR(hw_q - 1);
3987 queue->TBQP = GEM_TBQP(hw_q - 1);
3988 queue->RBQP = GEM_RBQP(hw_q - 1);
3989 queue->RBQS = GEM_RBQS(hw_q - 1);
3990 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
3991 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
3992 queue->TBQPH = GEM_TBQPH(hw_q - 1);
3993 queue->RBQPH = GEM_RBQPH(hw_q - 1);
3997 /* queue0 uses legacy registers */
3998 queue->ISR = MACB_ISR;
3999 queue->IER = MACB_IER;
4000 queue->IDR = MACB_IDR;
4001 queue->IMR = MACB_IMR;
4002 queue->TBQP = MACB_TBQP;
4003 queue->RBQP = MACB_RBQP;
4004 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4005 if (bp->hw_dma_cap & HW_DMA_CAP_64B) {
4006 queue->TBQPH = MACB_TBQPH;
4007 queue->RBQPH = MACB_RBQPH;
4012 /* get irq: here we use the linux queue index, not the hardware
4013 * queue index. the queue irq definitions in the device tree
4014 * must remove the optional gaps that could exist in the
4015 * hardware queue mask.
4017 queue->irq = platform_get_irq(pdev, q);
4018 err = devm_request_irq(&pdev->dev, queue->irq, macb_interrupt,
4019 IRQF_SHARED, dev->name, queue);
4022 "Unable to request IRQ %d (error %d)\n",
4027 INIT_WORK(&queue->tx_error_task, macb_tx_error_task);
4031 dev->netdev_ops = &macb_netdev_ops;
4033 /* setup appropriated routines according to adapter type */
4034 if (macb_is_gem(bp)) {
4035 bp->max_tx_length = GEM_MAX_TX_LEN;
4036 bp->macbgem_ops.mog_alloc_rx_buffers = gem_alloc_rx_buffers;
4037 bp->macbgem_ops.mog_free_rx_buffers = gem_free_rx_buffers;
4038 bp->macbgem_ops.mog_init_rings = gem_init_rings;
4039 bp->macbgem_ops.mog_rx = gem_rx;
4040 dev->ethtool_ops = &gem_ethtool_ops;
4042 bp->max_tx_length = MACB_MAX_TX_LEN;
4043 bp->macbgem_ops.mog_alloc_rx_buffers = macb_alloc_rx_buffers;
4044 bp->macbgem_ops.mog_free_rx_buffers = macb_free_rx_buffers;
4045 bp->macbgem_ops.mog_init_rings = macb_init_rings;
4046 bp->macbgem_ops.mog_rx = macb_rx;
4047 dev->ethtool_ops = &macb_ethtool_ops;
4051 dev->hw_features = NETIF_F_SG;
4053 /* Check LSO capability */
4054 if (GEM_BFEXT(PBUF_LSO, gem_readl(bp, DCFG6)))
4055 dev->hw_features |= MACB_NETIF_LSO;
4057 /* Checksum offload is only available on gem with packet buffer */
4058 if (macb_is_gem(bp) && !(bp->caps & MACB_CAPS_FIFO_MODE))
4059 dev->hw_features |= NETIF_F_HW_CSUM | NETIF_F_RXCSUM;
4060 if (bp->caps & MACB_CAPS_SG_DISABLED)
4061 dev->hw_features &= ~NETIF_F_SG;
4062 dev->features = dev->hw_features;
4064 /* Check RX Flow Filters support.
4065 * Max Rx flows set by availability of screeners & compare regs:
4066 * each 4-tuple define requires 1 T2 screener reg + 3 compare regs
4068 reg = gem_readl(bp, DCFG8);
4069 bp->max_tuples = min((GEM_BFEXT(SCR2CMP, reg) / 3),
4070 GEM_BFEXT(T2SCR, reg));
4071 INIT_LIST_HEAD(&bp->rx_fs_list.list);
4072 if (bp->max_tuples > 0) {
4073 /* also needs one ethtype match to check IPv4 */
4074 if (GEM_BFEXT(SCR2ETH, reg) > 0) {
4075 /* program this reg now */
4077 reg = GEM_BFINS(ETHTCMP, (uint16_t)ETH_P_IP, reg);
4078 gem_writel_n(bp, ETHT, SCRT2_ETHT, reg);
4079 /* Filtering is supported in hw but don't enable it in kernel now */
4080 dev->hw_features |= NETIF_F_NTUPLE;
4081 /* init Rx flow definitions */
4082 bp->rx_fs_list.count = 0;
4083 spin_lock_init(&bp->rx_fs_lock);
4088 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED)) {
4090 if (phy_interface_mode_is_rgmii(bp->phy_interface))
4091 val = bp->usrio->rgmii;
4092 else if (bp->phy_interface == PHY_INTERFACE_MODE_RMII &&
4093 (bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
4094 val = bp->usrio->rmii;
4095 else if (!(bp->caps & MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII))
4096 val = bp->usrio->mii;
4098 if (bp->caps & MACB_CAPS_USRIO_HAS_CLKEN)
4099 val |= bp->usrio->refclk;
4101 macb_or_gem_writel(bp, USRIO, val);
4104 /* Set MII management clock divider */
4105 val = macb_mdc_clk_div(bp);
4106 val |= macb_dbw(bp);
4107 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII)
4108 val |= GEM_BIT(SGMIIEN) | GEM_BIT(PCSSEL);
4109 macb_writel(bp, NCFGR, val);
4114 static const struct macb_usrio_config macb_default_usrio = {
4115 .mii = MACB_BIT(MII),
4116 .rmii = MACB_BIT(RMII),
4117 .rgmii = GEM_BIT(RGMII),
4118 .refclk = MACB_BIT(CLKEN),
4121 #if defined(CONFIG_OF)
4122 /* 1518 rounded up */
4123 #define AT91ETHER_MAX_RBUFF_SZ 0x600
4124 /* max number of receive buffers */
4125 #define AT91ETHER_MAX_RX_DESCR 9
4127 static struct sifive_fu540_macb_mgmt *mgmt;
4129 static int at91ether_alloc_coherent(struct macb *lp)
4131 struct macb_queue *q = &lp->queues[0];
4133 q->rx_ring = dma_alloc_coherent(&lp->pdev->dev,
4134 (AT91ETHER_MAX_RX_DESCR *
4135 macb_dma_desc_get_size(lp)),
4136 &q->rx_ring_dma, GFP_KERNEL);
4140 q->rx_buffers = dma_alloc_coherent(&lp->pdev->dev,
4141 AT91ETHER_MAX_RX_DESCR *
4142 AT91ETHER_MAX_RBUFF_SZ,
4143 &q->rx_buffers_dma, GFP_KERNEL);
4144 if (!q->rx_buffers) {
4145 dma_free_coherent(&lp->pdev->dev,
4146 AT91ETHER_MAX_RX_DESCR *
4147 macb_dma_desc_get_size(lp),
4148 q->rx_ring, q->rx_ring_dma);
4156 static void at91ether_free_coherent(struct macb *lp)
4158 struct macb_queue *q = &lp->queues[0];
4161 dma_free_coherent(&lp->pdev->dev,
4162 AT91ETHER_MAX_RX_DESCR *
4163 macb_dma_desc_get_size(lp),
4164 q->rx_ring, q->rx_ring_dma);
4168 if (q->rx_buffers) {
4169 dma_free_coherent(&lp->pdev->dev,
4170 AT91ETHER_MAX_RX_DESCR *
4171 AT91ETHER_MAX_RBUFF_SZ,
4172 q->rx_buffers, q->rx_buffers_dma);
4173 q->rx_buffers = NULL;
4177 /* Initialize and start the Receiver and Transmit subsystems */
4178 static int at91ether_start(struct macb *lp)
4180 struct macb_queue *q = &lp->queues[0];
4181 struct macb_dma_desc *desc;
4186 ret = at91ether_alloc_coherent(lp);
4190 addr = q->rx_buffers_dma;
4191 for (i = 0; i < AT91ETHER_MAX_RX_DESCR; i++) {
4192 desc = macb_rx_desc(q, i);
4193 macb_set_addr(lp, desc, addr);
4195 addr += AT91ETHER_MAX_RBUFF_SZ;
4198 /* Set the Wrap bit on the last descriptor */
4199 desc->addr |= MACB_BIT(RX_WRAP);
4201 /* Reset buffer index */
4204 /* Program address of descriptor list in Rx Buffer Queue register */
4205 macb_writel(lp, RBQP, q->rx_ring_dma);
4207 /* Enable Receive and Transmit */
4208 ctl = macb_readl(lp, NCR);
4209 macb_writel(lp, NCR, ctl | MACB_BIT(RE) | MACB_BIT(TE));
4211 /* Enable MAC interrupts */
4212 macb_writel(lp, IER, MACB_BIT(RCOMP) |
4214 MACB_BIT(ISR_TUND) |
4217 MACB_BIT(ISR_ROVR) |
4223 static void at91ether_stop(struct macb *lp)
4227 /* Disable MAC interrupts */
4228 macb_writel(lp, IDR, MACB_BIT(RCOMP) |
4230 MACB_BIT(ISR_TUND) |
4233 MACB_BIT(ISR_ROVR) |
4236 /* Disable Receiver and Transmitter */
4237 ctl = macb_readl(lp, NCR);
4238 macb_writel(lp, NCR, ctl & ~(MACB_BIT(TE) | MACB_BIT(RE)));
4240 /* Free resources. */
4241 at91ether_free_coherent(lp);
4244 /* Open the ethernet interface */
4245 static int at91ether_open(struct net_device *dev)
4247 struct macb *lp = netdev_priv(dev);
4251 ret = pm_runtime_resume_and_get(&lp->pdev->dev);
4255 /* Clear internal statistics */
4256 ctl = macb_readl(lp, NCR);
4257 macb_writel(lp, NCR, ctl | MACB_BIT(CLRSTAT));
4259 macb_set_hwaddr(lp);
4261 ret = at91ether_start(lp);
4265 ret = macb_phylink_connect(lp);
4269 netif_start_queue(dev);
4276 pm_runtime_put_sync(&lp->pdev->dev);
4280 /* Close the interface */
4281 static int at91ether_close(struct net_device *dev)
4283 struct macb *lp = netdev_priv(dev);
4285 netif_stop_queue(dev);
4287 phylink_stop(lp->phylink);
4288 phylink_disconnect_phy(lp->phylink);
4292 return pm_runtime_put(&lp->pdev->dev);
4295 /* Transmit packet */
4296 static netdev_tx_t at91ether_start_xmit(struct sk_buff *skb,
4297 struct net_device *dev)
4299 struct macb *lp = netdev_priv(dev);
4301 if (macb_readl(lp, TSR) & MACB_BIT(RM9200_BNQ)) {
4304 netif_stop_queue(dev);
4306 /* Store packet information (to free when Tx completed) */
4307 lp->rm9200_txq[desc].skb = skb;
4308 lp->rm9200_txq[desc].size = skb->len;
4309 lp->rm9200_txq[desc].mapping = dma_map_single(&lp->pdev->dev, skb->data,
4310 skb->len, DMA_TO_DEVICE);
4311 if (dma_mapping_error(&lp->pdev->dev, lp->rm9200_txq[desc].mapping)) {
4312 dev_kfree_skb_any(skb);
4313 dev->stats.tx_dropped++;
4314 netdev_err(dev, "%s: DMA mapping error\n", __func__);
4315 return NETDEV_TX_OK;
4318 /* Set address of the data in the Transmit Address register */
4319 macb_writel(lp, TAR, lp->rm9200_txq[desc].mapping);
4320 /* Set length of the packet in the Transmit Control register */
4321 macb_writel(lp, TCR, skb->len);
4324 netdev_err(dev, "%s called, but device is busy!\n", __func__);
4325 return NETDEV_TX_BUSY;
4328 return NETDEV_TX_OK;
4331 /* Extract received frame from buffer descriptors and sent to upper layers.
4332 * (Called from interrupt context)
4334 static void at91ether_rx(struct net_device *dev)
4336 struct macb *lp = netdev_priv(dev);
4337 struct macb_queue *q = &lp->queues[0];
4338 struct macb_dma_desc *desc;
4339 unsigned char *p_recv;
4340 struct sk_buff *skb;
4341 unsigned int pktlen;
4343 desc = macb_rx_desc(q, q->rx_tail);
4344 while (desc->addr & MACB_BIT(RX_USED)) {
4345 p_recv = q->rx_buffers + q->rx_tail * AT91ETHER_MAX_RBUFF_SZ;
4346 pktlen = MACB_BF(RX_FRMLEN, desc->ctrl);
4347 skb = netdev_alloc_skb(dev, pktlen + 2);
4349 skb_reserve(skb, 2);
4350 skb_put_data(skb, p_recv, pktlen);
4352 skb->protocol = eth_type_trans(skb, dev);
4353 dev->stats.rx_packets++;
4354 dev->stats.rx_bytes += pktlen;
4357 dev->stats.rx_dropped++;
4360 if (desc->ctrl & MACB_BIT(RX_MHASH_MATCH))
4361 dev->stats.multicast++;
4363 /* reset ownership bit */
4364 desc->addr &= ~MACB_BIT(RX_USED);
4366 /* wrap after last buffer */
4367 if (q->rx_tail == AT91ETHER_MAX_RX_DESCR - 1)
4372 desc = macb_rx_desc(q, q->rx_tail);
4376 /* MAC interrupt handler */
4377 static irqreturn_t at91ether_interrupt(int irq, void *dev_id)
4379 struct net_device *dev = dev_id;
4380 struct macb *lp = netdev_priv(dev);
4384 /* MAC Interrupt Status register indicates what interrupts are pending.
4385 * It is automatically cleared once read.
4387 intstatus = macb_readl(lp, ISR);
4389 /* Receive complete */
4390 if (intstatus & MACB_BIT(RCOMP))
4393 /* Transmit complete */
4394 if (intstatus & MACB_BIT(TCOMP)) {
4395 /* The TCOM bit is set even if the transmission failed */
4396 if (intstatus & (MACB_BIT(ISR_TUND) | MACB_BIT(ISR_RLE)))
4397 dev->stats.tx_errors++;
4400 if (lp->rm9200_txq[desc].skb) {
4401 dev_consume_skb_irq(lp->rm9200_txq[desc].skb);
4402 lp->rm9200_txq[desc].skb = NULL;
4403 dma_unmap_single(&lp->pdev->dev, lp->rm9200_txq[desc].mapping,
4404 lp->rm9200_txq[desc].size, DMA_TO_DEVICE);
4405 dev->stats.tx_packets++;
4406 dev->stats.tx_bytes += lp->rm9200_txq[desc].size;
4408 netif_wake_queue(dev);
4411 /* Work-around for EMAC Errata section 41.3.1 */
4412 if (intstatus & MACB_BIT(RXUBR)) {
4413 ctl = macb_readl(lp, NCR);
4414 macb_writel(lp, NCR, ctl & ~MACB_BIT(RE));
4416 macb_writel(lp, NCR, ctl | MACB_BIT(RE));
4419 if (intstatus & MACB_BIT(ISR_ROVR))
4420 netdev_err(dev, "ROVR error\n");
4425 #ifdef CONFIG_NET_POLL_CONTROLLER
4426 static void at91ether_poll_controller(struct net_device *dev)
4428 unsigned long flags;
4430 local_irq_save(flags);
4431 at91ether_interrupt(dev->irq, dev);
4432 local_irq_restore(flags);
4436 static const struct net_device_ops at91ether_netdev_ops = {
4437 .ndo_open = at91ether_open,
4438 .ndo_stop = at91ether_close,
4439 .ndo_start_xmit = at91ether_start_xmit,
4440 .ndo_get_stats = macb_get_stats,
4441 .ndo_set_rx_mode = macb_set_rx_mode,
4442 .ndo_set_mac_address = eth_mac_addr,
4443 .ndo_eth_ioctl = macb_ioctl,
4444 .ndo_validate_addr = eth_validate_addr,
4445 #ifdef CONFIG_NET_POLL_CONTROLLER
4446 .ndo_poll_controller = at91ether_poll_controller,
4450 static int at91ether_clk_init(struct platform_device *pdev, struct clk **pclk,
4451 struct clk **hclk, struct clk **tx_clk,
4452 struct clk **rx_clk, struct clk **tsu_clk)
4461 *pclk = devm_clk_get(&pdev->dev, "ether_clk");
4463 return PTR_ERR(*pclk);
4465 err = clk_prepare_enable(*pclk);
4467 dev_err(&pdev->dev, "failed to enable pclk (%d)\n", err);
4474 static int at91ether_init(struct platform_device *pdev)
4476 struct net_device *dev = platform_get_drvdata(pdev);
4477 struct macb *bp = netdev_priv(dev);
4480 bp->queues[0].bp = bp;
4482 dev->netdev_ops = &at91ether_netdev_ops;
4483 dev->ethtool_ops = &macb_ethtool_ops;
4485 err = devm_request_irq(&pdev->dev, dev->irq, at91ether_interrupt,
4490 macb_writel(bp, NCR, 0);
4492 macb_writel(bp, NCFGR, MACB_BF(CLK, MACB_CLK_DIV32) | MACB_BIT(BIG));
4497 static unsigned long fu540_macb_tx_recalc_rate(struct clk_hw *hw,
4498 unsigned long parent_rate)
4503 static long fu540_macb_tx_round_rate(struct clk_hw *hw, unsigned long rate,
4504 unsigned long *parent_rate)
4506 if (WARN_ON(rate < 2500000))
4508 else if (rate == 2500000)
4510 else if (WARN_ON(rate < 13750000))
4512 else if (WARN_ON(rate < 25000000))
4514 else if (rate == 25000000)
4516 else if (WARN_ON(rate < 75000000))
4518 else if (WARN_ON(rate < 125000000))
4520 else if (rate == 125000000)
4523 WARN_ON(rate > 125000000);
4528 static int fu540_macb_tx_set_rate(struct clk_hw *hw, unsigned long rate,
4529 unsigned long parent_rate)
4531 rate = fu540_macb_tx_round_rate(hw, rate, &parent_rate);
4532 if (rate != 125000000)
4533 iowrite32(1, mgmt->reg);
4535 iowrite32(0, mgmt->reg);
4541 static const struct clk_ops fu540_c000_ops = {
4542 .recalc_rate = fu540_macb_tx_recalc_rate,
4543 .round_rate = fu540_macb_tx_round_rate,
4544 .set_rate = fu540_macb_tx_set_rate,
4547 static int fu540_c000_clk_init(struct platform_device *pdev, struct clk **pclk,
4548 struct clk **hclk, struct clk **tx_clk,
4549 struct clk **rx_clk, struct clk **tsu_clk)
4551 struct clk_init_data init;
4554 err = macb_clk_init(pdev, pclk, hclk, tx_clk, rx_clk, tsu_clk);
4558 mgmt = devm_kzalloc(&pdev->dev, sizeof(*mgmt), GFP_KERNEL);
4561 goto err_disable_clks;
4564 init.name = "sifive-gemgxl-mgmt";
4565 init.ops = &fu540_c000_ops;
4567 init.num_parents = 0;
4570 mgmt->hw.init = &init;
4572 *tx_clk = devm_clk_register(&pdev->dev, &mgmt->hw);
4573 if (IS_ERR(*tx_clk)) {
4574 err = PTR_ERR(*tx_clk);
4575 goto err_disable_clks;
4578 err = clk_prepare_enable(*tx_clk);
4580 dev_err(&pdev->dev, "failed to enable tx_clk (%u)\n", err);
4582 goto err_disable_clks;
4584 dev_info(&pdev->dev, "Registered clk switch '%s'\n", init.name);
4590 macb_clks_disable(*pclk, *hclk, *tx_clk, *rx_clk, *tsu_clk);
4595 static int fu540_c000_init(struct platform_device *pdev)
4597 mgmt->reg = devm_platform_ioremap_resource(pdev, 1);
4598 if (IS_ERR(mgmt->reg))
4599 return PTR_ERR(mgmt->reg);
4601 return macb_init(pdev);
4604 static int init_reset_optional(struct platform_device *pdev)
4606 struct net_device *dev = platform_get_drvdata(pdev);
4607 struct macb *bp = netdev_priv(dev);
4610 if (bp->phy_interface == PHY_INTERFACE_MODE_SGMII) {
4611 /* Ensure PHY device used in SGMII mode is ready */
4612 bp->sgmii_phy = devm_phy_optional_get(&pdev->dev, NULL);
4614 if (IS_ERR(bp->sgmii_phy))
4615 return dev_err_probe(&pdev->dev, PTR_ERR(bp->sgmii_phy),
4616 "failed to get SGMII PHY\n");
4618 ret = phy_init(bp->sgmii_phy);
4620 return dev_err_probe(&pdev->dev, ret,
4621 "failed to init SGMII PHY\n");
4624 /* Fully reset controller at hardware level if mapped in device tree */
4625 ret = device_reset_optional(&pdev->dev);
4627 phy_exit(bp->sgmii_phy);
4628 return dev_err_probe(&pdev->dev, ret, "failed to reset controller");
4631 ret = macb_init(pdev);
4633 phy_exit(bp->sgmii_phy);
4638 static const struct macb_usrio_config sama7g5_usrio = {
4646 static const struct macb_config fu540_c000_config = {
4647 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
4648 MACB_CAPS_GEM_HAS_PTP,
4649 .dma_burst_length = 16,
4650 .clk_init = fu540_c000_clk_init,
4651 .init = fu540_c000_init,
4652 .jumbo_max_len = 10240,
4653 .usrio = &macb_default_usrio,
4656 static const struct macb_config at91sam9260_config = {
4657 .caps = MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4658 .clk_init = macb_clk_init,
4660 .usrio = &macb_default_usrio,
4663 static const struct macb_config sama5d3macb_config = {
4664 .caps = MACB_CAPS_SG_DISABLED |
4665 MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4666 .clk_init = macb_clk_init,
4668 .usrio = &macb_default_usrio,
4671 static const struct macb_config pc302gem_config = {
4672 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE,
4673 .dma_burst_length = 16,
4674 .clk_init = macb_clk_init,
4676 .usrio = &macb_default_usrio,
4679 static const struct macb_config sama5d2_config = {
4680 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4681 .dma_burst_length = 16,
4682 .clk_init = macb_clk_init,
4684 .usrio = &macb_default_usrio,
4687 static const struct macb_config sama5d29_config = {
4688 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_GEM_HAS_PTP,
4689 .dma_burst_length = 16,
4690 .clk_init = macb_clk_init,
4692 .usrio = &macb_default_usrio,
4695 static const struct macb_config sama5d3_config = {
4696 .caps = MACB_CAPS_SG_DISABLED | MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4697 MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII | MACB_CAPS_JUMBO,
4698 .dma_burst_length = 16,
4699 .clk_init = macb_clk_init,
4701 .jumbo_max_len = 10240,
4702 .usrio = &macb_default_usrio,
4705 static const struct macb_config sama5d4_config = {
4706 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII,
4707 .dma_burst_length = 4,
4708 .clk_init = macb_clk_init,
4710 .usrio = &macb_default_usrio,
4713 static const struct macb_config emac_config = {
4714 .caps = MACB_CAPS_NEEDS_RSTONUBR | MACB_CAPS_MACB_IS_EMAC,
4715 .clk_init = at91ether_clk_init,
4716 .init = at91ether_init,
4717 .usrio = &macb_default_usrio,
4720 static const struct macb_config np4_config = {
4721 .caps = MACB_CAPS_USRIO_DISABLED,
4722 .clk_init = macb_clk_init,
4724 .usrio = &macb_default_usrio,
4727 static const struct macb_config zynqmp_config = {
4728 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4730 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH,
4731 .dma_burst_length = 16,
4732 .clk_init = macb_clk_init,
4733 .init = init_reset_optional,
4734 .jumbo_max_len = 10240,
4735 .usrio = &macb_default_usrio,
4738 static const struct macb_config zynq_config = {
4739 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_NO_GIGABIT_HALF |
4740 MACB_CAPS_NEEDS_RSTONUBR,
4741 .dma_burst_length = 16,
4742 .clk_init = macb_clk_init,
4744 .usrio = &macb_default_usrio,
4747 static const struct macb_config mpfs_config = {
4748 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4750 MACB_CAPS_GEM_HAS_PTP,
4751 .dma_burst_length = 16,
4752 .clk_init = macb_clk_init,
4753 .init = init_reset_optional,
4754 .usrio = &macb_default_usrio,
4755 .jumbo_max_len = 10240,
4758 static const struct macb_config sama7g5_gem_config = {
4759 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_CLK_HW_CHG |
4760 MACB_CAPS_MIIONRGMII,
4761 .dma_burst_length = 16,
4762 .clk_init = macb_clk_init,
4764 .usrio = &sama7g5_usrio,
4767 static const struct macb_config sama7g5_emac_config = {
4768 .caps = MACB_CAPS_USRIO_DEFAULT_IS_MII_GMII |
4769 MACB_CAPS_USRIO_HAS_CLKEN | MACB_CAPS_MIIONRGMII,
4770 .dma_burst_length = 16,
4771 .clk_init = macb_clk_init,
4773 .usrio = &sama7g5_usrio,
4776 static const struct macb_config versal_config = {
4777 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE | MACB_CAPS_JUMBO |
4778 MACB_CAPS_GEM_HAS_PTP | MACB_CAPS_BD_RD_PREFETCH | MACB_CAPS_NEED_TSUCLK,
4779 .dma_burst_length = 16,
4780 .clk_init = macb_clk_init,
4781 .init = init_reset_optional,
4782 .jumbo_max_len = 10240,
4783 .usrio = &macb_default_usrio,
4786 static const struct of_device_id macb_dt_ids[] = {
4787 { .compatible = "cdns,at91sam9260-macb", .data = &at91sam9260_config },
4788 { .compatible = "cdns,macb" },
4789 { .compatible = "cdns,np4-macb", .data = &np4_config },
4790 { .compatible = "cdns,pc302-gem", .data = &pc302gem_config },
4791 { .compatible = "cdns,gem", .data = &pc302gem_config },
4792 { .compatible = "cdns,sam9x60-macb", .data = &at91sam9260_config },
4793 { .compatible = "atmel,sama5d2-gem", .data = &sama5d2_config },
4794 { .compatible = "atmel,sama5d29-gem", .data = &sama5d29_config },
4795 { .compatible = "atmel,sama5d3-gem", .data = &sama5d3_config },
4796 { .compatible = "atmel,sama5d3-macb", .data = &sama5d3macb_config },
4797 { .compatible = "atmel,sama5d4-gem", .data = &sama5d4_config },
4798 { .compatible = "cdns,at91rm9200-emac", .data = &emac_config },
4799 { .compatible = "cdns,emac", .data = &emac_config },
4800 { .compatible = "cdns,zynqmp-gem", .data = &zynqmp_config}, /* deprecated */
4801 { .compatible = "cdns,zynq-gem", .data = &zynq_config }, /* deprecated */
4802 { .compatible = "sifive,fu540-c000-gem", .data = &fu540_c000_config },
4803 { .compatible = "microchip,mpfs-macb", .data = &mpfs_config },
4804 { .compatible = "microchip,sama7g5-gem", .data = &sama7g5_gem_config },
4805 { .compatible = "microchip,sama7g5-emac", .data = &sama7g5_emac_config },
4806 { .compatible = "xlnx,zynqmp-gem", .data = &zynqmp_config},
4807 { .compatible = "xlnx,zynq-gem", .data = &zynq_config },
4808 { .compatible = "xlnx,versal-gem", .data = &versal_config},
4811 MODULE_DEVICE_TABLE(of, macb_dt_ids);
4812 #endif /* CONFIG_OF */
4814 static const struct macb_config default_gem_config = {
4815 .caps = MACB_CAPS_GIGABIT_MODE_AVAILABLE |
4817 MACB_CAPS_GEM_HAS_PTP,
4818 .dma_burst_length = 16,
4819 .clk_init = macb_clk_init,
4821 .usrio = &macb_default_usrio,
4822 .jumbo_max_len = 10240,
4825 static int macb_probe(struct platform_device *pdev)
4827 const struct macb_config *macb_config = &default_gem_config;
4828 int (*clk_init)(struct platform_device *, struct clk **,
4829 struct clk **, struct clk **, struct clk **,
4830 struct clk **) = macb_config->clk_init;
4831 int (*init)(struct platform_device *) = macb_config->init;
4832 struct device_node *np = pdev->dev.of_node;
4833 struct clk *pclk, *hclk = NULL, *tx_clk = NULL, *rx_clk = NULL;
4834 struct clk *tsu_clk = NULL;
4835 unsigned int queue_mask, num_queues;
4837 phy_interface_t interface;
4838 struct net_device *dev;
4839 struct resource *regs;
4844 mem = devm_platform_get_and_ioremap_resource(pdev, 0, ®s);
4846 return PTR_ERR(mem);
4849 const struct of_device_id *match;
4851 match = of_match_node(macb_dt_ids, np);
4852 if (match && match->data) {
4853 macb_config = match->data;
4854 clk_init = macb_config->clk_init;
4855 init = macb_config->init;
4859 err = clk_init(pdev, &pclk, &hclk, &tx_clk, &rx_clk, &tsu_clk);
4863 pm_runtime_set_autosuspend_delay(&pdev->dev, MACB_PM_TIMEOUT);
4864 pm_runtime_use_autosuspend(&pdev->dev);
4865 pm_runtime_get_noresume(&pdev->dev);
4866 pm_runtime_set_active(&pdev->dev);
4867 pm_runtime_enable(&pdev->dev);
4868 native_io = hw_is_native_io(mem);
4870 macb_probe_queues(mem, native_io, &queue_mask, &num_queues);
4871 dev = alloc_etherdev_mq(sizeof(*bp), num_queues);
4874 goto err_disable_clocks;
4877 dev->base_addr = regs->start;
4879 SET_NETDEV_DEV(dev, &pdev->dev);
4881 bp = netdev_priv(dev);
4885 bp->native_io = native_io;
4887 bp->macb_reg_readl = hw_readl_native;
4888 bp->macb_reg_writel = hw_writel_native;
4890 bp->macb_reg_readl = hw_readl;
4891 bp->macb_reg_writel = hw_writel;
4893 bp->num_queues = num_queues;
4894 bp->queue_mask = queue_mask;
4896 bp->dma_burst_length = macb_config->dma_burst_length;
4899 bp->tx_clk = tx_clk;
4900 bp->rx_clk = rx_clk;
4901 bp->tsu_clk = tsu_clk;
4903 bp->jumbo_max_len = macb_config->jumbo_max_len;
4906 if (of_get_property(np, "magic-packet", NULL))
4907 bp->wol |= MACB_WOL_HAS_MAGIC_PACKET;
4908 device_set_wakeup_capable(&pdev->dev, bp->wol & MACB_WOL_HAS_MAGIC_PACKET);
4910 bp->usrio = macb_config->usrio;
4912 spin_lock_init(&bp->lock);
4914 /* setup capabilities */
4915 macb_configure_caps(bp, macb_config);
4917 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
4918 if (GEM_BFEXT(DAW64, gem_readl(bp, DCFG6))) {
4919 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(44));
4920 bp->hw_dma_cap |= HW_DMA_CAP_64B;
4923 platform_set_drvdata(pdev, dev);
4925 dev->irq = platform_get_irq(pdev, 0);
4928 goto err_out_free_netdev;
4931 /* MTU range: 68 - 1500 or 10240 */
4932 dev->min_mtu = GEM_MTU_MIN_SIZE;
4933 if ((bp->caps & MACB_CAPS_JUMBO) && bp->jumbo_max_len)
4934 dev->max_mtu = bp->jumbo_max_len - ETH_HLEN - ETH_FCS_LEN;
4936 dev->max_mtu = ETH_DATA_LEN;
4938 if (bp->caps & MACB_CAPS_BD_RD_PREFETCH) {
4939 val = GEM_BFEXT(RXBD_RDBUFF, gem_readl(bp, DCFG10));
4941 bp->rx_bd_rd_prefetch = (2 << (val - 1)) *
4942 macb_dma_desc_get_size(bp);
4944 val = GEM_BFEXT(TXBD_RDBUFF, gem_readl(bp, DCFG10));
4946 bp->tx_bd_rd_prefetch = (2 << (val - 1)) *
4947 macb_dma_desc_get_size(bp);
4950 bp->rx_intr_mask = MACB_RX_INT_FLAGS;
4951 if (bp->caps & MACB_CAPS_NEEDS_RSTONUBR)
4952 bp->rx_intr_mask |= MACB_BIT(RXUBR);
4954 err = of_get_ethdev_address(np, bp->dev);
4955 if (err == -EPROBE_DEFER)
4956 goto err_out_free_netdev;
4958 macb_get_hwaddr(bp);
4960 err = of_get_phy_mode(np, &interface);
4962 /* not found in DT, MII by default */
4963 bp->phy_interface = PHY_INTERFACE_MODE_MII;
4965 bp->phy_interface = interface;
4967 /* IP specific init */
4970 goto err_out_free_netdev;
4972 err = macb_mii_init(bp);
4974 goto err_out_phy_exit;
4976 netif_carrier_off(dev);
4978 err = register_netdev(dev);
4980 dev_err(&pdev->dev, "Cannot register net device, aborting.\n");
4981 goto err_out_unregister_mdio;
4984 tasklet_setup(&bp->hresp_err_tasklet, macb_hresp_error_task);
4986 netdev_info(dev, "Cadence %s rev 0x%08x at 0x%08lx irq %d (%pM)\n",
4987 macb_is_gem(bp) ? "GEM" : "MACB", macb_readl(bp, MID),
4988 dev->base_addr, dev->irq, dev->dev_addr);
4990 pm_runtime_mark_last_busy(&bp->pdev->dev);
4991 pm_runtime_put_autosuspend(&bp->pdev->dev);
4995 err_out_unregister_mdio:
4996 mdiobus_unregister(bp->mii_bus);
4997 mdiobus_free(bp->mii_bus);
5000 phy_exit(bp->sgmii_phy);
5002 err_out_free_netdev:
5006 macb_clks_disable(pclk, hclk, tx_clk, rx_clk, tsu_clk);
5007 pm_runtime_disable(&pdev->dev);
5008 pm_runtime_set_suspended(&pdev->dev);
5009 pm_runtime_dont_use_autosuspend(&pdev->dev);
5014 static int macb_remove(struct platform_device *pdev)
5016 struct net_device *dev;
5019 dev = platform_get_drvdata(pdev);
5022 bp = netdev_priv(dev);
5023 phy_exit(bp->sgmii_phy);
5024 mdiobus_unregister(bp->mii_bus);
5025 mdiobus_free(bp->mii_bus);
5027 unregister_netdev(dev);
5028 tasklet_kill(&bp->hresp_err_tasklet);
5029 pm_runtime_disable(&pdev->dev);
5030 pm_runtime_dont_use_autosuspend(&pdev->dev);
5031 if (!pm_runtime_suspended(&pdev->dev)) {
5032 macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk,
5033 bp->rx_clk, bp->tsu_clk);
5034 pm_runtime_set_suspended(&pdev->dev);
5036 phylink_destroy(bp->phylink);
5043 static int __maybe_unused macb_suspend(struct device *dev)
5045 struct net_device *netdev = dev_get_drvdata(dev);
5046 struct macb *bp = netdev_priv(netdev);
5047 struct macb_queue *queue;
5048 unsigned long flags;
5052 if (!netif_running(netdev))
5055 if (bp->wol & MACB_WOL_ENABLED) {
5056 spin_lock_irqsave(&bp->lock, flags);
5057 /* Flush all status bits */
5058 macb_writel(bp, TSR, -1);
5059 macb_writel(bp, RSR, -1);
5060 for (q = 0, queue = bp->queues; q < bp->num_queues;
5062 /* Disable all interrupts */
5063 queue_writel(queue, IDR, -1);
5064 queue_readl(queue, ISR);
5065 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
5066 queue_writel(queue, ISR, -1);
5068 /* Change interrupt handler and
5069 * Enable WoL IRQ on queue 0
5071 devm_free_irq(dev, bp->queues[0].irq, bp->queues);
5072 if (macb_is_gem(bp)) {
5073 err = devm_request_irq(dev, bp->queues[0].irq, gem_wol_interrupt,
5074 IRQF_SHARED, netdev->name, bp->queues);
5077 "Unable to request IRQ %d (error %d)\n",
5078 bp->queues[0].irq, err);
5079 spin_unlock_irqrestore(&bp->lock, flags);
5082 queue_writel(bp->queues, IER, GEM_BIT(WOL));
5083 gem_writel(bp, WOL, MACB_BIT(MAG));
5085 err = devm_request_irq(dev, bp->queues[0].irq, macb_wol_interrupt,
5086 IRQF_SHARED, netdev->name, bp->queues);
5089 "Unable to request IRQ %d (error %d)\n",
5090 bp->queues[0].irq, err);
5091 spin_unlock_irqrestore(&bp->lock, flags);
5094 queue_writel(bp->queues, IER, MACB_BIT(WOL));
5095 macb_writel(bp, WOL, MACB_BIT(MAG));
5097 spin_unlock_irqrestore(&bp->lock, flags);
5099 enable_irq_wake(bp->queues[0].irq);
5102 netif_device_detach(netdev);
5103 for (q = 0, queue = bp->queues; q < bp->num_queues;
5105 napi_disable(&queue->napi_rx);
5106 napi_disable(&queue->napi_tx);
5109 if (!(bp->wol & MACB_WOL_ENABLED)) {
5111 phylink_stop(bp->phylink);
5113 spin_lock_irqsave(&bp->lock, flags);
5115 spin_unlock_irqrestore(&bp->lock, flags);
5118 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
5119 bp->pm_data.usrio = macb_or_gem_readl(bp, USRIO);
5121 if (netdev->hw_features & NETIF_F_NTUPLE)
5122 bp->pm_data.scrt2 = gem_readl_n(bp, ETHT, SCRT2_ETHT);
5125 bp->ptp_info->ptp_remove(netdev);
5126 if (!device_may_wakeup(dev))
5127 pm_runtime_force_suspend(dev);
5132 static int __maybe_unused macb_resume(struct device *dev)
5134 struct net_device *netdev = dev_get_drvdata(dev);
5135 struct macb *bp = netdev_priv(netdev);
5136 struct macb_queue *queue;
5137 unsigned long flags;
5141 if (!netif_running(netdev))
5144 if (!device_may_wakeup(dev))
5145 pm_runtime_force_resume(dev);
5147 if (bp->wol & MACB_WOL_ENABLED) {
5148 spin_lock_irqsave(&bp->lock, flags);
5150 if (macb_is_gem(bp)) {
5151 queue_writel(bp->queues, IDR, GEM_BIT(WOL));
5152 gem_writel(bp, WOL, 0);
5154 queue_writel(bp->queues, IDR, MACB_BIT(WOL));
5155 macb_writel(bp, WOL, 0);
5157 /* Clear ISR on queue 0 */
5158 queue_readl(bp->queues, ISR);
5159 if (bp->caps & MACB_CAPS_ISR_CLEAR_ON_WRITE)
5160 queue_writel(bp->queues, ISR, -1);
5161 /* Replace interrupt handler on queue 0 */
5162 devm_free_irq(dev, bp->queues[0].irq, bp->queues);
5163 err = devm_request_irq(dev, bp->queues[0].irq, macb_interrupt,
5164 IRQF_SHARED, netdev->name, bp->queues);
5167 "Unable to request IRQ %d (error %d)\n",
5168 bp->queues[0].irq, err);
5169 spin_unlock_irqrestore(&bp->lock, flags);
5172 spin_unlock_irqrestore(&bp->lock, flags);
5174 disable_irq_wake(bp->queues[0].irq);
5176 /* Now make sure we disable phy before moving
5177 * to common restore path
5180 phylink_stop(bp->phylink);
5184 for (q = 0, queue = bp->queues; q < bp->num_queues;
5186 napi_enable(&queue->napi_rx);
5187 napi_enable(&queue->napi_tx);
5190 if (netdev->hw_features & NETIF_F_NTUPLE)
5191 gem_writel_n(bp, ETHT, SCRT2_ETHT, bp->pm_data.scrt2);
5193 if (!(bp->caps & MACB_CAPS_USRIO_DISABLED))
5194 macb_or_gem_writel(bp, USRIO, bp->pm_data.usrio);
5196 macb_writel(bp, NCR, MACB_BIT(MPE));
5198 macb_set_rx_mode(netdev);
5199 macb_restore_features(bp);
5201 phylink_start(bp->phylink);
5204 netif_device_attach(netdev);
5206 bp->ptp_info->ptp_init(netdev);
5211 static int __maybe_unused macb_runtime_suspend(struct device *dev)
5213 struct net_device *netdev = dev_get_drvdata(dev);
5214 struct macb *bp = netdev_priv(netdev);
5216 if (!(device_may_wakeup(dev)))
5217 macb_clks_disable(bp->pclk, bp->hclk, bp->tx_clk, bp->rx_clk, bp->tsu_clk);
5218 else if (!(bp->caps & MACB_CAPS_NEED_TSUCLK))
5219 macb_clks_disable(NULL, NULL, NULL, NULL, bp->tsu_clk);
5224 static int __maybe_unused macb_runtime_resume(struct device *dev)
5226 struct net_device *netdev = dev_get_drvdata(dev);
5227 struct macb *bp = netdev_priv(netdev);
5229 if (!(device_may_wakeup(dev))) {
5230 clk_prepare_enable(bp->pclk);
5231 clk_prepare_enable(bp->hclk);
5232 clk_prepare_enable(bp->tx_clk);
5233 clk_prepare_enable(bp->rx_clk);
5234 clk_prepare_enable(bp->tsu_clk);
5235 } else if (!(bp->caps & MACB_CAPS_NEED_TSUCLK)) {
5236 clk_prepare_enable(bp->tsu_clk);
5242 static const struct dev_pm_ops macb_pm_ops = {
5243 SET_SYSTEM_SLEEP_PM_OPS(macb_suspend, macb_resume)
5244 SET_RUNTIME_PM_OPS(macb_runtime_suspend, macb_runtime_resume, NULL)
5247 static struct platform_driver macb_driver = {
5248 .probe = macb_probe,
5249 .remove = macb_remove,
5252 .of_match_table = of_match_ptr(macb_dt_ids),
5257 module_platform_driver(macb_driver);
5259 MODULE_LICENSE("GPL");
5260 MODULE_DESCRIPTION("Cadence MACB/GEM Ethernet driver");
5261 MODULE_AUTHOR("Haavard Skinnemoen (Atmel)");
5262 MODULE_ALIAS("platform:macb");