1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (c) 2015, 2019, The Linux Foundation. All rights reserved.
9 #include <linux/netdevice.h>
11 #include <linux/if_bridge.h>
15 #define MIB_DESC(_s, _o, _n) \
22 const struct qca8k_mib_desc ar8327_mib[] = {
23 MIB_DESC(1, 0x00, "RxBroad"),
24 MIB_DESC(1, 0x04, "RxPause"),
25 MIB_DESC(1, 0x08, "RxMulti"),
26 MIB_DESC(1, 0x0c, "RxFcsErr"),
27 MIB_DESC(1, 0x10, "RxAlignErr"),
28 MIB_DESC(1, 0x14, "RxRunt"),
29 MIB_DESC(1, 0x18, "RxFragment"),
30 MIB_DESC(1, 0x1c, "Rx64Byte"),
31 MIB_DESC(1, 0x20, "Rx128Byte"),
32 MIB_DESC(1, 0x24, "Rx256Byte"),
33 MIB_DESC(1, 0x28, "Rx512Byte"),
34 MIB_DESC(1, 0x2c, "Rx1024Byte"),
35 MIB_DESC(1, 0x30, "Rx1518Byte"),
36 MIB_DESC(1, 0x34, "RxMaxByte"),
37 MIB_DESC(1, 0x38, "RxTooLong"),
38 MIB_DESC(2, 0x3c, "RxGoodByte"),
39 MIB_DESC(2, 0x44, "RxBadByte"),
40 MIB_DESC(1, 0x4c, "RxOverFlow"),
41 MIB_DESC(1, 0x50, "Filtered"),
42 MIB_DESC(1, 0x54, "TxBroad"),
43 MIB_DESC(1, 0x58, "TxPause"),
44 MIB_DESC(1, 0x5c, "TxMulti"),
45 MIB_DESC(1, 0x60, "TxUnderRun"),
46 MIB_DESC(1, 0x64, "Tx64Byte"),
47 MIB_DESC(1, 0x68, "Tx128Byte"),
48 MIB_DESC(1, 0x6c, "Tx256Byte"),
49 MIB_DESC(1, 0x70, "Tx512Byte"),
50 MIB_DESC(1, 0x74, "Tx1024Byte"),
51 MIB_DESC(1, 0x78, "Tx1518Byte"),
52 MIB_DESC(1, 0x7c, "TxMaxByte"),
53 MIB_DESC(1, 0x80, "TxOverSize"),
54 MIB_DESC(2, 0x84, "TxByte"),
55 MIB_DESC(1, 0x8c, "TxCollision"),
56 MIB_DESC(1, 0x90, "TxAbortCol"),
57 MIB_DESC(1, 0x94, "TxMultiCol"),
58 MIB_DESC(1, 0x98, "TxSingleCol"),
59 MIB_DESC(1, 0x9c, "TxExcDefer"),
60 MIB_DESC(1, 0xa0, "TxDefer"),
61 MIB_DESC(1, 0xa4, "TxLateCol"),
62 MIB_DESC(1, 0xa8, "RXUnicast"),
63 MIB_DESC(1, 0xac, "TXUnicast"),
66 int qca8k_read(struct qca8k_priv *priv, u32 reg, u32 *val)
68 return regmap_read(priv->regmap, reg, val);
71 int qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
73 return regmap_write(priv->regmap, reg, val);
76 int qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 write_val)
78 return regmap_update_bits(priv->regmap, reg, mask, write_val);
81 static const struct regmap_range qca8k_readable_ranges[] = {
82 regmap_reg_range(0x0000, 0x00e4), /* Global control */
83 regmap_reg_range(0x0100, 0x0168), /* EEE control */
84 regmap_reg_range(0x0200, 0x0270), /* Parser control */
85 regmap_reg_range(0x0400, 0x0454), /* ACL */
86 regmap_reg_range(0x0600, 0x0718), /* Lookup */
87 regmap_reg_range(0x0800, 0x0b70), /* QM */
88 regmap_reg_range(0x0c00, 0x0c80), /* PKT */
89 regmap_reg_range(0x0e00, 0x0e98), /* L3 */
90 regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
91 regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
92 regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
93 regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
94 regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
95 regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
96 regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
99 const struct regmap_access_table qca8k_readable_table = {
100 .yes_ranges = qca8k_readable_ranges,
101 .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
104 /* TODO: remove these extra ops when we can support regmap bulk read/write */
105 static int qca8k_bulk_read(struct qca8k_priv *priv, u32 reg, u32 *val, int len)
107 int i, count = len / sizeof(u32), ret;
109 if (priv->mgmt_master && priv->info->ops->read_eth &&
110 !priv->info->ops->read_eth(priv, reg, val, len))
113 for (i = 0; i < count; i++) {
114 ret = regmap_read(priv->regmap, reg + (i * 4), val + i);
122 /* TODO: remove these extra ops when we can support regmap bulk read/write */
123 static int qca8k_bulk_write(struct qca8k_priv *priv, u32 reg, u32 *val, int len)
125 int i, count = len / sizeof(u32), ret;
128 if (priv->mgmt_master && priv->info->ops->write_eth &&
129 !priv->info->ops->write_eth(priv, reg, val, len))
132 for (i = 0; i < count; i++) {
135 ret = regmap_write(priv->regmap, reg + (i * 4), tmp);
143 static int qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)
147 return regmap_read_poll_timeout(priv->regmap, reg, val, !(val & mask), 0,
148 QCA8K_BUSY_WAIT_TIMEOUT * USEC_PER_MSEC);
151 static int qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb)
156 /* load the ARL table into an array */
157 ret = qca8k_bulk_read(priv, QCA8K_REG_ATU_DATA0, reg, sizeof(reg));
162 fdb->vid = FIELD_GET(QCA8K_ATU_VID_MASK, reg[2]);
164 fdb->aging = FIELD_GET(QCA8K_ATU_STATUS_MASK, reg[2]);
165 /* portmask - 54:48 */
166 fdb->port_mask = FIELD_GET(QCA8K_ATU_PORT_MASK, reg[1]);
168 fdb->mac[0] = FIELD_GET(QCA8K_ATU_ADDR0_MASK, reg[1]);
169 fdb->mac[1] = FIELD_GET(QCA8K_ATU_ADDR1_MASK, reg[1]);
170 fdb->mac[2] = FIELD_GET(QCA8K_ATU_ADDR2_MASK, reg[0]);
171 fdb->mac[3] = FIELD_GET(QCA8K_ATU_ADDR3_MASK, reg[0]);
172 fdb->mac[4] = FIELD_GET(QCA8K_ATU_ADDR4_MASK, reg[0]);
173 fdb->mac[5] = FIELD_GET(QCA8K_ATU_ADDR5_MASK, reg[0]);
178 static void qca8k_fdb_write(struct qca8k_priv *priv, u16 vid, u8 port_mask,
179 const u8 *mac, u8 aging)
184 reg[2] = FIELD_PREP(QCA8K_ATU_VID_MASK, vid);
186 reg[2] |= FIELD_PREP(QCA8K_ATU_STATUS_MASK, aging);
187 /* portmask - 54:48 */
188 reg[1] = FIELD_PREP(QCA8K_ATU_PORT_MASK, port_mask);
190 reg[1] |= FIELD_PREP(QCA8K_ATU_ADDR0_MASK, mac[0]);
191 reg[1] |= FIELD_PREP(QCA8K_ATU_ADDR1_MASK, mac[1]);
192 reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR2_MASK, mac[2]);
193 reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR3_MASK, mac[3]);
194 reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR4_MASK, mac[4]);
195 reg[0] |= FIELD_PREP(QCA8K_ATU_ADDR5_MASK, mac[5]);
197 /* load the array into the ARL table */
198 qca8k_bulk_write(priv, QCA8K_REG_ATU_DATA0, reg, sizeof(reg));
201 static int qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd,
207 /* Set the command and FDB index */
208 reg = QCA8K_ATU_FUNC_BUSY;
211 reg |= QCA8K_ATU_FUNC_PORT_EN;
212 reg |= FIELD_PREP(QCA8K_ATU_FUNC_PORT_MASK, port);
215 /* Write the function register triggering the table access */
216 ret = qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg);
220 /* wait for completion */
221 ret = qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY);
225 /* Check for table full violation when adding an entry */
226 if (cmd == QCA8K_FDB_LOAD) {
227 ret = qca8k_read(priv, QCA8K_REG_ATU_FUNC, ®);
230 if (reg & QCA8K_ATU_FUNC_FULL)
237 static int qca8k_fdb_next(struct qca8k_priv *priv, struct qca8k_fdb *fdb,
242 qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging);
243 ret = qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port);
247 return qca8k_fdb_read(priv, fdb);
250 static int qca8k_fdb_add(struct qca8k_priv *priv, const u8 *mac,
251 u16 port_mask, u16 vid, u8 aging)
255 mutex_lock(&priv->reg_mutex);
256 qca8k_fdb_write(priv, vid, port_mask, mac, aging);
257 ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
258 mutex_unlock(&priv->reg_mutex);
263 static int qca8k_fdb_del(struct qca8k_priv *priv, const u8 *mac,
264 u16 port_mask, u16 vid)
268 mutex_lock(&priv->reg_mutex);
269 qca8k_fdb_write(priv, vid, port_mask, mac, 0);
270 ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
271 mutex_unlock(&priv->reg_mutex);
276 void qca8k_fdb_flush(struct qca8k_priv *priv)
278 mutex_lock(&priv->reg_mutex);
279 qca8k_fdb_access(priv, QCA8K_FDB_FLUSH, -1);
280 mutex_unlock(&priv->reg_mutex);
283 static int qca8k_fdb_search_and_insert(struct qca8k_priv *priv, u8 port_mask,
284 const u8 *mac, u16 vid)
286 struct qca8k_fdb fdb = { 0 };
289 mutex_lock(&priv->reg_mutex);
291 qca8k_fdb_write(priv, vid, 0, mac, 0);
292 ret = qca8k_fdb_access(priv, QCA8K_FDB_SEARCH, -1);
296 ret = qca8k_fdb_read(priv, &fdb);
300 /* Rule exist. Delete first */
302 ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
307 /* Add port to fdb portmask */
308 fdb.port_mask |= port_mask;
310 qca8k_fdb_write(priv, vid, fdb.port_mask, mac, fdb.aging);
311 ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
314 mutex_unlock(&priv->reg_mutex);
318 static int qca8k_fdb_search_and_del(struct qca8k_priv *priv, u8 port_mask,
319 const u8 *mac, u16 vid)
321 struct qca8k_fdb fdb = { 0 };
324 mutex_lock(&priv->reg_mutex);
326 qca8k_fdb_write(priv, vid, 0, mac, 0);
327 ret = qca8k_fdb_access(priv, QCA8K_FDB_SEARCH, -1);
331 /* Rule doesn't exist. Why delete? */
337 ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
341 /* Only port in the rule is this port. Don't re insert */
342 if (fdb.port_mask == port_mask)
345 /* Remove port from port mask */
346 fdb.port_mask &= ~port_mask;
348 qca8k_fdb_write(priv, vid, fdb.port_mask, mac, fdb.aging);
349 ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
352 mutex_unlock(&priv->reg_mutex);
356 static int qca8k_vlan_access(struct qca8k_priv *priv,
357 enum qca8k_vlan_cmd cmd, u16 vid)
362 /* Set the command and VLAN index */
363 reg = QCA8K_VTU_FUNC1_BUSY;
365 reg |= FIELD_PREP(QCA8K_VTU_FUNC1_VID_MASK, vid);
367 /* Write the function register triggering the table access */
368 ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC1, reg);
372 /* wait for completion */
373 ret = qca8k_busy_wait(priv, QCA8K_REG_VTU_FUNC1, QCA8K_VTU_FUNC1_BUSY);
377 /* Check for table full violation when adding an entry */
378 if (cmd == QCA8K_VLAN_LOAD) {
379 ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC1, ®);
382 if (reg & QCA8K_VTU_FUNC1_FULL)
389 static int qca8k_vlan_add(struct qca8k_priv *priv, u8 port, u16 vid,
395 /* We do the right thing with VLAN 0 and treat it as untagged while
396 * preserving the tag on egress.
401 mutex_lock(&priv->reg_mutex);
402 ret = qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid);
406 ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, ®);
409 reg |= QCA8K_VTU_FUNC0_VALID | QCA8K_VTU_FUNC0_IVL_EN;
410 reg &= ~QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(port);
412 reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_UNTAG(port);
414 reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_TAG(port);
416 ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
419 ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);
422 mutex_unlock(&priv->reg_mutex);
427 static int qca8k_vlan_del(struct qca8k_priv *priv, u8 port, u16 vid)
433 mutex_lock(&priv->reg_mutex);
434 ret = qca8k_vlan_access(priv, QCA8K_VLAN_READ, vid);
438 ret = qca8k_read(priv, QCA8K_REG_VTU_FUNC0, ®);
441 reg &= ~QCA8K_VTU_FUNC0_EG_MODE_PORT_MASK(port);
442 reg |= QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(port);
444 /* Check if we're the last member to be removed */
446 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
447 mask = QCA8K_VTU_FUNC0_EG_MODE_PORT_NOT(i);
449 if ((reg & mask) != mask) {
456 ret = qca8k_vlan_access(priv, QCA8K_VLAN_PURGE, vid);
458 ret = qca8k_write(priv, QCA8K_REG_VTU_FUNC0, reg);
461 ret = qca8k_vlan_access(priv, QCA8K_VLAN_LOAD, vid);
465 mutex_unlock(&priv->reg_mutex);
470 int qca8k_mib_init(struct qca8k_priv *priv)
474 mutex_lock(&priv->reg_mutex);
475 ret = regmap_update_bits(priv->regmap, QCA8K_REG_MIB,
476 QCA8K_MIB_FUNC | QCA8K_MIB_BUSY,
477 FIELD_PREP(QCA8K_MIB_FUNC, QCA8K_MIB_FLUSH) |
482 ret = qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY);
486 ret = regmap_set_bits(priv->regmap, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);
490 ret = qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);
493 mutex_unlock(&priv->reg_mutex);
497 void qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable)
499 u32 mask = QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
501 /* Port 0 and 6 have no internal PHY */
502 if (port > 0 && port < 6)
503 mask |= QCA8K_PORT_STATUS_LINK_AUTO;
506 regmap_set_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask);
508 regmap_clear_bits(priv->regmap, QCA8K_REG_PORT_STATUS(port), mask);
511 void qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset,
514 struct qca8k_priv *priv = ds->priv;
517 if (stringset != ETH_SS_STATS)
520 for (i = 0; i < priv->info->mib_count; i++)
521 strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name,
525 void qca8k_get_ethtool_stats(struct dsa_switch *ds, int port,
528 struct qca8k_priv *priv = ds->priv;
529 const struct qca8k_mib_desc *mib;
534 if (priv->mgmt_master && priv->info->ops->autocast_mib &&
535 priv->info->ops->autocast_mib(ds, port, data) > 0)
538 for (i = 0; i < priv->info->mib_count; i++) {
539 mib = &ar8327_mib[i];
540 reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset;
542 ret = qca8k_read(priv, reg, &val);
546 if (mib->size == 2) {
547 ret = qca8k_read(priv, reg + 4, &hi);
554 data[i] |= (u64)hi << 32;
558 int qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset)
560 struct qca8k_priv *priv = ds->priv;
562 if (sset != ETH_SS_STATS)
565 return priv->info->mib_count;
568 int qca8k_set_mac_eee(struct dsa_switch *ds, int port,
569 struct ethtool_eee *eee)
571 u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port);
572 struct qca8k_priv *priv = ds->priv;
576 mutex_lock(&priv->reg_mutex);
577 ret = qca8k_read(priv, QCA8K_REG_EEE_CTRL, ®);
581 if (eee->eee_enabled)
585 ret = qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);
588 mutex_unlock(&priv->reg_mutex);
592 int qca8k_get_mac_eee(struct dsa_switch *ds, int port,
593 struct ethtool_eee *e)
595 /* Nothing to do on the port's MAC */
599 void qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
601 struct qca8k_priv *priv = ds->priv;
605 case BR_STATE_DISABLED:
606 stp_state = QCA8K_PORT_LOOKUP_STATE_DISABLED;
608 case BR_STATE_BLOCKING:
609 stp_state = QCA8K_PORT_LOOKUP_STATE_BLOCKING;
611 case BR_STATE_LISTENING:
612 stp_state = QCA8K_PORT_LOOKUP_STATE_LISTENING;
614 case BR_STATE_LEARNING:
615 stp_state = QCA8K_PORT_LOOKUP_STATE_LEARNING;
617 case BR_STATE_FORWARDING:
619 stp_state = QCA8K_PORT_LOOKUP_STATE_FORWARD;
623 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
624 QCA8K_PORT_LOOKUP_STATE_MASK, stp_state);
627 int qca8k_port_bridge_join(struct dsa_switch *ds, int port,
628 struct dsa_bridge bridge,
629 bool *tx_fwd_offload,
630 struct netlink_ext_ack *extack)
632 struct qca8k_priv *priv = ds->priv;
633 int port_mask, cpu_port;
636 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
637 port_mask = BIT(cpu_port);
639 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
640 if (dsa_is_cpu_port(ds, i))
642 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
644 /* Add this port to the portvlan mask of the other ports
647 ret = regmap_set_bits(priv->regmap,
648 QCA8K_PORT_LOOKUP_CTRL(i),
656 /* Add all other ports to this ports portvlan mask */
657 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
658 QCA8K_PORT_LOOKUP_MEMBER, port_mask);
663 void qca8k_port_bridge_leave(struct dsa_switch *ds, int port,
664 struct dsa_bridge bridge)
666 struct qca8k_priv *priv = ds->priv;
669 cpu_port = dsa_to_port(ds, port)->cpu_dp->index;
671 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
672 if (dsa_is_cpu_port(ds, i))
674 if (!dsa_port_offloads_bridge(dsa_to_port(ds, i), &bridge))
676 /* Remove this port to the portvlan mask of the other ports
679 regmap_clear_bits(priv->regmap,
680 QCA8K_PORT_LOOKUP_CTRL(i),
684 /* Set the cpu port to be the only one in the portvlan mask of
687 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
688 QCA8K_PORT_LOOKUP_MEMBER, BIT(cpu_port));
691 void qca8k_port_fast_age(struct dsa_switch *ds, int port)
693 struct qca8k_priv *priv = ds->priv;
695 mutex_lock(&priv->reg_mutex);
696 qca8k_fdb_access(priv, QCA8K_FDB_FLUSH_PORT, port);
697 mutex_unlock(&priv->reg_mutex);
700 int qca8k_set_ageing_time(struct dsa_switch *ds, unsigned int msecs)
702 struct qca8k_priv *priv = ds->priv;
703 unsigned int secs = msecs / 1000;
706 /* AGE_TIME reg is set in 7s step */
709 /* Handle case with 0 as val to NOT disable
715 return regmap_update_bits(priv->regmap, QCA8K_REG_ATU_CTRL,
716 QCA8K_ATU_AGE_TIME_MASK,
717 QCA8K_ATU_AGE_TIME(val));
720 int qca8k_port_enable(struct dsa_switch *ds, int port,
721 struct phy_device *phy)
723 struct qca8k_priv *priv = ds->priv;
725 qca8k_port_set_status(priv, port, 1);
726 priv->port_enabled_map |= BIT(port);
728 if (dsa_is_user_port(ds, port))
729 phy_support_asym_pause(phy);
734 void qca8k_port_disable(struct dsa_switch *ds, int port)
736 struct qca8k_priv *priv = ds->priv;
738 qca8k_port_set_status(priv, port, 0);
739 priv->port_enabled_map &= ~BIT(port);
742 int qca8k_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
744 struct qca8k_priv *priv = ds->priv;
747 /* We have only have a general MTU setting.
748 * DSA always set the CPU port's MTU to the largest MTU of the slave
750 * Setting MTU just for the CPU port is sufficient to correctly set a
751 * value for every port.
753 if (!dsa_is_cpu_port(ds, port))
756 /* To change the MAX_FRAME_SIZE the cpu ports must be off or
758 * Turn off both cpu ports before applying the new value to prevent
761 if (priv->port_enabled_map & BIT(0))
762 qca8k_port_set_status(priv, 0, 0);
764 if (priv->port_enabled_map & BIT(6))
765 qca8k_port_set_status(priv, 6, 0);
767 /* Include L2 header / FCS length */
768 ret = qca8k_write(priv, QCA8K_MAX_FRAME_SIZE, new_mtu +
769 ETH_HLEN + ETH_FCS_LEN);
771 if (priv->port_enabled_map & BIT(0))
772 qca8k_port_set_status(priv, 0, 1);
774 if (priv->port_enabled_map & BIT(6))
775 qca8k_port_set_status(priv, 6, 1);
780 int qca8k_port_max_mtu(struct dsa_switch *ds, int port)
782 return QCA8K_MAX_MTU;
785 int qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr,
786 u16 port_mask, u16 vid)
788 /* Set the vid to the port vlan id if no vid is set */
790 vid = QCA8K_PORT_VID_DEF;
792 return qca8k_fdb_add(priv, addr, port_mask, vid,
793 QCA8K_ATU_STATUS_STATIC);
796 int qca8k_port_fdb_add(struct dsa_switch *ds, int port,
797 const unsigned char *addr, u16 vid,
800 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
801 u16 port_mask = BIT(port);
803 return qca8k_port_fdb_insert(priv, addr, port_mask, vid);
806 int qca8k_port_fdb_del(struct dsa_switch *ds, int port,
807 const unsigned char *addr, u16 vid,
810 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
811 u16 port_mask = BIT(port);
814 vid = QCA8K_PORT_VID_DEF;
816 return qca8k_fdb_del(priv, addr, port_mask, vid);
819 int qca8k_port_fdb_dump(struct dsa_switch *ds, int port,
820 dsa_fdb_dump_cb_t *cb, void *data)
822 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
823 struct qca8k_fdb _fdb = { 0 };
824 int cnt = QCA8K_NUM_FDB_RECORDS;
828 mutex_lock(&priv->reg_mutex);
829 while (cnt-- && !qca8k_fdb_next(priv, &_fdb, port)) {
832 is_static = (_fdb.aging == QCA8K_ATU_STATUS_STATIC);
833 ret = cb(_fdb.mac, _fdb.vid, is_static, data);
837 mutex_unlock(&priv->reg_mutex);
842 int qca8k_port_mdb_add(struct dsa_switch *ds, int port,
843 const struct switchdev_obj_port_mdb *mdb,
846 struct qca8k_priv *priv = ds->priv;
847 const u8 *addr = mdb->addr;
850 return qca8k_fdb_search_and_insert(priv, BIT(port), addr, vid);
853 int qca8k_port_mdb_del(struct dsa_switch *ds, int port,
854 const struct switchdev_obj_port_mdb *mdb,
857 struct qca8k_priv *priv = ds->priv;
858 const u8 *addr = mdb->addr;
861 return qca8k_fdb_search_and_del(priv, BIT(port), addr, vid);
864 int qca8k_port_mirror_add(struct dsa_switch *ds, int port,
865 struct dsa_mall_mirror_tc_entry *mirror,
866 bool ingress, struct netlink_ext_ack *extack)
868 struct qca8k_priv *priv = ds->priv;
869 int monitor_port, ret;
872 /* Check for existent entry */
873 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port))
876 ret = regmap_read(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0, &val);
880 /* QCA83xx can have only one port set to mirror mode.
881 * Check that the correct port is requested and return error otherwise.
882 * When no mirror port is set, the values is set to 0xF
884 monitor_port = FIELD_GET(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val);
885 if (monitor_port != 0xF && monitor_port != mirror->to_local_port)
888 /* Set the monitor port */
889 val = FIELD_PREP(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM,
890 mirror->to_local_port);
891 ret = regmap_update_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,
892 QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val);
897 reg = QCA8K_PORT_LOOKUP_CTRL(port);
898 val = QCA8K_PORT_LOOKUP_ING_MIRROR_EN;
900 reg = QCA8K_REG_PORT_HOL_CTRL1(port);
901 val = QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN;
904 ret = regmap_update_bits(priv->regmap, reg, val, val);
908 /* Track mirror port for tx and rx to decide when the
909 * mirror port has to be disabled.
912 priv->mirror_rx |= BIT(port);
914 priv->mirror_tx |= BIT(port);
919 void qca8k_port_mirror_del(struct dsa_switch *ds, int port,
920 struct dsa_mall_mirror_tc_entry *mirror)
922 struct qca8k_priv *priv = ds->priv;
926 if (mirror->ingress) {
927 reg = QCA8K_PORT_LOOKUP_CTRL(port);
928 val = QCA8K_PORT_LOOKUP_ING_MIRROR_EN;
930 reg = QCA8K_REG_PORT_HOL_CTRL1(port);
931 val = QCA8K_PORT_HOL_CTRL1_EG_MIRROR_EN;
934 ret = regmap_clear_bits(priv->regmap, reg, val);
939 priv->mirror_rx &= ~BIT(port);
941 priv->mirror_tx &= ~BIT(port);
943 /* No port set to send packet to mirror port. Disable mirror port */
944 if (!priv->mirror_rx && !priv->mirror_tx) {
945 val = FIELD_PREP(QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, 0xF);
946 ret = regmap_update_bits(priv->regmap, QCA8K_REG_GLOBAL_FW_CTRL0,
947 QCA8K_GLOBAL_FW_CTRL0_MIRROR_PORT_NUM, val);
952 dev_err(priv->dev, "Failed to del mirror port from %d", port);
955 int qca8k_port_vlan_filtering(struct dsa_switch *ds, int port,
957 struct netlink_ext_ack *extack)
959 struct qca8k_priv *priv = ds->priv;
962 if (vlan_filtering) {
963 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
964 QCA8K_PORT_LOOKUP_VLAN_MODE_MASK,
965 QCA8K_PORT_LOOKUP_VLAN_MODE_SECURE);
967 ret = qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
968 QCA8K_PORT_LOOKUP_VLAN_MODE_MASK,
969 QCA8K_PORT_LOOKUP_VLAN_MODE_NONE);
975 int qca8k_port_vlan_add(struct dsa_switch *ds, int port,
976 const struct switchdev_obj_port_vlan *vlan,
977 struct netlink_ext_ack *extack)
979 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
980 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
981 struct qca8k_priv *priv = ds->priv;
984 ret = qca8k_vlan_add(priv, port, vlan->vid, untagged);
986 dev_err(priv->dev, "Failed to add VLAN to port %d (%d)", port, ret);
991 ret = qca8k_rmw(priv, QCA8K_EGRESS_VLAN(port),
992 QCA8K_EGREES_VLAN_PORT_MASK(port),
993 QCA8K_EGREES_VLAN_PORT(port, vlan->vid));
997 ret = qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(port),
998 QCA8K_PORT_VLAN_CVID(vlan->vid) |
999 QCA8K_PORT_VLAN_SVID(vlan->vid));
1005 int qca8k_port_vlan_del(struct dsa_switch *ds, int port,
1006 const struct switchdev_obj_port_vlan *vlan)
1008 struct qca8k_priv *priv = ds->priv;
1011 ret = qca8k_vlan_del(priv, port, vlan->vid);
1013 dev_err(priv->dev, "Failed to delete VLAN from port %d (%d)", port, ret);
1018 static bool qca8k_lag_can_offload(struct dsa_switch *ds,
1020 struct netdev_lag_upper_info *info)
1022 struct dsa_port *dp;
1028 dsa_lag_foreach_port(dp, ds->dst, &lag)
1029 /* Includes the port joining the LAG */
1032 if (members > QCA8K_NUM_PORTS_FOR_LAG)
1035 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH)
1038 if (info->hash_type != NETDEV_LAG_HASH_L2 &&
1039 info->hash_type != NETDEV_LAG_HASH_L23)
1045 static int qca8k_lag_setup_hash(struct dsa_switch *ds,
1047 struct netdev_lag_upper_info *info)
1049 struct net_device *lag_dev = lag.dev;
1050 struct qca8k_priv *priv = ds->priv;
1051 bool unique_lag = true;
1055 switch (info->hash_type) {
1056 case NETDEV_LAG_HASH_L23:
1057 hash |= QCA8K_TRUNK_HASH_SIP_EN;
1058 hash |= QCA8K_TRUNK_HASH_DIP_EN;
1060 case NETDEV_LAG_HASH_L2:
1061 hash |= QCA8K_TRUNK_HASH_SA_EN;
1062 hash |= QCA8K_TRUNK_HASH_DA_EN;
1064 default: /* We should NEVER reach this */
1068 /* Check if we are the unique configured LAG */
1069 dsa_lags_foreach_id(i, ds->dst)
1070 if (i != lag.id && dsa_lag_by_id(ds->dst, i)) {
1075 /* Hash Mode is global. Make sure the same Hash Mode
1076 * is set to all the 4 possible lag.
1077 * If we are the unique LAG we can set whatever hash
1079 * To change hash mode it's needed to remove all LAG
1080 * and change the mode with the latest.
1083 priv->lag_hash_mode = hash;
1084 } else if (priv->lag_hash_mode != hash) {
1085 netdev_err(lag_dev, "Error: Mismatched Hash Mode across different lag is not supported\n");
1089 return regmap_update_bits(priv->regmap, QCA8K_TRUNK_HASH_EN_CTRL,
1090 QCA8K_TRUNK_HASH_MASK, hash);
1093 static int qca8k_lag_refresh_portmap(struct dsa_switch *ds, int port,
1094 struct dsa_lag lag, bool delete)
1096 struct qca8k_priv *priv = ds->priv;
1100 /* DSA LAG IDs are one-based, hardware is zero-based */
1103 /* Read current port member */
1104 ret = regmap_read(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL0, &val);
1108 /* Shift val to the correct trunk */
1109 val >>= QCA8K_REG_GOL_TRUNK_SHIFT(id);
1110 val &= QCA8K_REG_GOL_TRUNK_MEMBER_MASK;
1116 /* Update port member. With empty portmap disable trunk */
1117 ret = regmap_update_bits(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL0,
1118 QCA8K_REG_GOL_TRUNK_MEMBER(id) |
1119 QCA8K_REG_GOL_TRUNK_EN(id),
1120 !val << QCA8K_REG_GOL_TRUNK_SHIFT(id) |
1121 val << QCA8K_REG_GOL_TRUNK_SHIFT(id));
1123 /* Search empty member if adding or port on deleting */
1124 for (i = 0; i < QCA8K_NUM_PORTS_FOR_LAG; i++) {
1125 ret = regmap_read(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL(id), &val);
1129 val >>= QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i);
1130 val &= QCA8K_REG_GOL_TRUNK_ID_MEM_ID_MASK;
1133 /* If port flagged to be disabled assume this member is
1136 if (val != QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK)
1139 val &= QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT_MASK;
1143 /* If port flagged to be enabled assume this member is
1146 if (val == QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN_MASK)
1150 /* We have found the member to add/remove */
1154 /* Set port in the correct port mask or disable port if in delete mode */
1155 return regmap_update_bits(priv->regmap, QCA8K_REG_GOL_TRUNK_CTRL(id),
1156 QCA8K_REG_GOL_TRUNK_ID_MEM_ID_EN(id, i) |
1157 QCA8K_REG_GOL_TRUNK_ID_MEM_ID_PORT(id, i),
1158 !delete << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i) |
1159 port << QCA8K_REG_GOL_TRUNK_ID_MEM_ID_SHIFT(id, i));
1162 int qca8k_port_lag_join(struct dsa_switch *ds, int port, struct dsa_lag lag,
1163 struct netdev_lag_upper_info *info)
1167 if (!qca8k_lag_can_offload(ds, lag, info))
1170 ret = qca8k_lag_setup_hash(ds, lag, info);
1174 return qca8k_lag_refresh_portmap(ds, port, lag, false);
1177 int qca8k_port_lag_leave(struct dsa_switch *ds, int port,
1180 return qca8k_lag_refresh_portmap(ds, port, lag, true);
1183 int qca8k_read_switch_id(struct qca8k_priv *priv)
1192 ret = qca8k_read(priv, QCA8K_REG_MASK_CTRL, &val);
1196 id = QCA8K_MASK_CTRL_DEVICE_ID(val);
1197 if (id != priv->info->id) {
1199 "Switch id detected %x but expected %x",
1200 id, priv->info->id);
1204 priv->switch_id = id;
1206 /* Save revision to communicate to the internal PHY driver */
1207 priv->switch_revision = QCA8K_MASK_CTRL_REV_ID(val);