1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
3 * Copyright (c) 2013-2020, Mellanox Technologies inc. All rights reserved.
4 * Copyright (c) 2020, Intel Corporation. All rights reserved.
10 #include <linux/kernel.h>
11 #include <linux/sched.h>
12 #include <rdma/ib_verbs.h>
13 #include <rdma/ib_umem.h>
14 #include <rdma/ib_smi.h>
15 #include <linux/mlx5/driver.h>
16 #include <linux/mlx5/cq.h>
17 #include <linux/mlx5/fs.h>
18 #include <linux/mlx5/qp.h>
19 #include <linux/types.h>
20 #include <linux/mlx5/transobj.h>
21 #include <rdma/ib_user_verbs.h>
22 #include <rdma/mlx5-abi.h>
23 #include <rdma/uverbs_ioctl.h>
24 #include <rdma/mlx5_user_ioctl_cmds.h>
25 #include <rdma/mlx5_user_ioctl_verbs.h>
29 #define mlx5_ib_dbg(_dev, format, arg...) \
30 dev_dbg(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \
31 __LINE__, current->pid, ##arg)
33 #define mlx5_ib_err(_dev, format, arg...) \
34 dev_err(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \
35 __LINE__, current->pid, ##arg)
37 #define mlx5_ib_warn(_dev, format, arg...) \
38 dev_warn(&(_dev)->ib_dev.dev, "%s:%d:(pid %d): " format, __func__, \
39 __LINE__, current->pid, ##arg)
41 #define MLX5_IB_DEFAULT_UIDX 0xffffff
42 #define MLX5_USER_ASSIGNED_UIDX_MASK __mlx5_mask(qpc, user_index)
44 static __always_inline unsigned long
45 __mlx5_log_page_size_to_bitmap(unsigned int log_pgsz_bits,
46 unsigned int pgsz_shift)
48 unsigned int largest_pg_shift =
49 min_t(unsigned long, (1ULL << log_pgsz_bits) - 1 + pgsz_shift,
53 * Despite a command allowing it, the device does not support lower than
56 pgsz_shift = max_t(unsigned int, MLX5_ADAPTER_PAGE_SHIFT, pgsz_shift);
57 return GENMASK(largest_pg_shift, pgsz_shift);
61 * For mkc users, instead of a page_offset the command has a start_iova which
62 * specifies both the page_offset and the on-the-wire IOVA
64 #define mlx5_umem_find_best_pgsz(umem, typ, log_pgsz_fld, pgsz_shift, iova) \
65 ib_umem_find_best_pgsz(umem, \
66 __mlx5_log_page_size_to_bitmap( \
67 __mlx5_bit_sz(typ, log_pgsz_fld), \
71 static __always_inline unsigned long
72 __mlx5_page_offset_to_bitmask(unsigned int page_offset_bits,
73 unsigned int offset_shift)
75 unsigned int largest_offset_shift =
76 min_t(unsigned long, page_offset_bits - 1 + offset_shift,
79 return GENMASK(largest_offset_shift, offset_shift);
83 * QP/CQ/WQ/etc type commands take a page offset that satisifies:
84 * page_offset_quantized * (page_size/scale) = page_offset
85 * Which restricts allowed page sizes to ones that satisify the above.
87 unsigned long __mlx5_umem_find_best_quantized_pgoff(
88 struct ib_umem *umem, unsigned long pgsz_bitmap,
89 unsigned int page_offset_bits, u64 pgoff_bitmask, unsigned int scale,
90 unsigned int *page_offset_quantized);
91 #define mlx5_umem_find_best_quantized_pgoff(umem, typ, log_pgsz_fld, \
92 pgsz_shift, page_offset_fld, \
93 scale, page_offset_quantized) \
94 __mlx5_umem_find_best_quantized_pgoff( \
96 __mlx5_log_page_size_to_bitmap( \
97 __mlx5_bit_sz(typ, log_pgsz_fld), pgsz_shift), \
98 __mlx5_bit_sz(typ, page_offset_fld), \
99 GENMASK(31, order_base_2(scale)), scale, \
100 page_offset_quantized)
102 #define mlx5_umem_find_best_cq_quantized_pgoff(umem, typ, log_pgsz_fld, \
103 pgsz_shift, page_offset_fld, \
104 scale, page_offset_quantized) \
105 __mlx5_umem_find_best_quantized_pgoff( \
107 __mlx5_log_page_size_to_bitmap( \
108 __mlx5_bit_sz(typ, log_pgsz_fld), pgsz_shift), \
109 __mlx5_bit_sz(typ, page_offset_fld), 0, scale, \
110 page_offset_quantized)
113 MLX5_IB_MMAP_OFFSET_START = 9,
114 MLX5_IB_MMAP_OFFSET_END = 255,
118 MLX5_IB_MMAP_CMD_SHIFT = 8,
119 MLX5_IB_MMAP_CMD_MASK = 0xff,
123 MLX5_RES_SCAT_DATA32_CQE = 0x1,
124 MLX5_RES_SCAT_DATA64_CQE = 0x2,
125 MLX5_REQ_SCAT_DATA32_CQE = 0x11,
126 MLX5_REQ_SCAT_DATA64_CQE = 0x22,
129 enum mlx5_ib_mad_ifc_flags {
130 MLX5_MAD_IFC_IGNORE_MKEY = 1,
131 MLX5_MAD_IFC_IGNORE_BKEY = 2,
132 MLX5_MAD_IFC_NET_VIEW = 4,
136 MLX5_CROSS_CHANNEL_BFREG = 0,
145 MLX5_TM_MAX_RNDV_MSG_SIZE = 64,
150 MLX5_IB_INVALID_UAR_INDEX = BIT(31),
151 MLX5_IB_INVALID_BFREG = BIT(31),
155 MLX5_MAX_MEMIC_PAGES = 0x100,
156 MLX5_MEMIC_ALLOC_SIZE_MASK = 0x3f,
160 MLX5_MEMIC_BASE_ALIGN = 6,
161 MLX5_MEMIC_BASE_SIZE = 1 << MLX5_MEMIC_BASE_ALIGN,
164 enum mlx5_ib_mmap_type {
165 MLX5_IB_MMAP_TYPE_MEMIC = 1,
166 MLX5_IB_MMAP_TYPE_VAR = 2,
167 MLX5_IB_MMAP_TYPE_UAR_WC = 3,
168 MLX5_IB_MMAP_TYPE_UAR_NC = 4,
169 MLX5_IB_MMAP_TYPE_MEMIC_OP = 5,
172 struct mlx5_bfreg_info {
174 int num_low_latency_bfregs;
178 * protect bfreg allocation data structs
185 u32 num_static_sys_pages;
186 u32 total_num_bfregs;
190 struct mlx5_ib_ucontext {
191 struct ib_ucontext ibucontext;
192 struct list_head db_page_list;
194 /* protect doorbell record alloc/free
196 struct mutex db_page_mutex;
197 struct mlx5_bfreg_info bfregi;
199 /* Transport Domain number */
204 /* For RoCE LAG TX affinity */
205 atomic_t tx_port_affinity;
208 static inline struct mlx5_ib_ucontext *to_mucontext(struct ib_ucontext *ibucontext)
210 return container_of(ibucontext, struct mlx5_ib_ucontext, ibucontext);
220 MLX5_IB_FLOW_ACTION_MODIFY_HEADER,
221 MLX5_IB_FLOW_ACTION_PACKET_REFORMAT,
222 MLX5_IB_FLOW_ACTION_DECAP,
225 #define MLX5_IB_FLOW_MCAST_PRIO (MLX5_BY_PASS_NUM_PRIOS - 1)
226 #define MLX5_IB_FLOW_LAST_PRIO (MLX5_BY_PASS_NUM_REGULAR_PRIOS - 1)
227 #if (MLX5_IB_FLOW_LAST_PRIO <= 0)
228 #error "Invalid number of bypass priorities"
230 #define MLX5_IB_FLOW_LEFTOVERS_PRIO (MLX5_IB_FLOW_MCAST_PRIO + 1)
232 #define MLX5_IB_NUM_FLOW_FT (MLX5_IB_FLOW_LEFTOVERS_PRIO + 1)
233 #define MLX5_IB_NUM_SNIFFER_FTS 2
234 #define MLX5_IB_NUM_EGRESS_FTS 1
235 #define MLX5_IB_NUM_FDB_FTS MLX5_BY_PASS_NUM_REGULAR_PRIOS
236 struct mlx5_ib_flow_prio {
237 struct mlx5_flow_table *flow_table;
238 unsigned int refcount;
241 struct mlx5_ib_flow_handler {
242 struct list_head list;
243 struct ib_flow ibflow;
244 struct mlx5_ib_flow_prio *prio;
245 struct mlx5_flow_handle *rule;
246 struct ib_counters *ibcounters;
247 struct mlx5_ib_dev *dev;
248 struct mlx5_ib_flow_matcher *flow_matcher;
251 struct mlx5_ib_flow_matcher {
252 struct mlx5_ib_match_params matcher_mask;
254 enum mlx5_ib_flow_type flow_type;
255 enum mlx5_flow_namespace_type ns_type;
257 struct mlx5_core_dev *mdev;
259 u8 match_criteria_enable;
262 struct mlx5_ib_steering_anchor {
263 struct mlx5_ib_flow_prio *ft_prio;
264 struct mlx5_ib_dev *dev;
270 struct mlx5_core_dev *mdev;
273 enum mlx5_ib_optional_counter_type {
274 MLX5_IB_OPCOUNTER_CC_RX_CE_PKTS,
275 MLX5_IB_OPCOUNTER_CC_RX_CNP_PKTS,
276 MLX5_IB_OPCOUNTER_CC_TX_CNP_PKTS,
278 MLX5_IB_OPCOUNTER_MAX,
281 struct mlx5_ib_flow_db {
282 struct mlx5_ib_flow_prio prios[MLX5_IB_NUM_FLOW_FT];
283 struct mlx5_ib_flow_prio egress_prios[MLX5_IB_NUM_FLOW_FT];
284 struct mlx5_ib_flow_prio sniffer[MLX5_IB_NUM_SNIFFER_FTS];
285 struct mlx5_ib_flow_prio egress[MLX5_IB_NUM_EGRESS_FTS];
286 struct mlx5_ib_flow_prio fdb[MLX5_IB_NUM_FDB_FTS];
287 struct mlx5_ib_flow_prio rdma_rx[MLX5_IB_NUM_FLOW_FT];
288 struct mlx5_ib_flow_prio rdma_tx[MLX5_IB_NUM_FLOW_FT];
289 struct mlx5_ib_flow_prio opfcs[MLX5_IB_OPCOUNTER_MAX];
290 struct mlx5_flow_table *lag_demux_ft;
291 /* Protect flow steering bypass flow tables
292 * when add/del flow rules.
293 * only single add/removal of flow steering rule could be done
299 /* Use macros here so that don't have to duplicate
300 * enum ib_qp_type for low-level driver
303 #define MLX5_IB_QPT_REG_UMR IB_QPT_RESERVED1
305 * IB_QPT_GSI creates the software wrapper around GSI, and MLX5_IB_QPT_HW_GSI
306 * creates the actual hardware QP.
308 #define MLX5_IB_QPT_HW_GSI IB_QPT_RESERVED2
309 #define MLX5_IB_QPT_DCI IB_QPT_RESERVED3
310 #define MLX5_IB_QPT_DCT IB_QPT_RESERVED4
311 #define MLX5_IB_WR_UMR IB_WR_RESERVED1
313 #define MLX5_IB_UPD_XLT_ZAP BIT(0)
314 #define MLX5_IB_UPD_XLT_ENABLE BIT(1)
315 #define MLX5_IB_UPD_XLT_ATOMIC BIT(2)
316 #define MLX5_IB_UPD_XLT_ADDR BIT(3)
317 #define MLX5_IB_UPD_XLT_PD BIT(4)
318 #define MLX5_IB_UPD_XLT_ACCESS BIT(5)
319 #define MLX5_IB_UPD_XLT_INDIRECT BIT(6)
321 /* Private QP creation flags to be passed in ib_qp_init_attr.create_flags.
323 * These flags are intended for internal use by the mlx5_ib driver, and they
324 * rely on the range reserved for that use in the ib_qp_create_flags enum.
326 #define MLX5_IB_QP_CREATE_SQPN_QP1 IB_QP_CREATE_RESERVED_START
327 #define MLX5_IB_QP_CREATE_WC_TEST (IB_QP_CREATE_RESERVED_START << 1)
334 enum mlx5_ib_rq_flags {
335 MLX5_IB_RQ_CVLAN_STRIPPING = 1 << 0,
336 MLX5_IB_RQ_PCI_WRITE_END_PADDING = 1 << 1,
340 struct mlx5_frag_buf_ctrl fbc;
343 struct wr_list *w_list;
347 /* serialize post to the work queue
362 enum mlx5_ib_wq_flags {
363 MLX5_IB_WQ_FLAGS_DELAY_DROP = 0x1,
364 MLX5_IB_WQ_FLAGS_STRIDING_RQ = 0x2,
367 #define MLX5_MIN_SINGLE_WQE_LOG_NUM_STRIDES 9
368 #define MLX5_MAX_SINGLE_WQE_LOG_NUM_STRIDES 16
369 #define MLX5_MIN_SINGLE_STRIDE_LOG_NUM_BYTES 6
370 #define MLX5_MAX_SINGLE_STRIDE_LOG_NUM_BYTES 13
371 #define MLX5_EXT_MIN_SINGLE_WQE_LOG_NUM_STRIDES 3
375 struct mlx5_core_qp core_qp;
382 u32 two_byte_shift_en;
383 u32 single_stride_log_num_of_bytes;
384 struct ib_umem *umem;
386 unsigned int page_shift;
392 u32 create_flags; /* Use enum mlx5_ib_wq_flags */
395 struct mlx5_ib_rwq_ind_table {
396 struct ib_rwq_ind_table ib_rwq_ind_tbl;
401 struct mlx5_ib_ubuffer {
402 struct ib_umem *umem;
407 struct mlx5_ib_qp_base {
408 struct mlx5_ib_qp *container_mibqp;
409 struct mlx5_core_qp mqp;
410 struct mlx5_ib_ubuffer ubuffer;
413 struct mlx5_ib_qp_trans {
414 struct mlx5_ib_qp_base base;
421 struct mlx5_ib_rss_qp {
426 struct mlx5_ib_qp_base base;
427 struct mlx5_ib_wq *rq;
428 struct mlx5_ib_ubuffer ubuffer;
429 struct mlx5_db *doorbell;
436 struct mlx5_ib_qp_base base;
437 struct mlx5_ib_wq *sq;
438 struct mlx5_ib_ubuffer ubuffer;
439 struct mlx5_db *doorbell;
440 struct mlx5_flow_handle *flow_rule;
445 struct mlx5_ib_raw_packet_qp {
446 struct mlx5_ib_sq sq;
447 struct mlx5_ib_rq rq;
452 unsigned long offset;
453 struct mlx5_sq_bfreg *bfreg;
457 struct mlx5_core_dct mdct;
461 struct mlx5_ib_gsi_qp {
464 struct ib_qp_cap cap;
466 struct mlx5_ib_gsi_wr *outstanding_wrs;
467 u32 outstanding_pi, outstanding_ci;
469 /* Protects access to the tx_qps. Post send operations synchronize
470 * with tx_qp creation in setup_qp(). Also protects the
471 * outstanding_wrs array and indices.
474 struct ib_qp **tx_qps;
480 struct mlx5_ib_qp_trans trans_qp;
481 struct mlx5_ib_raw_packet_qp raw_packet_qp;
482 struct mlx5_ib_rss_qp rss_qp;
483 struct mlx5_ib_dct dct;
484 struct mlx5_ib_gsi_qp gsi;
486 struct mlx5_frag_buf buf;
489 struct mlx5_ib_wq rq;
493 struct mlx5_ib_wq sq;
495 /* serialize qp state modifications
498 /* cached variant of create_flags from struct ib_qp_init_attr */
507 /* only for user space QPs. For kernel
508 * we have it from the bf object
512 struct list_head qps_list;
513 struct list_head cq_recv_list;
514 struct list_head cq_send_list;
515 struct mlx5_rate_limit rl;
519 * IB/core doesn't store low-level QP types, so
520 * store both MLX and IBTA types in the field below.
522 enum ib_qp_type type;
523 /* A flag to indicate if there's a new counter is configured
524 * but not take effective
530 struct mlx5_ib_cq_buf {
531 struct mlx5_frag_buf_ctrl fbc;
532 struct mlx5_frag_buf frag_buf;
533 struct ib_umem *umem;
538 enum mlx5_ib_cq_pr_flags {
539 MLX5_IB_CQ_PR_FLAGS_CQE_128_PAD = 1 << 0,
540 MLX5_IB_CQ_PR_FLAGS_REAL_TIME_TS = 1 << 1,
545 struct mlx5_core_cq mcq;
546 struct mlx5_ib_cq_buf buf;
549 /* serialize access to the CQ
555 struct mutex resize_mutex;
556 struct mlx5_ib_cq_buf *resize_buf;
557 struct ib_umem *resize_umem;
559 struct list_head list_send_qp;
560 struct list_head list_recv_qp;
562 struct list_head wc_list;
563 enum ib_cq_notify_flags notify_flags;
564 struct work_struct notify_work;
565 u16 private_flags; /* Use mlx5_ib_cq_pr_flags */
570 struct list_head list;
575 struct mlx5_core_srq msrq;
576 struct mlx5_frag_buf buf;
578 struct mlx5_frag_buf_ctrl fbc;
580 /* protect SRQ hanlding
586 struct ib_umem *umem;
587 /* serialize arming a SRQ
593 struct mlx5_ib_xrcd {
594 struct ib_xrcd ibxrcd;
598 enum mlx5_ib_mtt_access_flags {
599 MLX5_IB_MTT_READ = (1 << 0),
600 MLX5_IB_MTT_WRITE = (1 << 1),
603 struct mlx5_user_mmap_entry {
604 struct rdma_user_mmap_entry rdma_entry;
610 enum mlx5_mkey_type {
613 MLX5_MKEY_INDIRECT_DEVX,
616 struct mlx5_ib_mkey {
618 enum mlx5_mkey_type type;
620 struct wait_queue_head wait;
622 struct mlx5_cache_ent *cache_ent;
625 #define MLX5_IB_MTT_PRESENT (MLX5_IB_MTT_READ | MLX5_IB_MTT_WRITE)
627 #define MLX5_IB_DM_MEMIC_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\
628 IB_ACCESS_REMOTE_WRITE |\
629 IB_ACCESS_REMOTE_READ |\
630 IB_ACCESS_REMOTE_ATOMIC |\
633 #define MLX5_IB_DM_SW_ICM_ALLOWED_ACCESS (IB_ACCESS_LOCAL_WRITE |\
634 IB_ACCESS_REMOTE_WRITE |\
635 IB_ACCESS_REMOTE_READ |\
638 #define mlx5_update_odp_stats(mr, counter_name, value) \
639 atomic64_add(value, &((mr)->odp_stats.counter_name))
643 struct mlx5_ib_mkey mmkey;
645 struct ib_umem *umem;
648 /* Used only by kernel MRs (umem == NULL) */
657 /* For Kernel IB_MR_TYPE_INTEGRITY */
658 struct mlx5_core_sig_ctx *sig;
659 struct mlx5_ib_mr *pi_mr;
660 struct mlx5_ib_mr *klm_mr;
661 struct mlx5_ib_mr *mtt_mr;
669 /* Used only by User MRs (umem != NULL) */
671 unsigned int page_shift;
672 /* Current access_flags */
676 struct mlx5_ib_mr *parent;
677 struct xarray implicit_children;
679 struct work_struct work;
681 struct ib_odp_counters odp_stats;
682 bool is_odp_implicit;
687 static inline bool is_odp_mr(struct mlx5_ib_mr *mr)
689 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem &&
693 static inline bool is_dmabuf_mr(struct mlx5_ib_mr *mr)
695 return IS_ENABLED(CONFIG_INFINIBAND_ON_DEMAND_PAGING) && mr->umem &&
701 struct mlx5_ib_mkey mmkey;
704 struct mlx5_ib_umr_context {
706 enum ib_wc_status status;
707 struct completion done;
711 MLX5_UMR_STATE_ACTIVE,
712 MLX5_UMR_STATE_RECOVER,
720 /* Protects from UMR QP overflow
722 struct semaphore sem;
723 /* Protects from using UMR while the UMR is not active
729 struct mlx5_cache_ent {
731 unsigned long stored;
732 unsigned long reserved;
741 u8 fill_to_high_water:1;
744 * - limit is the low water mark for stored mkeys, 2* limit is the
753 struct mlx5_ib_dev *dev;
754 struct delayed_work dwork;
757 struct mlx5r_async_create_mkey {
759 u32 in[MLX5_ST_SZ_BYTES(create_mkey_in)];
760 u32 out[MLX5_ST_SZ_DW(create_mkey_out)];
762 struct mlx5_async_work cb_work;
763 struct mlx5_cache_ent *ent;
767 struct mlx5_mkey_cache {
768 struct workqueue_struct *wq;
769 struct mlx5_cache_ent ent[MAX_MKEY_CACHE_ENTRIES];
771 unsigned long last_add;
774 struct mlx5_ib_port_resources {
775 struct mlx5_ib_gsi_qp *gsi;
776 struct work_struct pkey_change_work;
779 struct mlx5_ib_resources {
786 struct mlx5_ib_port_resources ports[2];
789 #define MAX_OPFC_RULES 2
791 struct mlx5_ib_op_fc {
793 struct mlx5_flow_handle *rule[MAX_OPFC_RULES];
796 struct mlx5_ib_counters {
797 struct rdma_stat_desc *descs;
800 u32 num_cong_counters;
801 u32 num_ext_ppcnt_counters;
804 struct mlx5_ib_op_fc opfcs[MLX5_IB_OPCOUNTER_MAX];
807 int mlx5_ib_fs_add_op_fc(struct mlx5_ib_dev *dev, u32 port_num,
808 struct mlx5_ib_op_fc *opfc,
809 enum mlx5_ib_optional_counter_type type);
811 void mlx5_ib_fs_remove_op_fc(struct mlx5_ib_dev *dev,
812 struct mlx5_ib_op_fc *opfc,
813 enum mlx5_ib_optional_counter_type type);
815 struct mlx5_ib_multiport_info;
817 struct mlx5_ib_multiport {
818 struct mlx5_ib_multiport_info *mpi;
819 /* To be held when accessing the multiport info */
824 /* Protect mlx5_ib_get_netdev from invoking dev_hold() with a NULL
827 rwlock_t netdev_lock;
828 struct net_device *netdev;
829 struct notifier_block nb;
830 atomic_t tx_port_affinity;
831 enum ib_port_state last_port_state;
832 struct mlx5_ib_dev *dev;
836 struct mlx5_ib_port {
837 struct mlx5_ib_counters cnts;
838 struct mlx5_ib_multiport mp;
839 struct mlx5_ib_dbg_cc_params *dbg_cc_params;
840 struct mlx5_roce roce;
841 struct mlx5_eswitch_rep *rep;
844 struct mlx5_ib_dbg_param {
846 struct mlx5_ib_dev *dev;
847 struct dentry *dentry;
851 enum mlx5_ib_dbg_cc_types {
852 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE,
853 MLX5_IB_DBG_CC_RP_CLAMP_TGT_RATE_ATI,
854 MLX5_IB_DBG_CC_RP_TIME_RESET,
855 MLX5_IB_DBG_CC_RP_BYTE_RESET,
856 MLX5_IB_DBG_CC_RP_THRESHOLD,
857 MLX5_IB_DBG_CC_RP_AI_RATE,
858 MLX5_IB_DBG_CC_RP_MAX_RATE,
859 MLX5_IB_DBG_CC_RP_HAI_RATE,
860 MLX5_IB_DBG_CC_RP_MIN_DEC_FAC,
861 MLX5_IB_DBG_CC_RP_MIN_RATE,
862 MLX5_IB_DBG_CC_RP_RATE_TO_SET_ON_FIRST_CNP,
863 MLX5_IB_DBG_CC_RP_DCE_TCP_G,
864 MLX5_IB_DBG_CC_RP_DCE_TCP_RTT,
865 MLX5_IB_DBG_CC_RP_RATE_REDUCE_MONITOR_PERIOD,
866 MLX5_IB_DBG_CC_RP_INITIAL_ALPHA_VALUE,
867 MLX5_IB_DBG_CC_RP_GD,
868 MLX5_IB_DBG_CC_NP_MIN_TIME_BETWEEN_CNPS,
869 MLX5_IB_DBG_CC_NP_CNP_DSCP,
870 MLX5_IB_DBG_CC_NP_CNP_PRIO_MODE,
871 MLX5_IB_DBG_CC_NP_CNP_PRIO,
875 struct mlx5_ib_dbg_cc_params {
877 struct mlx5_ib_dbg_param params[MLX5_IB_DBG_CC_MAX];
881 MLX5_MAX_DELAY_DROP_TIMEOUT_MS = 100,
884 struct mlx5_ib_delay_drop {
885 struct mlx5_ib_dev *dev;
886 struct work_struct delay_drop_work;
887 /* serialize setting of delay drop */
893 struct dentry *dir_debugfs;
896 enum mlx5_ib_stages {
900 MLX5_IB_STAGE_NON_DEFAULT_CB,
904 MLX5_IB_STAGE_DEVICE_RESOURCES,
905 MLX5_IB_STAGE_DEVICE_NOTIFIER,
907 MLX5_IB_STAGE_COUNTERS,
908 MLX5_IB_STAGE_CONG_DEBUGFS,
911 MLX5_IB_STAGE_PRE_IB_REG_UMR,
912 MLX5_IB_STAGE_WHITELIST_UID,
913 MLX5_IB_STAGE_IB_REG,
914 MLX5_IB_STAGE_POST_IB_REG_UMR,
915 MLX5_IB_STAGE_DELAY_DROP,
916 MLX5_IB_STAGE_RESTRACK,
920 struct mlx5_ib_stage {
921 int (*init)(struct mlx5_ib_dev *dev);
922 void (*cleanup)(struct mlx5_ib_dev *dev);
925 #define STAGE_CREATE(_stage, _init, _cleanup) \
926 .stage[_stage] = {.init = _init, .cleanup = _cleanup}
928 struct mlx5_ib_profile {
929 struct mlx5_ib_stage stage[MLX5_IB_STAGE_MAX];
932 struct mlx5_ib_multiport_info {
933 struct list_head list;
934 struct mlx5_ib_dev *ibdev;
935 struct mlx5_core_dev *mdev;
936 struct notifier_block mdev_events;
937 struct completion unref_comp;
944 struct mlx5_ib_flow_action {
945 struct ib_flow_action ib_action;
949 struct mlx5_accel_esp_xfrm *ctx;
952 struct mlx5_ib_dev *dev;
955 struct mlx5_modify_hdr *modify_hdr;
956 struct mlx5_pkt_reformat *pkt_reformat;
963 struct mlx5_core_dev *dev;
964 /* This lock is used to protect the access to the shared
965 * allocation map when concurrent requests by different
966 * processes are handled.
969 DECLARE_BITMAP(memic_alloc_pages, MLX5_MAX_MEMIC_PAGES);
972 struct mlx5_read_counters_attr {
973 struct mlx5_fc *hw_cntrs_hndl;
978 enum mlx5_ib_counters_type {
979 MLX5_IB_COUNTERS_FLOW,
982 struct mlx5_ib_mcounters {
983 struct ib_counters ibcntrs;
984 enum mlx5_ib_counters_type type;
985 /* number of counters supported for this counters type */
987 struct mlx5_fc *hw_cntrs_hndl;
988 /* read function for this counters type */
989 int (*read_counters)(struct ib_device *ibdev,
990 struct mlx5_read_counters_attr *read_attr);
991 /* max index set as part of create_flow */
993 /* number of counters data entries (<description,index> pair) */
995 /* counters data array for descriptions and indexes */
996 struct mlx5_ib_flow_counters_desc *counters_data;
997 /* protects access to mcounters internal data */
998 struct mutex mcntrs_mutex;
1001 static inline struct mlx5_ib_mcounters *
1002 to_mcounters(struct ib_counters *ibcntrs)
1004 return container_of(ibcntrs, struct mlx5_ib_mcounters, ibcntrs);
1007 int parse_flow_flow_action(struct mlx5_ib_flow_action *maction,
1009 struct mlx5_flow_act *action);
1010 struct mlx5_ib_lb_state {
1011 /* protect the user_td */
1018 struct mlx5_ib_pf_eq {
1019 struct notifier_block irq_nb;
1020 struct mlx5_ib_dev *dev;
1021 struct mlx5_eq *core;
1022 struct work_struct work;
1023 spinlock_t lock; /* Pagefaults spinlock */
1024 struct workqueue_struct *wq;
1028 struct mlx5_devx_event_table {
1029 struct mlx5_nb devx_nb;
1030 /* serialize updating the event_xa */
1031 struct mutex event_xa_lock;
1032 struct xarray event_xa;
1035 struct mlx5_var_table {
1036 /* serialize updating the bitmap */
1037 struct mutex bitmap_lock;
1038 unsigned long *bitmap;
1041 u64 num_var_hw_entries;
1044 struct mlx5_port_caps {
1049 struct mlx5_ib_dev {
1050 struct ib_device ib_dev;
1051 struct mlx5_core_dev *mdev;
1052 struct notifier_block mdev_events;
1054 /* serialize update of capability mask
1056 struct mutex cap_mask_mutex;
1062 struct umr_common umrc;
1063 /* sync used page count stats
1065 struct mlx5_ib_resources devr;
1068 struct mlx5_mkey_cache cache;
1069 struct timer_list delay_timer;
1070 /* Prevents soft lock on massive reg MRs */
1071 struct mutex slow_path_mutex;
1072 struct ib_odp_caps odp_caps;
1074 struct mutex odp_eq_mutex;
1075 struct mlx5_ib_pf_eq odp_pf_eq;
1077 struct xarray odp_mkeys;
1080 struct mlx5_ib_flow_db *flow_db;
1081 /* protect resources needed as part of reset flow */
1082 spinlock_t reset_flow_resource_lock;
1083 struct list_head qp_list;
1084 /* Array with num_ports elements */
1085 struct mlx5_ib_port *port;
1086 struct mlx5_sq_bfreg bfreg;
1087 struct mlx5_sq_bfreg wc_bfreg;
1088 struct mlx5_sq_bfreg fp_bfreg;
1089 struct mlx5_ib_delay_drop delay_drop;
1090 const struct mlx5_ib_profile *profile;
1092 struct mlx5_ib_lb_state lb;
1094 struct list_head ib_dev_list;
1097 u16 devx_whitelist_uid;
1098 struct mlx5_srq_table srq_table;
1099 struct mlx5_qp_table qp_table;
1100 struct mlx5_async_ctx async_ctx;
1101 struct mlx5_devx_event_table devx_event_table;
1102 struct mlx5_var_table var_table;
1104 struct xarray sig_mrs;
1105 struct mlx5_port_caps port_caps[MLX5_MAX_PORTS];
1110 static inline struct mlx5_ib_cq *to_mibcq(struct mlx5_core_cq *mcq)
1112 return container_of(mcq, struct mlx5_ib_cq, mcq);
1115 static inline struct mlx5_ib_xrcd *to_mxrcd(struct ib_xrcd *ibxrcd)
1117 return container_of(ibxrcd, struct mlx5_ib_xrcd, ibxrcd);
1120 static inline struct mlx5_ib_dev *to_mdev(struct ib_device *ibdev)
1122 return container_of(ibdev, struct mlx5_ib_dev, ib_dev);
1125 static inline struct mlx5_ib_dev *mr_to_mdev(struct mlx5_ib_mr *mr)
1127 return to_mdev(mr->ibmr.device);
1130 static inline struct mlx5_ib_dev *mlx5_udata_to_mdev(struct ib_udata *udata)
1132 struct mlx5_ib_ucontext *context = rdma_udata_to_drv_context(
1133 udata, struct mlx5_ib_ucontext, ibucontext);
1135 return to_mdev(context->ibucontext.device);
1138 static inline struct mlx5_ib_cq *to_mcq(struct ib_cq *ibcq)
1140 return container_of(ibcq, struct mlx5_ib_cq, ibcq);
1143 static inline struct mlx5_ib_qp *to_mibqp(struct mlx5_core_qp *mqp)
1145 return container_of(mqp, struct mlx5_ib_qp_base, mqp)->container_mibqp;
1148 static inline struct mlx5_ib_rwq *to_mibrwq(struct mlx5_core_qp *core_qp)
1150 return container_of(core_qp, struct mlx5_ib_rwq, core_qp);
1153 static inline struct mlx5_ib_pd *to_mpd(struct ib_pd *ibpd)
1155 return container_of(ibpd, struct mlx5_ib_pd, ibpd);
1158 static inline struct mlx5_ib_srq *to_msrq(struct ib_srq *ibsrq)
1160 return container_of(ibsrq, struct mlx5_ib_srq, ibsrq);
1163 static inline struct mlx5_ib_qp *to_mqp(struct ib_qp *ibqp)
1165 return container_of(ibqp, struct mlx5_ib_qp, ibqp);
1168 static inline struct mlx5_ib_rwq *to_mrwq(struct ib_wq *ibwq)
1170 return container_of(ibwq, struct mlx5_ib_rwq, ibwq);
1173 static inline struct mlx5_ib_rwq_ind_table *to_mrwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_tbl)
1175 return container_of(ib_rwq_ind_tbl, struct mlx5_ib_rwq_ind_table, ib_rwq_ind_tbl);
1178 static inline struct mlx5_ib_srq *to_mibsrq(struct mlx5_core_srq *msrq)
1180 return container_of(msrq, struct mlx5_ib_srq, msrq);
1183 static inline struct mlx5_ib_mr *to_mmr(struct ib_mr *ibmr)
1185 return container_of(ibmr, struct mlx5_ib_mr, ibmr);
1188 static inline struct mlx5_ib_mw *to_mmw(struct ib_mw *ibmw)
1190 return container_of(ibmw, struct mlx5_ib_mw, ibmw);
1193 static inline struct mlx5_ib_flow_action *
1194 to_mflow_act(struct ib_flow_action *ibact)
1196 return container_of(ibact, struct mlx5_ib_flow_action, ib_action);
1199 static inline struct mlx5_user_mmap_entry *
1200 to_mmmap(struct rdma_user_mmap_entry *rdma_entry)
1202 return container_of(rdma_entry,
1203 struct mlx5_user_mmap_entry, rdma_entry);
1206 int mlx5_ib_db_map_user(struct mlx5_ib_ucontext *context, unsigned long virt,
1207 struct mlx5_db *db);
1208 void mlx5_ib_db_unmap_user(struct mlx5_ib_ucontext *context, struct mlx5_db *db);
1209 void __mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
1210 void mlx5_ib_cq_clean(struct mlx5_ib_cq *cq, u32 qpn, struct mlx5_ib_srq *srq);
1211 void mlx5_ib_free_srq_wqe(struct mlx5_ib_srq *srq, int wqe_index);
1212 int mlx5_ib_create_ah(struct ib_ah *ah, struct rdma_ah_init_attr *init_attr,
1213 struct ib_udata *udata);
1214 int mlx5_ib_query_ah(struct ib_ah *ibah, struct rdma_ah_attr *ah_attr);
1215 static inline int mlx5_ib_destroy_ah(struct ib_ah *ah, u32 flags)
1219 int mlx5_ib_create_srq(struct ib_srq *srq, struct ib_srq_init_attr *init_attr,
1220 struct ib_udata *udata);
1221 int mlx5_ib_modify_srq(struct ib_srq *ibsrq, struct ib_srq_attr *attr,
1222 enum ib_srq_attr_mask attr_mask, struct ib_udata *udata);
1223 int mlx5_ib_query_srq(struct ib_srq *ibsrq, struct ib_srq_attr *srq_attr);
1224 int mlx5_ib_destroy_srq(struct ib_srq *srq, struct ib_udata *udata);
1225 int mlx5_ib_post_srq_recv(struct ib_srq *ibsrq, const struct ib_recv_wr *wr,
1226 const struct ib_recv_wr **bad_wr);
1227 int mlx5_ib_enable_lb(struct mlx5_ib_dev *dev, bool td, bool qp);
1228 void mlx5_ib_disable_lb(struct mlx5_ib_dev *dev, bool td, bool qp);
1229 int mlx5_ib_create_qp(struct ib_qp *qp, struct ib_qp_init_attr *init_attr,
1230 struct ib_udata *udata);
1231 int mlx5_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
1232 int attr_mask, struct ib_udata *udata);
1233 int mlx5_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *qp_attr, int qp_attr_mask,
1234 struct ib_qp_init_attr *qp_init_attr);
1235 int mlx5_ib_destroy_qp(struct ib_qp *qp, struct ib_udata *udata);
1236 void mlx5_ib_drain_sq(struct ib_qp *qp);
1237 void mlx5_ib_drain_rq(struct ib_qp *qp);
1238 int mlx5_ib_read_wqe_sq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
1239 size_t buflen, size_t *bc);
1240 int mlx5_ib_read_wqe_rq(struct mlx5_ib_qp *qp, int wqe_index, void *buffer,
1241 size_t buflen, size_t *bc);
1242 int mlx5_ib_read_wqe_srq(struct mlx5_ib_srq *srq, int wqe_index, void *buffer,
1243 size_t buflen, size_t *bc);
1244 int mlx5_ib_create_cq(struct ib_cq *ibcq, const struct ib_cq_init_attr *attr,
1245 struct ib_udata *udata);
1246 int mlx5_ib_destroy_cq(struct ib_cq *cq, struct ib_udata *udata);
1247 int mlx5_ib_poll_cq(struct ib_cq *ibcq, int num_entries, struct ib_wc *wc);
1248 int mlx5_ib_arm_cq(struct ib_cq *ibcq, enum ib_cq_notify_flags flags);
1249 int mlx5_ib_modify_cq(struct ib_cq *cq, u16 cq_count, u16 cq_period);
1250 int mlx5_ib_resize_cq(struct ib_cq *ibcq, int entries, struct ib_udata *udata);
1251 struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc);
1252 struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
1253 u64 virt_addr, int access_flags,
1254 struct ib_udata *udata);
1255 struct ib_mr *mlx5_ib_reg_user_mr_dmabuf(struct ib_pd *pd, u64 start,
1256 u64 length, u64 virt_addr,
1257 int fd, int access_flags,
1258 struct ib_udata *udata);
1259 int mlx5_ib_advise_mr(struct ib_pd *pd,
1260 enum ib_uverbs_advise_mr_advice advice,
1262 struct ib_sge *sg_list,
1264 struct uverbs_attr_bundle *attrs);
1265 int mlx5_ib_alloc_mw(struct ib_mw *mw, struct ib_udata *udata);
1266 int mlx5_ib_dealloc_mw(struct ib_mw *mw);
1267 struct mlx5_ib_mr *mlx5_ib_alloc_implicit_mr(struct mlx5_ib_pd *pd,
1269 void mlx5_ib_free_implicit_mr(struct mlx5_ib_mr *mr);
1270 void mlx5_ib_free_odp_mr(struct mlx5_ib_mr *mr);
1271 struct ib_mr *mlx5_ib_rereg_user_mr(struct ib_mr *ib_mr, int flags, u64 start,
1272 u64 length, u64 virt_addr, int access_flags,
1273 struct ib_pd *pd, struct ib_udata *udata);
1274 int mlx5_ib_dereg_mr(struct ib_mr *ibmr, struct ib_udata *udata);
1275 struct ib_mr *mlx5_ib_alloc_mr(struct ib_pd *pd, enum ib_mr_type mr_type,
1277 struct ib_mr *mlx5_ib_alloc_mr_integrity(struct ib_pd *pd,
1279 u32 max_num_meta_sg);
1280 int mlx5_ib_map_mr_sg(struct ib_mr *ibmr, struct scatterlist *sg, int sg_nents,
1281 unsigned int *sg_offset);
1282 int mlx5_ib_map_mr_sg_pi(struct ib_mr *ibmr, struct scatterlist *data_sg,
1283 int data_sg_nents, unsigned int *data_sg_offset,
1284 struct scatterlist *meta_sg, int meta_sg_nents,
1285 unsigned int *meta_sg_offset);
1286 int mlx5_ib_process_mad(struct ib_device *ibdev, int mad_flags, u32 port_num,
1287 const struct ib_wc *in_wc, const struct ib_grh *in_grh,
1288 const struct ib_mad *in, struct ib_mad *out,
1289 size_t *out_mad_size, u16 *out_mad_pkey_index);
1290 int mlx5_ib_alloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata);
1291 int mlx5_ib_dealloc_xrcd(struct ib_xrcd *xrcd, struct ib_udata *udata);
1292 int mlx5_query_ext_port_caps(struct mlx5_ib_dev *dev, unsigned int port);
1293 int mlx5_query_mad_ifc_system_image_guid(struct ib_device *ibdev,
1294 __be64 *sys_image_guid);
1295 int mlx5_query_mad_ifc_max_pkeys(struct ib_device *ibdev,
1297 int mlx5_query_mad_ifc_vendor_id(struct ib_device *ibdev,
1299 int mlx5_query_mad_ifc_node_desc(struct mlx5_ib_dev *dev, char *node_desc);
1300 int mlx5_query_mad_ifc_node_guid(struct mlx5_ib_dev *dev, __be64 *node_guid);
1301 int mlx5_query_mad_ifc_pkey(struct ib_device *ibdev, u32 port, u16 index,
1303 int mlx5_query_mad_ifc_gids(struct ib_device *ibdev, u32 port, int index,
1305 int mlx5_query_mad_ifc_port(struct ib_device *ibdev, u32 port,
1306 struct ib_port_attr *props);
1307 int mlx5_ib_query_port(struct ib_device *ibdev, u32 port,
1308 struct ib_port_attr *props);
1309 void mlx5_ib_populate_pas(struct ib_umem *umem, size_t page_size, __be64 *pas,
1311 void mlx5_ib_copy_pas(u64 *old, u64 *new, int step, int num);
1312 int mlx5_ib_get_cqe_size(struct ib_cq *ibcq);
1313 int mlx5_mkey_cache_init(struct mlx5_ib_dev *dev);
1314 int mlx5_mkey_cache_cleanup(struct mlx5_ib_dev *dev);
1316 struct mlx5_ib_mr *mlx5_mr_cache_alloc(struct mlx5_ib_dev *dev,
1317 struct mlx5_cache_ent *ent,
1320 int mlx5_ib_check_mr_status(struct ib_mr *ibmr, u32 check_mask,
1321 struct ib_mr_status *mr_status);
1322 struct ib_wq *mlx5_ib_create_wq(struct ib_pd *pd,
1323 struct ib_wq_init_attr *init_attr,
1324 struct ib_udata *udata);
1325 int mlx5_ib_destroy_wq(struct ib_wq *wq, struct ib_udata *udata);
1326 int mlx5_ib_modify_wq(struct ib_wq *wq, struct ib_wq_attr *wq_attr,
1327 u32 wq_attr_mask, struct ib_udata *udata);
1328 int mlx5_ib_create_rwq_ind_table(struct ib_rwq_ind_table *ib_rwq_ind_table,
1329 struct ib_rwq_ind_table_init_attr *init_attr,
1330 struct ib_udata *udata);
1331 int mlx5_ib_destroy_rwq_ind_table(struct ib_rwq_ind_table *wq_ind_table);
1332 struct ib_mr *mlx5_ib_reg_dm_mr(struct ib_pd *pd, struct ib_dm *dm,
1333 struct ib_dm_mr_attr *attr,
1334 struct uverbs_attr_bundle *attrs);
1336 #ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1337 int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev);
1338 int mlx5r_odp_create_eq(struct mlx5_ib_dev *dev, struct mlx5_ib_pf_eq *eq);
1339 void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev);
1340 int __init mlx5_ib_odp_init(void);
1341 void mlx5_ib_odp_cleanup(void);
1342 void mlx5_odp_init_mkey_cache_entry(struct mlx5_cache_ent *ent);
1343 void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries,
1344 struct mlx5_ib_mr *mr, int flags);
1346 int mlx5_ib_advise_mr_prefetch(struct ib_pd *pd,
1347 enum ib_uverbs_advise_mr_advice advice,
1348 u32 flags, struct ib_sge *sg_list, u32 num_sge);
1349 int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr);
1350 int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr);
1351 #else /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
1352 static inline int mlx5_ib_odp_init_one(struct mlx5_ib_dev *ibdev) { return 0; }
1353 static inline int mlx5r_odp_create_eq(struct mlx5_ib_dev *dev,
1354 struct mlx5_ib_pf_eq *eq)
1358 static inline void mlx5_ib_odp_cleanup_one(struct mlx5_ib_dev *ibdev) {}
1359 static inline int mlx5_ib_odp_init(void) { return 0; }
1360 static inline void mlx5_ib_odp_cleanup(void) {}
1361 static inline void mlx5_odp_init_mkey_cache_entry(struct mlx5_cache_ent *ent) {}
1362 static inline void mlx5_odp_populate_xlt(void *xlt, size_t idx, size_t nentries,
1363 struct mlx5_ib_mr *mr, int flags) {}
1366 mlx5_ib_advise_mr_prefetch(struct ib_pd *pd,
1367 enum ib_uverbs_advise_mr_advice advice, u32 flags,
1368 struct ib_sge *sg_list, u32 num_sge)
1372 static inline int mlx5_ib_init_odp_mr(struct mlx5_ib_mr *mr)
1376 static inline int mlx5_ib_init_dmabuf_mr(struct mlx5_ib_mr *mr)
1380 #endif /* CONFIG_INFINIBAND_ON_DEMAND_PAGING */
1382 extern const struct mmu_interval_notifier_ops mlx5_mn_ops;
1384 /* Needed for rep profile */
1385 void __mlx5_ib_remove(struct mlx5_ib_dev *dev,
1386 const struct mlx5_ib_profile *profile,
1388 int __mlx5_ib_add(struct mlx5_ib_dev *dev,
1389 const struct mlx5_ib_profile *profile);
1391 int mlx5_ib_get_vf_config(struct ib_device *device, int vf,
1392 u32 port, struct ifla_vf_info *info);
1393 int mlx5_ib_set_vf_link_state(struct ib_device *device, int vf,
1394 u32 port, int state);
1395 int mlx5_ib_get_vf_stats(struct ib_device *device, int vf,
1396 u32 port, struct ifla_vf_stats *stats);
1397 int mlx5_ib_get_vf_guid(struct ib_device *device, int vf, u32 port,
1398 struct ifla_vf_guid *node_guid,
1399 struct ifla_vf_guid *port_guid);
1400 int mlx5_ib_set_vf_guid(struct ib_device *device, int vf, u32 port,
1401 u64 guid, int type);
1403 __be16 mlx5_get_roce_udp_sport_min(const struct mlx5_ib_dev *dev,
1404 const struct ib_gid_attr *attr);
1406 void mlx5_ib_cleanup_cong_debugfs(struct mlx5_ib_dev *dev, u32 port_num);
1407 void mlx5_ib_init_cong_debugfs(struct mlx5_ib_dev *dev, u32 port_num);
1409 /* GSI QP helper functions */
1410 int mlx5_ib_create_gsi(struct ib_pd *pd, struct mlx5_ib_qp *mqp,
1411 struct ib_qp_init_attr *attr);
1412 int mlx5_ib_destroy_gsi(struct mlx5_ib_qp *mqp);
1413 int mlx5_ib_gsi_modify_qp(struct ib_qp *qp, struct ib_qp_attr *attr,
1415 int mlx5_ib_gsi_query_qp(struct ib_qp *qp, struct ib_qp_attr *qp_attr,
1417 struct ib_qp_init_attr *qp_init_attr);
1418 int mlx5_ib_gsi_post_send(struct ib_qp *qp, const struct ib_send_wr *wr,
1419 const struct ib_send_wr **bad_wr);
1420 int mlx5_ib_gsi_post_recv(struct ib_qp *qp, const struct ib_recv_wr *wr,
1421 const struct ib_recv_wr **bad_wr);
1422 void mlx5_ib_gsi_pkey_change(struct mlx5_ib_gsi_qp *gsi);
1424 int mlx5_ib_generate_wc(struct ib_cq *ibcq, struct ib_wc *wc);
1426 void mlx5_ib_free_bfreg(struct mlx5_ib_dev *dev, struct mlx5_bfreg_info *bfregi,
1428 struct mlx5_ib_dev *mlx5_ib_get_ibdev_from_mpi(struct mlx5_ib_multiport_info *mpi);
1429 struct mlx5_core_dev *mlx5_ib_get_native_port_mdev(struct mlx5_ib_dev *dev,
1431 u32 *native_port_num);
1432 void mlx5_ib_put_native_port_mdev(struct mlx5_ib_dev *dev,
1435 extern const struct uapi_definition mlx5_ib_devx_defs[];
1436 extern const struct uapi_definition mlx5_ib_flow_defs[];
1437 extern const struct uapi_definition mlx5_ib_qos_defs[];
1438 extern const struct uapi_definition mlx5_ib_std_types_defs[];
1440 static inline int is_qp1(enum ib_qp_type qp_type)
1442 return qp_type == MLX5_IB_QPT_HW_GSI || qp_type == IB_QPT_GSI;
1445 static inline u32 check_cq_create_flags(u32 flags)
1448 * It returns non-zero value for unsupported CQ
1449 * create flags, otherwise it returns zero.
1451 return (flags & ~(IB_UVERBS_CQ_FLAGS_IGNORE_OVERRUN |
1452 IB_UVERBS_CQ_FLAGS_TIMESTAMP_COMPLETION));
1455 static inline int verify_assign_uidx(u8 cqe_version, u32 cmd_uidx,
1459 if ((cmd_uidx == MLX5_IB_DEFAULT_UIDX) ||
1460 (cmd_uidx & ~MLX5_USER_ASSIGNED_UIDX_MASK))
1462 *user_index = cmd_uidx;
1464 *user_index = MLX5_IB_DEFAULT_UIDX;
1470 static inline int get_qp_user_index(struct mlx5_ib_ucontext *ucontext,
1471 struct mlx5_ib_create_qp *ucmd,
1475 u8 cqe_version = ucontext->cqe_version;
1477 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version &&
1478 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
1481 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version)
1484 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
1487 static inline int get_srq_user_index(struct mlx5_ib_ucontext *ucontext,
1488 struct mlx5_ib_create_srq *ucmd,
1492 u8 cqe_version = ucontext->cqe_version;
1494 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) && !cqe_version &&
1495 (ucmd->uidx == MLX5_IB_DEFAULT_UIDX))
1498 if ((offsetofend(typeof(*ucmd), uidx) <= inlen) != !!cqe_version)
1501 return verify_assign_uidx(cqe_version, ucmd->uidx, user_index);
1504 static inline int get_uars_per_sys_page(struct mlx5_ib_dev *dev, bool lib_support)
1506 return lib_support && MLX5_CAP_GEN(dev->mdev, uar_4k) ?
1507 MLX5_UARS_IN_PAGE : 1;
1510 extern void *xlt_emergency_page;
1512 int bfregn_to_uar_index(struct mlx5_ib_dev *dev,
1513 struct mlx5_bfreg_info *bfregi, u32 bfregn,
1516 static inline int mlx5r_store_odp_mkey(struct mlx5_ib_dev *dev,
1517 struct mlx5_ib_mkey *mmkey)
1519 refcount_set(&mmkey->usecount, 1);
1521 return xa_err(xa_store(&dev->odp_mkeys, mlx5_base_mkey(mmkey->key),
1522 mmkey, GFP_KERNEL));
1525 /* deref an mkey that can participate in ODP flow */
1526 static inline void mlx5r_deref_odp_mkey(struct mlx5_ib_mkey *mmkey)
1528 if (refcount_dec_and_test(&mmkey->usecount))
1529 wake_up(&mmkey->wait);
1532 /* deref an mkey that can participate in ODP flow and wait for relese */
1533 static inline void mlx5r_deref_wait_odp_mkey(struct mlx5_ib_mkey *mmkey)
1535 mlx5r_deref_odp_mkey(mmkey);
1536 wait_event(mmkey->wait, refcount_read(&mmkey->usecount) == 0);
1539 int mlx5_ib_test_wc(struct mlx5_ib_dev *dev);
1541 static inline bool mlx5_ib_lag_should_assign_affinity(struct mlx5_ib_dev *dev)
1543 return dev->lag_active ||
1544 (MLX5_CAP_GEN(dev->mdev, num_lag_ports) > 1 &&
1545 MLX5_CAP_GEN(dev->mdev, lag_tx_port_affinity));
1548 static inline bool rt_supported(int ts_cap)
1550 return ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_REAL_TIME ||
1551 ts_cap == MLX5_TIMESTAMP_FORMAT_CAP_FREE_RUNNING_AND_REAL_TIME;
1553 #endif /* MLX5_IB_H */