drivers/gpu/drm/radeon/atombios_encoders.c

   1 /*
   2  * Copyright 2007-11 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  *
   5  * Permission is hereby granted, free of charge, to any person obtaining a
   6  * copy of this software and associated documentation files (the "Software"),
   7  * to deal in the Software without restriction, including without limitation
   8  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   9  * and/or sell copies of the Software, and to permit persons to whom the
  10  * Software is furnished to do so, subject to the following conditions:
  11  *
  12  * The above copyright notice and this permission notice shall be included in
  13  * all copies or substantial portions of the Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  21  * OTHER DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors: Dave Airlie
  24  *          Alex Deucher
  25  */
  26
  27 #include <linux/backlight.h>
  28 #include <linux/dmi.h>
  29 #include <linux/pci.h>
  30
  31 #include <drm/drm_crtc_helper.h>
  32 #include <drm/drm_file.h>
  33 #include <drm/radeon_drm.h>
  34
  35 #include "atom.h"
  36 #include "radeon_atombios.h"
  37 #include "radeon.h"
  38 #include "radeon_asic.h"
  39 #include "radeon_audio.h"
  40
  41 extern int atom_debug;
  42
  43 static u8
  44 radeon_atom_get_backlight_level_from_reg(struct radeon_device *rdev)
  45 {
  46         u8 backlight_level;
  47         u32 bios_2_scratch;
  48
  49         if (rdev->family >= CHIP_R600)
  50                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  51         else
  52                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  53
  54         backlight_level = ((bios_2_scratch & ATOM_S2_CURRENT_BL_LEVEL_MASK) >>
  55                            ATOM_S2_CURRENT_BL_LEVEL_SHIFT);
  56
  57         return backlight_level;
  58 }
  59
  60 static void
  61 radeon_atom_set_backlight_level_to_reg(struct radeon_device *rdev,
  62                                        u8 backlight_level)
  63 {
  64         u32 bios_2_scratch;
  65
  66         if (rdev->family >= CHIP_R600)
  67                 bios_2_scratch = RREG32(R600_BIOS_2_SCRATCH);
  68         else
  69                 bios_2_scratch = RREG32(RADEON_BIOS_2_SCRATCH);
  70
  71         bios_2_scratch &= ~ATOM_S2_CURRENT_BL_LEVEL_MASK;
  72         bios_2_scratch |= ((backlight_level << ATOM_S2_CURRENT_BL_LEVEL_SHIFT) &
  73                            ATOM_S2_CURRENT_BL_LEVEL_MASK);
  74
  75         if (rdev->family >= CHIP_R600)
  76                 WREG32(R600_BIOS_2_SCRATCH, bios_2_scratch);
  77         else
  78                 WREG32(RADEON_BIOS_2_SCRATCH, bios_2_scratch);
  79 }
  80
  81 u8
  82 atombios_get_backlight_level(struct radeon_encoder *radeon_encoder)
  83 {
  84         struct drm_device *dev = radeon_encoder->base.dev;
  85         struct radeon_device *rdev = dev->dev_private;
  86
  87         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
  88                 return 0;
  89
  90         return radeon_atom_get_backlight_level_from_reg(rdev);
  91 }
  92
  93 void
  94 atombios_set_backlight_level(struct radeon_encoder *radeon_encoder, u8 level)
  95 {
  96         struct drm_encoder *encoder = &radeon_encoder->base;
  97         struct drm_device *dev = radeon_encoder->base.dev;
  98         struct radeon_device *rdev = dev->dev_private;
  99         struct radeon_encoder_atom_dig *dig;
 100         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
 101         int index;
 102
 103         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 104                 return;
 105
 106         if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
 107             radeon_encoder->enc_priv) {
 108                 dig = radeon_encoder->enc_priv;
 109                 dig->backlight_level = level;
 110                 radeon_atom_set_backlight_level_to_reg(rdev, dig->backlight_level);
 111
 112                 switch (radeon_encoder->encoder_id) {
 113                 case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 114                 case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 115                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
 116                         if (dig->backlight_level == 0) {
 117                                 args.ucAction = ATOM_LCD_BLOFF;
 118                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 119                         } else {
 120                                 args.ucAction = ATOM_LCD_BL_BRIGHTNESS_CONTROL;
 121                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 122                                 args.ucAction = ATOM_LCD_BLON;
 123                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 124                         }
 125                         break;
 126                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 127                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 128                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 129                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 130                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
 131                         if (dig->backlight_level == 0)
 132                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
 133                         else {
 134                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_BL_BRIGHTNESS_CONTROL, 0, 0);
 135                                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
 136                         }
 137                         break;
 138                 default:
 139                         break;
 140                 }
 141         }
 142 }
 143
 144 static u8 radeon_atom_bl_level(struct backlight_device *bd)
 145 {
 146         u8 level;
 147
 148         /* Convert brightness to hardware level */
 149         if (bd->props.brightness < 0)
 150                 level = 0;
 151         else if (bd->props.brightness > RADEON_MAX_BL_LEVEL)
 152                 level = RADEON_MAX_BL_LEVEL;
 153         else
 154                 level = bd->props.brightness;
 155
 156         return level;
 157 }
 158
 159 static int radeon_atom_backlight_update_status(struct backlight_device *bd)
 160 {
 161         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 162         struct radeon_encoder *radeon_encoder = pdata->encoder;
 163
 164         atombios_set_backlight_level(radeon_encoder, radeon_atom_bl_level(bd));
 165
 166         return 0;
 167 }
 168
 169 static int radeon_atom_backlight_get_brightness(struct backlight_device *bd)
 170 {
 171         struct radeon_backlight_privdata *pdata = bl_get_data(bd);
 172         struct radeon_encoder *radeon_encoder = pdata->encoder;
 173         struct drm_device *dev = radeon_encoder->base.dev;
 174         struct radeon_device *rdev = dev->dev_private;
 175
 176         return radeon_atom_get_backlight_level_from_reg(rdev);
 177 }
 178
 179 static const struct backlight_ops radeon_atom_backlight_ops = {
 180         .get_brightness = radeon_atom_backlight_get_brightness,
 181         .update_status  = radeon_atom_backlight_update_status,
 182 };
 183
 184 void radeon_atom_backlight_init(struct radeon_encoder *radeon_encoder,
 185                                 struct drm_connector *drm_connector)
 186 {
 187         struct drm_device *dev = radeon_encoder->base.dev;
 188         struct radeon_device *rdev = dev->dev_private;
 189         struct backlight_device *bd;
 190         struct backlight_properties props;
 191         struct radeon_backlight_privdata *pdata;
 192         struct radeon_encoder_atom_dig *dig;
 193         char bl_name[16];
 194
 195         /* Mac laptops with multiple GPUs use the gmux driver for backlight
 196          * so don't register a backlight device
 197          */
 198         if ((rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
 199             (rdev->pdev->device == 0x6741) &&
 200             !dmi_match(DMI_PRODUCT_NAME, "iMac12,1"))
 201                 return;
 202
 203         if (!radeon_encoder->enc_priv)
 204                 return;
 205
 206         if (!rdev->is_atom_bios)
 207                 return;
 208
 209         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 210                 return;
 211
 212         pdata = kmalloc(sizeof(struct radeon_backlight_privdata), GFP_KERNEL);
 213         if (!pdata) {
 214                 DRM_ERROR("Memory allocation failed\n");
 215                 goto error;
 216         }
 217
 218         memset(&props, 0, sizeof(props));
 219         props.max_brightness = RADEON_MAX_BL_LEVEL;
 220         props.type = BACKLIGHT_RAW;
 221         snprintf(bl_name, sizeof(bl_name),
 222                  "radeon_bl%d", dev->primary->index);
 223         bd = backlight_device_register(bl_name, drm_connector->kdev,
 224                                        pdata, &radeon_atom_backlight_ops, &props);
 225         if (IS_ERR(bd)) {
 226                 DRM_ERROR("Backlight registration failed\n");
 227                 goto error;
 228         }
 229
 230         pdata->encoder = radeon_encoder;
 231
 232         dig = radeon_encoder->enc_priv;
 233         dig->bl_dev = bd;
 234
 235         bd->props.brightness = radeon_atom_backlight_get_brightness(bd);
 236         /* Set a reasonable default here if the level is 0 otherwise
 237          * fbdev will attempt to turn the backlight on after console
 238          * unblanking and it will try and restore 0 which turns the backlight
 239          * off again.
 240          */
 241         if (bd->props.brightness == 0)
 242                 bd->props.brightness = RADEON_MAX_BL_LEVEL;
 243         bd->props.power = FB_BLANK_UNBLANK;
 244         backlight_update_status(bd);
 245
 246         DRM_INFO("radeon atom DIG backlight initialized\n");
 247         rdev->mode_info.bl_encoder = radeon_encoder;
 248
 249         return;
 250
 251 error:
 252         kfree(pdata);
 253         return;
 254 }
 255
 256 static void radeon_atom_backlight_exit(struct radeon_encoder *radeon_encoder)
 257 {
 258         struct drm_device *dev = radeon_encoder->base.dev;
 259         struct radeon_device *rdev = dev->dev_private;
 260         struct backlight_device *bd = NULL;
 261         struct radeon_encoder_atom_dig *dig;
 262
 263         if (!radeon_encoder->enc_priv)
 264                 return;
 265
 266         if (!rdev->is_atom_bios)
 267                 return;
 268
 269         if (!(rdev->mode_info.firmware_flags & ATOM_BIOS_INFO_BL_CONTROLLED_BY_GPU))
 270                 return;
 271
 272         dig = radeon_encoder->enc_priv;
 273         bd = dig->bl_dev;
 274         dig->bl_dev = NULL;
 275
 276         if (bd) {
 277                 struct radeon_legacy_backlight_privdata *pdata;
 278
 279                 pdata = bl_get_data(bd);
 280                 backlight_device_unregister(bd);
 281                 kfree(pdata);
 282
 283                 DRM_INFO("radeon atom LVDS backlight unloaded\n");
 284         }
 285 }
 286
 287 static bool radeon_atom_mode_fixup(struct drm_encoder *encoder,
 288                                    const struct drm_display_mode *mode,
 289                                    struct drm_display_mode *adjusted_mode)
 290 {
 291         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 292         struct drm_device *dev = encoder->dev;
 293         struct radeon_device *rdev = dev->dev_private;
 294
 295         /* set the active encoder to connector routing */
 296         radeon_encoder_set_active_device(encoder);
 297         drm_mode_set_crtcinfo(adjusted_mode, 0);
 298
 299         /* hw bug */
 300         if ((mode->flags & DRM_MODE_FLAG_INTERLACE)
 301             && (mode->crtc_vsync_start < (mode->crtc_vdisplay + 2)))
 302                 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vdisplay + 2;
 303
 304         /* vertical FP must be at least 1 */
 305         if (mode->crtc_vsync_start == mode->crtc_vdisplay)
 306                 adjusted_mode->crtc_vsync_start++;
 307
 308         /* get the native mode for scaling */
 309         if (radeon_encoder->active_device & (ATOM_DEVICE_LCD_SUPPORT)) {
 310                 radeon_panel_mode_fixup(encoder, adjusted_mode);
 311         } else if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)) {
 312                 struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv;
 313                 if (tv_dac) {
 314                         if (tv_dac->tv_std == TV_STD_NTSC ||
 315                             tv_dac->tv_std == TV_STD_NTSC_J ||
 316                             tv_dac->tv_std == TV_STD_PAL_M)
 317                                 radeon_atom_get_tv_timings(rdev, 0, adjusted_mode);
 318                         else
 319                                 radeon_atom_get_tv_timings(rdev, 1, adjusted_mode);
 320                 }
 321         } else if (radeon_encoder->rmx_type != RMX_OFF) {
 322                 radeon_panel_mode_fixup(encoder, adjusted_mode);
 323         }
 324
 325         if (ASIC_IS_DCE3(rdev) &&
 326             ((radeon_encoder->active_device & (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
 327              (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE))) {
 328                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 329                 radeon_dp_set_link_config(connector, adjusted_mode);
 330         }
 331
 332         return true;
 333 }
 334
 335 static void
 336 atombios_dac_setup(struct drm_encoder *encoder, int action)
 337 {
 338         struct drm_device *dev = encoder->dev;
 339         struct radeon_device *rdev = dev->dev_private;
 340         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 341         DAC_ENCODER_CONTROL_PS_ALLOCATION args;
 342         int index = 0;
 343         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 344
 345         memset(&args, 0, sizeof(args));
 346
 347         switch (radeon_encoder->encoder_id) {
 348         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
 349         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
 350                 index = GetIndexIntoMasterTable(COMMAND, DAC1EncoderControl);
 351                 break;
 352         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
 353         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
 354                 index = GetIndexIntoMasterTable(COMMAND, DAC2EncoderControl);
 355                 break;
 356         }
 357
 358         args.ucAction = action;
 359
 360         if (radeon_encoder->active_device & (ATOM_DEVICE_CRT_SUPPORT))
 361                 args.ucDacStandard = ATOM_DAC1_PS2;
 362         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 363                 args.ucDacStandard = ATOM_DAC1_CV;
 364         else {
 365                 switch (dac_info->tv_std) {
 366                 case TV_STD_PAL:
 367                 case TV_STD_PAL_M:
 368                 case TV_STD_SCART_PAL:
 369                 case TV_STD_SECAM:
 370                 case TV_STD_PAL_CN:
 371                         args.ucDacStandard = ATOM_DAC1_PAL;
 372                         break;
 373                 case TV_STD_NTSC:
 374                 case TV_STD_NTSC_J:
 375                 case TV_STD_PAL_60:
 376                 default:
 377                         args.ucDacStandard = ATOM_DAC1_NTSC;
 378                         break;
 379                 }
 380         }
 381         args.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 382
 383         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 384
 385 }
 386
 387 static void
 388 atombios_tv_setup(struct drm_encoder *encoder, int action)
 389 {
 390         struct drm_device *dev = encoder->dev;
 391         struct radeon_device *rdev = dev->dev_private;
 392         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 393         TV_ENCODER_CONTROL_PS_ALLOCATION args;
 394         int index = 0;
 395         struct radeon_encoder_atom_dac *dac_info = radeon_encoder->enc_priv;
 396
 397         memset(&args, 0, sizeof(args));
 398
 399         index = GetIndexIntoMasterTable(COMMAND, TVEncoderControl);
 400
 401         args.sTVEncoder.ucAction = action;
 402
 403         if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
 404                 args.sTVEncoder.ucTvStandard = ATOM_TV_CV;
 405         else {
 406                 switch (dac_info->tv_std) {
 407                 case TV_STD_NTSC:
 408                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 409                         break;
 410                 case TV_STD_PAL:
 411                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL;
 412                         break;
 413                 case TV_STD_PAL_M:
 414                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALM;
 415                         break;
 416                 case TV_STD_PAL_60:
 417                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL60;
 418                         break;
 419                 case TV_STD_NTSC_J:
 420                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSCJ;
 421                         break;
 422                 case TV_STD_SCART_PAL:
 423                         args.sTVEncoder.ucTvStandard = ATOM_TV_PAL; /* ??? */
 424                         break;
 425                 case TV_STD_SECAM:
 426                         args.sTVEncoder.ucTvStandard = ATOM_TV_SECAM;
 427                         break;
 428                 case TV_STD_PAL_CN:
 429                         args.sTVEncoder.ucTvStandard = ATOM_TV_PALCN;
 430                         break;
 431                 default:
 432                         args.sTVEncoder.ucTvStandard = ATOM_TV_NTSC;
 433                         break;
 434                 }
 435         }
 436
 437         args.sTVEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 438
 439         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 440
 441 }
 442
 443 static u8 radeon_atom_get_bpc(struct drm_encoder *encoder)
 444 {
 445         int bpc = 8;
 446
 447         if (encoder->crtc) {
 448                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
 449                 bpc = radeon_crtc->bpc;
 450         }
 451
 452         switch (bpc) {
 453         case 0:
 454                 return PANEL_BPC_UNDEFINE;
 455         case 6:
 456                 return PANEL_6BIT_PER_COLOR;
 457         case 8:
 458         default:
 459                 return PANEL_8BIT_PER_COLOR;
 460         case 10:
 461                 return PANEL_10BIT_PER_COLOR;
 462         case 12:
 463                 return PANEL_12BIT_PER_COLOR;
 464         case 16:
 465                 return PANEL_16BIT_PER_COLOR;
 466         }
 467 }
 468
 469 union dvo_encoder_control {
 470         ENABLE_EXTERNAL_TMDS_ENCODER_PS_ALLOCATION ext_tmds;
 471         DVO_ENCODER_CONTROL_PS_ALLOCATION dvo;
 472         DVO_ENCODER_CONTROL_PS_ALLOCATION_V3 dvo_v3;
 473         DVO_ENCODER_CONTROL_PS_ALLOCATION_V1_4 dvo_v4;
 474 };
 475
 476 void
 477 atombios_dvo_setup(struct drm_encoder *encoder, int action)
 478 {
 479         struct drm_device *dev = encoder->dev;
 480         struct radeon_device *rdev = dev->dev_private;
 481         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 482         union dvo_encoder_control args;
 483         int index = GetIndexIntoMasterTable(COMMAND, DVOEncoderControl);
 484         uint8_t frev, crev;
 485
 486         memset(&args, 0, sizeof(args));
 487
 488         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 489                 return;
 490
 491         /* some R4xx chips have the wrong frev */
 492         if (rdev->family <= CHIP_RV410)
 493                 frev = 1;
 494
 495         switch (frev) {
 496         case 1:
 497                 switch (crev) {
 498                 case 1:
 499                         /* R4xx, R5xx */
 500                         args.ext_tmds.sXTmdsEncoder.ucEnable = action;
 501
 502                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 503                                 args.ext_tmds.sXTmdsEncoder.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 504
 505                         args.ext_tmds.sXTmdsEncoder.ucMisc |= ATOM_PANEL_MISC_888RGB;
 506                         break;
 507                 case 2:
 508                         /* RS600/690/740 */
 509                         args.dvo.sDVOEncoder.ucAction = action;
 510                         args.dvo.sDVOEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 511                         /* DFP1, CRT1, TV1 depending on the type of port */
 512                         args.dvo.sDVOEncoder.ucDeviceType = ATOM_DEVICE_DFP1_INDEX;
 513
 514                         if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 515                                 args.dvo.sDVOEncoder.usDevAttr.sDigAttrib.ucAttribute |= PANEL_ENCODER_MISC_DUAL;
 516                         break;
 517                 case 3:
 518                         /* R6xx */
 519                         args.dvo_v3.ucAction = action;
 520                         args.dvo_v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 521                         args.dvo_v3.ucDVOConfig = 0; /* XXX */
 522                         break;
 523                 case 4:
 524                         /* DCE8 */
 525                         args.dvo_v4.ucAction = action;
 526                         args.dvo_v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 527                         args.dvo_v4.ucDVOConfig = 0; /* XXX */
 528                         args.dvo_v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
 529                         break;
 530                 default:
 531                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 532                         break;
 533                 }
 534                 break;
 535         default:
 536                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 537                 break;
 538         }
 539
 540         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 541 }
 542
 543 union lvds_encoder_control {
 544         LVDS_ENCODER_CONTROL_PS_ALLOCATION    v1;
 545         LVDS_ENCODER_CONTROL_PS_ALLOCATION_V2 v2;
 546 };
 547
 548 void
 549 atombios_digital_setup(struct drm_encoder *encoder, int action)
 550 {
 551         struct drm_device *dev = encoder->dev;
 552         struct radeon_device *rdev = dev->dev_private;
 553         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 554         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 555         union lvds_encoder_control args;
 556         int index = 0;
 557         int hdmi_detected = 0;
 558         uint8_t frev, crev;
 559
 560         if (!dig)
 561                 return;
 562
 563         if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI)
 564                 hdmi_detected = 1;
 565
 566         memset(&args, 0, sizeof(args));
 567
 568         switch (radeon_encoder->encoder_id) {
 569         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
 570                 index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 571                 break;
 572         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
 573         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
 574                 index = GetIndexIntoMasterTable(COMMAND, TMDS1EncoderControl);
 575                 break;
 576         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
 577                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
 578                         index = GetIndexIntoMasterTable(COMMAND, LVDSEncoderControl);
 579                 else
 580                         index = GetIndexIntoMasterTable(COMMAND, TMDS2EncoderControl);
 581                 break;
 582         }
 583
 584         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 585                 return;
 586
 587         switch (frev) {
 588         case 1:
 589         case 2:
 590                 switch (crev) {
 591                 case 1:
 592                         args.v1.ucMisc = 0;
 593                         args.v1.ucAction = action;
 594                         if (hdmi_detected)
 595                                 args.v1.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 596                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 597                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 598                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 599                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 600                                 if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 601                                         args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 602                         } else {
 603                                 if (dig->linkb)
 604                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 605                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 606                                         args.v1.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 607                                 /*if (pScrn->rgbBits == 8) */
 608                                 args.v1.ucMisc |= ATOM_PANEL_MISC_888RGB;
 609                         }
 610                         break;
 611                 case 2:
 612                 case 3:
 613                         args.v2.ucMisc = 0;
 614                         args.v2.ucAction = action;
 615                         if (crev == 3) {
 616                                 if (dig->coherent_mode)
 617                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_COHERENT;
 618                         }
 619                         if (hdmi_detected)
 620                                 args.v2.ucMisc |= PANEL_ENCODER_MISC_HDMI_TYPE;
 621                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 622                         args.v2.ucTruncate = 0;
 623                         args.v2.ucSpatial = 0;
 624                         args.v2.ucTemporal = 0;
 625                         args.v2.ucFRC = 0;
 626                         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
 627                                 if (dig->lcd_misc & ATOM_PANEL_MISC_DUAL)
 628                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 629                                 if (dig->lcd_misc & ATOM_PANEL_MISC_SPATIAL) {
 630                                         args.v2.ucSpatial = PANEL_ENCODER_SPATIAL_DITHER_EN;
 631                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 632                                                 args.v2.ucSpatial |= PANEL_ENCODER_SPATIAL_DITHER_DEPTH;
 633                                 }
 634                                 if (dig->lcd_misc & ATOM_PANEL_MISC_TEMPORAL) {
 635                                         args.v2.ucTemporal = PANEL_ENCODER_TEMPORAL_DITHER_EN;
 636                                         if (dig->lcd_misc & ATOM_PANEL_MISC_888RGB)
 637                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_DITHER_DEPTH;
 638                                         if (((dig->lcd_misc >> ATOM_PANEL_MISC_GREY_LEVEL_SHIFT) & 0x3) == 2)
 639                                                 args.v2.ucTemporal |= PANEL_ENCODER_TEMPORAL_LEVEL_4;
 640                                 }
 641                         } else {
 642                                 if (dig->linkb)
 643                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_TMDS_LINKB;
 644                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 645                                         args.v2.ucMisc |= PANEL_ENCODER_MISC_DUAL;
 646                         }
 647                         break;
 648                 default:
 649                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 650                         break;
 651                 }
 652                 break;
 653         default:
 654                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 655                 break;
 656         }
 657
 658         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 659 }
 660
 661 int
 662 atombios_get_encoder_mode(struct drm_encoder *encoder)
 663 {
 664         struct drm_device *dev = encoder->dev;
 665         struct radeon_device *rdev = dev->dev_private;
 666         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 667         struct drm_connector *connector;
 668         struct radeon_connector *radeon_connector;
 669         struct radeon_connector_atom_dig *dig_connector;
 670         struct radeon_encoder_atom_dig *dig_enc;
 671
 672         if (radeon_encoder_is_digital(encoder)) {
 673                 dig_enc = radeon_encoder->enc_priv;
 674                 if (dig_enc->active_mst_links)
 675                         return ATOM_ENCODER_MODE_DP_MST;
 676         }
 677         if (radeon_encoder->is_mst_encoder || radeon_encoder->offset)
 678                 return ATOM_ENCODER_MODE_DP_MST;
 679         /* dp bridges are always DP */
 680         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)
 681                 return ATOM_ENCODER_MODE_DP;
 682
 683         /* DVO is always DVO */
 684         if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DVO1) ||
 685             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1))
 686                 return ATOM_ENCODER_MODE_DVO;
 687
 688         connector = radeon_get_connector_for_encoder(encoder);
 689         /* if we don't have an active device yet, just use one of
 690          * the connectors tied to the encoder.
 691          */
 692         if (!connector)
 693                 connector = radeon_get_connector_for_encoder_init(encoder);
 694         radeon_connector = to_radeon_connector(connector);
 695
 696         switch (connector->connector_type) {
 697         case DRM_MODE_CONNECTOR_DVII:
 698         case DRM_MODE_CONNECTOR_HDMIB: /* HDMI-B is basically DL-DVI; analog works fine */
 699                 if (radeon_audio != 0) {
 700                         if (radeon_connector->use_digital &&
 701                             (radeon_connector->audio == RADEON_AUDIO_ENABLE))
 702                                 return ATOM_ENCODER_MODE_HDMI;
 703                         else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
 704                                  (radeon_connector->audio == RADEON_AUDIO_AUTO))
 705                                 return ATOM_ENCODER_MODE_HDMI;
 706                         else if (radeon_connector->use_digital)
 707                                 return ATOM_ENCODER_MODE_DVI;
 708                         else
 709                                 return ATOM_ENCODER_MODE_CRT;
 710                 } else if (radeon_connector->use_digital) {
 711                         return ATOM_ENCODER_MODE_DVI;
 712                 } else {
 713                         return ATOM_ENCODER_MODE_CRT;
 714                 }
 715                 break;
 716         case DRM_MODE_CONNECTOR_DVID:
 717         case DRM_MODE_CONNECTOR_HDMIA:
 718         default:
 719                 if (radeon_audio != 0) {
 720                         if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
 721                                 return ATOM_ENCODER_MODE_HDMI;
 722                         else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
 723                                  (radeon_connector->audio == RADEON_AUDIO_AUTO))
 724                                 return ATOM_ENCODER_MODE_HDMI;
 725                         else
 726                                 return ATOM_ENCODER_MODE_DVI;
 727                 } else {
 728                         return ATOM_ENCODER_MODE_DVI;
 729                 }
 730                 break;
 731         case DRM_MODE_CONNECTOR_LVDS:
 732                 return ATOM_ENCODER_MODE_LVDS;
 733                 break;
 734         case DRM_MODE_CONNECTOR_DisplayPort:
 735                 dig_connector = radeon_connector->con_priv;
 736                 if ((dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_DISPLAYPORT) ||
 737                     (dig_connector->dp_sink_type == CONNECTOR_OBJECT_ID_eDP)) {
 738                         if (radeon_audio != 0 &&
 739                             drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
 740                             ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
 741                                 return ATOM_ENCODER_MODE_DP_AUDIO;
 742                         return ATOM_ENCODER_MODE_DP;
 743                 } else if (radeon_audio != 0) {
 744                         if (radeon_connector->audio == RADEON_AUDIO_ENABLE)
 745                                 return ATOM_ENCODER_MODE_HDMI;
 746                         else if (drm_detect_hdmi_monitor(radeon_connector_edid(connector)) &&
 747                                  (radeon_connector->audio == RADEON_AUDIO_AUTO))
 748                                 return ATOM_ENCODER_MODE_HDMI;
 749                         else
 750                                 return ATOM_ENCODER_MODE_DVI;
 751                 } else {
 752                         return ATOM_ENCODER_MODE_DVI;
 753                 }
 754                 break;
 755         case DRM_MODE_CONNECTOR_eDP:
 756                 if (radeon_audio != 0 &&
 757                     drm_detect_monitor_audio(radeon_connector_edid(connector)) &&
 758                     ASIC_IS_DCE4(rdev) && !ASIC_IS_DCE5(rdev))
 759                         return ATOM_ENCODER_MODE_DP_AUDIO;
 760                 return ATOM_ENCODER_MODE_DP;
 761         case DRM_MODE_CONNECTOR_DVIA:
 762         case DRM_MODE_CONNECTOR_VGA:
 763                 return ATOM_ENCODER_MODE_CRT;
 764                 break;
 765         case DRM_MODE_CONNECTOR_Composite:
 766         case DRM_MODE_CONNECTOR_SVIDEO:
 767         case DRM_MODE_CONNECTOR_9PinDIN:
 768                 /* fix me */
 769                 return ATOM_ENCODER_MODE_TV;
 770                 /*return ATOM_ENCODER_MODE_CV;*/
 771                 break;
 772         }
 773 }
 774
 775 /*
 776  * DIG Encoder/Transmitter Setup
 777  *
 778  * DCE 3.0/3.1
 779  * - 2 DIG transmitter blocks. UNIPHY (links A and B) and LVTMA.
 780  * Supports up to 3 digital outputs
 781  * - 2 DIG encoder blocks.
 782  * DIG1 can drive UNIPHY link A or link B
 783  * DIG2 can drive UNIPHY link B or LVTMA
 784  *
 785  * DCE 3.2
 786  * - 3 DIG transmitter blocks. UNIPHY0/1/2 (links A and B).
 787  * Supports up to 5 digital outputs
 788  * - 2 DIG encoder blocks.
 789  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 790  *
 791  * DCE 4.0/5.0/6.0
 792  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 793  * Supports up to 6 digital outputs
 794  * - 6 DIG encoder blocks.
 795  * - DIG to PHY mapping is hardcoded
 796  * DIG1 drives UNIPHY0 link A, A+B
 797  * DIG2 drives UNIPHY0 link B
 798  * DIG3 drives UNIPHY1 link A, A+B
 799  * DIG4 drives UNIPHY1 link B
 800  * DIG5 drives UNIPHY2 link A, A+B
 801  * DIG6 drives UNIPHY2 link B
 802  *
 803  * DCE 4.1
 804  * - 3 DIG transmitter blocks UNIPHY0/1/2 (links A and B).
 805  * Supports up to 6 digital outputs
 806  * - 2 DIG encoder blocks.
 807  * llano
 808  * DIG1/2 can drive UNIPHY0/1/2 link A or link B
 809  * ontario
 810  * DIG1 drives UNIPHY0/1/2 link A
 811  * DIG2 drives UNIPHY0/1/2 link B
 812  *
 813  * Routing
 814  * crtc -> dig encoder -> UNIPHY/LVTMA (1 or 2 links)
 815  * Examples:
 816  * crtc0 -> dig2 -> LVTMA   links A+B -> TMDS/HDMI
 817  * crtc1 -> dig1 -> UNIPHY0 link  B   -> DP
 818  * crtc0 -> dig1 -> UNIPHY2 link  A   -> LVDS
 819  * crtc1 -> dig2 -> UNIPHY1 link  B+A -> TMDS/HDMI
 820  */
 821
 822 union dig_encoder_control {
 823         DIG_ENCODER_CONTROL_PS_ALLOCATION v1;
 824         DIG_ENCODER_CONTROL_PARAMETERS_V2 v2;
 825         DIG_ENCODER_CONTROL_PARAMETERS_V3 v3;
 826         DIG_ENCODER_CONTROL_PARAMETERS_V4 v4;
 827 };
 828
 829 void
 830 atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override)
 831 {
 832         struct drm_device *dev = encoder->dev;
 833         struct radeon_device *rdev = dev->dev_private;
 834         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
 835         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
 836         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
 837         union dig_encoder_control args;
 838         int index = 0;
 839         uint8_t frev, crev;
 840         int dp_clock = 0;
 841         int dp_lane_count = 0;
 842         int hpd_id = RADEON_HPD_NONE;
 843
 844         if (connector) {
 845                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 846                 struct radeon_connector_atom_dig *dig_connector =
 847                         radeon_connector->con_priv;
 848
 849                 dp_clock = dig_connector->dp_clock;
 850                 dp_lane_count = dig_connector->dp_lane_count;
 851                 hpd_id = radeon_connector->hpd.hpd;
 852         }
 853
 854         /* no dig encoder assigned */
 855         if (dig->dig_encoder == -1)
 856                 return;
 857
 858         memset(&args, 0, sizeof(args));
 859
 860         if (ASIC_IS_DCE4(rdev))
 861                 index = GetIndexIntoMasterTable(COMMAND, DIGxEncoderControl);
 862         else {
 863                 if (dig->dig_encoder)
 864                         index = GetIndexIntoMasterTable(COMMAND, DIG2EncoderControl);
 865                 else
 866                         index = GetIndexIntoMasterTable(COMMAND, DIG1EncoderControl);
 867         }
 868
 869         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
 870                 return;
 871
 872         switch (frev) {
 873         case 1:
 874                 switch (crev) {
 875                 case 1:
 876                         args.v1.ucAction = action;
 877                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 878                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 879                                 args.v3.ucPanelMode = panel_mode;
 880                         else
 881                                 args.v1.ucEncoderMode = atombios_get_encoder_mode(encoder);
 882
 883                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode))
 884                                 args.v1.ucLaneNum = dp_lane_count;
 885                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 886                                 args.v1.ucLaneNum = 8;
 887                         else
 888                                 args.v1.ucLaneNum = 4;
 889
 890                         switch (radeon_encoder->encoder_id) {
 891                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
 892                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER1;
 893                                 break;
 894                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
 895                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
 896                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER2;
 897                                 break;
 898                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
 899                                 args.v1.ucConfig = ATOM_ENCODER_CONFIG_V2_TRANSMITTER3;
 900                                 break;
 901                         }
 902                         if (dig->linkb)
 903                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKB;
 904                         else
 905                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_LINKA;
 906
 907                         if (ENCODER_MODE_IS_DP(args.v1.ucEncoderMode) && (dp_clock == 270000))
 908                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
 909
 910                         break;
 911                 case 2:
 912                 case 3:
 913                         args.v3.ucAction = action;
 914                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 915                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 916                                 args.v3.ucPanelMode = panel_mode;
 917                         else
 918                                 args.v3.ucEncoderMode = atombios_get_encoder_mode(encoder);
 919
 920                         if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode))
 921                                 args.v3.ucLaneNum = dp_lane_count;
 922                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 923                                 args.v3.ucLaneNum = 8;
 924                         else
 925                                 args.v3.ucLaneNum = 4;
 926
 927                         if (ENCODER_MODE_IS_DP(args.v3.ucEncoderMode) && (dp_clock == 270000))
 928                                 args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
 929                         if (enc_override != -1)
 930                                 args.v3.acConfig.ucDigSel = enc_override;
 931                         else
 932                                 args.v3.acConfig.ucDigSel = dig->dig_encoder;
 933                         args.v3.ucBitPerColor = radeon_atom_get_bpc(encoder);
 934                         break;
 935                 case 4:
 936                         args.v4.ucAction = action;
 937                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
 938                         if (action == ATOM_ENCODER_CMD_SETUP_PANEL_MODE)
 939                                 args.v4.ucPanelMode = panel_mode;
 940                         else
 941                                 args.v4.ucEncoderMode = atombios_get_encoder_mode(encoder);
 942
 943                         if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode))
 944                                 args.v4.ucLaneNum = dp_lane_count;
 945                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
 946                                 args.v4.ucLaneNum = 8;
 947                         else
 948                                 args.v4.ucLaneNum = 4;
 949
 950                         if (ENCODER_MODE_IS_DP(args.v4.ucEncoderMode)) {
 951                                 if (dp_clock == 540000)
 952                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_5_40GHZ;
 953                                 else if (dp_clock == 324000)
 954                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_3_24GHZ;
 955                                 else if (dp_clock == 270000)
 956                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_2_70GHZ;
 957                                 else
 958                                         args.v1.ucConfig |= ATOM_ENCODER_CONFIG_V4_DPLINKRATE_1_62GHZ;
 959                         }
 960
 961                         if (enc_override != -1)
 962                                 args.v4.acConfig.ucDigSel = enc_override;
 963                         else
 964                                 args.v4.acConfig.ucDigSel = dig->dig_encoder;
 965                         args.v4.ucBitPerColor = radeon_atom_get_bpc(encoder);
 966                         if (hpd_id == RADEON_HPD_NONE)
 967                                 args.v4.ucHPD_ID = 0;
 968                         else
 969                                 args.v4.ucHPD_ID = hpd_id + 1;
 970                         break;
 971                 default:
 972                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 973                         break;
 974                 }
 975                 break;
 976         default:
 977                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
 978                 break;
 979         }
 980
 981         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
 982
 983 }
 984
 985 void
 986 atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode)
 987 {
 988         atombios_dig_encoder_setup2(encoder, action, panel_mode, -1);
 989 }
 990
 991 union dig_transmitter_control {
 992         DIG_TRANSMITTER_CONTROL_PS_ALLOCATION v1;
 993         DIG_TRANSMITTER_CONTROL_PARAMETERS_V2 v2;
 994         DIG_TRANSMITTER_CONTROL_PARAMETERS_V3 v3;
 995         DIG_TRANSMITTER_CONTROL_PARAMETERS_V4 v4;
 996         DIG_TRANSMITTER_CONTROL_PARAMETERS_V1_5 v5;
 997 };
 998
 999 void
1000 atombios_dig_transmitter_setup2(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set, int fe)
1001 {
1002         struct drm_device *dev = encoder->dev;
1003         struct radeon_device *rdev = dev->dev_private;
1004         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1005         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1006         struct drm_connector *connector;
1007         union dig_transmitter_control args;
1008         int index = 0;
1009         uint8_t frev, crev;
1010         bool is_dp = false;
1011         int pll_id = 0;
1012         int dp_clock = 0;
1013         int dp_lane_count = 0;
1014         int connector_object_id = 0;
1015         int igp_lane_info = 0;
1016         int dig_encoder = dig->dig_encoder;
1017         int hpd_id = RADEON_HPD_NONE;
1018
1019         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1020                 connector = radeon_get_connector_for_encoder_init(encoder);
1021                 /* just needed to avoid bailing in the encoder check.  the encoder
1022                  * isn't used for init
1023                  */
1024                 dig_encoder = 0;
1025         } else
1026                 connector = radeon_get_connector_for_encoder(encoder);
1027
1028         if (connector) {
1029                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1030                 struct radeon_connector_atom_dig *dig_connector =
1031                         radeon_connector->con_priv;
1032
1033                 hpd_id = radeon_connector->hpd.hpd;
1034                 dp_clock = dig_connector->dp_clock;
1035                 dp_lane_count = dig_connector->dp_lane_count;
1036                 connector_object_id =
1037                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1038                 igp_lane_info = dig_connector->igp_lane_info;
1039         }
1040
1041         if (encoder->crtc) {
1042                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1043                 pll_id = radeon_crtc->pll_id;
1044         }
1045
1046         /* no dig encoder assigned */
1047         if (dig_encoder == -1)
1048                 return;
1049
1050         if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)))
1051                 is_dp = true;
1052
1053         memset(&args, 0, sizeof(args));
1054
1055         switch (radeon_encoder->encoder_id) {
1056         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1057                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1058                 break;
1059         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1060         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1061         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1062         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1063                 index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1064                 break;
1065         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1066                 index = GetIndexIntoMasterTable(COMMAND, LVTMATransmitterControl);
1067                 break;
1068         }
1069
1070         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1071                 return;
1072
1073         switch (frev) {
1074         case 1:
1075                 switch (crev) {
1076                 case 1:
1077                         args.v1.ucAction = action;
1078                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1079                                 args.v1.usInitInfo = cpu_to_le16(connector_object_id);
1080                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1081                                 args.v1.asMode.ucLaneSel = lane_num;
1082                                 args.v1.asMode.ucLaneSet = lane_set;
1083                         } else {
1084                                 if (is_dp)
1085                                         args.v1.usPixelClock = cpu_to_le16(dp_clock / 10);
1086                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1087                                         args.v1.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1088                                 else
1089                                         args.v1.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1090                         }
1091
1092                         args.v1.ucConfig = ATOM_TRANSMITTER_CONFIG_CLKSRC_PPLL;
1093
1094                         if (dig_encoder)
1095                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG2_ENCODER;
1096                         else
1097                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_DIG1_ENCODER;
1098
1099                         if ((rdev->flags & RADEON_IS_IGP) &&
1100                             (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_UNIPHY)) {
1101                                 if (is_dp ||
1102                                     !radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock)) {
1103                                         if (igp_lane_info & 0x1)
1104                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_3;
1105                                         else if (igp_lane_info & 0x2)
1106                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_4_7;
1107                                         else if (igp_lane_info & 0x4)
1108                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_11;
1109                                         else if (igp_lane_info & 0x8)
1110                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_12_15;
1111                                 } else {
1112                                         if (igp_lane_info & 0x3)
1113                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_0_7;
1114                                         else if (igp_lane_info & 0xc)
1115                                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LANE_8_15;
1116                                 }
1117                         }
1118
1119                         if (dig->linkb)
1120                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKB;
1121                         else
1122                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_LINKA;
1123
1124                         if (is_dp)
1125                                 args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1126                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1127                                 if (dig->coherent_mode)
1128                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_COHERENT;
1129                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1130                                         args.v1.ucConfig |= ATOM_TRANSMITTER_CONFIG_8LANE_LINK;
1131                         }
1132                         break;
1133                 case 2:
1134                         args.v2.ucAction = action;
1135                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1136                                 args.v2.usInitInfo = cpu_to_le16(connector_object_id);
1137                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1138                                 args.v2.asMode.ucLaneSel = lane_num;
1139                                 args.v2.asMode.ucLaneSet = lane_set;
1140                         } else {
1141                                 if (is_dp)
1142                                         args.v2.usPixelClock = cpu_to_le16(dp_clock / 10);
1143                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1144                                         args.v2.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1145                                 else
1146                                         args.v2.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1147                         }
1148
1149                         args.v2.acConfig.ucEncoderSel = dig_encoder;
1150                         if (dig->linkb)
1151                                 args.v2.acConfig.ucLinkSel = 1;
1152
1153                         switch (radeon_encoder->encoder_id) {
1154                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1155                                 args.v2.acConfig.ucTransmitterSel = 0;
1156                                 break;
1157                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1158                                 args.v2.acConfig.ucTransmitterSel = 1;
1159                                 break;
1160                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1161                                 args.v2.acConfig.ucTransmitterSel = 2;
1162                                 break;
1163                         }
1164
1165                         if (is_dp) {
1166                                 args.v2.acConfig.fCoherentMode = 1;
1167                                 args.v2.acConfig.fDPConnector = 1;
1168                         } else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1169                                 if (dig->coherent_mode)
1170                                         args.v2.acConfig.fCoherentMode = 1;
1171                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1172                                         args.v2.acConfig.fDualLinkConnector = 1;
1173                         }
1174                         break;
1175                 case 3:
1176                         args.v3.ucAction = action;
1177                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1178                                 args.v3.usInitInfo = cpu_to_le16(connector_object_id);
1179                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1180                                 args.v3.asMode.ucLaneSel = lane_num;
1181                                 args.v3.asMode.ucLaneSet = lane_set;
1182                         } else {
1183                                 if (is_dp)
1184                                         args.v3.usPixelClock = cpu_to_le16(dp_clock / 10);
1185                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1186                                         args.v3.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1187                                 else
1188                                         args.v3.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1189                         }
1190
1191                         if (is_dp)
1192                                 args.v3.ucLaneNum = dp_lane_count;
1193                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1194                                 args.v3.ucLaneNum = 8;
1195                         else
1196                                 args.v3.ucLaneNum = 4;
1197
1198                         if (dig->linkb)
1199                                 args.v3.acConfig.ucLinkSel = 1;
1200                         if (dig_encoder & 1)
1201                                 args.v3.acConfig.ucEncoderSel = 1;
1202
1203                         /* Select the PLL for the PHY
1204                          * DP PHY should be clocked from external src if there is
1205                          * one.
1206                          */
1207                         /* On DCE4, if there is an external clock, it generates the DP ref clock */
1208                         if (is_dp && rdev->clock.dp_extclk)
1209                                 args.v3.acConfig.ucRefClkSource = 2; /* external src */
1210                         else
1211                                 args.v3.acConfig.ucRefClkSource = pll_id;
1212
1213                         switch (radeon_encoder->encoder_id) {
1214                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1215                                 args.v3.acConfig.ucTransmitterSel = 0;
1216                                 break;
1217                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1218                                 args.v3.acConfig.ucTransmitterSel = 1;
1219                                 break;
1220                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1221                                 args.v3.acConfig.ucTransmitterSel = 2;
1222                                 break;
1223                         }
1224
1225                         if (is_dp)
1226                                 args.v3.acConfig.fCoherentMode = 1; /* DP requires coherent */
1227                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1228                                 if (dig->coherent_mode)
1229                                         args.v3.acConfig.fCoherentMode = 1;
1230                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1231                                         args.v3.acConfig.fDualLinkConnector = 1;
1232                         }
1233                         break;
1234                 case 4:
1235                         args.v4.ucAction = action;
1236                         if (action == ATOM_TRANSMITTER_ACTION_INIT) {
1237                                 args.v4.usInitInfo = cpu_to_le16(connector_object_id);
1238                         } else if (action == ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH) {
1239                                 args.v4.asMode.ucLaneSel = lane_num;
1240                                 args.v4.asMode.ucLaneSet = lane_set;
1241                         } else {
1242                                 if (is_dp)
1243                                         args.v4.usPixelClock = cpu_to_le16(dp_clock / 10);
1244                                 else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1245                                         args.v4.usPixelClock = cpu_to_le16((radeon_encoder->pixel_clock / 2) / 10);
1246                                 else
1247                                         args.v4.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1248                         }
1249
1250                         if (is_dp)
1251                                 args.v4.ucLaneNum = dp_lane_count;
1252                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1253                                 args.v4.ucLaneNum = 8;
1254                         else
1255                                 args.v4.ucLaneNum = 4;
1256
1257                         if (dig->linkb)
1258                                 args.v4.acConfig.ucLinkSel = 1;
1259                         if (dig_encoder & 1)
1260                                 args.v4.acConfig.ucEncoderSel = 1;
1261
1262                         /* Select the PLL for the PHY
1263                          * DP PHY should be clocked from external src if there is
1264                          * one.
1265                          */
1266                         /* On DCE5 DCPLL usually generates the DP ref clock */
1267                         if (is_dp) {
1268                                 if (rdev->clock.dp_extclk)
1269                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK;
1270                                 else
1271                                         args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL;
1272                         } else
1273                                 args.v4.acConfig.ucRefClkSource = pll_id;
1274
1275                         switch (radeon_encoder->encoder_id) {
1276                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1277                                 args.v4.acConfig.ucTransmitterSel = 0;
1278                                 break;
1279                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1280                                 args.v4.acConfig.ucTransmitterSel = 1;
1281                                 break;
1282                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1283                                 args.v4.acConfig.ucTransmitterSel = 2;
1284                                 break;
1285                         }
1286
1287                         if (is_dp)
1288                                 args.v4.acConfig.fCoherentMode = 1; /* DP requires coherent */
1289                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1290                                 if (dig->coherent_mode)
1291                                         args.v4.acConfig.fCoherentMode = 1;
1292                                 if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1293                                         args.v4.acConfig.fDualLinkConnector = 1;
1294                         }
1295                         break;
1296                 case 5:
1297                         args.v5.ucAction = action;
1298                         if (is_dp)
1299                                 args.v5.usSymClock = cpu_to_le16(dp_clock / 10);
1300                         else
1301                                 args.v5.usSymClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1302
1303                         switch (radeon_encoder->encoder_id) {
1304                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1305                                 if (dig->linkb)
1306                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYB;
1307                                 else
1308                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYA;
1309                                 break;
1310                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1311                                 if (dig->linkb)
1312                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYD;
1313                                 else
1314                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYC;
1315                                 break;
1316                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1317                                 if (dig->linkb)
1318                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYF;
1319                                 else
1320                                         args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYE;
1321                                 break;
1322                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1323                                 args.v5.ucPhyId = ATOM_PHY_ID_UNIPHYG;
1324                                 break;
1325                         }
1326                         if (is_dp)
1327                                 args.v5.ucLaneNum = dp_lane_count;
1328                         else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1329                                 args.v5.ucLaneNum = 8;
1330                         else
1331                                 args.v5.ucLaneNum = 4;
1332                         args.v5.ucConnObjId = connector_object_id;
1333                         args.v5.ucDigMode = atombios_get_encoder_mode(encoder);
1334
1335                         if (is_dp && rdev->clock.dp_extclk)
1336                                 args.v5.asConfig.ucPhyClkSrcId = ENCODER_REFCLK_SRC_EXTCLK;
1337                         else
1338                                 args.v5.asConfig.ucPhyClkSrcId = pll_id;
1339
1340                         if (is_dp)
1341                                 args.v5.asConfig.ucCoherentMode = 1; /* DP requires coherent */
1342                         else if (radeon_encoder->devices & (ATOM_DEVICE_DFP_SUPPORT)) {
1343                                 if (dig->coherent_mode)
1344                                         args.v5.asConfig.ucCoherentMode = 1;
1345                         }
1346                         if (hpd_id == RADEON_HPD_NONE)
1347                                 args.v5.asConfig.ucHPDSel = 0;
1348                         else
1349                                 args.v5.asConfig.ucHPDSel = hpd_id + 1;
1350                         args.v5.ucDigEncoderSel = (fe != -1) ? (1 << fe) : (1 << dig_encoder);
1351                         args.v5.ucDPLaneSet = lane_set;
1352                         break;
1353                 default:
1354                         DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1355                         break;
1356                 }
1357                 break;
1358         default:
1359                 DRM_ERROR("Unknown table version %d, %d\n", frev, crev);
1360                 break;
1361         }
1362
1363         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1364 }
1365
1366 void
1367 atombios_dig_transmitter_setup(struct drm_encoder *encoder, int action, uint8_t lane_num, uint8_t lane_set)
1368 {
1369         atombios_dig_transmitter_setup2(encoder, action, lane_num, lane_set, -1);
1370 }
1371
1372 bool
1373 atombios_set_edp_panel_power(struct drm_connector *connector, int action)
1374 {
1375         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1376         struct drm_device *dev = radeon_connector->base.dev;
1377         struct radeon_device *rdev = dev->dev_private;
1378         union dig_transmitter_control args;
1379         int index = GetIndexIntoMasterTable(COMMAND, UNIPHYTransmitterControl);
1380         uint8_t frev, crev;
1381
1382         if (connector->connector_type != DRM_MODE_CONNECTOR_eDP)
1383                 goto done;
1384
1385         if (!ASIC_IS_DCE4(rdev))
1386                 goto done;
1387
1388         if ((action != ATOM_TRANSMITTER_ACTION_POWER_ON) &&
1389             (action != ATOM_TRANSMITTER_ACTION_POWER_OFF))
1390                 goto done;
1391
1392         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1393                 goto done;
1394
1395         memset(&args, 0, sizeof(args));
1396
1397         args.v1.ucAction = action;
1398
1399         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1400
1401         /* wait for the panel to power up */
1402         if (action == ATOM_TRANSMITTER_ACTION_POWER_ON) {
1403                 int i;
1404
1405                 for (i = 0; i < 300; i++) {
1406                         if (radeon_hpd_sense(rdev, radeon_connector->hpd.hpd))
1407                                 return true;
1408                         mdelay(1);
1409                 }
1410                 return false;
1411         }
1412 done:
1413         return true;
1414 }
1415
1416 union external_encoder_control {
1417         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION v1;
1418         EXTERNAL_ENCODER_CONTROL_PS_ALLOCATION_V3 v3;
1419 };
1420
1421 static void
1422 atombios_external_encoder_setup(struct drm_encoder *encoder,
1423                                 struct drm_encoder *ext_encoder,
1424                                 int action)
1425 {
1426         struct drm_device *dev = encoder->dev;
1427         struct radeon_device *rdev = dev->dev_private;
1428         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1429         struct radeon_encoder *ext_radeon_encoder = to_radeon_encoder(ext_encoder);
1430         union external_encoder_control args;
1431         struct drm_connector *connector;
1432         int index = GetIndexIntoMasterTable(COMMAND, ExternalEncoderControl);
1433         u8 frev, crev;
1434         int dp_clock = 0;
1435         int dp_lane_count = 0;
1436         int connector_object_id = 0;
1437         u32 ext_enum = (ext_radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
1438
1439         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1440                 connector = radeon_get_connector_for_encoder_init(encoder);
1441         else
1442                 connector = radeon_get_connector_for_encoder(encoder);
1443
1444         if (connector) {
1445                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
1446                 struct radeon_connector_atom_dig *dig_connector =
1447                         radeon_connector->con_priv;
1448
1449                 dp_clock = dig_connector->dp_clock;
1450                 dp_lane_count = dig_connector->dp_lane_count;
1451                 connector_object_id =
1452                         (radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
1453         }
1454
1455         memset(&args, 0, sizeof(args));
1456
1457         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1458                 return;
1459
1460         switch (frev) {
1461         case 1:
1462                 /* no params on frev 1 */
1463                 break;
1464         case 2:
1465                 switch (crev) {
1466                 case 1:
1467                 case 2:
1468                         args.v1.sDigEncoder.ucAction = action;
1469                         args.v1.sDigEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1470                         args.v1.sDigEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1471
1472                         if (ENCODER_MODE_IS_DP(args.v1.sDigEncoder.ucEncoderMode)) {
1473                                 if (dp_clock == 270000)
1474                                         args.v1.sDigEncoder.ucConfig |= ATOM_ENCODER_CONFIG_DPLINKRATE_2_70GHZ;
1475                                 args.v1.sDigEncoder.ucLaneNum = dp_lane_count;
1476                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1477                                 args.v1.sDigEncoder.ucLaneNum = 8;
1478                         else
1479                                 args.v1.sDigEncoder.ucLaneNum = 4;
1480                         break;
1481                 case 3:
1482                         args.v3.sExtEncoder.ucAction = action;
1483                         if (action == EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT)
1484                                 args.v3.sExtEncoder.usConnectorId = cpu_to_le16(connector_object_id);
1485                         else
1486                                 args.v3.sExtEncoder.usPixelClock = cpu_to_le16(radeon_encoder->pixel_clock / 10);
1487                         args.v3.sExtEncoder.ucEncoderMode = atombios_get_encoder_mode(encoder);
1488
1489                         if (ENCODER_MODE_IS_DP(args.v3.sExtEncoder.ucEncoderMode)) {
1490                                 if (dp_clock == 270000)
1491                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_2_70GHZ;
1492                                 else if (dp_clock == 540000)
1493                                         args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_DPLINKRATE_5_40GHZ;
1494                                 args.v3.sExtEncoder.ucLaneNum = dp_lane_count;
1495                         } else if (radeon_dig_monitor_is_duallink(encoder, radeon_encoder->pixel_clock))
1496                                 args.v3.sExtEncoder.ucLaneNum = 8;
1497                         else
1498                                 args.v3.sExtEncoder.ucLaneNum = 4;
1499                         switch (ext_enum) {
1500                         case GRAPH_OBJECT_ENUM_ID1:
1501                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER1;
1502                                 break;
1503                         case GRAPH_OBJECT_ENUM_ID2:
1504                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER2;
1505                                 break;
1506                         case GRAPH_OBJECT_ENUM_ID3:
1507                                 args.v3.sExtEncoder.ucConfig |= EXTERNAL_ENCODER_CONFIG_V3_ENCODER3;
1508                                 break;
1509                         }
1510                         args.v3.sExtEncoder.ucBitPerColor = radeon_atom_get_bpc(encoder);
1511                         break;
1512                 default:
1513                         DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1514                         return;
1515                 }
1516                 break;
1517         default:
1518                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1519                 return;
1520         }
1521         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1522 }
1523
1524 static void
1525 atombios_yuv_setup(struct drm_encoder *encoder, bool enable)
1526 {
1527         struct drm_device *dev = encoder->dev;
1528         struct radeon_device *rdev = dev->dev_private;
1529         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1530         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1531         ENABLE_YUV_PS_ALLOCATION args;
1532         int index = GetIndexIntoMasterTable(COMMAND, EnableYUV);
1533         uint32_t temp, reg;
1534
1535         memset(&args, 0, sizeof(args));
1536
1537         if (rdev->family >= CHIP_R600)
1538                 reg = R600_BIOS_3_SCRATCH;
1539         else
1540                 reg = RADEON_BIOS_3_SCRATCH;
1541
1542         /* XXX: fix up scratch reg handling */
1543         temp = RREG32(reg);
1544         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1545                 WREG32(reg, (ATOM_S3_TV1_ACTIVE |
1546                              (radeon_crtc->crtc_id << 18)));
1547         else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1548                 WREG32(reg, (ATOM_S3_CV_ACTIVE | (radeon_crtc->crtc_id << 24)));
1549         else
1550                 WREG32(reg, 0);
1551
1552         if (enable)
1553                 args.ucEnable = ATOM_ENABLE;
1554         args.ucCRTC = radeon_crtc->crtc_id;
1555
1556         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1557
1558         WREG32(reg, temp);
1559 }
1560
1561 static void
1562 radeon_atom_encoder_dpms_avivo(struct drm_encoder *encoder, int mode)
1563 {
1564         struct drm_device *dev = encoder->dev;
1565         struct radeon_device *rdev = dev->dev_private;
1566         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1567         DISPLAY_DEVICE_OUTPUT_CONTROL_PS_ALLOCATION args;
1568         int index = 0;
1569
1570         memset(&args, 0, sizeof(args));
1571
1572         switch (radeon_encoder->encoder_id) {
1573         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1574         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1575                 index = GetIndexIntoMasterTable(COMMAND, TMDSAOutputControl);
1576                 break;
1577         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1578         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1579         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1580                 index = GetIndexIntoMasterTable(COMMAND, DVOOutputControl);
1581                 break;
1582         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1583                 index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1584                 break;
1585         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1586                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1587                         index = GetIndexIntoMasterTable(COMMAND, LCD1OutputControl);
1588                 else
1589                         index = GetIndexIntoMasterTable(COMMAND, LVTMAOutputControl);
1590                 break;
1591         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1592         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1593                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1594                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1595                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1596                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1597                 else
1598                         index = GetIndexIntoMasterTable(COMMAND, DAC1OutputControl);
1599                 break;
1600         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1601         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1602                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1603                         index = GetIndexIntoMasterTable(COMMAND, TV1OutputControl);
1604                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1605                         index = GetIndexIntoMasterTable(COMMAND, CV1OutputControl);
1606                 else
1607                         index = GetIndexIntoMasterTable(COMMAND, DAC2OutputControl);
1608                 break;
1609         default:
1610                 return;
1611         }
1612
1613         switch (mode) {
1614         case DRM_MODE_DPMS_ON:
1615                 args.ucAction = ATOM_ENABLE;
1616                 /* workaround for DVOOutputControl on some RS690 systems */
1617                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DDI) {
1618                         u32 reg = RREG32(RADEON_BIOS_3_SCRATCH);
1619                         WREG32(RADEON_BIOS_3_SCRATCH, reg & ~ATOM_S3_DFP2I_ACTIVE);
1620                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1621                         WREG32(RADEON_BIOS_3_SCRATCH, reg);
1622                 } else
1623                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1624                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1625                         if (rdev->mode_info.bl_encoder) {
1626                                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1627
1628                                 atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
1629                         } else {
1630                                 args.ucAction = ATOM_LCD_BLON;
1631                                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1632                         }
1633                 }
1634                 break;
1635         case DRM_MODE_DPMS_STANDBY:
1636         case DRM_MODE_DPMS_SUSPEND:
1637         case DRM_MODE_DPMS_OFF:
1638                 args.ucAction = ATOM_DISABLE;
1639                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1640                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1641                         args.ucAction = ATOM_LCD_BLOFF;
1642                         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1643                 }
1644                 break;
1645         }
1646 }
1647
1648 static void
1649 radeon_atom_encoder_dpms_dig(struct drm_encoder *encoder, int mode)
1650 {
1651         struct drm_device *dev = encoder->dev;
1652         struct radeon_device *rdev = dev->dev_private;
1653         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1654         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
1655         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
1656         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1657         struct radeon_connector *radeon_connector = NULL;
1658         struct radeon_connector_atom_dig *radeon_dig_connector = NULL;
1659         bool travis_quirk = false;
1660
1661         if (connector) {
1662                 radeon_connector = to_radeon_connector(connector);
1663                 radeon_dig_connector = radeon_connector->con_priv;
1664                 if ((radeon_connector_encoder_get_dp_bridge_encoder_id(connector) ==
1665                      ENCODER_OBJECT_ID_TRAVIS) &&
1666                     (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) &&
1667                     !ASIC_IS_DCE5(rdev))
1668                         travis_quirk = true;
1669         }
1670
1671         switch (mode) {
1672         case DRM_MODE_DPMS_ON:
1673                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE5(rdev)) {
1674                         if (!connector)
1675                                 dig->panel_mode = DP_PANEL_MODE_EXTERNAL_DP_MODE;
1676                         else
1677                                 dig->panel_mode = radeon_dp_get_panel_mode(encoder, connector);
1678
1679                         /* setup and enable the encoder */
1680                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1681                         atombios_dig_encoder_setup(encoder,
1682                                                    ATOM_ENCODER_CMD_SETUP_PANEL_MODE,
1683                                                    dig->panel_mode);
1684                         if (ext_encoder) {
1685                                 if (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev))
1686                                         atombios_external_encoder_setup(encoder, ext_encoder,
1687                                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_SETUP);
1688                         }
1689                 } else if (ASIC_IS_DCE4(rdev)) {
1690                         /* setup and enable the encoder */
1691                         atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_SETUP, 0);
1692                 } else {
1693                         /* setup and enable the encoder and transmitter */
1694                         atombios_dig_encoder_setup(encoder, ATOM_ENABLE, 0);
1695                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_SETUP, 0, 0);
1696                 }
1697                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1698                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1699                                 atombios_set_edp_panel_power(connector,
1700                                                              ATOM_TRANSMITTER_ACTION_POWER_ON);
1701                                 radeon_dig_connector->edp_on = true;
1702                         }
1703                 }
1704                 /* enable the transmitter */
1705                 atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_ENABLE, 0, 0);
1706                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1707                         /* DP_SET_POWER_D0 is set in radeon_dp_link_train */
1708                         radeon_dp_link_train(encoder, connector);
1709                         if (ASIC_IS_DCE4(rdev))
1710                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_ON, 0);
1711                 }
1712                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1713                         if (rdev->mode_info.bl_encoder)
1714                                 atombios_set_backlight_level(radeon_encoder, dig->backlight_level);
1715                         else
1716                                 atombios_dig_transmitter_setup(encoder,
1717                                                                ATOM_TRANSMITTER_ACTION_LCD_BLON, 0, 0);
1718                 }
1719                 if (ext_encoder)
1720                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_ENABLE);
1721                 break;
1722         case DRM_MODE_DPMS_STANDBY:
1723         case DRM_MODE_DPMS_SUSPEND:
1724         case DRM_MODE_DPMS_OFF:
1725
1726                 /* don't power off encoders with active MST links */
1727                 if (dig->active_mst_links)
1728                         return;
1729
1730                 if (ASIC_IS_DCE4(rdev)) {
1731                         if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector)
1732                                 atombios_dig_encoder_setup(encoder, ATOM_ENCODER_CMD_DP_VIDEO_OFF, 0);
1733                 }
1734                 if (ext_encoder)
1735                         atombios_external_encoder_setup(encoder, ext_encoder, ATOM_DISABLE);
1736                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
1737                         atombios_dig_transmitter_setup(encoder,
1738                                                        ATOM_TRANSMITTER_ACTION_LCD_BLOFF, 0, 0);
1739
1740                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) &&
1741                     connector && !travis_quirk)
1742                         radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1743                 if (ASIC_IS_DCE4(rdev)) {
1744                         /* disable the transmitter */
1745                         atombios_dig_transmitter_setup(encoder,
1746                                                        ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1747                 } else {
1748                         /* disable the encoder and transmitter */
1749                         atombios_dig_transmitter_setup(encoder,
1750                                                        ATOM_TRANSMITTER_ACTION_DISABLE, 0, 0);
1751                         atombios_dig_encoder_setup(encoder, ATOM_DISABLE, 0);
1752                 }
1753                 if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(encoder)) && connector) {
1754                         if (travis_quirk)
1755                                 radeon_dp_set_rx_power_state(connector, DP_SET_POWER_D3);
1756                         if (connector->connector_type == DRM_MODE_CONNECTOR_eDP) {
1757                                 atombios_set_edp_panel_power(connector,
1758                                                              ATOM_TRANSMITTER_ACTION_POWER_OFF);
1759                                 radeon_dig_connector->edp_on = false;
1760                         }
1761                 }
1762                 break;
1763         }
1764 }
1765
1766 static void
1767 radeon_atom_encoder_dpms(struct drm_encoder *encoder, int mode)
1768 {
1769         struct drm_device *dev = encoder->dev;
1770         struct radeon_device *rdev = dev->dev_private;
1771         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1772         int encoder_mode = atombios_get_encoder_mode(encoder);
1773
1774         DRM_DEBUG_KMS("encoder dpms %d to mode %d, devices %08x, active_devices %08x\n",
1775                   radeon_encoder->encoder_id, mode, radeon_encoder->devices,
1776                   radeon_encoder->active_device);
1777
1778         if ((radeon_audio != 0) &&
1779             ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
1780              ENCODER_MODE_IS_DP(encoder_mode)))
1781                 radeon_audio_dpms(encoder, mode);
1782
1783         switch (radeon_encoder->encoder_id) {
1784         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1785         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1786         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1787         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1788         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1789         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1790         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1791         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1792                 radeon_atom_encoder_dpms_avivo(encoder, mode);
1793                 break;
1794         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1795         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1796         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1797         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1798         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1799                 radeon_atom_encoder_dpms_dig(encoder, mode);
1800                 break;
1801         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1802                 if (ASIC_IS_DCE5(rdev)) {
1803                         switch (mode) {
1804                         case DRM_MODE_DPMS_ON:
1805                                 atombios_dvo_setup(encoder, ATOM_ENABLE);
1806                                 break;
1807                         case DRM_MODE_DPMS_STANDBY:
1808                         case DRM_MODE_DPMS_SUSPEND:
1809                         case DRM_MODE_DPMS_OFF:
1810                                 atombios_dvo_setup(encoder, ATOM_DISABLE);
1811                                 break;
1812                         }
1813                 } else if (ASIC_IS_DCE3(rdev))
1814                         radeon_atom_encoder_dpms_dig(encoder, mode);
1815                 else
1816                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1817                 break;
1818         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1819         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1820                 if (ASIC_IS_DCE5(rdev)) {
1821                         switch (mode) {
1822                         case DRM_MODE_DPMS_ON:
1823                                 atombios_dac_setup(encoder, ATOM_ENABLE);
1824                                 break;
1825                         case DRM_MODE_DPMS_STANDBY:
1826                         case DRM_MODE_DPMS_SUSPEND:
1827                         case DRM_MODE_DPMS_OFF:
1828                                 atombios_dac_setup(encoder, ATOM_DISABLE);
1829                                 break;
1830                         }
1831                 } else
1832                         radeon_atom_encoder_dpms_avivo(encoder, mode);
1833                 break;
1834         default:
1835                 return;
1836         }
1837
1838         radeon_atombios_encoder_dpms_scratch_regs(encoder, (mode == DRM_MODE_DPMS_ON) ? true : false);
1839
1840 }
1841
1842 union crtc_source_param {
1843         SELECT_CRTC_SOURCE_PS_ALLOCATION v1;
1844         SELECT_CRTC_SOURCE_PARAMETERS_V2 v2;
1845 };
1846
1847 static void
1848 atombios_set_encoder_crtc_source(struct drm_encoder *encoder)
1849 {
1850         struct drm_device *dev = encoder->dev;
1851         struct radeon_device *rdev = dev->dev_private;
1852         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
1853         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
1854         union crtc_source_param args;
1855         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
1856         uint8_t frev, crev;
1857         struct radeon_encoder_atom_dig *dig;
1858
1859         memset(&args, 0, sizeof(args));
1860
1861         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
1862                 return;
1863
1864         switch (frev) {
1865         case 1:
1866                 switch (crev) {
1867                 case 1:
1868                 default:
1869                         if (ASIC_IS_AVIVO(rdev))
1870                                 args.v1.ucCRTC = radeon_crtc->crtc_id;
1871                         else {
1872                                 if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1)
1873                                         args.v1.ucCRTC = radeon_crtc->crtc_id;
1874                                 else
1875                                         args.v1.ucCRTC = radeon_crtc->crtc_id << 2;
1876                         }
1877                         switch (radeon_encoder->encoder_id) {
1878                         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
1879                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
1880                                 args.v1.ucDevice = ATOM_DEVICE_DFP1_INDEX;
1881                                 break;
1882                         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
1883                         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
1884                                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT)
1885                                         args.v1.ucDevice = ATOM_DEVICE_LCD1_INDEX;
1886                                 else
1887                                         args.v1.ucDevice = ATOM_DEVICE_DFP3_INDEX;
1888                                 break;
1889                         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
1890                         case ENCODER_OBJECT_ID_INTERNAL_DDI:
1891                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1892                                 args.v1.ucDevice = ATOM_DEVICE_DFP2_INDEX;
1893                                 break;
1894                         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
1895                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1896                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1897                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1898                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1899                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1900                                 else
1901                                         args.v1.ucDevice = ATOM_DEVICE_CRT1_INDEX;
1902                                 break;
1903                         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
1904                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1905                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1906                                         args.v1.ucDevice = ATOM_DEVICE_TV1_INDEX;
1907                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1908                                         args.v1.ucDevice = ATOM_DEVICE_CV_INDEX;
1909                                 else
1910                                         args.v1.ucDevice = ATOM_DEVICE_CRT2_INDEX;
1911                                 break;
1912                         }
1913                         break;
1914                 case 2:
1915                         args.v2.ucCRTC = radeon_crtc->crtc_id;
1916                         if (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE) {
1917                                 struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
1918
1919                                 if (connector->connector_type == DRM_MODE_CONNECTOR_LVDS)
1920                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1921                                 else if (connector->connector_type == DRM_MODE_CONNECTOR_VGA)
1922                                         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_CRT;
1923                                 else
1924                                         args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1925                         } else if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
1926                                 args.v2.ucEncodeMode = ATOM_ENCODER_MODE_LVDS;
1927                         } else {
1928                                 args.v2.ucEncodeMode = atombios_get_encoder_mode(encoder);
1929                         }
1930                         switch (radeon_encoder->encoder_id) {
1931                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
1932                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
1933                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
1934                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
1935                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
1936                                 dig = radeon_encoder->enc_priv;
1937                                 switch (dig->dig_encoder) {
1938                                 case 0:
1939                                         args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
1940                                         break;
1941                                 case 1:
1942                                         args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
1943                                         break;
1944                                 case 2:
1945                                         args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
1946                                         break;
1947                                 case 3:
1948                                         args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
1949                                         break;
1950                                 case 4:
1951                                         args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
1952                                         break;
1953                                 case 5:
1954                                         args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
1955                                         break;
1956                                 case 6:
1957                                         args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
1958                                         break;
1959                                 }
1960                                 break;
1961                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
1962                                 args.v2.ucEncoderID = ASIC_INT_DVO_ENCODER_ID;
1963                                 break;
1964                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
1965                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1966                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1967                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1968                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1969                                 else
1970                                         args.v2.ucEncoderID = ASIC_INT_DAC1_ENCODER_ID;
1971                                 break;
1972                         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
1973                                 if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT))
1974                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1975                                 else if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT))
1976                                         args.v2.ucEncoderID = ASIC_INT_TV_ENCODER_ID;
1977                                 else
1978                                         args.v2.ucEncoderID = ASIC_INT_DAC2_ENCODER_ID;
1979                                 break;
1980                         }
1981                         break;
1982                 }
1983                 break;
1984         default:
1985                 DRM_ERROR("Unknown table version: %d, %d\n", frev, crev);
1986                 return;
1987         }
1988
1989         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
1990
1991         /* update scratch regs with new routing */
1992         radeon_atombios_encoder_crtc_scratch_regs(encoder, radeon_crtc->crtc_id);
1993 }
1994
1995 void
1996 atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder, int fe)
1997 {
1998         struct drm_device *dev = encoder->dev;
1999         struct radeon_device *rdev = dev->dev_private;
2000         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2001         int index = GetIndexIntoMasterTable(COMMAND, SelectCRTC_Source);
2002         uint8_t frev, crev;
2003         union crtc_source_param args;
2004
2005         memset(&args, 0, sizeof(args));
2006
2007         if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2008                 return;
2009
2010         if (frev != 1 && crev != 2)
2011                 DRM_ERROR("Unknown table for MST %d, %d\n", frev, crev);
2012
2013         args.v2.ucCRTC = radeon_crtc->crtc_id;
2014         args.v2.ucEncodeMode = ATOM_ENCODER_MODE_DP_MST;
2015
2016         switch (fe) {
2017         case 0:
2018                 args.v2.ucEncoderID = ASIC_INT_DIG1_ENCODER_ID;
2019                 break;
2020         case 1:
2021                 args.v2.ucEncoderID = ASIC_INT_DIG2_ENCODER_ID;
2022                 break;
2023         case 2:
2024                 args.v2.ucEncoderID = ASIC_INT_DIG3_ENCODER_ID;
2025                 break;
2026         case 3:
2027                 args.v2.ucEncoderID = ASIC_INT_DIG4_ENCODER_ID;
2028                 break;
2029         case 4:
2030                 args.v2.ucEncoderID = ASIC_INT_DIG5_ENCODER_ID;
2031                 break;
2032         case 5:
2033                 args.v2.ucEncoderID = ASIC_INT_DIG6_ENCODER_ID;
2034                 break;
2035         case 6:
2036                 args.v2.ucEncoderID = ASIC_INT_DIG7_ENCODER_ID;
2037                 break;
2038         }
2039         atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2040 }
2041
2042 static void
2043 atombios_apply_encoder_quirks(struct drm_encoder *encoder,
2044                               struct drm_display_mode *mode)
2045 {
2046         struct drm_device *dev = encoder->dev;
2047         struct radeon_device *rdev = dev->dev_private;
2048         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2049         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2050
2051         /* Funky macbooks */
2052         if ((rdev->pdev->device == 0x71C5) &&
2053             (rdev->pdev->subsystem_vendor == 0x106b) &&
2054             (rdev->pdev->subsystem_device == 0x0080)) {
2055                 if (radeon_encoder->devices & ATOM_DEVICE_LCD1_SUPPORT) {
2056                         uint32_t lvtma_bit_depth_control = RREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL);
2057
2058                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_TRUNCATE_EN;
2059                         lvtma_bit_depth_control &= ~AVIVO_LVTMA_BIT_DEPTH_CONTROL_SPATIAL_DITHER_EN;
2060
2061                         WREG32(AVIVO_LVTMA_BIT_DEPTH_CONTROL, lvtma_bit_depth_control);
2062                 }
2063         }
2064
2065         /* set scaler clears this on some chips */
2066         if (ASIC_IS_AVIVO(rdev) &&
2067             (!(radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT)))) {
2068                 if (ASIC_IS_DCE8(rdev)) {
2069                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2070                                 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset,
2071                                        CIK_INTERLEAVE_EN);
2072                         else
2073                                 WREG32(CIK_LB_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2074                 } else if (ASIC_IS_DCE4(rdev)) {
2075                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2076                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset,
2077                                        EVERGREEN_INTERLEAVE_EN);
2078                         else
2079                                 WREG32(EVERGREEN_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2080                 } else {
2081                         if (mode->flags & DRM_MODE_FLAG_INTERLACE)
2082                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset,
2083                                        AVIVO_D1MODE_INTERLEAVE_EN);
2084                         else
2085                                 WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0);
2086                 }
2087         }
2088 }
2089
2090 void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx)
2091 {
2092         if (enc_idx < 0)
2093                 return;
2094         rdev->mode_info.active_encoders &= ~(1 << enc_idx);
2095 }
2096
2097 int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx)
2098 {
2099         struct drm_device *dev = encoder->dev;
2100         struct radeon_device *rdev = dev->dev_private;
2101         struct radeon_crtc *radeon_crtc = to_radeon_crtc(encoder->crtc);
2102         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2103         struct drm_encoder *test_encoder;
2104         struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2105         uint32_t dig_enc_in_use = 0;
2106         int enc_idx = -1;
2107
2108         if (fe_idx >= 0) {
2109                 enc_idx = fe_idx;
2110                 goto assigned;
2111         }
2112         if (ASIC_IS_DCE6(rdev)) {
2113                 /* DCE6 */
2114                 switch (radeon_encoder->encoder_id) {
2115                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2116                         if (dig->linkb)
2117                                 enc_idx = 1;
2118                         else
2119                                 enc_idx = 0;
2120                         break;
2121                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2122                         if (dig->linkb)
2123                                 enc_idx = 3;
2124                         else
2125                                 enc_idx = 2;
2126                         break;
2127                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2128                         if (dig->linkb)
2129                                 enc_idx = 5;
2130                         else
2131                                 enc_idx = 4;
2132                         break;
2133                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2134                         enc_idx = 6;
2135                         break;
2136                 }
2137                 goto assigned;
2138         } else if (ASIC_IS_DCE4(rdev)) {
2139                 /* DCE4/5 */
2140                 if (ASIC_IS_DCE41(rdev) && !ASIC_IS_DCE61(rdev)) {
2141                         /* ontario follows DCE4 */
2142                         if (rdev->family == CHIP_PALM) {
2143                                 if (dig->linkb)
2144                                         enc_idx = 1;
2145                                 else
2146                                         enc_idx = 0;
2147                         } else
2148                                 /* llano follows DCE3.2 */
2149                                 enc_idx = radeon_crtc->crtc_id;
2150                 } else {
2151                         switch (radeon_encoder->encoder_id) {
2152                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2153                                 if (dig->linkb)
2154                                         enc_idx = 1;
2155                                 else
2156                                         enc_idx = 0;
2157                                 break;
2158                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2159                                 if (dig->linkb)
2160                                         enc_idx = 3;
2161                                 else
2162                                         enc_idx = 2;
2163                                 break;
2164                         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2165                                 if (dig->linkb)
2166                                         enc_idx = 5;
2167                                 else
2168                                         enc_idx = 4;
2169                                 break;
2170                         }
2171                 }
2172                 goto assigned;
2173         }
2174
2175         /*
2176          * On DCE32 any encoder can drive any block so usually just use crtc id,
2177          * but Apple thinks different at least on iMac10,1, so there use linkb,
2178          * otherwise the internal eDP panel will stay dark.
2179          */
2180         if (ASIC_IS_DCE32(rdev)) {
2181                 if (dmi_match(DMI_PRODUCT_NAME, "iMac10,1"))
2182                         enc_idx = (dig->linkb) ? 1 : 0;
2183                 else
2184                         enc_idx = radeon_crtc->crtc_id;
2185
2186                 goto assigned;
2187         }
2188
2189         /* on DCE3 - LVTMA can only be driven by DIGB */
2190         list_for_each_entry(test_encoder, &dev->mode_config.encoder_list, head) {
2191                 struct radeon_encoder *radeon_test_encoder;
2192
2193                 if (encoder == test_encoder)
2194                         continue;
2195
2196                 if (!radeon_encoder_is_digital(test_encoder))
2197                         continue;
2198
2199                 radeon_test_encoder = to_radeon_encoder(test_encoder);
2200                 dig = radeon_test_encoder->enc_priv;
2201
2202                 if (dig->dig_encoder >= 0)
2203                         dig_enc_in_use |= (1 << dig->dig_encoder);
2204         }
2205
2206         if (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA) {
2207                 if (dig_enc_in_use & 0x2)
2208                         DRM_ERROR("LVDS required digital encoder 2 but it was in use - stealing\n");
2209                 return 1;
2210         }
2211         if (!(dig_enc_in_use & 1))
2212                 return 0;
2213         return 1;
2214
2215 assigned:
2216         if (enc_idx == -1) {
2217                 DRM_ERROR("Got encoder index incorrect - returning 0\n");
2218                 return 0;
2219         }
2220         if (rdev->mode_info.active_encoders & (1 << enc_idx))
2221                 DRM_ERROR("chosen encoder in use %d\n", enc_idx);
2222
2223         rdev->mode_info.active_encoders |= (1 << enc_idx);
2224         return enc_idx;
2225 }
2226
2227 /* This only needs to be called once at startup */
2228 void
2229 radeon_atom_encoder_init(struct radeon_device *rdev)
2230 {
2231         struct drm_device *dev = rdev->ddev;
2232         struct drm_encoder *encoder;
2233
2234         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2235                 struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2236                 struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2237
2238                 switch (radeon_encoder->encoder_id) {
2239                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2240                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2241                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2242                 case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2243                 case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2244                         atombios_dig_transmitter_setup(encoder, ATOM_TRANSMITTER_ACTION_INIT, 0, 0);
2245                         break;
2246                 default:
2247                         break;
2248                 }
2249
2250                 if (ext_encoder && (ASIC_IS_DCE41(rdev) || ASIC_IS_DCE61(rdev)))
2251                         atombios_external_encoder_setup(encoder, ext_encoder,
2252                                                         EXTERNAL_ENCODER_ACTION_V3_ENCODER_INIT);
2253         }
2254 }
2255
2256 static void
2257 radeon_atom_encoder_mode_set(struct drm_encoder *encoder,
2258                              struct drm_display_mode *mode,
2259                              struct drm_display_mode *adjusted_mode)
2260 {
2261         struct drm_device *dev = encoder->dev;
2262         struct radeon_device *rdev = dev->dev_private;
2263         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2264         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2265         int encoder_mode;
2266
2267         radeon_encoder->pixel_clock = adjusted_mode->clock;
2268
2269         /* need to call this here rather than in prepare() since we need some crtc info */
2270         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2271
2272         if (ASIC_IS_AVIVO(rdev) && !ASIC_IS_DCE4(rdev)) {
2273                 if (radeon_encoder->active_device & (ATOM_DEVICE_CV_SUPPORT | ATOM_DEVICE_TV_SUPPORT))
2274                         atombios_yuv_setup(encoder, true);
2275                 else
2276                         atombios_yuv_setup(encoder, false);
2277         }
2278
2279         switch (radeon_encoder->encoder_id) {
2280         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2281         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2282         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2283         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2284                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_ENABLE);
2285                 break;
2286         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2287         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2288         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2289         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2290         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2291                 /* handled in dpms */
2292                 break;
2293         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2294         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2295         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2296                 atombios_dvo_setup(encoder, ATOM_ENABLE);
2297                 break;
2298         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2299         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2300         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2301         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2302                 atombios_dac_setup(encoder, ATOM_ENABLE);
2303                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT)) {
2304                         if (radeon_encoder->active_device & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2305                                 atombios_tv_setup(encoder, ATOM_ENABLE);
2306                         else
2307                                 atombios_tv_setup(encoder, ATOM_DISABLE);
2308                 }
2309                 break;
2310         }
2311
2312         atombios_apply_encoder_quirks(encoder, adjusted_mode);
2313
2314         encoder_mode = atombios_get_encoder_mode(encoder);
2315         if (connector && (radeon_audio != 0) &&
2316             ((encoder_mode == ATOM_ENCODER_MODE_HDMI) ||
2317              ENCODER_MODE_IS_DP(encoder_mode)))
2318                 radeon_audio_mode_set(encoder, adjusted_mode);
2319 }
2320
2321 static bool
2322 atombios_dac_load_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2323 {
2324         struct drm_device *dev = encoder->dev;
2325         struct radeon_device *rdev = dev->dev_private;
2326         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2327         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2328
2329         if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT |
2330                                        ATOM_DEVICE_CV_SUPPORT |
2331                                        ATOM_DEVICE_CRT_SUPPORT)) {
2332                 DAC_LOAD_DETECTION_PS_ALLOCATION args;
2333                 int index = GetIndexIntoMasterTable(COMMAND, DAC_LoadDetection);
2334                 uint8_t frev, crev;
2335
2336                 memset(&args, 0, sizeof(args));
2337
2338                 if (!atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, &crev))
2339                         return false;
2340
2341                 args.sDacload.ucMisc = 0;
2342
2343                 if ((radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_DAC1) ||
2344                     (radeon_encoder->encoder_id == ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1))
2345                         args.sDacload.ucDacType = ATOM_DAC_A;
2346                 else
2347                         args.sDacload.ucDacType = ATOM_DAC_B;
2348
2349                 if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT)
2350                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT1_SUPPORT);
2351                 else if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT)
2352                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CRT2_SUPPORT);
2353                 else if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2354                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_CV_SUPPORT);
2355                         if (crev >= 3)
2356                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2357                 } else if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2358                         args.sDacload.usDeviceID = cpu_to_le16(ATOM_DEVICE_TV1_SUPPORT);
2359                         if (crev >= 3)
2360                                 args.sDacload.ucMisc = DAC_LOAD_MISC_YPrPb;
2361                 }
2362
2363                 atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args);
2364
2365                 return true;
2366         } else
2367                 return false;
2368 }
2369
2370 static enum drm_connector_status
2371 radeon_atom_dac_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2372 {
2373         struct drm_device *dev = encoder->dev;
2374         struct radeon_device *rdev = dev->dev_private;
2375         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2376         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2377         uint32_t bios_0_scratch;
2378
2379         if (!atombios_dac_load_detect(encoder, connector)) {
2380                 DRM_DEBUG_KMS("detect returned false \n");
2381                 return connector_status_unknown;
2382         }
2383
2384         if (rdev->family >= CHIP_R600)
2385                 bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2386         else
2387                 bios_0_scratch = RREG32(RADEON_BIOS_0_SCRATCH);
2388
2389         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2390         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2391                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2392                         return connector_status_connected;
2393         }
2394         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2395                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2396                         return connector_status_connected;
2397         }
2398         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2399                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2400                         return connector_status_connected;
2401         }
2402         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2403                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2404                         return connector_status_connected; /* CTV */
2405                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2406                         return connector_status_connected; /* STV */
2407         }
2408         return connector_status_disconnected;
2409 }
2410
2411 static enum drm_connector_status
2412 radeon_atom_dig_detect(struct drm_encoder *encoder, struct drm_connector *connector)
2413 {
2414         struct drm_device *dev = encoder->dev;
2415         struct radeon_device *rdev = dev->dev_private;
2416         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2417         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2418         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2419         u32 bios_0_scratch;
2420
2421         if (!ASIC_IS_DCE4(rdev))
2422                 return connector_status_unknown;
2423
2424         if (!ext_encoder)
2425                 return connector_status_unknown;
2426
2427         if ((radeon_connector->devices & ATOM_DEVICE_CRT_SUPPORT) == 0)
2428                 return connector_status_unknown;
2429
2430         /* load detect on the dp bridge */
2431         atombios_external_encoder_setup(encoder, ext_encoder,
2432                                         EXTERNAL_ENCODER_ACTION_V3_DACLOAD_DETECTION);
2433
2434         bios_0_scratch = RREG32(R600_BIOS_0_SCRATCH);
2435
2436         DRM_DEBUG_KMS("Bios 0 scratch %x %08x\n", bios_0_scratch, radeon_encoder->devices);
2437         if (radeon_connector->devices & ATOM_DEVICE_CRT1_SUPPORT) {
2438                 if (bios_0_scratch & ATOM_S0_CRT1_MASK)
2439                         return connector_status_connected;
2440         }
2441         if (radeon_connector->devices & ATOM_DEVICE_CRT2_SUPPORT) {
2442                 if (bios_0_scratch & ATOM_S0_CRT2_MASK)
2443                         return connector_status_connected;
2444         }
2445         if (radeon_connector->devices & ATOM_DEVICE_CV_SUPPORT) {
2446                 if (bios_0_scratch & (ATOM_S0_CV_MASK|ATOM_S0_CV_MASK_A))
2447                         return connector_status_connected;
2448         }
2449         if (radeon_connector->devices & ATOM_DEVICE_TV1_SUPPORT) {
2450                 if (bios_0_scratch & (ATOM_S0_TV1_COMPOSITE | ATOM_S0_TV1_COMPOSITE_A))
2451                         return connector_status_connected; /* CTV */
2452                 else if (bios_0_scratch & (ATOM_S0_TV1_SVIDEO | ATOM_S0_TV1_SVIDEO_A))
2453                         return connector_status_connected; /* STV */
2454         }
2455         return connector_status_disconnected;
2456 }
2457
2458 void
2459 radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder)
2460 {
2461         struct drm_encoder *ext_encoder = radeon_get_external_encoder(encoder);
2462
2463         if (ext_encoder)
2464                 /* ddc_setup on the dp bridge */
2465                 atombios_external_encoder_setup(encoder, ext_encoder,
2466                                                 EXTERNAL_ENCODER_ACTION_V3_DDC_SETUP);
2467
2468 }
2469
2470 static void radeon_atom_encoder_prepare(struct drm_encoder *encoder)
2471 {
2472         struct radeon_device *rdev = encoder->dev->dev_private;
2473         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2474         struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
2475
2476         if ((radeon_encoder->active_device &
2477              (ATOM_DEVICE_DFP_SUPPORT | ATOM_DEVICE_LCD_SUPPORT)) ||
2478             (radeon_encoder_get_dp_bridge_encoder_id(encoder) !=
2479              ENCODER_OBJECT_ID_NONE)) {
2480                 struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv;
2481                 if (dig) {
2482                         if (dig->dig_encoder >= 0)
2483                                 radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2484                         dig->dig_encoder = radeon_atom_pick_dig_encoder(encoder, -1);
2485                         if (radeon_encoder->active_device & ATOM_DEVICE_DFP_SUPPORT) {
2486                                 if (rdev->family >= CHIP_R600)
2487                                         dig->afmt = rdev->mode_info.afmt[dig->dig_encoder];
2488                                 else
2489                                         /* RS600/690/740 have only 1 afmt block */
2490                                         dig->afmt = rdev->mode_info.afmt[0];
2491                         }
2492                 }
2493         }
2494
2495         radeon_atom_output_lock(encoder, true);
2496
2497         if (connector) {
2498                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
2499
2500                 /* select the clock/data port if it uses a router */
2501                 if (radeon_connector->router.cd_valid)
2502                         radeon_router_select_cd_port(radeon_connector);
2503
2504                 /* turn eDP panel on for mode set */
2505                 if (connector->connector_type == DRM_MODE_CONNECTOR_eDP)
2506                         atombios_set_edp_panel_power(connector,
2507                                                      ATOM_TRANSMITTER_ACTION_POWER_ON);
2508         }
2509
2510         /* this is needed for the pll/ss setup to work correctly in some cases */
2511         atombios_set_encoder_crtc_source(encoder);
2512         /* set up the FMT blocks */
2513         if (ASIC_IS_DCE8(rdev))
2514                 dce8_program_fmt(encoder);
2515         else if (ASIC_IS_DCE4(rdev))
2516                 dce4_program_fmt(encoder);
2517         else if (ASIC_IS_DCE3(rdev))
2518                 dce3_program_fmt(encoder);
2519         else if (ASIC_IS_AVIVO(rdev))
2520                 avivo_program_fmt(encoder);
2521 }
2522
2523 static void radeon_atom_encoder_commit(struct drm_encoder *encoder)
2524 {
2525         /* need to call this here as we need the crtc set up */
2526         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_ON);
2527         radeon_atom_output_lock(encoder, false);
2528 }
2529
2530 static void radeon_atom_encoder_disable(struct drm_encoder *encoder)
2531 {
2532         struct drm_device *dev = encoder->dev;
2533         struct radeon_device *rdev = dev->dev_private;
2534         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2535         struct radeon_encoder_atom_dig *dig;
2536
2537         /* check for pre-DCE3 cards with shared encoders;
2538          * can't really use the links individually, so don't disable
2539          * the encoder if it's in use by another connector
2540          */
2541         if (!ASIC_IS_DCE3(rdev)) {
2542                 struct drm_encoder *other_encoder;
2543                 struct radeon_encoder *other_radeon_encoder;
2544
2545                 list_for_each_entry(other_encoder, &dev->mode_config.encoder_list, head) {
2546                         other_radeon_encoder = to_radeon_encoder(other_encoder);
2547                         if ((radeon_encoder->encoder_id == other_radeon_encoder->encoder_id) &&
2548                             drm_helper_encoder_in_use(other_encoder))
2549                                 goto disable_done;
2550                 }
2551         }
2552
2553         radeon_atom_encoder_dpms(encoder, DRM_MODE_DPMS_OFF);
2554
2555         switch (radeon_encoder->encoder_id) {
2556         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2557         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2558         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2559         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2560                 atombios_digital_setup(encoder, PANEL_ENCODER_ACTION_DISABLE);
2561                 break;
2562         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2563         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2564         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2565         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2566         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2567                 /* handled in dpms */
2568                 break;
2569         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2570         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2571         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2572                 atombios_dvo_setup(encoder, ATOM_DISABLE);
2573                 break;
2574         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2575         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2576         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2577         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2578                 atombios_dac_setup(encoder, ATOM_DISABLE);
2579                 if (radeon_encoder->devices & (ATOM_DEVICE_TV_SUPPORT | ATOM_DEVICE_CV_SUPPORT))
2580                         atombios_tv_setup(encoder, ATOM_DISABLE);
2581                 break;
2582         }
2583
2584 disable_done:
2585         if (radeon_encoder_is_digital(encoder)) {
2586                 if (atombios_get_encoder_mode(encoder) == ATOM_ENCODER_MODE_HDMI) {
2587                         if (rdev->asic->display.hdmi_enable)
2588                                 radeon_hdmi_enable(rdev, encoder, false);
2589                 }
2590                 if (atombios_get_encoder_mode(encoder) != ATOM_ENCODER_MODE_DP_MST) {
2591                         dig = radeon_encoder->enc_priv;
2592                         radeon_atom_release_dig_encoder(rdev, dig->dig_encoder);
2593                         dig->dig_encoder = -1;
2594                         radeon_encoder->active_device = 0;
2595                 }
2596         } else
2597                 radeon_encoder->active_device = 0;
2598 }
2599
2600 /* these are handled by the primary encoders */
2601 static void radeon_atom_ext_prepare(struct drm_encoder *encoder)
2602 {
2603
2604 }
2605
2606 static void radeon_atom_ext_commit(struct drm_encoder *encoder)
2607 {
2608
2609 }
2610
2611 static void
2612 radeon_atom_ext_mode_set(struct drm_encoder *encoder,
2613                          struct drm_display_mode *mode,
2614                          struct drm_display_mode *adjusted_mode)
2615 {
2616
2617 }
2618
2619 static void radeon_atom_ext_disable(struct drm_encoder *encoder)
2620 {
2621
2622 }
2623
2624 static void
2625 radeon_atom_ext_dpms(struct drm_encoder *encoder, int mode)
2626 {
2627
2628 }
2629
2630 static const struct drm_encoder_helper_funcs radeon_atom_ext_helper_funcs = {
2631         .dpms = radeon_atom_ext_dpms,
2632         .prepare = radeon_atom_ext_prepare,
2633         .mode_set = radeon_atom_ext_mode_set,
2634         .commit = radeon_atom_ext_commit,
2635         .disable = radeon_atom_ext_disable,
2636         /* no detect for TMDS/LVDS yet */
2637 };
2638
2639 static const struct drm_encoder_helper_funcs radeon_atom_dig_helper_funcs = {
2640         .dpms = radeon_atom_encoder_dpms,
2641         .mode_fixup = radeon_atom_mode_fixup,
2642         .prepare = radeon_atom_encoder_prepare,
2643         .mode_set = radeon_atom_encoder_mode_set,
2644         .commit = radeon_atom_encoder_commit,
2645         .disable = radeon_atom_encoder_disable,
2646         .detect = radeon_atom_dig_detect,
2647 };
2648
2649 static const struct drm_encoder_helper_funcs radeon_atom_dac_helper_funcs = {
2650         .dpms = radeon_atom_encoder_dpms,
2651         .mode_fixup = radeon_atom_mode_fixup,
2652         .prepare = radeon_atom_encoder_prepare,
2653         .mode_set = radeon_atom_encoder_mode_set,
2654         .commit = radeon_atom_encoder_commit,
2655         .detect = radeon_atom_dac_detect,
2656 };
2657
2658 void radeon_enc_destroy(struct drm_encoder *encoder)
2659 {
2660         struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder);
2661         if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2662                 radeon_atom_backlight_exit(radeon_encoder);
2663         kfree(radeon_encoder->enc_priv);
2664         drm_encoder_cleanup(encoder);
2665         kfree(radeon_encoder);
2666 }
2667
2668 static const struct drm_encoder_funcs radeon_atom_enc_funcs = {
2669         .destroy = radeon_enc_destroy,
2670 };
2671
2672 static struct radeon_encoder_atom_dac *
2673 radeon_atombios_set_dac_info(struct radeon_encoder *radeon_encoder)
2674 {
2675         struct drm_device *dev = radeon_encoder->base.dev;
2676         struct radeon_device *rdev = dev->dev_private;
2677         struct radeon_encoder_atom_dac *dac = kzalloc(sizeof(struct radeon_encoder_atom_dac), GFP_KERNEL);
2678
2679         if (!dac)
2680                 return NULL;
2681
2682         dac->tv_std = radeon_atombios_get_tv_info(rdev);
2683         return dac;
2684 }
2685
2686 static struct radeon_encoder_atom_dig *
2687 radeon_atombios_set_dig_info(struct radeon_encoder *radeon_encoder)
2688 {
2689         int encoder_enum = (radeon_encoder->encoder_enum & ENUM_ID_MASK) >> ENUM_ID_SHIFT;
2690         struct radeon_encoder_atom_dig *dig = kzalloc(sizeof(struct radeon_encoder_atom_dig), GFP_KERNEL);
2691
2692         if (!dig)
2693                 return NULL;
2694
2695         /* coherent mode by default */
2696         dig->coherent_mode = true;
2697         dig->dig_encoder = -1;
2698
2699         if (encoder_enum == 2)
2700                 dig->linkb = true;
2701         else
2702                 dig->linkb = false;
2703
2704         return dig;
2705 }
2706
2707 void
2708 radeon_add_atom_encoder(struct drm_device *dev,
2709                         uint32_t encoder_enum,
2710                         uint32_t supported_device,
2711                         u16 caps)
2712 {
2713         struct radeon_device *rdev = dev->dev_private;
2714         struct drm_encoder *encoder;
2715         struct radeon_encoder *radeon_encoder;
2716
2717         /* see if we already added it */
2718         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
2719                 radeon_encoder = to_radeon_encoder(encoder);
2720                 if (radeon_encoder->encoder_enum == encoder_enum) {
2721                         radeon_encoder->devices |= supported_device;
2722                         return;
2723                 }
2724
2725         }
2726
2727         /* add a new one */
2728         radeon_encoder = kzalloc(sizeof(struct radeon_encoder), GFP_KERNEL);
2729         if (!radeon_encoder)
2730                 return;
2731
2732         encoder = &radeon_encoder->base;
2733         switch (rdev->num_crtc) {
2734         case 1:
2735                 encoder->possible_crtcs = 0x1;
2736                 break;
2737         case 2:
2738         default:
2739                 encoder->possible_crtcs = 0x3;
2740                 break;
2741         case 4:
2742                 encoder->possible_crtcs = 0xf;
2743                 break;
2744         case 6:
2745                 encoder->possible_crtcs = 0x3f;
2746                 break;
2747         }
2748
2749         radeon_encoder->enc_priv = NULL;
2750
2751         radeon_encoder->encoder_enum = encoder_enum;
2752         radeon_encoder->encoder_id = (encoder_enum & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
2753         radeon_encoder->devices = supported_device;
2754         radeon_encoder->rmx_type = RMX_OFF;
2755         radeon_encoder->underscan_type = UNDERSCAN_OFF;
2756         radeon_encoder->is_ext_encoder = false;
2757         radeon_encoder->caps = caps;
2758
2759         switch (radeon_encoder->encoder_id) {
2760         case ENCODER_OBJECT_ID_INTERNAL_LVDS:
2761         case ENCODER_OBJECT_ID_INTERNAL_TMDS1:
2762         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_TMDS1:
2763         case ENCODER_OBJECT_ID_INTERNAL_LVTM1:
2764                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2765                         radeon_encoder->rmx_type = RMX_FULL;
2766                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2767                                          DRM_MODE_ENCODER_LVDS, NULL);
2768                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2769                 } else {
2770                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2771                                          DRM_MODE_ENCODER_TMDS, NULL);
2772                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2773                 }
2774                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2775                 break;
2776         case ENCODER_OBJECT_ID_INTERNAL_DAC1:
2777                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2778                                  DRM_MODE_ENCODER_DAC, NULL);
2779                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2780                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2781                 break;
2782         case ENCODER_OBJECT_ID_INTERNAL_DAC2:
2783         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC1:
2784         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DAC2:
2785                 drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2786                                  DRM_MODE_ENCODER_TVDAC, NULL);
2787                 radeon_encoder->enc_priv = radeon_atombios_set_dac_info(radeon_encoder);
2788                 drm_encoder_helper_add(encoder, &radeon_atom_dac_helper_funcs);
2789                 break;
2790         case ENCODER_OBJECT_ID_INTERNAL_DVO1:
2791         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_DVO1:
2792         case ENCODER_OBJECT_ID_INTERNAL_DDI:
2793         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY:
2794         case ENCODER_OBJECT_ID_INTERNAL_KLDSCP_LVTMA:
2795         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY1:
2796         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY2:
2797         case ENCODER_OBJECT_ID_INTERNAL_UNIPHY3:
2798                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
2799                         radeon_encoder->rmx_type = RMX_FULL;
2800                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2801                                          DRM_MODE_ENCODER_LVDS, NULL);
2802                         radeon_encoder->enc_priv = radeon_atombios_get_lvds_info(radeon_encoder);
2803                 } else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT)) {
2804                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2805                                          DRM_MODE_ENCODER_DAC, NULL);
2806                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2807                 } else {
2808                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2809                                          DRM_MODE_ENCODER_TMDS, NULL);
2810                         radeon_encoder->enc_priv = radeon_atombios_set_dig_info(radeon_encoder);
2811                 }
2812                 drm_encoder_helper_add(encoder, &radeon_atom_dig_helper_funcs);
2813                 break;
2814         case ENCODER_OBJECT_ID_SI170B:
2815         case ENCODER_OBJECT_ID_CH7303:
2816         case ENCODER_OBJECT_ID_EXTERNAL_SDVOA:
2817         case ENCODER_OBJECT_ID_EXTERNAL_SDVOB:
2818         case ENCODER_OBJECT_ID_TITFP513:
2819         case ENCODER_OBJECT_ID_VT1623:
2820         case ENCODER_OBJECT_ID_HDMI_SI1930:
2821         case ENCODER_OBJECT_ID_TRAVIS:
2822         case ENCODER_OBJECT_ID_NUTMEG:
2823                 /* these are handled by the primary encoders */
2824                 radeon_encoder->is_ext_encoder = true;
2825                 if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT))
2826                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2827                                          DRM_MODE_ENCODER_LVDS, NULL);
2828                 else if (radeon_encoder->devices & (ATOM_DEVICE_CRT_SUPPORT))
2829                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2830                                          DRM_MODE_ENCODER_DAC, NULL);
2831                 else
2832                         drm_encoder_init(dev, encoder, &radeon_atom_enc_funcs,
2833                                          DRM_MODE_ENCODER_TMDS, NULL);
2834                 drm_encoder_helper_add(encoder, &radeon_atom_ext_helper_funcs);
2835                 break;
2836         }
2837 }