1 // SPDX-License-Identifier: GPL-2.0-or-later
5 * This code is based on drivers/gpu/drm/mxsfb/mxsfb*
10 #include <linux/iopoll.h>
11 #include <linux/media-bus-format.h>
12 #include <linux/pm_runtime.h>
13 #include <linux/spinlock.h>
15 #include <drm/drm_atomic.h>
16 #include <drm/drm_atomic_helper.h>
17 #include <drm/drm_bridge.h>
18 #include <drm/drm_crtc.h>
19 #include <drm/drm_encoder.h>
20 #include <drm/drm_framebuffer.h>
21 #include <drm/drm_fb_cma_helper.h>
22 #include <drm/drm_fourcc.h>
23 #include <drm/drm_gem_atomic_helper.h>
24 #include <drm/drm_gem_cma_helper.h>
25 #include <drm/drm_plane.h>
26 #include <drm/drm_plane_helper.h>
27 #include <drm/drm_vblank.h>
29 #include "lcdif_drv.h"
30 #include "lcdif_regs.h"
32 /* -----------------------------------------------------------------------------
35 static void lcdif_set_formats(struct lcdif_drm_private *lcdif,
38 struct drm_device *drm = lcdif->drm;
39 const u32 format = lcdif->crtc.primary->state->fb->format->format;
41 writel(CSC0_CTRL_BYPASS, lcdif->base + LCDC_V8_CSC0_CTRL);
44 case MEDIA_BUS_FMT_RGB565_1X16:
45 writel(DISP_PARA_LINE_PATTERN_RGB565,
46 lcdif->base + LCDC_V8_DISP_PARA);
48 case MEDIA_BUS_FMT_RGB888_1X24:
49 writel(DISP_PARA_LINE_PATTERN_RGB888,
50 lcdif->base + LCDC_V8_DISP_PARA);
52 case MEDIA_BUS_FMT_UYVY8_1X16:
53 writel(DISP_PARA_LINE_PATTERN_UYVY_H,
54 lcdif->base + LCDC_V8_DISP_PARA);
56 /* CSC: BT.601 Full Range RGB to YCbCr coefficients. */
57 writel(CSC0_COEF0_A2(0x096) | CSC0_COEF0_A1(0x04c),
58 lcdif->base + LCDC_V8_CSC0_COEF0);
59 writel(CSC0_COEF1_B1(0x7d5) | CSC0_COEF1_A3(0x01d),
60 lcdif->base + LCDC_V8_CSC0_COEF1);
61 writel(CSC0_COEF2_B3(0x080) | CSC0_COEF2_B2(0x7ac),
62 lcdif->base + LCDC_V8_CSC0_COEF2);
63 writel(CSC0_COEF3_C2(0x795) | CSC0_COEF3_C1(0x080),
64 lcdif->base + LCDC_V8_CSC0_COEF3);
65 writel(CSC0_COEF4_D1(0x000) | CSC0_COEF4_C3(0x7ec),
66 lcdif->base + LCDC_V8_CSC0_COEF4);
67 writel(CSC0_COEF5_D3(0x080) | CSC0_COEF5_D2(0x080),
68 lcdif->base + LCDC_V8_CSC0_COEF5);
70 writel(CSC0_CTRL_CSC_MODE_RGB2YCbCr,
71 lcdif->base + LCDC_V8_CSC0_CTRL);
75 dev_err(drm->dev, "Unknown media bus format 0x%x\n", bus_format);
80 case DRM_FORMAT_RGB565:
81 writel(CTRLDESCL0_5_BPP_16_RGB565,
82 lcdif->base + LCDC_V8_CTRLDESCL0_5);
84 case DRM_FORMAT_RGB888:
85 writel(CTRLDESCL0_5_BPP_24_RGB888,
86 lcdif->base + LCDC_V8_CTRLDESCL0_5);
88 case DRM_FORMAT_XRGB1555:
89 writel(CTRLDESCL0_5_BPP_16_ARGB1555,
90 lcdif->base + LCDC_V8_CTRLDESCL0_5);
92 case DRM_FORMAT_XRGB4444:
93 writel(CTRLDESCL0_5_BPP_16_ARGB4444,
94 lcdif->base + LCDC_V8_CTRLDESCL0_5);
96 case DRM_FORMAT_XBGR8888:
97 writel(CTRLDESCL0_5_BPP_32_ABGR8888,
98 lcdif->base + LCDC_V8_CTRLDESCL0_5);
100 case DRM_FORMAT_XRGB8888:
101 writel(CTRLDESCL0_5_BPP_32_ARGB8888,
102 lcdif->base + LCDC_V8_CTRLDESCL0_5);
105 dev_err(drm->dev, "Unknown pixel format 0x%x\n", format);
110 static void lcdif_set_mode(struct lcdif_drm_private *lcdif, u32 bus_flags)
112 struct drm_display_mode *m = &lcdif->crtc.state->adjusted_mode;
115 if (m->flags & DRM_MODE_FLAG_NHSYNC)
117 if (m->flags & DRM_MODE_FLAG_NVSYNC)
119 if (bus_flags & DRM_BUS_FLAG_DE_LOW)
121 if (bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
122 ctrl |= CTRL_INV_PXCK;
124 writel(ctrl, lcdif->base + LCDC_V8_CTRL);
126 writel(DISP_SIZE_DELTA_Y(m->crtc_vdisplay) |
127 DISP_SIZE_DELTA_X(m->crtc_hdisplay),
128 lcdif->base + LCDC_V8_DISP_SIZE);
130 writel(HSYN_PARA_BP_H(m->htotal - m->hsync_end) |
131 HSYN_PARA_FP_H(m->hsync_start - m->hdisplay),
132 lcdif->base + LCDC_V8_HSYN_PARA);
134 writel(VSYN_PARA_BP_V(m->vtotal - m->vsync_end) |
135 VSYN_PARA_FP_V(m->vsync_start - m->vdisplay),
136 lcdif->base + LCDC_V8_VSYN_PARA);
138 writel(VSYN_HSYN_WIDTH_PW_V(m->vsync_end - m->vsync_start) |
139 VSYN_HSYN_WIDTH_PW_H(m->hsync_end - m->hsync_start),
140 lcdif->base + LCDC_V8_VSYN_HSYN_WIDTH);
142 writel(CTRLDESCL0_1_HEIGHT(m->crtc_vdisplay) |
143 CTRLDESCL0_1_WIDTH(m->crtc_hdisplay),
144 lcdif->base + LCDC_V8_CTRLDESCL0_1);
146 writel(CTRLDESCL0_3_PITCH(lcdif->crtc.primary->state->fb->pitches[0]),
147 lcdif->base + LCDC_V8_CTRLDESCL0_3);
150 static void lcdif_enable_controller(struct lcdif_drm_private *lcdif)
154 reg = readl(lcdif->base + LCDC_V8_DISP_PARA);
155 reg |= DISP_PARA_DISP_ON;
156 writel(reg, lcdif->base + LCDC_V8_DISP_PARA);
158 reg = readl(lcdif->base + LCDC_V8_CTRLDESCL0_5);
159 reg |= CTRLDESCL0_5_EN;
160 writel(reg, lcdif->base + LCDC_V8_CTRLDESCL0_5);
163 static void lcdif_disable_controller(struct lcdif_drm_private *lcdif)
168 reg = readl(lcdif->base + LCDC_V8_CTRLDESCL0_5);
169 reg &= ~CTRLDESCL0_5_EN;
170 writel(reg, lcdif->base + LCDC_V8_CTRLDESCL0_5);
172 ret = readl_poll_timeout(lcdif->base + LCDC_V8_CTRLDESCL0_5,
173 reg, !(reg & CTRLDESCL0_5_EN),
174 0, 36000); /* Wait ~2 frame times max */
176 drm_err(lcdif->drm, "Failed to disable controller!\n");
178 reg = readl(lcdif->base + LCDC_V8_DISP_PARA);
179 reg &= ~DISP_PARA_DISP_ON;
180 writel(reg, lcdif->base + LCDC_V8_DISP_PARA);
183 static void lcdif_reset_block(struct lcdif_drm_private *lcdif)
185 writel(CTRL_SW_RESET, lcdif->base + LCDC_V8_CTRL + REG_SET);
186 readl(lcdif->base + LCDC_V8_CTRL);
187 writel(CTRL_SW_RESET, lcdif->base + LCDC_V8_CTRL + REG_CLR);
188 readl(lcdif->base + LCDC_V8_CTRL);
191 static void lcdif_crtc_mode_set_nofb(struct lcdif_drm_private *lcdif,
192 struct drm_bridge_state *bridge_state,
193 const u32 bus_format)
195 struct drm_device *drm = lcdif->crtc.dev;
196 struct drm_display_mode *m = &lcdif->crtc.state->adjusted_mode;
199 if (lcdif->bridge && lcdif->bridge->timings)
200 bus_flags = lcdif->bridge->timings->input_bus_flags;
201 else if (bridge_state)
202 bus_flags = bridge_state->input_bus_cfg.flags;
204 DRM_DEV_DEBUG_DRIVER(drm->dev, "Pixel clock: %dkHz (actual: %dkHz)\n",
206 (int)(clk_get_rate(lcdif->clk) / 1000));
207 DRM_DEV_DEBUG_DRIVER(drm->dev, "Connector bus_flags: 0x%08X\n",
209 DRM_DEV_DEBUG_DRIVER(drm->dev, "Mode flags: 0x%08X\n", m->flags);
211 /* Mandatory eLCDIF reset as per the Reference Manual */
212 lcdif_reset_block(lcdif);
214 lcdif_set_formats(lcdif, bus_format);
216 lcdif_set_mode(lcdif, bus_flags);
219 static int lcdif_crtc_atomic_check(struct drm_crtc *crtc,
220 struct drm_atomic_state *state)
222 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
224 bool has_primary = crtc_state->plane_mask &
225 drm_plane_mask(crtc->primary);
227 /* The primary plane has to be enabled when the CRTC is active. */
228 if (crtc_state->active && !has_primary)
231 return drm_atomic_add_affected_planes(state, crtc);
234 static void lcdif_crtc_atomic_flush(struct drm_crtc *crtc,
235 struct drm_atomic_state *state)
237 struct lcdif_drm_private *lcdif = to_lcdif_drm_private(crtc->dev);
238 struct drm_pending_vblank_event *event;
241 reg = readl(lcdif->base + LCDC_V8_CTRLDESCL0_5);
242 reg |= CTRLDESCL0_5_SHADOW_LOAD_EN;
243 writel(reg, lcdif->base + LCDC_V8_CTRLDESCL0_5);
245 event = crtc->state->event;
246 crtc->state->event = NULL;
251 spin_lock_irq(&crtc->dev->event_lock);
252 if (drm_crtc_vblank_get(crtc) == 0)
253 drm_crtc_arm_vblank_event(crtc, event);
255 drm_crtc_send_vblank_event(crtc, event);
256 spin_unlock_irq(&crtc->dev->event_lock);
259 static void lcdif_crtc_atomic_enable(struct drm_crtc *crtc,
260 struct drm_atomic_state *state)
262 struct lcdif_drm_private *lcdif = to_lcdif_drm_private(crtc->dev);
263 struct drm_plane_state *new_pstate = drm_atomic_get_new_plane_state(state,
265 struct drm_display_mode *m = &lcdif->crtc.state->adjusted_mode;
266 struct drm_bridge_state *bridge_state = NULL;
267 struct drm_device *drm = lcdif->drm;
271 /* If there is a bridge attached to the LCDIF, use its bus format */
274 drm_atomic_get_new_bridge_state(state,
277 bus_format = MEDIA_BUS_FMT_FIXED;
279 bus_format = bridge_state->input_bus_cfg.format;
281 if (bus_format == MEDIA_BUS_FMT_FIXED) {
282 dev_warn_once(drm->dev,
283 "Bridge does not provide bus format, assuming MEDIA_BUS_FMT_RGB888_1X24.\n"
284 "Please fix bridge driver by handling atomic_get_input_bus_fmts.\n");
285 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
289 /* If all else fails, default to RGB888_1X24 */
291 bus_format = MEDIA_BUS_FMT_RGB888_1X24;
293 clk_set_rate(lcdif->clk, m->crtc_clock * 1000);
295 pm_runtime_get_sync(drm->dev);
297 lcdif_crtc_mode_set_nofb(lcdif, bridge_state, bus_format);
299 /* Write cur_buf as well to avoid an initial corrupt frame */
300 paddr = drm_fb_cma_get_gem_addr(new_pstate->fb, new_pstate, 0);
302 writel(lower_32_bits(paddr),
303 lcdif->base + LCDC_V8_CTRLDESCL_LOW0_4);
304 writel(CTRLDESCL_HIGH0_4_ADDR_HIGH(upper_32_bits(paddr)),
305 lcdif->base + LCDC_V8_CTRLDESCL_HIGH0_4);
307 lcdif_enable_controller(lcdif);
309 drm_crtc_vblank_on(crtc);
312 static void lcdif_crtc_atomic_disable(struct drm_crtc *crtc,
313 struct drm_atomic_state *state)
315 struct lcdif_drm_private *lcdif = to_lcdif_drm_private(crtc->dev);
316 struct drm_device *drm = lcdif->drm;
317 struct drm_pending_vblank_event *event;
319 drm_crtc_vblank_off(crtc);
321 lcdif_disable_controller(lcdif);
323 spin_lock_irq(&drm->event_lock);
324 event = crtc->state->event;
326 crtc->state->event = NULL;
327 drm_crtc_send_vblank_event(crtc, event);
329 spin_unlock_irq(&drm->event_lock);
331 pm_runtime_put_sync(drm->dev);
334 static int lcdif_crtc_enable_vblank(struct drm_crtc *crtc)
336 struct lcdif_drm_private *lcdif = to_lcdif_drm_private(crtc->dev);
338 /* Clear and enable VBLANK IRQ */
339 writel(INT_STATUS_D0_VS_BLANK, lcdif->base + LCDC_V8_INT_STATUS_D0);
340 writel(INT_ENABLE_D0_VS_BLANK_EN, lcdif->base + LCDC_V8_INT_ENABLE_D0);
345 static void lcdif_crtc_disable_vblank(struct drm_crtc *crtc)
347 struct lcdif_drm_private *lcdif = to_lcdif_drm_private(crtc->dev);
349 /* Disable and clear VBLANK IRQ */
350 writel(0, lcdif->base + LCDC_V8_INT_ENABLE_D0);
351 writel(INT_STATUS_D0_VS_BLANK, lcdif->base + LCDC_V8_INT_STATUS_D0);
354 static const struct drm_crtc_helper_funcs lcdif_crtc_helper_funcs = {
355 .atomic_check = lcdif_crtc_atomic_check,
356 .atomic_flush = lcdif_crtc_atomic_flush,
357 .atomic_enable = lcdif_crtc_atomic_enable,
358 .atomic_disable = lcdif_crtc_atomic_disable,
361 static const struct drm_crtc_funcs lcdif_crtc_funcs = {
362 .reset = drm_atomic_helper_crtc_reset,
363 .destroy = drm_crtc_cleanup,
364 .set_config = drm_atomic_helper_set_config,
365 .page_flip = drm_atomic_helper_page_flip,
366 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
367 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
368 .enable_vblank = lcdif_crtc_enable_vblank,
369 .disable_vblank = lcdif_crtc_disable_vblank,
372 /* -----------------------------------------------------------------------------
376 static const struct drm_encoder_funcs lcdif_encoder_funcs = {
377 .destroy = drm_encoder_cleanup,
380 /* -----------------------------------------------------------------------------
384 static int lcdif_plane_atomic_check(struct drm_plane *plane,
385 struct drm_atomic_state *state)
387 struct drm_plane_state *plane_state = drm_atomic_get_new_plane_state(state,
389 struct lcdif_drm_private *lcdif = to_lcdif_drm_private(plane->dev);
390 struct drm_crtc_state *crtc_state;
392 crtc_state = drm_atomic_get_new_crtc_state(state,
395 return drm_atomic_helper_check_plane_state(plane_state, crtc_state,
396 DRM_PLANE_HELPER_NO_SCALING,
397 DRM_PLANE_HELPER_NO_SCALING,
401 static void lcdif_plane_primary_atomic_update(struct drm_plane *plane,
402 struct drm_atomic_state *state)
404 struct lcdif_drm_private *lcdif = to_lcdif_drm_private(plane->dev);
405 struct drm_plane_state *new_pstate = drm_atomic_get_new_plane_state(state,
409 paddr = drm_fb_cma_get_gem_addr(new_pstate->fb, new_pstate, 0);
411 writel(lower_32_bits(paddr),
412 lcdif->base + LCDC_V8_CTRLDESCL_LOW0_4);
413 writel(CTRLDESCL_HIGH0_4_ADDR_HIGH(upper_32_bits(paddr)),
414 lcdif->base + LCDC_V8_CTRLDESCL_HIGH0_4);
418 static bool lcdif_format_mod_supported(struct drm_plane *plane,
422 return modifier == DRM_FORMAT_MOD_LINEAR;
425 static const struct drm_plane_helper_funcs lcdif_plane_primary_helper_funcs = {
426 .atomic_check = lcdif_plane_atomic_check,
427 .atomic_update = lcdif_plane_primary_atomic_update,
430 static const struct drm_plane_funcs lcdif_plane_funcs = {
431 .format_mod_supported = lcdif_format_mod_supported,
432 .update_plane = drm_atomic_helper_update_plane,
433 .disable_plane = drm_atomic_helper_disable_plane,
434 .destroy = drm_plane_cleanup,
435 .reset = drm_atomic_helper_plane_reset,
436 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
437 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
440 static const u32 lcdif_primary_plane_formats[] = {
449 static const u64 lcdif_modifiers[] = {
450 DRM_FORMAT_MOD_LINEAR,
451 DRM_FORMAT_MOD_INVALID
454 /* -----------------------------------------------------------------------------
458 int lcdif_kms_init(struct lcdif_drm_private *lcdif)
460 struct drm_encoder *encoder = &lcdif->encoder;
461 struct drm_crtc *crtc = &lcdif->crtc;
464 drm_plane_helper_add(&lcdif->planes.primary,
465 &lcdif_plane_primary_helper_funcs);
466 ret = drm_universal_plane_init(lcdif->drm, &lcdif->planes.primary, 1,
468 lcdif_primary_plane_formats,
469 ARRAY_SIZE(lcdif_primary_plane_formats),
470 lcdif_modifiers, DRM_PLANE_TYPE_PRIMARY,
475 drm_crtc_helper_add(crtc, &lcdif_crtc_helper_funcs);
476 ret = drm_crtc_init_with_planes(lcdif->drm, crtc,
477 &lcdif->planes.primary, NULL,
478 &lcdif_crtc_funcs, NULL);
482 encoder->possible_crtcs = drm_crtc_mask(crtc);
483 return drm_encoder_init(lcdif->drm, encoder, &lcdif_encoder_funcs,
484 DRM_MODE_ENCODER_NONE, NULL);