drivers/gpu/drm/mediatek/mtk_disp_rdma.c

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (c) 2015 MediaTek Inc.
   4  */
   5
   6 #include <drm/drm_fourcc.h>
   7
   8 #include <linux/clk.h>
   9 #include <linux/component.h>
  10 #include <linux/module.h>
  11 #include <linux/of_device.h>
  12 #include <linux/of_irq.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/pm_runtime.h>
  15 #include <linux/soc/mediatek/mtk-cmdq.h>
  16
  17 #include "mtk_disp_drv.h"
  18 #include "mtk_drm_crtc.h"
  19 #include "mtk_drm_ddp_comp.h"
  20
  21 #define DISP_REG_RDMA_INT_ENABLE                0x0000
  22 #define DISP_REG_RDMA_INT_STATUS                0x0004
  23 #define RDMA_TARGET_LINE_INT                            BIT(5)
  24 #define RDMA_FIFO_UNDERFLOW_INT                         BIT(4)
  25 #define RDMA_EOF_ABNORMAL_INT                           BIT(3)
  26 #define RDMA_FRAME_END_INT                              BIT(2)
  27 #define RDMA_FRAME_START_INT                            BIT(1)
  28 #define RDMA_REG_UPDATE_INT                             BIT(0)
  29 #define DISP_REG_RDMA_GLOBAL_CON                0x0010
  30 #define RDMA_ENGINE_EN                                  BIT(0)
  31 #define RDMA_MODE_MEMORY                                BIT(1)
  32 #define DISP_REG_RDMA_SIZE_CON_0                0x0014
  33 #define RDMA_MATRIX_ENABLE                              BIT(17)
  34 #define RDMA_MATRIX_INT_MTX_SEL                         GENMASK(23, 20)
  35 #define RDMA_MATRIX_INT_MTX_BT601_to_RGB                (6 << 20)
  36 #define DISP_REG_RDMA_SIZE_CON_1                0x0018
  37 #define DISP_REG_RDMA_TARGET_LINE               0x001c
  38 #define DISP_RDMA_MEM_CON                       0x0024
  39 #define MEM_MODE_INPUT_FORMAT_RGB565                    (0x000 << 4)
  40 #define MEM_MODE_INPUT_FORMAT_RGB888                    (0x001 << 4)
  41 #define MEM_MODE_INPUT_FORMAT_RGBA8888                  (0x002 << 4)
  42 #define MEM_MODE_INPUT_FORMAT_ARGB8888                  (0x003 << 4)
  43 #define MEM_MODE_INPUT_FORMAT_UYVY                      (0x004 << 4)
  44 #define MEM_MODE_INPUT_FORMAT_YUYV                      (0x005 << 4)
  45 #define MEM_MODE_INPUT_SWAP                             BIT(8)
  46 #define DISP_RDMA_MEM_SRC_PITCH                 0x002c
  47 #define DISP_RDMA_MEM_GMC_SETTING_0             0x0030
  48 #define DISP_REG_RDMA_FIFO_CON                  0x0040
  49 #define RDMA_FIFO_UNDERFLOW_EN                          BIT(31)
  50 #define RDMA_FIFO_PSEUDO_SIZE(bytes)                    (((bytes) / 16) << 16)
  51 #define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes)         ((bytes) / 16)
  52 #define RDMA_FIFO_SIZE(rdma)                    ((rdma)->data->fifo_size)
  53 #define DISP_RDMA_MEM_START_ADDR                0x0f00
  54
  55 #define RDMA_MEM_GMC                            0x40402020
  56
  57 struct mtk_disp_rdma_data {
  58         unsigned int fifo_size;
  59 };
  60
  61 /*
  62  * struct mtk_disp_rdma - DISP_RDMA driver structure
  63  * @data: local driver data
  64  */
  65 struct mtk_disp_rdma {
  66         struct clk                      *clk;
  67         void __iomem                    *regs;
  68         struct cmdq_client_reg          cmdq_reg;
  69         const struct mtk_disp_rdma_data *data;
  70         void                            (*vblank_cb)(void *data);
  71         void                            *vblank_cb_data;
  72         u32                             fifo_size;
  73 };
  74
  75 static irqreturn_t mtk_disp_rdma_irq_handler(int irq, void *dev_id)
  76 {
  77         struct mtk_disp_rdma *priv = dev_id;
  78
  79         /* Clear frame completion interrupt */
  80         writel(0x0, priv->regs + DISP_REG_RDMA_INT_STATUS);
  81
  82         if (!priv->vblank_cb)
  83                 return IRQ_NONE;
  84
  85         priv->vblank_cb(priv->vblank_cb_data);
  86
  87         return IRQ_HANDLED;
  88 }
  89
  90 static void rdma_update_bits(struct device *dev, unsigned int reg,
  91                              unsigned int mask, unsigned int val)
  92 {
  93         struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
  94         unsigned int tmp = readl(rdma->regs + reg);
  95
  96         tmp = (tmp & ~mask) | (val & mask);
  97         writel(tmp, rdma->regs + reg);
  98 }
  99
 100 void mtk_rdma_register_vblank_cb(struct device *dev,
 101                                  void (*vblank_cb)(void *),
 102                                  void *vblank_cb_data)
 103 {
 104         struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
 105
 106         rdma->vblank_cb = vblank_cb;
 107         rdma->vblank_cb_data = vblank_cb_data;
 108 }
 109
 110 void mtk_rdma_unregister_vblank_cb(struct device *dev)
 111 {
 112         struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
 113
 114         rdma->vblank_cb = NULL;
 115         rdma->vblank_cb_data = NULL;
 116 }
 117
 118 void mtk_rdma_enable_vblank(struct device *dev)
 119 {
 120         rdma_update_bits(dev, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT,
 121                          RDMA_FRAME_END_INT);
 122 }
 123
 124 void mtk_rdma_disable_vblank(struct device *dev)
 125 {
 126         rdma_update_bits(dev, DISP_REG_RDMA_INT_ENABLE, RDMA_FRAME_END_INT, 0);
 127 }
 128
 129 int mtk_rdma_clk_enable(struct device *dev)
 130 {
 131         struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
 132
 133         return clk_prepare_enable(rdma->clk);
 134 }
 135
 136 void mtk_rdma_clk_disable(struct device *dev)
 137 {
 138         struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
 139
 140         clk_disable_unprepare(rdma->clk);
 141 }
 142
 143 void mtk_rdma_start(struct device *dev)
 144 {
 145         rdma_update_bits(dev, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN,
 146                          RDMA_ENGINE_EN);
 147 }
 148
 149 void mtk_rdma_stop(struct device *dev)
 150 {
 151         rdma_update_bits(dev, DISP_REG_RDMA_GLOBAL_CON, RDMA_ENGINE_EN, 0);
 152 }
 153
 154 void mtk_rdma_config(struct device *dev, unsigned int width,
 155                      unsigned int height, unsigned int vrefresh,
 156                      unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
 157 {
 158         unsigned int threshold;
 159         unsigned int reg;
 160         struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
 161         u32 rdma_fifo_size;
 162
 163         mtk_ddp_write_mask(cmdq_pkt, width, &rdma->cmdq_reg, rdma->regs,
 164                            DISP_REG_RDMA_SIZE_CON_0, 0xfff);
 165         mtk_ddp_write_mask(cmdq_pkt, height, &rdma->cmdq_reg, rdma->regs,
 166                            DISP_REG_RDMA_SIZE_CON_1, 0xfffff);
 167
 168         if (rdma->fifo_size)
 169                 rdma_fifo_size = rdma->fifo_size;
 170         else
 171                 rdma_fifo_size = RDMA_FIFO_SIZE(rdma);
 172
 173         /*
 174          * Enable FIFO underflow since DSI and DPI can't be blocked.
 175          * Keep the FIFO pseudo size reset default of 8 KiB. Set the
 176          * output threshold to 70% of max fifo size to make sure the
 177          * threhold will not overflow
 178          */
 179         threshold = rdma_fifo_size * 7 / 10;
 180         reg = RDMA_FIFO_UNDERFLOW_EN |
 181               RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) |
 182               RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);
 183         mtk_ddp_write(cmdq_pkt, reg, &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_FIFO_CON);
 184 }
 185
 186 static unsigned int rdma_fmt_convert(struct mtk_disp_rdma *rdma,
 187                                      unsigned int fmt)
 188 {
 189         /* The return value in switch "MEM_MODE_INPUT_FORMAT_XXX"
 190          * is defined in mediatek HW data sheet.
 191          * The alphabet order in XXX is no relation to data
 192          * arrangement in memory.
 193          */
 194         switch (fmt) {
 195         default:
 196         case DRM_FORMAT_RGB565:
 197                 return MEM_MODE_INPUT_FORMAT_RGB565;
 198         case DRM_FORMAT_BGR565:
 199                 return MEM_MODE_INPUT_FORMAT_RGB565 | MEM_MODE_INPUT_SWAP;
 200         case DRM_FORMAT_RGB888:
 201                 return MEM_MODE_INPUT_FORMAT_RGB888;
 202         case DRM_FORMAT_BGR888:
 203                 return MEM_MODE_INPUT_FORMAT_RGB888 | MEM_MODE_INPUT_SWAP;
 204         case DRM_FORMAT_RGBX8888:
 205         case DRM_FORMAT_RGBA8888:
 206                 return MEM_MODE_INPUT_FORMAT_ARGB8888;
 207         case DRM_FORMAT_BGRX8888:
 208         case DRM_FORMAT_BGRA8888:
 209                 return MEM_MODE_INPUT_FORMAT_ARGB8888 | MEM_MODE_INPUT_SWAP;
 210         case DRM_FORMAT_XRGB8888:
 211         case DRM_FORMAT_ARGB8888:
 212                 return MEM_MODE_INPUT_FORMAT_RGBA8888;
 213         case DRM_FORMAT_XBGR8888:
 214         case DRM_FORMAT_ABGR8888:
 215                 return MEM_MODE_INPUT_FORMAT_RGBA8888 | MEM_MODE_INPUT_SWAP;
 216         case DRM_FORMAT_UYVY:
 217                 return MEM_MODE_INPUT_FORMAT_UYVY;
 218         case DRM_FORMAT_YUYV:
 219                 return MEM_MODE_INPUT_FORMAT_YUYV;
 220         }
 221 }
 222
 223 unsigned int mtk_rdma_layer_nr(struct device *dev)
 224 {
 225         return 1;
 226 }
 227
 228 void mtk_rdma_layer_config(struct device *dev, unsigned int idx,
 229                            struct mtk_plane_state *state,
 230                            struct cmdq_pkt *cmdq_pkt)
 231 {
 232         struct mtk_disp_rdma *rdma = dev_get_drvdata(dev);
 233         struct mtk_plane_pending_state *pending = &state->pending;
 234         unsigned int addr = pending->addr;
 235         unsigned int pitch = pending->pitch & 0xffff;
 236         unsigned int fmt = pending->format;
 237         unsigned int con;
 238
 239         con = rdma_fmt_convert(rdma, fmt);
 240         mtk_ddp_write_relaxed(cmdq_pkt, con, &rdma->cmdq_reg, rdma->regs, DISP_RDMA_MEM_CON);
 241
 242         if (fmt == DRM_FORMAT_UYVY || fmt == DRM_FORMAT_YUYV) {
 243                 mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_ENABLE, &rdma->cmdq_reg, rdma->regs,
 244                                    DISP_REG_RDMA_SIZE_CON_0,
 245                                    RDMA_MATRIX_ENABLE);
 246                 mtk_ddp_write_mask(cmdq_pkt, RDMA_MATRIX_INT_MTX_BT601_to_RGB,
 247                                    &rdma->cmdq_reg, rdma->regs, DISP_REG_RDMA_SIZE_CON_0,
 248                                    RDMA_MATRIX_INT_MTX_SEL);
 249         } else {
 250                 mtk_ddp_write_mask(cmdq_pkt, 0, &rdma->cmdq_reg, rdma->regs,
 251                                    DISP_REG_RDMA_SIZE_CON_0,
 252                                    RDMA_MATRIX_ENABLE);
 253         }
 254         mtk_ddp_write_relaxed(cmdq_pkt, addr, &rdma->cmdq_reg, rdma->regs,
 255                               DISP_RDMA_MEM_START_ADDR);
 256         mtk_ddp_write_relaxed(cmdq_pkt, pitch, &rdma->cmdq_reg, rdma->regs,
 257                               DISP_RDMA_MEM_SRC_PITCH);
 258         mtk_ddp_write(cmdq_pkt, RDMA_MEM_GMC, &rdma->cmdq_reg, rdma->regs,
 259                       DISP_RDMA_MEM_GMC_SETTING_0);
 260         mtk_ddp_write_mask(cmdq_pkt, RDMA_MODE_MEMORY, &rdma->cmdq_reg, rdma->regs,
 261                            DISP_REG_RDMA_GLOBAL_CON, RDMA_MODE_MEMORY);
 262
 263 }
 264
 265 static int mtk_disp_rdma_bind(struct device *dev, struct device *master,
 266                               void *data)
 267 {
 268         return 0;
 269
 270 }
 271
 272 static void mtk_disp_rdma_unbind(struct device *dev, struct device *master,
 273                                  void *data)
 274 {
 275 }
 276
 277 static const struct component_ops mtk_disp_rdma_component_ops = {
 278         .bind   = mtk_disp_rdma_bind,
 279         .unbind = mtk_disp_rdma_unbind,
 280 };
 281
 282 static int mtk_disp_rdma_probe(struct platform_device *pdev)
 283 {
 284         struct device *dev = &pdev->dev;
 285         struct mtk_disp_rdma *priv;
 286         struct resource *res;
 287         int irq;
 288         int ret;
 289
 290         priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 291         if (!priv)
 292                 return -ENOMEM;
 293
 294         irq = platform_get_irq(pdev, 0);
 295         if (irq < 0)
 296                 return irq;
 297
 298         priv->clk = devm_clk_get(dev, NULL);
 299         if (IS_ERR(priv->clk)) {
 300                 dev_err(dev, "failed to get rdma clk\n");
 301                 return PTR_ERR(priv->clk);
 302         }
 303
 304         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 305         priv->regs = devm_ioremap_resource(dev, res);
 306         if (IS_ERR(priv->regs)) {
 307                 dev_err(dev, "failed to ioremap rdma\n");
 308                 return PTR_ERR(priv->regs);
 309         }
 310 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
 311         ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
 312         if (ret)
 313                 dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
 314 #endif
 315
 316         if (of_find_property(dev->of_node, "mediatek,rdma-fifo-size", &ret)) {
 317                 ret = of_property_read_u32(dev->of_node,
 318                                            "mediatek,rdma-fifo-size",
 319                                            &priv->fifo_size);
 320                 if (ret) {
 321                         dev_err(dev, "Failed to get rdma fifo size\n");
 322                         return ret;
 323                 }
 324         }
 325
 326         /* Disable and clear pending interrupts */
 327         writel(0x0, priv->regs + DISP_REG_RDMA_INT_ENABLE);
 328         writel(0x0, priv->regs + DISP_REG_RDMA_INT_STATUS);
 329
 330         ret = devm_request_irq(dev, irq, mtk_disp_rdma_irq_handler,
 331                                IRQF_TRIGGER_NONE, dev_name(dev), priv);
 332         if (ret < 0) {
 333                 dev_err(dev, "Failed to request irq %d: %d\n", irq, ret);
 334                 return ret;
 335         }
 336
 337         priv->data = of_device_get_match_data(dev);
 338
 339         platform_set_drvdata(pdev, priv);
 340
 341         pm_runtime_enable(dev);
 342
 343         ret = component_add(dev, &mtk_disp_rdma_component_ops);
 344         if (ret) {
 345                 pm_runtime_disable(dev);
 346                 dev_err(dev, "Failed to add component: %d\n", ret);
 347         }
 348
 349         return ret;
 350 }
 351
 352 static int mtk_disp_rdma_remove(struct platform_device *pdev)
 353 {
 354         component_del(&pdev->dev, &mtk_disp_rdma_component_ops);
 355
 356         pm_runtime_disable(&pdev->dev);
 357
 358         return 0;
 359 }
 360
 361 static const struct mtk_disp_rdma_data mt2701_rdma_driver_data = {
 362         .fifo_size = SZ_4K,
 363 };
 364
 365 static const struct mtk_disp_rdma_data mt8173_rdma_driver_data = {
 366         .fifo_size = SZ_8K,
 367 };
 368
 369 static const struct mtk_disp_rdma_data mt8183_rdma_driver_data = {
 370         .fifo_size = 5 * SZ_1K,
 371 };
 372
 373 static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
 374         .fifo_size = 1920,
 375 };
 376
 377 static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
 378         { .compatible = "mediatek,mt2701-disp-rdma",
 379           .data = &mt2701_rdma_driver_data},
 380         { .compatible = "mediatek,mt8173-disp-rdma",
 381           .data = &mt8173_rdma_driver_data},
 382         { .compatible = "mediatek,mt8183-disp-rdma",
 383           .data = &mt8183_rdma_driver_data},
 384         { .compatible = "mediatek,mt8195-disp-rdma",
 385           .data = &mt8195_rdma_driver_data},
 386         {},
 387 };
 388 MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
 389
 390 struct platform_driver mtk_disp_rdma_driver = {
 391         .probe          = mtk_disp_rdma_probe,
 392         .remove         = mtk_disp_rdma_remove,
 393         .driver         = {
 394                 .name   = "mediatek-disp-rdma",
 395                 .owner  = THIS_MODULE,
 396                 .of_match_table = mtk_disp_rdma_driver_dt_match,
 397         },
 398 };