drivers/gpu/drm/i915/intel_pci_config.h

   1 /* SPDX-License-Identifier: MIT */
   2 /*
   3  * Copyright © 2022 Intel Corporation
   4  */
   5
   6 #ifndef __INTEL_PCI_CONFIG_H__
   7 #define __INTEL_PCI_CONFIG_H__
   8
   9 /* BSM in include/drm/i915_drm.h */
  10
  11 #define MCHBAR_I915                             0x44
  12 #define MCHBAR_I965                             0x48
  13 #define   MCHBAR_SIZE                           (4 * 4096)
  14
  15 #define DEVEN                                   0x54
  16 #define   DEVEN_MCHBAR_EN                       (1 << 28)
  17
  18 #define HPLLCC                                  0xc0 /* 85x only */
  19 #define   GC_CLOCK_CONTROL_MASK                 (0x7 << 0)
  20 #define   GC_CLOCK_133_200                      (0 << 0)
  21 #define   GC_CLOCK_100_200                      (1 << 0)
  22 #define   GC_CLOCK_100_133                      (2 << 0)
  23 #define   GC_CLOCK_133_266                      (3 << 0)
  24 #define   GC_CLOCK_133_200_2                    (4 << 0)
  25 #define   GC_CLOCK_133_266_2                    (5 << 0)
  26 #define   GC_CLOCK_166_266                      (6 << 0)
  27 #define   GC_CLOCK_166_250                      (7 << 0)
  28
  29 #define I915_GDRST                              0xc0
  30 #define   GRDOM_FULL                            (0 << 2)
  31 #define   GRDOM_RENDER                          (1 << 2)
  32 #define   GRDOM_MEDIA                           (3 << 2)
  33 #define   GRDOM_MASK                            (3 << 2)
  34 #define   GRDOM_RESET_STATUS                    (1 << 1)
  35 #define   GRDOM_RESET_ENABLE                    (1 << 0)
  36
  37 /* BSpec only has register offset, PCI device and bit found empirically */
  38 #define I830_CLOCK_GATE                         0xc8 /* device 0 */
  39 #define   I830_L2_CACHE_CLOCK_GATE_DISABLE      (1 << 2)
  40
  41 #define GCDGMBUS                                0xcc
  42
  43 #define GCFGC2                                  0xda
  44 #define GCFGC                                   0xf0 /* 915+ only */
  45 #define   GC_LOW_FREQUENCY_ENABLE               (1 << 7)
  46 #define   GC_DISPLAY_CLOCK_190_200_MHZ          (0 << 4)
  47 #define   GC_DISPLAY_CLOCK_333_320_MHZ          (4 << 4)
  48 #define   GC_DISPLAY_CLOCK_267_MHZ_PNV          (0 << 4)
  49 #define   GC_DISPLAY_CLOCK_333_MHZ_PNV          (1 << 4)
  50 #define   GC_DISPLAY_CLOCK_444_MHZ_PNV          (2 << 4)
  51 #define   GC_DISPLAY_CLOCK_200_MHZ_PNV          (5 << 4)
  52 #define   GC_DISPLAY_CLOCK_133_MHZ_PNV          (6 << 4)
  53 #define   GC_DISPLAY_CLOCK_167_MHZ_PNV          (7 << 4)
  54 #define   GC_DISPLAY_CLOCK_MASK                 (7 << 4)
  55 #define   GM45_GC_RENDER_CLOCK_MASK             (0xf << 0)
  56 #define   GM45_GC_RENDER_CLOCK_266_MHZ          (8 << 0)
  57 #define   GM45_GC_RENDER_CLOCK_320_MHZ          (9 << 0)
  58 #define   GM45_GC_RENDER_CLOCK_400_MHZ          (0xb << 0)
  59 #define   GM45_GC_RENDER_CLOCK_533_MHZ          (0xc << 0)
  60 #define   I965_GC_RENDER_CLOCK_MASK             (0xf << 0)
  61 #define   I965_GC_RENDER_CLOCK_267_MHZ          (2 << 0)
  62 #define   I965_GC_RENDER_CLOCK_333_MHZ          (3 << 0)
  63 #define   I965_GC_RENDER_CLOCK_444_MHZ          (4 << 0)
  64 #define   I965_GC_RENDER_CLOCK_533_MHZ          (5 << 0)
  65 #define   I945_GC_RENDER_CLOCK_MASK             (7 << 0)
  66 #define   I945_GC_RENDER_CLOCK_166_MHZ          (0 << 0)
  67 #define   I945_GC_RENDER_CLOCK_200_MHZ          (1 << 0)
  68 #define   I945_GC_RENDER_CLOCK_250_MHZ          (3 << 0)
  69 #define   I945_GC_RENDER_CLOCK_400_MHZ          (5 << 0)
  70 #define   I915_GC_RENDER_CLOCK_MASK             (7 << 0)
  71 #define   I915_GC_RENDER_CLOCK_166_MHZ          (0 << 0)
  72 #define   I915_GC_RENDER_CLOCK_200_MHZ          (1 << 0)
  73 #define   I915_GC_RENDER_CLOCK_333_MHZ          (4 << 0)
  74
  75 #define ASLE                                    0xe4
  76 #define ASLS                                    0xfc
  77
  78 #define SWSCI                                   0xe8
  79 #define   SWSCI_SCISEL                          (1 << 15)
  80 #define   SWSCI_GSSCIE                          (1 << 0)
  81
  82 /* legacy/combination backlight modes, also called LBB */
  83 #define LBPC                                    0xf4
  84
  85 #endif /* __INTEL_PCI_CONFIG_H__ */