2 * Copyright © 2015-2016 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
29 * DOC: i915 Perf Overview
31 * Gen graphics supports a large number of performance counters that can help
32 * driver and application developers understand and optimize their use of the
35 * This i915 perf interface enables userspace to configure and open a file
36 * descriptor representing a stream of GPU metrics which can then be read() as
37 * a stream of sample records.
39 * The interface is particularly suited to exposing buffered metrics that are
40 * captured by DMA from the GPU, unsynchronized with and unrelated to the CPU.
42 * Streams representing a single context are accessible to applications with a
43 * corresponding drm file descriptor, such that OpenGL can use the interface
44 * without special privileges. Access to system-wide metrics requires root
45 * privileges by default, unless changed via the dev.i915.perf_event_paranoid
51 * DOC: i915 Perf History and Comparison with Core Perf
53 * The interface was initially inspired by the core Perf infrastructure but
54 * some notable differences are:
56 * i915 perf file descriptors represent a "stream" instead of an "event"; where
57 * a perf event primarily corresponds to a single 64bit value, while a stream
58 * might sample sets of tightly-coupled counters, depending on the
59 * configuration. For example the Gen OA unit isn't designed to support
60 * orthogonal configurations of individual counters; it's configured for a set
61 * of related counters. Samples for an i915 perf stream capturing OA metrics
62 * will include a set of counter values packed in a compact HW specific format.
63 * The OA unit supports a number of different packing formats which can be
64 * selected by the user opening the stream. Perf has support for grouping
65 * events, but each event in the group is configured, validated and
66 * authenticated individually with separate system calls.
68 * i915 perf stream configurations are provided as an array of u64 (key,value)
69 * pairs, instead of a fixed struct with multiple miscellaneous config members,
70 * interleaved with event-type specific members.
72 * i915 perf doesn't support exposing metrics via an mmap'd circular buffer.
73 * The supported metrics are being written to memory by the GPU unsynchronized
74 * with the CPU, using HW specific packing formats for counter sets. Sometimes
75 * the constraints on HW configuration require reports to be filtered before it
76 * would be acceptable to expose them to unprivileged applications - to hide
77 * the metrics of other processes/contexts. For these use cases a read() based
78 * interface is a good fit, and provides an opportunity to filter data as it
79 * gets copied from the GPU mapped buffers to userspace buffers.
82 * Issues hit with first prototype based on Core Perf
83 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
85 * The first prototype of this driver was based on the core perf
86 * infrastructure, and while we did make that mostly work, with some changes to
87 * perf, we found we were breaking or working around too many assumptions baked
88 * into perf's currently cpu centric design.
90 * In the end we didn't see a clear benefit to making perf's implementation and
91 * interface more complex by changing design assumptions while we knew we still
92 * wouldn't be able to use any existing perf based userspace tools.
94 * Also considering the Gen specific nature of the Observability hardware and
95 * how userspace will sometimes need to combine i915 perf OA metrics with
96 * side-band OA data captured via MI_REPORT_PERF_COUNT commands; we're
97 * expecting the interface to be used by a platform specific userspace such as
98 * OpenGL or tools. This is to say; we aren't inherently missing out on having
99 * a standard vendor/architecture agnostic interface by not using perf.
102 * For posterity, in case we might re-visit trying to adapt core perf to be
103 * better suited to exposing i915 metrics these were the main pain points we
106 * - The perf based OA PMU driver broke some significant design assumptions:
108 * Existing perf pmus are used for profiling work on a cpu and we were
109 * introducing the idea of _IS_DEVICE pmus with different security
110 * implications, the need to fake cpu-related data (such as user/kernel
111 * registers) to fit with perf's current design, and adding _DEVICE records
112 * as a way to forward device-specific status records.
114 * The OA unit writes reports of counters into a circular buffer, without
115 * involvement from the CPU, making our PMU driver the first of a kind.
117 * Given the way we were periodically forward data from the GPU-mapped, OA
118 * buffer to perf's buffer, those bursts of sample writes looked to perf like
119 * we were sampling too fast and so we had to subvert its throttling checks.
121 * Perf supports groups of counters and allows those to be read via
122 * transactions internally but transactions currently seem designed to be
123 * explicitly initiated from the cpu (say in response to a userspace read())
124 * and while we could pull a report out of the OA buffer we can't
125 * trigger a report from the cpu on demand.
127 * Related to being report based; the OA counters are configured in HW as a
128 * set while perf generally expects counter configurations to be orthogonal.
129 * Although counters can be associated with a group leader as they are
130 * opened, there's no clear precedent for being able to provide group-wide
131 * configuration attributes (for example we want to let userspace choose the
132 * OA unit report format used to capture all counters in a set, or specify a
133 * GPU context to filter metrics on). We avoided using perf's grouping
134 * feature and forwarded OA reports to userspace via perf's 'raw' sample
135 * field. This suited our userspace well considering how coupled the counters
136 * are when dealing with normalizing. It would be inconvenient to split
137 * counters up into separate events, only to require userspace to recombine
138 * them. For Mesa it's also convenient to be forwarded raw, periodic reports
139 * for combining with the side-band raw reports it captures using
140 * MI_REPORT_PERF_COUNT commands.
142 * - As a side note on perf's grouping feature; there was also some concern
143 * that using PERF_FORMAT_GROUP as a way to pack together counter values
144 * would quite drastically inflate our sample sizes, which would likely
145 * lower the effective sampling resolutions we could use when the available
146 * memory bandwidth is limited.
148 * With the OA unit's report formats, counters are packed together as 32
149 * or 40bit values, with the largest report size being 256 bytes.
151 * PERF_FORMAT_GROUP values are 64bit, but there doesn't appear to be a
152 * documented ordering to the values, implying PERF_FORMAT_ID must also be
153 * used to add a 64bit ID before each value; giving 16 bytes per counter.
155 * Related to counter orthogonality; we can't time share the OA unit, while
156 * event scheduling is a central design idea within perf for allowing
157 * userspace to open + enable more events than can be configured in HW at any
158 * one time. The OA unit is not designed to allow re-configuration while in
159 * use. We can't reconfigure the OA unit without losing internal OA unit
160 * state which we can't access explicitly to save and restore. Reconfiguring
161 * the OA unit is also relatively slow, involving ~100 register writes. From
162 * userspace Mesa also depends on a stable OA configuration when emitting
163 * MI_REPORT_PERF_COUNT commands and importantly the OA unit can't be
164 * disabled while there are outstanding MI_RPC commands lest we hang the
167 * The contents of sample records aren't extensible by device drivers (i.e.
168 * the sample_type bits). As an example; Sourab Gupta had been looking to
169 * attach GPU timestamps to our OA samples. We were shoehorning OA reports
170 * into sample records by using the 'raw' field, but it's tricky to pack more
171 * than one thing into this field because events/core.c currently only lets a
172 * pmu give a single raw data pointer plus len which will be copied into the
173 * ring buffer. To include more than the OA report we'd have to copy the
174 * report into an intermediate larger buffer. I'd been considering allowing a
175 * vector of data+len values to be specified for copying the raw data, but
176 * it felt like a kludge to being using the raw field for this purpose.
178 * - It felt like our perf based PMU was making some technical compromises
179 * just for the sake of using perf:
181 * perf_event_open() requires events to either relate to a pid or a specific
182 * cpu core, while our device pmu related to neither. Events opened with a
183 * pid will be automatically enabled/disabled according to the scheduling of
184 * that process - so not appropriate for us. When an event is related to a
185 * cpu id, perf ensures pmu methods will be invoked via an inter process
186 * interrupt on that core. To avoid invasive changes our userspace opened OA
187 * perf events for a specific cpu. This was workable but it meant the
188 * majority of the OA driver ran in atomic context, including all OA report
189 * forwarding, which wasn't really necessary in our case and seems to make
190 * our locking requirements somewhat complex as we handled the interaction
191 * with the rest of the i915 driver.
194 #include <linux/anon_inodes.h>
195 #include <linux/sizes.h>
196 #include <linux/uuid.h>
198 #include "gem/i915_gem_context.h"
199 #include "gem/i915_gem_internal.h"
200 #include "gt/intel_engine_pm.h"
201 #include "gt/intel_engine_regs.h"
202 #include "gt/intel_engine_user.h"
203 #include "gt/intel_execlists_submission.h"
204 #include "gt/intel_gpu_commands.h"
205 #include "gt/intel_gt.h"
206 #include "gt/intel_gt_clock_utils.h"
207 #include "gt/intel_gt_regs.h"
208 #include "gt/intel_lrc.h"
209 #include "gt/intel_lrc_reg.h"
210 #include "gt/intel_ring.h"
212 #include "i915_drv.h"
213 #include "i915_file_private.h"
214 #include "i915_perf.h"
215 #include "i915_perf_oa_regs.h"
217 /* HW requires this to be a power of two, between 128k and 16M, though driver
218 * is currently generally designed assuming the largest 16M size is used such
219 * that the overflow cases are unlikely in normal operation.
221 #define OA_BUFFER_SIZE SZ_16M
223 #define OA_TAKEN(tail, head) ((tail - head) & (OA_BUFFER_SIZE - 1))
226 * DOC: OA Tail Pointer Race
228 * There's a HW race condition between OA unit tail pointer register updates and
229 * writes to memory whereby the tail pointer can sometimes get ahead of what's
230 * been written out to the OA buffer so far (in terms of what's visible to the
233 * Although this can be observed explicitly while copying reports to userspace
234 * by checking for a zeroed report-id field in tail reports, we want to account
235 * for this earlier, as part of the oa_buffer_check_unlocked to avoid lots of
236 * redundant read() attempts.
238 * We workaround this issue in oa_buffer_check_unlocked() by reading the reports
239 * in the OA buffer, starting from the tail reported by the HW until we find a
240 * report with its first 2 dwords not 0 meaning its previous report is
241 * completely in memory and ready to be read. Those dwords are also set to 0
242 * once read and the whole buffer is cleared upon OA buffer initialization. The
243 * first dword is the reason for this report while the second is the timestamp,
244 * making the chances of having those 2 fields at 0 fairly unlikely. A more
245 * detailed explanation is available in oa_buffer_check_unlocked().
247 * Most of the implementation details for this workaround are in
248 * oa_buffer_check_unlocked() and _append_oa_reports()
250 * Note for posterity: previously the driver used to define an effective tail
251 * pointer that lagged the real pointer by a 'tail margin' measured in bytes
252 * derived from %OA_TAIL_MARGIN_NSEC and the configured sampling frequency.
253 * This was flawed considering that the OA unit may also automatically generate
254 * non-periodic reports (such as on context switch) or the OA unit may be
255 * enabled without any periodic sampling.
257 #define OA_TAIL_MARGIN_NSEC 100000ULL
258 #define INVALID_TAIL_PTR 0xffffffff
260 /* The default frequency for checking whether the OA unit has written new
261 * reports to the circular OA buffer...
263 #define DEFAULT_POLL_FREQUENCY_HZ 200
264 #define DEFAULT_POLL_PERIOD_NS (NSEC_PER_SEC / DEFAULT_POLL_FREQUENCY_HZ)
266 /* for sysctl proc_dointvec_minmax of dev.i915.perf_stream_paranoid */
267 static u32 i915_perf_stream_paranoid = true;
269 /* The maximum exponent the hardware accepts is 63 (essentially it selects one
270 * of the 64bit timestamp bits to trigger reports from) but there's currently
271 * no known use case for sampling as infrequently as once per 47 thousand years.
273 * Since the timestamps included in OA reports are only 32bits it seems
274 * reasonable to limit the OA exponent where it's still possible to account for
275 * overflow in OA report timestamps.
277 #define OA_EXPONENT_MAX 31
279 #define INVALID_CTX_ID 0xffffffff
281 /* On Gen8+ automatically triggered OA reports include a 'reason' field... */
282 #define OAREPORT_REASON_MASK 0x3f
283 #define OAREPORT_REASON_MASK_EXTENDED 0x7f
284 #define OAREPORT_REASON_SHIFT 19
285 #define OAREPORT_REASON_TIMER (1<<0)
286 #define OAREPORT_REASON_CTX_SWITCH (1<<3)
287 #define OAREPORT_REASON_CLK_RATIO (1<<5)
290 /* For sysctl proc_dointvec_minmax of i915_oa_max_sample_rate
292 * The highest sampling frequency we can theoretically program the OA unit
293 * with is always half the timestamp frequency: E.g. 6.25Mhz for Haswell.
295 * Initialized just before we register the sysctl parameter.
297 static int oa_sample_rate_hard_limit;
299 /* Theoretically we can program the OA unit to sample every 160ns but don't
300 * allow that by default unless root...
302 * The default threshold of 100000Hz is based on perf's similar
303 * kernel.perf_event_max_sample_rate sysctl parameter.
305 static u32 i915_oa_max_sample_rate = 100000;
307 /* XXX: beware if future OA HW adds new report formats that the current
308 * code assumes all reports have a power-of-two size and ~(size - 1) can
309 * be used as a mask to align the OA tail pointer.
311 static const struct i915_oa_format oa_formats[I915_OA_FORMAT_MAX] = {
312 [I915_OA_FORMAT_A13] = { 0, 64 },
313 [I915_OA_FORMAT_A29] = { 1, 128 },
314 [I915_OA_FORMAT_A13_B8_C8] = { 2, 128 },
315 /* A29_B8_C8 Disallowed as 192 bytes doesn't factor into buffer size */
316 [I915_OA_FORMAT_B4_C8] = { 4, 64 },
317 [I915_OA_FORMAT_A45_B8_C8] = { 5, 256 },
318 [I915_OA_FORMAT_B4_C8_A16] = { 6, 128 },
319 [I915_OA_FORMAT_C4_B8] = { 7, 64 },
320 [I915_OA_FORMAT_A12] = { 0, 64 },
321 [I915_OA_FORMAT_A12_B8_C8] = { 2, 128 },
322 [I915_OA_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 },
325 #define SAMPLE_OA_REPORT (1<<0)
328 * struct perf_open_properties - for validated properties given to open a stream
329 * @sample_flags: `DRM_I915_PERF_PROP_SAMPLE_*` properties are tracked as flags
330 * @single_context: Whether a single or all gpu contexts should be monitored
331 * @hold_preemption: Whether the preemption is disabled for the filtered
333 * @ctx_handle: A gem ctx handle for use with @single_context
334 * @metrics_set: An ID for an OA unit metric set advertised via sysfs
335 * @oa_format: An OA unit HW report format
336 * @oa_periodic: Whether to enable periodic OA unit sampling
337 * @oa_period_exponent: The OA unit sampling period is derived from this
338 * @engine: The engine (typically rcs0) being monitored by the OA unit
339 * @has_sseu: Whether @sseu was specified by userspace
340 * @sseu: internal SSEU configuration computed either from the userspace
341 * specified configuration in the opening parameters or a default value
342 * (see get_default_sseu_config())
343 * @poll_oa_period: The period in nanoseconds at which the CPU will check for OA
346 * As read_properties_unlocked() enumerates and validates the properties given
347 * to open a stream of metrics the configuration is built up in the structure
348 * which starts out zero initialized.
350 struct perf_open_properties {
353 u64 single_context:1;
354 u64 hold_preemption:1;
357 /* OA sampling state */
361 int oa_period_exponent;
363 struct intel_engine_cs *engine;
366 struct intel_sseu sseu;
371 struct i915_oa_config_bo {
372 struct llist_node node;
374 struct i915_oa_config *oa_config;
375 struct i915_vma *vma;
378 static struct ctl_table_header *sysctl_header;
380 static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer);
382 void i915_oa_config_release(struct kref *ref)
384 struct i915_oa_config *oa_config =
385 container_of(ref, typeof(*oa_config), ref);
387 kfree(oa_config->flex_regs);
388 kfree(oa_config->b_counter_regs);
389 kfree(oa_config->mux_regs);
391 kfree_rcu(oa_config, rcu);
394 struct i915_oa_config *
395 i915_perf_get_oa_config(struct i915_perf *perf, int metrics_set)
397 struct i915_oa_config *oa_config;
400 oa_config = idr_find(&perf->metrics_idr, metrics_set);
402 oa_config = i915_oa_config_get(oa_config);
408 static void free_oa_config_bo(struct i915_oa_config_bo *oa_bo)
410 i915_oa_config_put(oa_bo->oa_config);
411 i915_vma_put(oa_bo->vma);
415 static u32 gen12_oa_hw_tail_read(struct i915_perf_stream *stream)
417 struct intel_uncore *uncore = stream->uncore;
419 return intel_uncore_read(uncore, GEN12_OAG_OATAILPTR) &
420 GEN12_OAG_OATAILPTR_MASK;
423 static u32 gen8_oa_hw_tail_read(struct i915_perf_stream *stream)
425 struct intel_uncore *uncore = stream->uncore;
427 return intel_uncore_read(uncore, GEN8_OATAILPTR) & GEN8_OATAILPTR_MASK;
430 static u32 gen7_oa_hw_tail_read(struct i915_perf_stream *stream)
432 struct intel_uncore *uncore = stream->uncore;
433 u32 oastatus1 = intel_uncore_read(uncore, GEN7_OASTATUS1);
435 return oastatus1 & GEN7_OASTATUS1_TAIL_MASK;
439 * oa_buffer_check_unlocked - check for data and update tail ptr state
440 * @stream: i915 stream instance
442 * This is either called via fops (for blocking reads in user ctx) or the poll
443 * check hrtimer (atomic ctx) to check the OA buffer tail pointer and check
444 * if there is data available for userspace to read.
446 * This function is central to providing a workaround for the OA unit tail
447 * pointer having a race with respect to what data is visible to the CPU.
448 * It is responsible for reading tail pointers from the hardware and giving
449 * the pointers time to 'age' before they are made available for reading.
450 * (See description of OA_TAIL_MARGIN_NSEC above for further details.)
452 * Besides returning true when there is data available to read() this function
453 * also updates the tail, aging_tail and aging_timestamp in the oa_buffer
456 * Note: It's safe to read OA config state here unlocked, assuming that this is
457 * only called while the stream is enabled, while the global OA configuration
460 * Returns: %true if the OA buffer contains data, else %false
462 static bool oa_buffer_check_unlocked(struct i915_perf_stream *stream)
464 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
465 int report_size = stream->oa_buffer.format_size;
471 /* We have to consider the (unlikely) possibility that read() errors
472 * could result in an OA buffer reset which might reset the head and
475 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
477 hw_tail = stream->perf->ops.oa_hw_tail_read(stream);
479 /* The tail pointer increases in 64 byte increments,
480 * not in report_size steps...
482 hw_tail &= ~(report_size - 1);
484 now = ktime_get_mono_fast_ns();
486 if (hw_tail == stream->oa_buffer.aging_tail &&
487 (now - stream->oa_buffer.aging_timestamp) > OA_TAIL_MARGIN_NSEC) {
488 /* If the HW tail hasn't move since the last check and the HW
489 * tail has been aging for long enough, declare it the new
492 stream->oa_buffer.tail = stream->oa_buffer.aging_tail;
494 u32 head, tail, aged_tail;
496 /* NB: The head we observe here might effectively be a little
497 * out of date. If a read() is in progress, the head could be
498 * anywhere between this head and stream->oa_buffer.tail.
500 head = stream->oa_buffer.head - gtt_offset;
501 aged_tail = stream->oa_buffer.tail - gtt_offset;
503 hw_tail -= gtt_offset;
506 /* Walk the stream backward until we find a report with dword 0
507 * & 1 not at 0. Since the circular buffer pointers progress by
508 * increments of 64 bytes and that reports can be up to 256
509 * bytes long, we can't tell whether a report has fully landed
510 * in memory before the first 2 dwords of the following report
511 * have effectively landed.
513 * This is assuming that the writes of the OA unit land in
514 * memory in the order they were written to.
515 * If not : (╯°□°)╯︵ ┻━┻
517 while (OA_TAKEN(tail, aged_tail) >= report_size) {
518 u32 *report32 = (void *)(stream->oa_buffer.vaddr + tail);
520 if (report32[0] != 0 || report32[1] != 0)
523 tail = (tail - report_size) & (OA_BUFFER_SIZE - 1);
526 if (OA_TAKEN(hw_tail, tail) > report_size &&
527 __ratelimit(&stream->perf->tail_pointer_race))
528 DRM_NOTE("unlanded report(s) head=0x%x "
529 "tail=0x%x hw_tail=0x%x\n",
530 head, tail, hw_tail);
532 stream->oa_buffer.tail = gtt_offset + tail;
533 stream->oa_buffer.aging_tail = gtt_offset + hw_tail;
534 stream->oa_buffer.aging_timestamp = now;
537 pollin = OA_TAKEN(stream->oa_buffer.tail - gtt_offset,
538 stream->oa_buffer.head - gtt_offset) >= report_size;
540 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
546 * append_oa_status - Appends a status record to a userspace read() buffer.
547 * @stream: An i915-perf stream opened for OA metrics
548 * @buf: destination buffer given by userspace
549 * @count: the number of bytes userspace wants to read
550 * @offset: (inout): the current position for writing into @buf
551 * @type: The kind of status to report to userspace
553 * Writes a status record (such as `DRM_I915_PERF_RECORD_OA_REPORT_LOST`)
554 * into the userspace read() buffer.
556 * The @buf @offset will only be updated on success.
558 * Returns: 0 on success, negative error code on failure.
560 static int append_oa_status(struct i915_perf_stream *stream,
564 enum drm_i915_perf_record_type type)
566 struct drm_i915_perf_record_header header = { type, 0, sizeof(header) };
568 if ((count - *offset) < header.size)
571 if (copy_to_user(buf + *offset, &header, sizeof(header)))
574 (*offset) += header.size;
580 * append_oa_sample - Copies single OA report into userspace read() buffer.
581 * @stream: An i915-perf stream opened for OA metrics
582 * @buf: destination buffer given by userspace
583 * @count: the number of bytes userspace wants to read
584 * @offset: (inout): the current position for writing into @buf
585 * @report: A single OA report to (optionally) include as part of the sample
587 * The contents of a sample are configured through `DRM_I915_PERF_PROP_SAMPLE_*`
588 * properties when opening a stream, tracked as `stream->sample_flags`. This
589 * function copies the requested components of a single sample to the given
592 * The @buf @offset will only be updated on success.
594 * Returns: 0 on success, negative error code on failure.
596 static int append_oa_sample(struct i915_perf_stream *stream,
602 int report_size = stream->oa_buffer.format_size;
603 struct drm_i915_perf_record_header header;
605 header.type = DRM_I915_PERF_RECORD_SAMPLE;
607 header.size = stream->sample_size;
609 if ((count - *offset) < header.size)
613 if (copy_to_user(buf, &header, sizeof(header)))
615 buf += sizeof(header);
617 if (copy_to_user(buf, report, report_size))
620 (*offset) += header.size;
626 * gen8_append_oa_reports - Copies all buffered OA reports into
627 * userspace read() buffer.
628 * @stream: An i915-perf stream opened for OA metrics
629 * @buf: destination buffer given by userspace
630 * @count: the number of bytes userspace wants to read
631 * @offset: (inout): the current position for writing into @buf
633 * Notably any error condition resulting in a short read (-%ENOSPC or
634 * -%EFAULT) will be returned even though one or more records may
635 * have been successfully copied. In this case it's up to the caller
636 * to decide if the error should be squashed before returning to
639 * Note: reports are consumed from the head, and appended to the
640 * tail, so the tail chases the head?... If you think that's mad
641 * and back-to-front you're not alone, but this follows the
642 * Gen PRM naming convention.
644 * Returns: 0 on success, negative error code on failure.
646 static int gen8_append_oa_reports(struct i915_perf_stream *stream,
651 struct intel_uncore *uncore = stream->uncore;
652 int report_size = stream->oa_buffer.format_size;
653 u8 *oa_buf_base = stream->oa_buffer.vaddr;
654 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
655 u32 mask = (OA_BUFFER_SIZE - 1);
656 size_t start_offset = *offset;
662 if (drm_WARN_ON(&uncore->i915->drm, !stream->enabled))
665 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
667 head = stream->oa_buffer.head;
668 tail = stream->oa_buffer.tail;
670 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
673 * NB: oa_buffer.head/tail include the gtt_offset which we don't want
674 * while indexing relative to oa_buf_base.
680 * An out of bounds or misaligned head or tail pointer implies a driver
681 * bug since we validate + align the tail pointers we read from the
682 * hardware and we are in full control of the head pointer which should
683 * only be incremented by multiples of the report size (notably also
684 * all a power of two).
686 if (drm_WARN_ONCE(&uncore->i915->drm,
687 head > OA_BUFFER_SIZE || head % report_size ||
688 tail > OA_BUFFER_SIZE || tail % report_size,
689 "Inconsistent OA buffer pointers: head = %u, tail = %u\n",
695 (taken = OA_TAKEN(tail, head));
696 head = (head + report_size) & mask) {
697 u8 *report = oa_buf_base + head;
698 u32 *report32 = (void *)report;
703 * All the report sizes factor neatly into the buffer
704 * size so we never expect to see a report split
705 * between the beginning and end of the buffer.
707 * Given the initial alignment check a misalignment
708 * here would imply a driver bug that would result
711 if (drm_WARN_ON(&uncore->i915->drm,
712 (OA_BUFFER_SIZE - head) < report_size)) {
713 drm_err(&uncore->i915->drm,
714 "Spurious OA head ptr: non-integral report offset\n");
719 * The reason field includes flags identifying what
720 * triggered this specific report (mostly timer
721 * triggered or e.g. due to a context switch).
723 * This field is never expected to be zero so we can
724 * check that the report isn't invalid before copying
727 reason = ((report32[0] >> OAREPORT_REASON_SHIFT) &
728 (GRAPHICS_VER(stream->perf->i915) == 12 ?
729 OAREPORT_REASON_MASK_EXTENDED :
730 OAREPORT_REASON_MASK));
732 ctx_id = report32[2] & stream->specific_ctx_id_mask;
735 * Squash whatever is in the CTX_ID field if it's marked as
736 * invalid to be sure we avoid false-positive, single-context
739 * Note: that we don't clear the valid_ctx_bit so userspace can
740 * understand that the ID has been squashed by the kernel.
742 if (!(report32[0] & stream->perf->gen8_valid_ctx_bit) &&
743 GRAPHICS_VER(stream->perf->i915) <= 11)
744 ctx_id = report32[2] = INVALID_CTX_ID;
747 * NB: For Gen 8 the OA unit no longer supports clock gating
748 * off for a specific context and the kernel can't securely
749 * stop the counters from updating as system-wide / global
752 * Automatic reports now include a context ID so reports can be
753 * filtered on the cpu but it's not worth trying to
754 * automatically subtract/hide counter progress for other
755 * contexts while filtering since we can't stop userspace
756 * issuing MI_REPORT_PERF_COUNT commands which would still
757 * provide a side-band view of the real values.
759 * To allow userspace (such as Mesa/GL_INTEL_performance_query)
760 * to normalize counters for a single filtered context then it
761 * needs be forwarded bookend context-switch reports so that it
762 * can track switches in between MI_REPORT_PERF_COUNT commands
763 * and can itself subtract/ignore the progress of counters
764 * associated with other contexts. Note that the hardware
765 * automatically triggers reports when switching to a new
766 * context which are tagged with the ID of the newly active
767 * context. To avoid the complexity (and likely fragility) of
768 * reading ahead while parsing reports to try and minimize
769 * forwarding redundant context switch reports (i.e. between
770 * other, unrelated contexts) we simply elect to forward them
773 * We don't rely solely on the reason field to identify context
774 * switches since it's not-uncommon for periodic samples to
775 * identify a switch before any 'context switch' report.
777 if (!stream->perf->exclusive_stream->ctx ||
778 stream->specific_ctx_id == ctx_id ||
779 stream->oa_buffer.last_ctx_id == stream->specific_ctx_id ||
780 reason & OAREPORT_REASON_CTX_SWITCH) {
783 * While filtering for a single context we avoid
784 * leaking the IDs of other contexts.
786 if (stream->perf->exclusive_stream->ctx &&
787 stream->specific_ctx_id != ctx_id) {
788 report32[2] = INVALID_CTX_ID;
791 ret = append_oa_sample(stream, buf, count, offset,
796 stream->oa_buffer.last_ctx_id = ctx_id;
800 * Clear out the first 2 dword as a mean to detect unlanded
807 if (start_offset != *offset) {
808 i915_reg_t oaheadptr;
810 oaheadptr = GRAPHICS_VER(stream->perf->i915) == 12 ?
811 GEN12_OAG_OAHEADPTR : GEN8_OAHEADPTR;
813 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
816 * We removed the gtt_offset for the copy loop above, indexing
817 * relative to oa_buf_base so put back here...
820 intel_uncore_write(uncore, oaheadptr,
821 head & GEN12_OAG_OAHEADPTR_MASK);
822 stream->oa_buffer.head = head;
824 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
831 * gen8_oa_read - copy status records then buffered OA reports
832 * @stream: An i915-perf stream opened for OA metrics
833 * @buf: destination buffer given by userspace
834 * @count: the number of bytes userspace wants to read
835 * @offset: (inout): the current position for writing into @buf
837 * Checks OA unit status registers and if necessary appends corresponding
838 * status records for userspace (such as for a buffer full condition) and then
839 * initiate appending any buffered OA reports.
841 * Updates @offset according to the number of bytes successfully copied into
842 * the userspace buffer.
844 * NB: some data may be successfully copied to the userspace buffer
845 * even if an error is returned, and this is reflected in the
848 * Returns: zero on success or a negative error code
850 static int gen8_oa_read(struct i915_perf_stream *stream,
855 struct intel_uncore *uncore = stream->uncore;
857 i915_reg_t oastatus_reg;
860 if (drm_WARN_ON(&uncore->i915->drm, !stream->oa_buffer.vaddr))
863 oastatus_reg = GRAPHICS_VER(stream->perf->i915) == 12 ?
864 GEN12_OAG_OASTATUS : GEN8_OASTATUS;
866 oastatus = intel_uncore_read(uncore, oastatus_reg);
869 * We treat OABUFFER_OVERFLOW as a significant error:
871 * Although theoretically we could handle this more gracefully
872 * sometimes, some Gens don't correctly suppress certain
873 * automatically triggered reports in this condition and so we
874 * have to assume that old reports are now being trampled
877 * Considering how we don't currently give userspace control
878 * over the OA buffer size and always configure a large 16MB
879 * buffer, then a buffer overflow does anyway likely indicate
880 * that something has gone quite badly wrong.
882 if (oastatus & GEN8_OASTATUS_OABUFFER_OVERFLOW) {
883 ret = append_oa_status(stream, buf, count, offset,
884 DRM_I915_PERF_RECORD_OA_BUFFER_LOST);
888 drm_dbg(&stream->perf->i915->drm,
889 "OA buffer overflow (exponent = %d): force restart\n",
890 stream->period_exponent);
892 stream->perf->ops.oa_disable(stream);
893 stream->perf->ops.oa_enable(stream);
896 * Note: .oa_enable() is expected to re-init the oabuffer and
897 * reset GEN8_OASTATUS for us
899 oastatus = intel_uncore_read(uncore, oastatus_reg);
902 if (oastatus & GEN8_OASTATUS_REPORT_LOST) {
903 ret = append_oa_status(stream, buf, count, offset,
904 DRM_I915_PERF_RECORD_OA_REPORT_LOST);
908 intel_uncore_rmw(uncore, oastatus_reg,
909 GEN8_OASTATUS_COUNTER_OVERFLOW |
910 GEN8_OASTATUS_REPORT_LOST,
911 IS_GRAPHICS_VER(uncore->i915, 8, 11) ?
912 (GEN8_OASTATUS_HEAD_POINTER_WRAP |
913 GEN8_OASTATUS_TAIL_POINTER_WRAP) : 0);
916 return gen8_append_oa_reports(stream, buf, count, offset);
920 * gen7_append_oa_reports - Copies all buffered OA reports into
921 * userspace read() buffer.
922 * @stream: An i915-perf stream opened for OA metrics
923 * @buf: destination buffer given by userspace
924 * @count: the number of bytes userspace wants to read
925 * @offset: (inout): the current position for writing into @buf
927 * Notably any error condition resulting in a short read (-%ENOSPC or
928 * -%EFAULT) will be returned even though one or more records may
929 * have been successfully copied. In this case it's up to the caller
930 * to decide if the error should be squashed before returning to
933 * Note: reports are consumed from the head, and appended to the
934 * tail, so the tail chases the head?... If you think that's mad
935 * and back-to-front you're not alone, but this follows the
936 * Gen PRM naming convention.
938 * Returns: 0 on success, negative error code on failure.
940 static int gen7_append_oa_reports(struct i915_perf_stream *stream,
945 struct intel_uncore *uncore = stream->uncore;
946 int report_size = stream->oa_buffer.format_size;
947 u8 *oa_buf_base = stream->oa_buffer.vaddr;
948 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
949 u32 mask = (OA_BUFFER_SIZE - 1);
950 size_t start_offset = *offset;
956 if (drm_WARN_ON(&uncore->i915->drm, !stream->enabled))
959 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
961 head = stream->oa_buffer.head;
962 tail = stream->oa_buffer.tail;
964 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
966 /* NB: oa_buffer.head/tail include the gtt_offset which we don't want
967 * while indexing relative to oa_buf_base.
972 /* An out of bounds or misaligned head or tail pointer implies a driver
973 * bug since we validate + align the tail pointers we read from the
974 * hardware and we are in full control of the head pointer which should
975 * only be incremented by multiples of the report size (notably also
976 * all a power of two).
978 if (drm_WARN_ONCE(&uncore->i915->drm,
979 head > OA_BUFFER_SIZE || head % report_size ||
980 tail > OA_BUFFER_SIZE || tail % report_size,
981 "Inconsistent OA buffer pointers: head = %u, tail = %u\n",
987 (taken = OA_TAKEN(tail, head));
988 head = (head + report_size) & mask) {
989 u8 *report = oa_buf_base + head;
990 u32 *report32 = (void *)report;
992 /* All the report sizes factor neatly into the buffer
993 * size so we never expect to see a report split
994 * between the beginning and end of the buffer.
996 * Given the initial alignment check a misalignment
997 * here would imply a driver bug that would result
1000 if (drm_WARN_ON(&uncore->i915->drm,
1001 (OA_BUFFER_SIZE - head) < report_size)) {
1002 drm_err(&uncore->i915->drm,
1003 "Spurious OA head ptr: non-integral report offset\n");
1007 /* The report-ID field for periodic samples includes
1008 * some undocumented flags related to what triggered
1009 * the report and is never expected to be zero so we
1010 * can check that the report isn't invalid before
1011 * copying it to userspace...
1013 if (report32[0] == 0) {
1014 if (__ratelimit(&stream->perf->spurious_report_rs))
1015 DRM_NOTE("Skipping spurious, invalid OA report\n");
1019 ret = append_oa_sample(stream, buf, count, offset, report);
1023 /* Clear out the first 2 dwords as a mean to detect unlanded
1030 if (start_offset != *offset) {
1031 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
1033 /* We removed the gtt_offset for the copy loop above, indexing
1034 * relative to oa_buf_base so put back here...
1038 intel_uncore_write(uncore, GEN7_OASTATUS2,
1039 (head & GEN7_OASTATUS2_HEAD_MASK) |
1040 GEN7_OASTATUS2_MEM_SELECT_GGTT);
1041 stream->oa_buffer.head = head;
1043 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
1050 * gen7_oa_read - copy status records then buffered OA reports
1051 * @stream: An i915-perf stream opened for OA metrics
1052 * @buf: destination buffer given by userspace
1053 * @count: the number of bytes userspace wants to read
1054 * @offset: (inout): the current position for writing into @buf
1056 * Checks Gen 7 specific OA unit status registers and if necessary appends
1057 * corresponding status records for userspace (such as for a buffer full
1058 * condition) and then initiate appending any buffered OA reports.
1060 * Updates @offset according to the number of bytes successfully copied into
1061 * the userspace buffer.
1063 * Returns: zero on success or a negative error code
1065 static int gen7_oa_read(struct i915_perf_stream *stream,
1070 struct intel_uncore *uncore = stream->uncore;
1074 if (drm_WARN_ON(&uncore->i915->drm, !stream->oa_buffer.vaddr))
1077 oastatus1 = intel_uncore_read(uncore, GEN7_OASTATUS1);
1079 /* XXX: On Haswell we don't have a safe way to clear oastatus1
1080 * bits while the OA unit is enabled (while the tail pointer
1081 * may be updated asynchronously) so we ignore status bits
1082 * that have already been reported to userspace.
1084 oastatus1 &= ~stream->perf->gen7_latched_oastatus1;
1086 /* We treat OABUFFER_OVERFLOW as a significant error:
1088 * - The status can be interpreted to mean that the buffer is
1089 * currently full (with a higher precedence than OA_TAKEN()
1090 * which will start to report a near-empty buffer after an
1091 * overflow) but it's awkward that we can't clear the status
1092 * on Haswell, so without a reset we won't be able to catch
1095 * - Since it also implies the HW has started overwriting old
1096 * reports it may also affect our sanity checks for invalid
1097 * reports when copying to userspace that assume new reports
1098 * are being written to cleared memory.
1100 * - In the future we may want to introduce a flight recorder
1101 * mode where the driver will automatically maintain a safe
1102 * guard band between head/tail, avoiding this overflow
1103 * condition, but we avoid the added driver complexity for
1106 if (unlikely(oastatus1 & GEN7_OASTATUS1_OABUFFER_OVERFLOW)) {
1107 ret = append_oa_status(stream, buf, count, offset,
1108 DRM_I915_PERF_RECORD_OA_BUFFER_LOST);
1112 drm_dbg(&stream->perf->i915->drm,
1113 "OA buffer overflow (exponent = %d): force restart\n",
1114 stream->period_exponent);
1116 stream->perf->ops.oa_disable(stream);
1117 stream->perf->ops.oa_enable(stream);
1119 oastatus1 = intel_uncore_read(uncore, GEN7_OASTATUS1);
1122 if (unlikely(oastatus1 & GEN7_OASTATUS1_REPORT_LOST)) {
1123 ret = append_oa_status(stream, buf, count, offset,
1124 DRM_I915_PERF_RECORD_OA_REPORT_LOST);
1127 stream->perf->gen7_latched_oastatus1 |=
1128 GEN7_OASTATUS1_REPORT_LOST;
1131 return gen7_append_oa_reports(stream, buf, count, offset);
1135 * i915_oa_wait_unlocked - handles blocking IO until OA data available
1136 * @stream: An i915-perf stream opened for OA metrics
1138 * Called when userspace tries to read() from a blocking stream FD opened
1139 * for OA metrics. It waits until the hrtimer callback finds a non-empty
1140 * OA buffer and wakes us.
1142 * Note: it's acceptable to have this return with some false positives
1143 * since any subsequent read handling will return -EAGAIN if there isn't
1144 * really data ready for userspace yet.
1146 * Returns: zero on success or a negative error code
1148 static int i915_oa_wait_unlocked(struct i915_perf_stream *stream)
1150 /* We would wait indefinitely if periodic sampling is not enabled */
1151 if (!stream->periodic)
1154 return wait_event_interruptible(stream->poll_wq,
1155 oa_buffer_check_unlocked(stream));
1159 * i915_oa_poll_wait - call poll_wait() for an OA stream poll()
1160 * @stream: An i915-perf stream opened for OA metrics
1161 * @file: An i915 perf stream file
1162 * @wait: poll() state table
1164 * For handling userspace polling on an i915 perf stream opened for OA metrics,
1165 * this starts a poll_wait with the wait queue that our hrtimer callback wakes
1166 * when it sees data ready to read in the circular OA buffer.
1168 static void i915_oa_poll_wait(struct i915_perf_stream *stream,
1172 poll_wait(file, &stream->poll_wq, wait);
1176 * i915_oa_read - just calls through to &i915_oa_ops->read
1177 * @stream: An i915-perf stream opened for OA metrics
1178 * @buf: destination buffer given by userspace
1179 * @count: the number of bytes userspace wants to read
1180 * @offset: (inout): the current position for writing into @buf
1182 * Updates @offset according to the number of bytes successfully copied into
1183 * the userspace buffer.
1185 * Returns: zero on success or a negative error code
1187 static int i915_oa_read(struct i915_perf_stream *stream,
1192 return stream->perf->ops.read(stream, buf, count, offset);
1195 static struct intel_context *oa_pin_context(struct i915_perf_stream *stream)
1197 struct i915_gem_engines_iter it;
1198 struct i915_gem_context *ctx = stream->ctx;
1199 struct intel_context *ce;
1200 struct i915_gem_ww_ctx ww;
1203 for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
1204 if (ce->engine != stream->engine) /* first match! */
1210 i915_gem_context_unlock_engines(ctx);
1213 return ERR_PTR(err);
1215 i915_gem_ww_ctx_init(&ww, true);
1218 * As the ID is the gtt offset of the context's vma we
1219 * pin the vma to ensure the ID remains fixed.
1221 err = intel_context_pin_ww(ce, &ww);
1222 if (err == -EDEADLK) {
1223 err = i915_gem_ww_ctx_backoff(&ww);
1227 i915_gem_ww_ctx_fini(&ww);
1230 return ERR_PTR(err);
1232 stream->pinned_ctx = ce;
1233 return stream->pinned_ctx;
1237 * oa_get_render_ctx_id - determine and hold ctx hw id
1238 * @stream: An i915-perf stream opened for OA metrics
1240 * Determine the render context hw id, and ensure it remains fixed for the
1241 * lifetime of the stream. This ensures that we don't have to worry about
1242 * updating the context ID in OACONTROL on the fly.
1244 * Returns: zero on success or a negative error code
1246 static int oa_get_render_ctx_id(struct i915_perf_stream *stream)
1248 struct intel_context *ce;
1250 ce = oa_pin_context(stream);
1254 switch (GRAPHICS_VER(ce->engine->i915)) {
1257 * On Haswell we don't do any post processing of the reports
1258 * and don't need to use the mask.
1260 stream->specific_ctx_id = i915_ggtt_offset(ce->state);
1261 stream->specific_ctx_id_mask = 0;
1267 if (intel_engine_uses_guc(ce->engine)) {
1269 * When using GuC, the context descriptor we write in
1270 * i915 is read by GuC and rewritten before it's
1271 * actually written into the hardware. The LRCA is
1272 * what is put into the context id field of the
1273 * context descriptor by GuC. Because it's aligned to
1274 * a page, the lower 12bits are always at 0 and
1275 * dropped by GuC. They won't be part of the context
1276 * ID in the OA reports, so squash those lower bits.
1278 stream->specific_ctx_id = ce->lrc.lrca >> 12;
1281 * GuC uses the top bit to signal proxy submission, so
1284 stream->specific_ctx_id_mask =
1285 (1U << (GEN8_CTX_ID_WIDTH - 1)) - 1;
1287 stream->specific_ctx_id_mask =
1288 (1U << GEN8_CTX_ID_WIDTH) - 1;
1289 stream->specific_ctx_id = stream->specific_ctx_id_mask;
1295 if (GRAPHICS_VER_FULL(ce->engine->i915) >= IP_VER(12, 50)) {
1296 stream->specific_ctx_id_mask =
1297 ((1U << XEHP_SW_CTX_ID_WIDTH) - 1) <<
1298 (XEHP_SW_CTX_ID_SHIFT - 32);
1299 stream->specific_ctx_id =
1300 (XEHP_MAX_CONTEXT_HW_ID - 1) <<
1301 (XEHP_SW_CTX_ID_SHIFT - 32);
1303 stream->specific_ctx_id_mask =
1304 ((1U << GEN11_SW_CTX_ID_WIDTH) - 1) << (GEN11_SW_CTX_ID_SHIFT - 32);
1306 * Pick an unused context id
1307 * 0 - BITS_PER_LONG are used by other contexts
1308 * GEN12_MAX_CONTEXT_HW_ID (0x7ff) is used by idle context
1310 stream->specific_ctx_id =
1311 (GEN12_MAX_CONTEXT_HW_ID - 1) << (GEN11_SW_CTX_ID_SHIFT - 32);
1316 MISSING_CASE(GRAPHICS_VER(ce->engine->i915));
1319 ce->tag = stream->specific_ctx_id;
1321 drm_dbg(&stream->perf->i915->drm,
1322 "filtering on ctx_id=0x%x ctx_id_mask=0x%x\n",
1323 stream->specific_ctx_id,
1324 stream->specific_ctx_id_mask);
1330 * oa_put_render_ctx_id - counterpart to oa_get_render_ctx_id releases hold
1331 * @stream: An i915-perf stream opened for OA metrics
1333 * In case anything needed doing to ensure the context HW ID would remain valid
1334 * for the lifetime of the stream, then that can be undone here.
1336 static void oa_put_render_ctx_id(struct i915_perf_stream *stream)
1338 struct intel_context *ce;
1340 ce = fetch_and_zero(&stream->pinned_ctx);
1342 ce->tag = 0; /* recomputed on next submission after parking */
1343 intel_context_unpin(ce);
1346 stream->specific_ctx_id = INVALID_CTX_ID;
1347 stream->specific_ctx_id_mask = 0;
1351 free_oa_buffer(struct i915_perf_stream *stream)
1353 i915_vma_unpin_and_release(&stream->oa_buffer.vma,
1354 I915_VMA_RELEASE_MAP);
1356 stream->oa_buffer.vaddr = NULL;
1360 free_oa_configs(struct i915_perf_stream *stream)
1362 struct i915_oa_config_bo *oa_bo, *tmp;
1364 i915_oa_config_put(stream->oa_config);
1365 llist_for_each_entry_safe(oa_bo, tmp, stream->oa_config_bos.first, node)
1366 free_oa_config_bo(oa_bo);
1370 free_noa_wait(struct i915_perf_stream *stream)
1372 i915_vma_unpin_and_release(&stream->noa_wait, 0);
1375 static void i915_oa_stream_destroy(struct i915_perf_stream *stream)
1377 struct i915_perf *perf = stream->perf;
1379 BUG_ON(stream != perf->exclusive_stream);
1382 * Unset exclusive_stream first, it will be checked while disabling
1383 * the metric set on gen8+.
1385 * See i915_oa_init_reg_state() and lrc_configure_all_contexts()
1387 WRITE_ONCE(perf->exclusive_stream, NULL);
1388 perf->ops.disable_metric_set(stream);
1390 free_oa_buffer(stream);
1392 intel_uncore_forcewake_put(stream->uncore, FORCEWAKE_ALL);
1393 intel_engine_pm_put(stream->engine);
1396 oa_put_render_ctx_id(stream);
1398 free_oa_configs(stream);
1399 free_noa_wait(stream);
1401 if (perf->spurious_report_rs.missed) {
1402 DRM_NOTE("%d spurious OA report notices suppressed due to ratelimiting\n",
1403 perf->spurious_report_rs.missed);
1407 static void gen7_init_oa_buffer(struct i915_perf_stream *stream)
1409 struct intel_uncore *uncore = stream->uncore;
1410 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
1411 unsigned long flags;
1413 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
1415 /* Pre-DevBDW: OABUFFER must be set with counters off,
1416 * before OASTATUS1, but after OASTATUS2
1418 intel_uncore_write(uncore, GEN7_OASTATUS2, /* head */
1419 gtt_offset | GEN7_OASTATUS2_MEM_SELECT_GGTT);
1420 stream->oa_buffer.head = gtt_offset;
1422 intel_uncore_write(uncore, GEN7_OABUFFER, gtt_offset);
1424 intel_uncore_write(uncore, GEN7_OASTATUS1, /* tail */
1425 gtt_offset | OABUFFER_SIZE_16M);
1427 /* Mark that we need updated tail pointers to read from... */
1428 stream->oa_buffer.aging_tail = INVALID_TAIL_PTR;
1429 stream->oa_buffer.tail = gtt_offset;
1431 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
1433 /* On Haswell we have to track which OASTATUS1 flags we've
1434 * already seen since they can't be cleared while periodic
1435 * sampling is enabled.
1437 stream->perf->gen7_latched_oastatus1 = 0;
1439 /* NB: although the OA buffer will initially be allocated
1440 * zeroed via shmfs (and so this memset is redundant when
1441 * first allocating), we may re-init the OA buffer, either
1442 * when re-enabling a stream or in error/reset paths.
1444 * The reason we clear the buffer for each re-init is for the
1445 * sanity check in gen7_append_oa_reports() that looks at the
1446 * report-id field to make sure it's non-zero which relies on
1447 * the assumption that new reports are being written to zeroed
1450 memset(stream->oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
1453 static void gen8_init_oa_buffer(struct i915_perf_stream *stream)
1455 struct intel_uncore *uncore = stream->uncore;
1456 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
1457 unsigned long flags;
1459 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
1461 intel_uncore_write(uncore, GEN8_OASTATUS, 0);
1462 intel_uncore_write(uncore, GEN8_OAHEADPTR, gtt_offset);
1463 stream->oa_buffer.head = gtt_offset;
1465 intel_uncore_write(uncore, GEN8_OABUFFER_UDW, 0);
1470 * "This MMIO must be set before the OATAILPTR
1471 * register and after the OAHEADPTR register. This is
1472 * to enable proper functionality of the overflow
1475 intel_uncore_write(uncore, GEN8_OABUFFER, gtt_offset |
1476 OABUFFER_SIZE_16M | GEN8_OABUFFER_MEM_SELECT_GGTT);
1477 intel_uncore_write(uncore, GEN8_OATAILPTR, gtt_offset & GEN8_OATAILPTR_MASK);
1479 /* Mark that we need updated tail pointers to read from... */
1480 stream->oa_buffer.aging_tail = INVALID_TAIL_PTR;
1481 stream->oa_buffer.tail = gtt_offset;
1484 * Reset state used to recognise context switches, affecting which
1485 * reports we will forward to userspace while filtering for a single
1488 stream->oa_buffer.last_ctx_id = INVALID_CTX_ID;
1490 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
1493 * NB: although the OA buffer will initially be allocated
1494 * zeroed via shmfs (and so this memset is redundant when
1495 * first allocating), we may re-init the OA buffer, either
1496 * when re-enabling a stream or in error/reset paths.
1498 * The reason we clear the buffer for each re-init is for the
1499 * sanity check in gen8_append_oa_reports() that looks at the
1500 * reason field to make sure it's non-zero which relies on
1501 * the assumption that new reports are being written to zeroed
1504 memset(stream->oa_buffer.vaddr, 0, OA_BUFFER_SIZE);
1507 static void gen12_init_oa_buffer(struct i915_perf_stream *stream)
1509 struct intel_uncore *uncore = stream->uncore;
1510 u32 gtt_offset = i915_ggtt_offset(stream->oa_buffer.vma);
1511 unsigned long flags;
1513 spin_lock_irqsave(&stream->oa_buffer.ptr_lock, flags);
1515 intel_uncore_write(uncore, GEN12_OAG_OASTATUS, 0);
1516 intel_uncore_write(uncore, GEN12_OAG_OAHEADPTR,
1517 gtt_offset & GEN12_OAG_OAHEADPTR_MASK);
1518 stream->oa_buffer.head = gtt_offset;
1523 * "This MMIO must be set before the OATAILPTR
1524 * register and after the OAHEADPTR register. This is
1525 * to enable proper functionality of the overflow
1528 intel_uncore_write(uncore, GEN12_OAG_OABUFFER, gtt_offset |
1529 OABUFFER_SIZE_16M | GEN8_OABUFFER_MEM_SELECT_GGTT);
1530 intel_uncore_write(uncore, GEN12_OAG_OATAILPTR,
1531 gtt_offset & GEN12_OAG_OATAILPTR_MASK);
1533 /* Mark that we need updated tail pointers to read from... */
1534 stream->oa_buffer.aging_tail = INVALID_TAIL_PTR;
1535 stream->oa_buffer.tail = gtt_offset;
1538 * Reset state used to recognise context switches, affecting which
1539 * reports we will forward to userspace while filtering for a single
1542 stream->oa_buffer.last_ctx_id = INVALID_CTX_ID;
1544 spin_unlock_irqrestore(&stream->oa_buffer.ptr_lock, flags);
1547 * NB: although the OA buffer will initially be allocated
1548 * zeroed via shmfs (and so this memset is redundant when
1549 * first allocating), we may re-init the OA buffer, either
1550 * when re-enabling a stream or in error/reset paths.
1552 * The reason we clear the buffer for each re-init is for the
1553 * sanity check in gen8_append_oa_reports() that looks at the
1554 * reason field to make sure it's non-zero which relies on
1555 * the assumption that new reports are being written to zeroed
1558 memset(stream->oa_buffer.vaddr, 0,
1559 stream->oa_buffer.vma->size);
1562 static int alloc_oa_buffer(struct i915_perf_stream *stream)
1564 struct drm_i915_private *i915 = stream->perf->i915;
1565 struct drm_i915_gem_object *bo;
1566 struct i915_vma *vma;
1569 if (drm_WARN_ON(&i915->drm, stream->oa_buffer.vma))
1572 BUILD_BUG_ON_NOT_POWER_OF_2(OA_BUFFER_SIZE);
1573 BUILD_BUG_ON(OA_BUFFER_SIZE < SZ_128K || OA_BUFFER_SIZE > SZ_16M);
1575 bo = i915_gem_object_create_shmem(stream->perf->i915, OA_BUFFER_SIZE);
1577 drm_err(&i915->drm, "Failed to allocate OA buffer\n");
1581 i915_gem_object_set_cache_coherency(bo, I915_CACHE_LLC);
1583 /* PreHSW required 512K alignment, HSW requires 16M */
1584 vma = i915_gem_object_ggtt_pin(bo, NULL, 0, SZ_16M, 0);
1589 stream->oa_buffer.vma = vma;
1591 stream->oa_buffer.vaddr =
1592 i915_gem_object_pin_map_unlocked(bo, I915_MAP_WB);
1593 if (IS_ERR(stream->oa_buffer.vaddr)) {
1594 ret = PTR_ERR(stream->oa_buffer.vaddr);
1601 __i915_vma_unpin(vma);
1604 i915_gem_object_put(bo);
1606 stream->oa_buffer.vaddr = NULL;
1607 stream->oa_buffer.vma = NULL;
1612 static u32 *save_restore_register(struct i915_perf_stream *stream, u32 *cs,
1613 bool save, i915_reg_t reg, u32 offset,
1619 cmd = save ? MI_STORE_REGISTER_MEM : MI_LOAD_REGISTER_MEM;
1620 cmd |= MI_SRM_LRM_GLOBAL_GTT;
1621 if (GRAPHICS_VER(stream->perf->i915) >= 8)
1624 for (d = 0; d < dword_count; d++) {
1626 *cs++ = i915_mmio_reg_offset(reg) + 4 * d;
1627 *cs++ = intel_gt_scratch_offset(stream->engine->gt,
1635 static int alloc_noa_wait(struct i915_perf_stream *stream)
1637 struct drm_i915_private *i915 = stream->perf->i915;
1638 struct drm_i915_gem_object *bo;
1639 struct i915_vma *vma;
1640 const u64 delay_ticks = 0xffffffffffffffff -
1641 intel_gt_ns_to_clock_interval(to_gt(stream->perf->i915),
1642 atomic64_read(&stream->perf->noa_programming_delay));
1643 const u32 base = stream->engine->mmio_base;
1644 #define CS_GPR(x) GEN8_RING_CS_GPR(base, x)
1645 u32 *batch, *ts0, *cs, *jump;
1646 struct i915_gem_ww_ctx ww;
1657 bo = i915_gem_object_create_internal(i915, 4096);
1660 "Failed to allocate NOA wait batchbuffer\n");
1664 i915_gem_ww_ctx_init(&ww, true);
1666 ret = i915_gem_object_lock(bo, &ww);
1671 * We pin in GGTT because we jump into this buffer now because
1672 * multiple OA config BOs will have a jump to this address and it
1673 * needs to be fixed during the lifetime of the i915/perf stream.
1675 vma = i915_gem_object_ggtt_pin_ww(bo, &ww, NULL, 0, 0, PIN_HIGH);
1681 batch = cs = i915_gem_object_pin_map(bo, I915_MAP_WB);
1682 if (IS_ERR(batch)) {
1683 ret = PTR_ERR(batch);
1687 /* Save registers. */
1688 for (i = 0; i < N_CS_GPR; i++)
1689 cs = save_restore_register(
1690 stream, cs, true /* save */, CS_GPR(i),
1691 INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
1692 cs = save_restore_register(
1693 stream, cs, true /* save */, MI_PREDICATE_RESULT_1(RENDER_RING_BASE),
1694 INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
1696 /* First timestamp snapshot location. */
1700 * Initial snapshot of the timestamp register to implement the wait.
1701 * We work with 32b values, so clear out the top 32b bits of the
1702 * register because the ALU works 64bits.
1704 *cs++ = MI_LOAD_REGISTER_IMM(1);
1705 *cs++ = i915_mmio_reg_offset(CS_GPR(START_TS)) + 4;
1707 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
1708 *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base));
1709 *cs++ = i915_mmio_reg_offset(CS_GPR(START_TS));
1712 * This is the location we're going to jump back into until the
1713 * required amount of time has passed.
1718 * Take another snapshot of the timestamp register. Take care to clear
1719 * up the top 32bits of CS_GPR(1) as we're using it for other
1722 *cs++ = MI_LOAD_REGISTER_IMM(1);
1723 *cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS)) + 4;
1725 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
1726 *cs++ = i915_mmio_reg_offset(RING_TIMESTAMP(base));
1727 *cs++ = i915_mmio_reg_offset(CS_GPR(NOW_TS));
1730 * Do a diff between the 2 timestamps and store the result back into
1734 *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(NOW_TS));
1735 *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(START_TS));
1736 *cs++ = MI_MATH_SUB;
1737 *cs++ = MI_MATH_STORE(MI_MATH_REG(DELTA_TS), MI_MATH_REG_ACCU);
1738 *cs++ = MI_MATH_STORE(MI_MATH_REG(JUMP_PREDICATE), MI_MATH_REG_CF);
1741 * Transfer the carry flag (set to 1 if ts1 < ts0, meaning the
1742 * timestamp have rolled over the 32bits) into the predicate register
1743 * to be used for the predicated jump.
1745 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
1746 *cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));
1747 *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1(RENDER_RING_BASE));
1749 /* Restart from the beginning if we had timestamps roll over. */
1750 *cs++ = (GRAPHICS_VER(i915) < 8 ?
1751 MI_BATCH_BUFFER_START :
1752 MI_BATCH_BUFFER_START_GEN8) |
1754 *cs++ = i915_ggtt_offset(vma) + (ts0 - batch) * 4;
1758 * Now add the diff between to previous timestamps and add it to :
1759 * (((1 * << 64) - 1) - delay_ns)
1761 * When the Carry Flag contains 1 this means the elapsed time is
1762 * longer than the expected delay, and we can exit the wait loop.
1764 *cs++ = MI_LOAD_REGISTER_IMM(2);
1765 *cs++ = i915_mmio_reg_offset(CS_GPR(DELTA_TARGET));
1766 *cs++ = lower_32_bits(delay_ticks);
1767 *cs++ = i915_mmio_reg_offset(CS_GPR(DELTA_TARGET)) + 4;
1768 *cs++ = upper_32_bits(delay_ticks);
1771 *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCA, MI_MATH_REG(DELTA_TS));
1772 *cs++ = MI_MATH_LOAD(MI_MATH_REG_SRCB, MI_MATH_REG(DELTA_TARGET));
1773 *cs++ = MI_MATH_ADD;
1774 *cs++ = MI_MATH_STOREINV(MI_MATH_REG(JUMP_PREDICATE), MI_MATH_REG_CF);
1776 *cs++ = MI_ARB_CHECK;
1779 * Transfer the result into the predicate register to be used for the
1782 *cs++ = MI_LOAD_REGISTER_REG | (3 - 2);
1783 *cs++ = i915_mmio_reg_offset(CS_GPR(JUMP_PREDICATE));
1784 *cs++ = i915_mmio_reg_offset(MI_PREDICATE_RESULT_1(RENDER_RING_BASE));
1786 /* Predicate the jump. */
1787 *cs++ = (GRAPHICS_VER(i915) < 8 ?
1788 MI_BATCH_BUFFER_START :
1789 MI_BATCH_BUFFER_START_GEN8) |
1791 *cs++ = i915_ggtt_offset(vma) + (jump - batch) * 4;
1794 /* Restore registers. */
1795 for (i = 0; i < N_CS_GPR; i++)
1796 cs = save_restore_register(
1797 stream, cs, false /* restore */, CS_GPR(i),
1798 INTEL_GT_SCRATCH_FIELD_PERF_CS_GPR + 8 * i, 2);
1799 cs = save_restore_register(
1800 stream, cs, false /* restore */, MI_PREDICATE_RESULT_1(RENDER_RING_BASE),
1801 INTEL_GT_SCRATCH_FIELD_PERF_PREDICATE_RESULT_1, 1);
1803 /* And return to the ring. */
1804 *cs++ = MI_BATCH_BUFFER_END;
1806 GEM_BUG_ON(cs - batch > PAGE_SIZE / sizeof(*batch));
1808 i915_gem_object_flush_map(bo);
1809 __i915_gem_object_release_map(bo);
1811 stream->noa_wait = vma;
1815 i915_vma_unpin_and_release(&vma, 0);
1817 if (ret == -EDEADLK) {
1818 ret = i915_gem_ww_ctx_backoff(&ww);
1822 i915_gem_ww_ctx_fini(&ww);
1824 i915_gem_object_put(bo);
1828 static u32 *write_cs_mi_lri(u32 *cs,
1829 const struct i915_oa_reg *reg_data,
1834 for (i = 0; i < n_regs; i++) {
1835 if ((i % MI_LOAD_REGISTER_IMM_MAX_REGS) == 0) {
1836 u32 n_lri = min_t(u32,
1838 MI_LOAD_REGISTER_IMM_MAX_REGS);
1840 *cs++ = MI_LOAD_REGISTER_IMM(n_lri);
1842 *cs++ = i915_mmio_reg_offset(reg_data[i].addr);
1843 *cs++ = reg_data[i].value;
1849 static int num_lri_dwords(int num_regs)
1854 count += DIV_ROUND_UP(num_regs, MI_LOAD_REGISTER_IMM_MAX_REGS);
1855 count += num_regs * 2;
1861 static struct i915_oa_config_bo *
1862 alloc_oa_config_buffer(struct i915_perf_stream *stream,
1863 struct i915_oa_config *oa_config)
1865 struct drm_i915_gem_object *obj;
1866 struct i915_oa_config_bo *oa_bo;
1867 struct i915_gem_ww_ctx ww;
1868 size_t config_length = 0;
1872 oa_bo = kzalloc(sizeof(*oa_bo), GFP_KERNEL);
1874 return ERR_PTR(-ENOMEM);
1876 config_length += num_lri_dwords(oa_config->mux_regs_len);
1877 config_length += num_lri_dwords(oa_config->b_counter_regs_len);
1878 config_length += num_lri_dwords(oa_config->flex_regs_len);
1879 config_length += 3; /* MI_BATCH_BUFFER_START */
1880 config_length = ALIGN(sizeof(u32) * config_length, I915_GTT_PAGE_SIZE);
1882 obj = i915_gem_object_create_shmem(stream->perf->i915, config_length);
1888 i915_gem_ww_ctx_init(&ww, true);
1890 err = i915_gem_object_lock(obj, &ww);
1894 cs = i915_gem_object_pin_map(obj, I915_MAP_WB);
1900 cs = write_cs_mi_lri(cs,
1901 oa_config->mux_regs,
1902 oa_config->mux_regs_len);
1903 cs = write_cs_mi_lri(cs,
1904 oa_config->b_counter_regs,
1905 oa_config->b_counter_regs_len);
1906 cs = write_cs_mi_lri(cs,
1907 oa_config->flex_regs,
1908 oa_config->flex_regs_len);
1910 /* Jump into the active wait. */
1911 *cs++ = (GRAPHICS_VER(stream->perf->i915) < 8 ?
1912 MI_BATCH_BUFFER_START :
1913 MI_BATCH_BUFFER_START_GEN8);
1914 *cs++ = i915_ggtt_offset(stream->noa_wait);
1917 i915_gem_object_flush_map(obj);
1918 __i915_gem_object_release_map(obj);
1920 oa_bo->vma = i915_vma_instance(obj,
1921 &stream->engine->gt->ggtt->vm,
1923 if (IS_ERR(oa_bo->vma)) {
1924 err = PTR_ERR(oa_bo->vma);
1928 oa_bo->oa_config = i915_oa_config_get(oa_config);
1929 llist_add(&oa_bo->node, &stream->oa_config_bos);
1932 if (err == -EDEADLK) {
1933 err = i915_gem_ww_ctx_backoff(&ww);
1937 i915_gem_ww_ctx_fini(&ww);
1940 i915_gem_object_put(obj);
1944 return ERR_PTR(err);
1949 static struct i915_vma *
1950 get_oa_vma(struct i915_perf_stream *stream, struct i915_oa_config *oa_config)
1952 struct i915_oa_config_bo *oa_bo;
1955 * Look for the buffer in the already allocated BOs attached
1958 llist_for_each_entry(oa_bo, stream->oa_config_bos.first, node) {
1959 if (oa_bo->oa_config == oa_config &&
1960 memcmp(oa_bo->oa_config->uuid,
1962 sizeof(oa_config->uuid)) == 0)
1966 oa_bo = alloc_oa_config_buffer(stream, oa_config);
1968 return ERR_CAST(oa_bo);
1971 return i915_vma_get(oa_bo->vma);
1975 emit_oa_config(struct i915_perf_stream *stream,
1976 struct i915_oa_config *oa_config,
1977 struct intel_context *ce,
1978 struct i915_active *active)
1980 struct i915_request *rq;
1981 struct i915_vma *vma;
1982 struct i915_gem_ww_ctx ww;
1985 vma = get_oa_vma(stream, oa_config);
1987 return PTR_ERR(vma);
1989 i915_gem_ww_ctx_init(&ww, true);
1991 err = i915_gem_object_lock(vma->obj, &ww);
1995 err = i915_vma_pin_ww(vma, &ww, 0, 0, PIN_GLOBAL | PIN_HIGH);
1999 intel_engine_pm_get(ce->engine);
2000 rq = i915_request_create(ce);
2001 intel_engine_pm_put(ce->engine);
2007 if (!IS_ERR_OR_NULL(active)) {
2008 /* After all individual context modifications */
2009 err = i915_request_await_active(rq, active,
2010 I915_ACTIVE_AWAIT_ACTIVE);
2012 goto err_add_request;
2014 err = i915_active_add_request(active, rq);
2016 goto err_add_request;
2019 err = i915_request_await_object(rq, vma->obj, 0);
2021 err = i915_vma_move_to_active(vma, rq, 0);
2023 goto err_add_request;
2025 err = rq->engine->emit_bb_start(rq,
2027 I915_DISPATCH_SECURE);
2029 goto err_add_request;
2032 i915_request_add(rq);
2034 i915_vma_unpin(vma);
2036 if (err == -EDEADLK) {
2037 err = i915_gem_ww_ctx_backoff(&ww);
2042 i915_gem_ww_ctx_fini(&ww);
2047 static struct intel_context *oa_context(struct i915_perf_stream *stream)
2049 return stream->pinned_ctx ?: stream->engine->kernel_context;
2053 hsw_enable_metric_set(struct i915_perf_stream *stream,
2054 struct i915_active *active)
2056 struct intel_uncore *uncore = stream->uncore;
2061 * OA unit is using “crclk” for its functionality. When trunk
2062 * level clock gating takes place, OA clock would be gated,
2063 * unable to count the events from non-render clock domain.
2064 * Render clock gating must be disabled when OA is enabled to
2065 * count the events from non-render domain. Unit level clock
2066 * gating for RCS should also be disabled.
2068 intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
2069 GEN7_DOP_CLOCK_GATE_ENABLE, 0);
2070 intel_uncore_rmw(uncore, GEN6_UCGCTL1,
2071 0, GEN6_CSUNIT_CLOCK_GATE_DISABLE);
2073 return emit_oa_config(stream,
2074 stream->oa_config, oa_context(stream),
2078 static void hsw_disable_metric_set(struct i915_perf_stream *stream)
2080 struct intel_uncore *uncore = stream->uncore;
2082 intel_uncore_rmw(uncore, GEN6_UCGCTL1,
2083 GEN6_CSUNIT_CLOCK_GATE_DISABLE, 0);
2084 intel_uncore_rmw(uncore, GEN7_MISCCPCTL,
2085 0, GEN7_DOP_CLOCK_GATE_ENABLE);
2087 intel_uncore_rmw(uncore, GDT_CHICKEN_BITS, GT_NOA_ENABLE, 0);
2090 static u32 oa_config_flex_reg(const struct i915_oa_config *oa_config,
2093 u32 mmio = i915_mmio_reg_offset(reg);
2097 * This arbitrary default will select the 'EU FPU0 Pipeline
2098 * Active' event. In the future it's anticipated that there
2099 * will be an explicit 'No Event' we can select, but not yet...
2104 for (i = 0; i < oa_config->flex_regs_len; i++) {
2105 if (i915_mmio_reg_offset(oa_config->flex_regs[i].addr) == mmio)
2106 return oa_config->flex_regs[i].value;
2112 * NB: It must always remain pointer safe to run this even if the OA unit
2113 * has been disabled.
2115 * It's fine to put out-of-date values into these per-context registers
2116 * in the case that the OA unit has been disabled.
2119 gen8_update_reg_state_unlocked(const struct intel_context *ce,
2120 const struct i915_perf_stream *stream)
2122 u32 ctx_oactxctrl = stream->perf->ctx_oactxctrl_offset;
2123 u32 ctx_flexeu0 = stream->perf->ctx_flexeu0_offset;
2124 /* The MMIO offsets for Flex EU registers aren't contiguous */
2125 static const i915_reg_t flex_regs[] = {
2134 u32 *reg_state = ce->lrc_reg_state;
2137 reg_state[ctx_oactxctrl + 1] =
2138 (stream->period_exponent << GEN8_OA_TIMER_PERIOD_SHIFT) |
2139 (stream->periodic ? GEN8_OA_TIMER_ENABLE : 0) |
2140 GEN8_OA_COUNTER_RESUME;
2142 for (i = 0; i < ARRAY_SIZE(flex_regs); i++)
2143 reg_state[ctx_flexeu0 + i * 2 + 1] =
2144 oa_config_flex_reg(stream->oa_config, flex_regs[i]);
2154 gen8_store_flex(struct i915_request *rq,
2155 struct intel_context *ce,
2156 const struct flex *flex, unsigned int count)
2161 cs = intel_ring_begin(rq, 4 * count);
2165 offset = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET;
2167 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT;
2168 *cs++ = offset + flex->offset * sizeof(u32);
2170 *cs++ = flex->value;
2171 } while (flex++, --count);
2173 intel_ring_advance(rq, cs);
2179 gen8_load_flex(struct i915_request *rq,
2180 struct intel_context *ce,
2181 const struct flex *flex, unsigned int count)
2185 GEM_BUG_ON(!count || count > 63);
2187 cs = intel_ring_begin(rq, 2 * count + 2);
2191 *cs++ = MI_LOAD_REGISTER_IMM(count);
2193 *cs++ = i915_mmio_reg_offset(flex->reg);
2194 *cs++ = flex->value;
2195 } while (flex++, --count);
2198 intel_ring_advance(rq, cs);
2203 static int gen8_modify_context(struct intel_context *ce,
2204 const struct flex *flex, unsigned int count)
2206 struct i915_request *rq;
2209 rq = intel_engine_create_kernel_request(ce->engine);
2213 /* Serialise with the remote context */
2214 err = intel_context_prepare_remote_request(ce, rq);
2216 err = gen8_store_flex(rq, ce, flex, count);
2218 i915_request_add(rq);
2223 gen8_modify_self(struct intel_context *ce,
2224 const struct flex *flex, unsigned int count,
2225 struct i915_active *active)
2227 struct i915_request *rq;
2230 intel_engine_pm_get(ce->engine);
2231 rq = i915_request_create(ce);
2232 intel_engine_pm_put(ce->engine);
2236 if (!IS_ERR_OR_NULL(active)) {
2237 err = i915_active_add_request(active, rq);
2239 goto err_add_request;
2242 err = gen8_load_flex(rq, ce, flex, count);
2244 goto err_add_request;
2247 i915_request_add(rq);
2251 static int gen8_configure_context(struct i915_gem_context *ctx,
2252 struct flex *flex, unsigned int count)
2254 struct i915_gem_engines_iter it;
2255 struct intel_context *ce;
2258 for_each_gem_engine(ce, i915_gem_context_lock_engines(ctx), it) {
2259 GEM_BUG_ON(ce == ce->engine->kernel_context);
2261 if (ce->engine->class != RENDER_CLASS)
2264 /* Otherwise OA settings will be set upon first use */
2265 if (!intel_context_pin_if_active(ce))
2268 flex->value = intel_sseu_make_rpcs(ce->engine->gt, &ce->sseu);
2269 err = gen8_modify_context(ce, flex, count);
2271 intel_context_unpin(ce);
2275 i915_gem_context_unlock_engines(ctx);
2280 static int gen12_configure_oar_context(struct i915_perf_stream *stream,
2281 struct i915_active *active)
2284 struct intel_context *ce = stream->pinned_ctx;
2285 u32 format = stream->oa_buffer.format;
2286 struct flex regs_context[] = {
2289 stream->perf->ctx_oactxctrl_offset + 1,
2290 active ? GEN8_OA_COUNTER_RESUME : 0,
2293 /* Offsets in regs_lri are not used since this configuration is only
2294 * applied using LRI. Initialize the correct offsets for posterity.
2296 #define GEN12_OAR_OACONTROL_OFFSET 0x5B0
2297 struct flex regs_lri[] = {
2299 GEN12_OAR_OACONTROL,
2300 GEN12_OAR_OACONTROL_OFFSET + 1,
2301 (format << GEN12_OAR_OACONTROL_COUNTER_FORMAT_SHIFT) |
2302 (active ? GEN12_OAR_OACONTROL_COUNTER_ENABLE : 0)
2305 RING_CONTEXT_CONTROL(ce->engine->mmio_base),
2306 CTX_CONTEXT_CONTROL,
2307 _MASKED_FIELD(GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE,
2309 GEN12_CTX_CTRL_OAR_CONTEXT_ENABLE :
2314 /* Modify the context image of pinned context with regs_context*/
2315 err = intel_context_lock_pinned(ce);
2319 err = gen8_modify_context(ce, regs_context, ARRAY_SIZE(regs_context));
2320 intel_context_unlock_pinned(ce);
2324 /* Apply regs_lri using LRI with pinned context */
2325 return gen8_modify_self(ce, regs_lri, ARRAY_SIZE(regs_lri), active);
2329 * Manages updating the per-context aspects of the OA stream
2330 * configuration across all contexts.
2332 * The awkward consideration here is that OACTXCONTROL controls the
2333 * exponent for periodic sampling which is primarily used for system
2334 * wide profiling where we'd like a consistent sampling period even in
2335 * the face of context switches.
2337 * Our approach of updating the register state context (as opposed to
2338 * say using a workaround batch buffer) ensures that the hardware
2339 * won't automatically reload an out-of-date timer exponent even
2340 * transiently before a WA BB could be parsed.
2342 * This function needs to:
2343 * - Ensure the currently running context's per-context OA state is
2345 * - Ensure that all existing contexts will have the correct per-context
2346 * OA state if they are scheduled for use.
2347 * - Ensure any new contexts will be initialized with the correct
2348 * per-context OA state.
2350 * Note: it's only the RCS/Render context that has any OA state.
2351 * Note: the first flex register passed must always be R_PWR_CLK_STATE
2354 oa_configure_all_contexts(struct i915_perf_stream *stream,
2357 struct i915_active *active)
2359 struct drm_i915_private *i915 = stream->perf->i915;
2360 struct intel_engine_cs *engine;
2361 struct i915_gem_context *ctx, *cn;
2364 lockdep_assert_held(&stream->perf->lock);
2367 * The OA register config is setup through the context image. This image
2368 * might be written to by the GPU on context switch (in particular on
2369 * lite-restore). This means we can't safely update a context's image,
2370 * if this context is scheduled/submitted to run on the GPU.
2372 * We could emit the OA register config through the batch buffer but
2373 * this might leave small interval of time where the OA unit is
2374 * configured at an invalid sampling period.
2376 * Note that since we emit all requests from a single ring, there
2377 * is still an implicit global barrier here that may cause a high
2378 * priority context to wait for an otherwise independent low priority
2379 * context. Contexts idle at the time of reconfiguration are not
2380 * trapped behind the barrier.
2382 spin_lock(&i915->gem.contexts.lock);
2383 list_for_each_entry_safe(ctx, cn, &i915->gem.contexts.list, link) {
2384 if (!kref_get_unless_zero(&ctx->ref))
2387 spin_unlock(&i915->gem.contexts.lock);
2389 err = gen8_configure_context(ctx, regs, num_regs);
2391 i915_gem_context_put(ctx);
2395 spin_lock(&i915->gem.contexts.lock);
2396 list_safe_reset_next(ctx, cn, link);
2397 i915_gem_context_put(ctx);
2399 spin_unlock(&i915->gem.contexts.lock);
2402 * After updating all other contexts, we need to modify ourselves.
2403 * If we don't modify the kernel_context, we do not get events while
2406 for_each_uabi_engine(engine, i915) {
2407 struct intel_context *ce = engine->kernel_context;
2409 if (engine->class != RENDER_CLASS)
2412 regs[0].value = intel_sseu_make_rpcs(engine->gt, &ce->sseu);
2414 err = gen8_modify_self(ce, regs, num_regs, active);
2423 gen12_configure_all_contexts(struct i915_perf_stream *stream,
2424 const struct i915_oa_config *oa_config,
2425 struct i915_active *active)
2427 struct flex regs[] = {
2429 GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),
2430 CTX_R_PWR_CLK_STATE,
2434 return oa_configure_all_contexts(stream,
2435 regs, ARRAY_SIZE(regs),
2440 lrc_configure_all_contexts(struct i915_perf_stream *stream,
2441 const struct i915_oa_config *oa_config,
2442 struct i915_active *active)
2444 /* The MMIO offsets for Flex EU registers aren't contiguous */
2445 const u32 ctx_flexeu0 = stream->perf->ctx_flexeu0_offset;
2446 #define ctx_flexeuN(N) (ctx_flexeu0 + 2 * (N) + 1)
2447 struct flex regs[] = {
2449 GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE),
2450 CTX_R_PWR_CLK_STATE,
2454 stream->perf->ctx_oactxctrl_offset + 1,
2456 { EU_PERF_CNTL0, ctx_flexeuN(0) },
2457 { EU_PERF_CNTL1, ctx_flexeuN(1) },
2458 { EU_PERF_CNTL2, ctx_flexeuN(2) },
2459 { EU_PERF_CNTL3, ctx_flexeuN(3) },
2460 { EU_PERF_CNTL4, ctx_flexeuN(4) },
2461 { EU_PERF_CNTL5, ctx_flexeuN(5) },
2462 { EU_PERF_CNTL6, ctx_flexeuN(6) },
2468 (stream->period_exponent << GEN8_OA_TIMER_PERIOD_SHIFT) |
2469 (stream->periodic ? GEN8_OA_TIMER_ENABLE : 0) |
2470 GEN8_OA_COUNTER_RESUME;
2472 for (i = 2; i < ARRAY_SIZE(regs); i++)
2473 regs[i].value = oa_config_flex_reg(oa_config, regs[i].reg);
2475 return oa_configure_all_contexts(stream,
2476 regs, ARRAY_SIZE(regs),
2481 gen8_enable_metric_set(struct i915_perf_stream *stream,
2482 struct i915_active *active)
2484 struct intel_uncore *uncore = stream->uncore;
2485 struct i915_oa_config *oa_config = stream->oa_config;
2489 * We disable slice/unslice clock ratio change reports on SKL since
2490 * they are too noisy. The HW generates a lot of redundant reports
2491 * where the ratio hasn't really changed causing a lot of redundant
2492 * work to processes and increasing the chances we'll hit buffer
2495 * Although we don't currently use the 'disable overrun' OABUFFER
2496 * feature it's worth noting that clock ratio reports have to be
2497 * disabled before considering to use that feature since the HW doesn't
2498 * correctly block these reports.
2500 * Currently none of the high-level metrics we have depend on knowing
2501 * this ratio to normalize.
2503 * Note: This register is not power context saved and restored, but
2504 * that's OK considering that we disable RC6 while the OA unit is
2507 * The _INCLUDE_CLK_RATIO bit allows the slice/unslice frequency to
2508 * be read back from automatically triggered reports, as part of the
2511 if (IS_GRAPHICS_VER(stream->perf->i915, 9, 11)) {
2512 intel_uncore_write(uncore, GEN8_OA_DEBUG,
2513 _MASKED_BIT_ENABLE(GEN9_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
2514 GEN9_OA_DEBUG_INCLUDE_CLK_RATIO));
2518 * Update all contexts prior writing the mux configurations as we need
2519 * to make sure all slices/subslices are ON before writing to NOA
2522 ret = lrc_configure_all_contexts(stream, oa_config, active);
2526 return emit_oa_config(stream,
2527 stream->oa_config, oa_context(stream),
2531 static u32 oag_report_ctx_switches(const struct i915_perf_stream *stream)
2533 return _MASKED_FIELD(GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS,
2534 (stream->sample_flags & SAMPLE_OA_REPORT) ?
2535 0 : GEN12_OAG_OA_DEBUG_DISABLE_CTX_SWITCH_REPORTS);
2539 gen12_enable_metric_set(struct i915_perf_stream *stream,
2540 struct i915_active *active)
2542 struct intel_uncore *uncore = stream->uncore;
2543 struct i915_oa_config *oa_config = stream->oa_config;
2544 bool periodic = stream->periodic;
2545 u32 period_exponent = stream->period_exponent;
2548 intel_uncore_write(uncore, GEN12_OAG_OA_DEBUG,
2549 /* Disable clk ratio reports, like previous Gens. */
2550 _MASKED_BIT_ENABLE(GEN12_OAG_OA_DEBUG_DISABLE_CLK_RATIO_REPORTS |
2551 GEN12_OAG_OA_DEBUG_INCLUDE_CLK_RATIO) |
2553 * If the user didn't require OA reports, instruct
2554 * the hardware not to emit ctx switch reports.
2556 oag_report_ctx_switches(stream));
2558 intel_uncore_write(uncore, GEN12_OAG_OAGLBCTXCTRL, periodic ?
2559 (GEN12_OAG_OAGLBCTXCTRL_COUNTER_RESUME |
2560 GEN12_OAG_OAGLBCTXCTRL_TIMER_ENABLE |
2561 (period_exponent << GEN12_OAG_OAGLBCTXCTRL_TIMER_PERIOD_SHIFT))
2565 * Update all contexts prior writing the mux configurations as we need
2566 * to make sure all slices/subslices are ON before writing to NOA
2569 ret = gen12_configure_all_contexts(stream, oa_config, active);
2574 * For Gen12, performance counters are context
2575 * saved/restored. Only enable it for the context that
2579 ret = gen12_configure_oar_context(stream, active);
2584 return emit_oa_config(stream,
2585 stream->oa_config, oa_context(stream),
2589 static void gen8_disable_metric_set(struct i915_perf_stream *stream)
2591 struct intel_uncore *uncore = stream->uncore;
2593 /* Reset all contexts' slices/subslices configurations. */
2594 lrc_configure_all_contexts(stream, NULL, NULL);
2596 intel_uncore_rmw(uncore, GDT_CHICKEN_BITS, GT_NOA_ENABLE, 0);
2599 static void gen11_disable_metric_set(struct i915_perf_stream *stream)
2601 struct intel_uncore *uncore = stream->uncore;
2603 /* Reset all contexts' slices/subslices configurations. */
2604 lrc_configure_all_contexts(stream, NULL, NULL);
2606 /* Make sure we disable noa to save power. */
2607 intel_uncore_rmw(uncore, RPM_CONFIG1, GEN10_GT_NOA_ENABLE, 0);
2610 static void gen12_disable_metric_set(struct i915_perf_stream *stream)
2612 struct intel_uncore *uncore = stream->uncore;
2614 /* Reset all contexts' slices/subslices configurations. */
2615 gen12_configure_all_contexts(stream, NULL, NULL);
2617 /* disable the context save/restore or OAR counters */
2619 gen12_configure_oar_context(stream, NULL);
2621 /* Make sure we disable noa to save power. */
2622 intel_uncore_rmw(uncore, RPM_CONFIG1, GEN10_GT_NOA_ENABLE, 0);
2625 static void gen7_oa_enable(struct i915_perf_stream *stream)
2627 struct intel_uncore *uncore = stream->uncore;
2628 struct i915_gem_context *ctx = stream->ctx;
2629 u32 ctx_id = stream->specific_ctx_id;
2630 bool periodic = stream->periodic;
2631 u32 period_exponent = stream->period_exponent;
2632 u32 report_format = stream->oa_buffer.format;
2635 * Reset buf pointers so we don't forward reports from before now.
2637 * Think carefully if considering trying to avoid this, since it
2638 * also ensures status flags and the buffer itself are cleared
2639 * in error paths, and we have checks for invalid reports based
2640 * on the assumption that certain fields are written to zeroed
2641 * memory which this helps maintains.
2643 gen7_init_oa_buffer(stream);
2645 intel_uncore_write(uncore, GEN7_OACONTROL,
2646 (ctx_id & GEN7_OACONTROL_CTX_MASK) |
2648 GEN7_OACONTROL_TIMER_PERIOD_SHIFT) |
2649 (periodic ? GEN7_OACONTROL_TIMER_ENABLE : 0) |
2650 (report_format << GEN7_OACONTROL_FORMAT_SHIFT) |
2651 (ctx ? GEN7_OACONTROL_PER_CTX_ENABLE : 0) |
2652 GEN7_OACONTROL_ENABLE);
2655 static void gen8_oa_enable(struct i915_perf_stream *stream)
2657 struct intel_uncore *uncore = stream->uncore;
2658 u32 report_format = stream->oa_buffer.format;
2661 * Reset buf pointers so we don't forward reports from before now.
2663 * Think carefully if considering trying to avoid this, since it
2664 * also ensures status flags and the buffer itself are cleared
2665 * in error paths, and we have checks for invalid reports based
2666 * on the assumption that certain fields are written to zeroed
2667 * memory which this helps maintains.
2669 gen8_init_oa_buffer(stream);
2672 * Note: we don't rely on the hardware to perform single context
2673 * filtering and instead filter on the cpu based on the context-id
2676 intel_uncore_write(uncore, GEN8_OACONTROL,
2677 (report_format << GEN8_OA_REPORT_FORMAT_SHIFT) |
2678 GEN8_OA_COUNTER_ENABLE);
2681 static void gen12_oa_enable(struct i915_perf_stream *stream)
2683 struct intel_uncore *uncore = stream->uncore;
2684 u32 report_format = stream->oa_buffer.format;
2687 * If we don't want OA reports from the OA buffer, then we don't even
2688 * need to program the OAG unit.
2690 if (!(stream->sample_flags & SAMPLE_OA_REPORT))
2693 gen12_init_oa_buffer(stream);
2695 intel_uncore_write(uncore, GEN12_OAG_OACONTROL,
2696 (report_format << GEN12_OAG_OACONTROL_OA_COUNTER_FORMAT_SHIFT) |
2697 GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE);
2701 * i915_oa_stream_enable - handle `I915_PERF_IOCTL_ENABLE` for OA stream
2702 * @stream: An i915 perf stream opened for OA metrics
2704 * [Re]enables hardware periodic sampling according to the period configured
2705 * when opening the stream. This also starts a hrtimer that will periodically
2706 * check for data in the circular OA buffer for notifying userspace (e.g.
2707 * during a read() or poll()).
2709 static void i915_oa_stream_enable(struct i915_perf_stream *stream)
2711 stream->pollin = false;
2713 stream->perf->ops.oa_enable(stream);
2715 if (stream->sample_flags & SAMPLE_OA_REPORT)
2716 hrtimer_start(&stream->poll_check_timer,
2717 ns_to_ktime(stream->poll_oa_period),
2718 HRTIMER_MODE_REL_PINNED);
2721 static void gen7_oa_disable(struct i915_perf_stream *stream)
2723 struct intel_uncore *uncore = stream->uncore;
2725 intel_uncore_write(uncore, GEN7_OACONTROL, 0);
2726 if (intel_wait_for_register(uncore,
2727 GEN7_OACONTROL, GEN7_OACONTROL_ENABLE, 0,
2729 drm_err(&stream->perf->i915->drm,
2730 "wait for OA to be disabled timed out\n");
2733 static void gen8_oa_disable(struct i915_perf_stream *stream)
2735 struct intel_uncore *uncore = stream->uncore;
2737 intel_uncore_write(uncore, GEN8_OACONTROL, 0);
2738 if (intel_wait_for_register(uncore,
2739 GEN8_OACONTROL, GEN8_OA_COUNTER_ENABLE, 0,
2741 drm_err(&stream->perf->i915->drm,
2742 "wait for OA to be disabled timed out\n");
2745 static void gen12_oa_disable(struct i915_perf_stream *stream)
2747 struct intel_uncore *uncore = stream->uncore;
2749 intel_uncore_write(uncore, GEN12_OAG_OACONTROL, 0);
2750 if (intel_wait_for_register(uncore,
2751 GEN12_OAG_OACONTROL,
2752 GEN12_OAG_OACONTROL_OA_COUNTER_ENABLE, 0,
2754 drm_err(&stream->perf->i915->drm,
2755 "wait for OA to be disabled timed out\n");
2757 intel_uncore_write(uncore, GEN12_OA_TLB_INV_CR, 1);
2758 if (intel_wait_for_register(uncore,
2759 GEN12_OA_TLB_INV_CR,
2762 drm_err(&stream->perf->i915->drm,
2763 "wait for OA tlb invalidate timed out\n");
2767 * i915_oa_stream_disable - handle `I915_PERF_IOCTL_DISABLE` for OA stream
2768 * @stream: An i915 perf stream opened for OA metrics
2770 * Stops the OA unit from periodically writing counter reports into the
2771 * circular OA buffer. This also stops the hrtimer that periodically checks for
2772 * data in the circular OA buffer, for notifying userspace.
2774 static void i915_oa_stream_disable(struct i915_perf_stream *stream)
2776 stream->perf->ops.oa_disable(stream);
2778 if (stream->sample_flags & SAMPLE_OA_REPORT)
2779 hrtimer_cancel(&stream->poll_check_timer);
2782 static const struct i915_perf_stream_ops i915_oa_stream_ops = {
2783 .destroy = i915_oa_stream_destroy,
2784 .enable = i915_oa_stream_enable,
2785 .disable = i915_oa_stream_disable,
2786 .wait_unlocked = i915_oa_wait_unlocked,
2787 .poll_wait = i915_oa_poll_wait,
2788 .read = i915_oa_read,
2791 static int i915_perf_stream_enable_sync(struct i915_perf_stream *stream)
2793 struct i915_active *active;
2796 active = i915_active_create();
2800 err = stream->perf->ops.enable_metric_set(stream, active);
2802 __i915_active_wait(active, TASK_UNINTERRUPTIBLE);
2804 i915_active_put(active);
2809 get_default_sseu_config(struct intel_sseu *out_sseu,
2810 struct intel_engine_cs *engine)
2812 const struct sseu_dev_info *devinfo_sseu = &engine->gt->info.sseu;
2814 *out_sseu = intel_sseu_from_device_info(devinfo_sseu);
2816 if (GRAPHICS_VER(engine->i915) == 11) {
2818 * We only need subslice count so it doesn't matter which ones
2819 * we select - just turn off low bits in the amount of half of
2820 * all available subslices per slice.
2822 out_sseu->subslice_mask =
2823 ~(~0 << (hweight8(out_sseu->subslice_mask) / 2));
2824 out_sseu->slice_mask = 0x1;
2829 get_sseu_config(struct intel_sseu *out_sseu,
2830 struct intel_engine_cs *engine,
2831 const struct drm_i915_gem_context_param_sseu *drm_sseu)
2833 if (drm_sseu->engine.engine_class != engine->uabi_class ||
2834 drm_sseu->engine.engine_instance != engine->uabi_instance)
2837 return i915_gem_user_to_context_sseu(engine->gt, drm_sseu, out_sseu);
2841 * i915_oa_stream_init - validate combined props for OA stream and init
2842 * @stream: An i915 perf stream
2843 * @param: The open parameters passed to `DRM_I915_PERF_OPEN`
2844 * @props: The property state that configures stream (individually validated)
2846 * While read_properties_unlocked() validates properties in isolation it
2847 * doesn't ensure that the combination necessarily makes sense.
2849 * At this point it has been determined that userspace wants a stream of
2850 * OA metrics, but still we need to further validate the combined
2851 * properties are OK.
2853 * If the configuration makes sense then we can allocate memory for
2854 * a circular OA buffer and apply the requested metric set configuration.
2856 * Returns: zero on success or a negative error code.
2858 static int i915_oa_stream_init(struct i915_perf_stream *stream,
2859 struct drm_i915_perf_open_param *param,
2860 struct perf_open_properties *props)
2862 struct drm_i915_private *i915 = stream->perf->i915;
2863 struct i915_perf *perf = stream->perf;
2867 if (!props->engine) {
2868 drm_dbg(&stream->perf->i915->drm,
2869 "OA engine not specified\n");
2874 * If the sysfs metrics/ directory wasn't registered for some
2875 * reason then don't let userspace try their luck with config
2878 if (!perf->metrics_kobj) {
2879 drm_dbg(&stream->perf->i915->drm,
2880 "OA metrics weren't advertised via sysfs\n");
2884 if (!(props->sample_flags & SAMPLE_OA_REPORT) &&
2885 (GRAPHICS_VER(perf->i915) < 12 || !stream->ctx)) {
2886 drm_dbg(&stream->perf->i915->drm,
2887 "Only OA report sampling supported\n");
2891 if (!perf->ops.enable_metric_set) {
2892 drm_dbg(&stream->perf->i915->drm,
2893 "OA unit not supported\n");
2898 * To avoid the complexity of having to accurately filter
2899 * counter reports and marshal to the appropriate client
2900 * we currently only allow exclusive access
2902 if (perf->exclusive_stream) {
2903 drm_dbg(&stream->perf->i915->drm,
2904 "OA unit already in use\n");
2908 if (!props->oa_format) {
2909 drm_dbg(&stream->perf->i915->drm,
2910 "OA report format not specified\n");
2914 stream->engine = props->engine;
2915 stream->uncore = stream->engine->gt->uncore;
2917 stream->sample_size = sizeof(struct drm_i915_perf_record_header);
2919 format_size = perf->oa_formats[props->oa_format].size;
2921 stream->sample_flags = props->sample_flags;
2922 stream->sample_size += format_size;
2924 stream->oa_buffer.format_size = format_size;
2925 if (drm_WARN_ON(&i915->drm, stream->oa_buffer.format_size == 0))
2928 stream->hold_preemption = props->hold_preemption;
2930 stream->oa_buffer.format =
2931 perf->oa_formats[props->oa_format].format;
2933 stream->periodic = props->oa_periodic;
2934 if (stream->periodic)
2935 stream->period_exponent = props->oa_period_exponent;
2938 ret = oa_get_render_ctx_id(stream);
2940 drm_dbg(&stream->perf->i915->drm,
2941 "Invalid context id to filter with\n");
2946 ret = alloc_noa_wait(stream);
2948 drm_dbg(&stream->perf->i915->drm,
2949 "Unable to allocate NOA wait batch buffer\n");
2950 goto err_noa_wait_alloc;
2953 stream->oa_config = i915_perf_get_oa_config(perf, props->metrics_set);
2954 if (!stream->oa_config) {
2955 drm_dbg(&stream->perf->i915->drm,
2956 "Invalid OA config id=%i\n", props->metrics_set);
2961 /* PRM - observability performance counters:
2963 * OACONTROL, performance counter enable, note:
2965 * "When this bit is set, in order to have coherent counts,
2966 * RC6 power state and trunk clock gating must be disabled.
2967 * This can be achieved by programming MMIO registers as
2968 * 0xA094=0 and 0xA090[31]=1"
2970 * In our case we are expecting that taking pm + FORCEWAKE
2971 * references will effectively disable RC6.
2973 intel_engine_pm_get(stream->engine);
2974 intel_uncore_forcewake_get(stream->uncore, FORCEWAKE_ALL);
2976 ret = alloc_oa_buffer(stream);
2978 goto err_oa_buf_alloc;
2980 stream->ops = &i915_oa_stream_ops;
2982 perf->sseu = props->sseu;
2983 WRITE_ONCE(perf->exclusive_stream, stream);
2985 ret = i915_perf_stream_enable_sync(stream);
2987 drm_dbg(&stream->perf->i915->drm,
2988 "Unable to enable metric set\n");
2992 drm_dbg(&stream->perf->i915->drm,
2993 "opening stream oa config uuid=%s\n",
2994 stream->oa_config->uuid);
2996 hrtimer_init(&stream->poll_check_timer,
2997 CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2998 stream->poll_check_timer.function = oa_poll_check_timer_cb;
2999 init_waitqueue_head(&stream->poll_wq);
3000 spin_lock_init(&stream->oa_buffer.ptr_lock);
3005 WRITE_ONCE(perf->exclusive_stream, NULL);
3006 perf->ops.disable_metric_set(stream);
3008 free_oa_buffer(stream);
3011 free_oa_configs(stream);
3013 intel_uncore_forcewake_put(stream->uncore, FORCEWAKE_ALL);
3014 intel_engine_pm_put(stream->engine);
3017 free_noa_wait(stream);
3021 oa_put_render_ctx_id(stream);
3026 void i915_oa_init_reg_state(const struct intel_context *ce,
3027 const struct intel_engine_cs *engine)
3029 struct i915_perf_stream *stream;
3031 if (engine->class != RENDER_CLASS)
3034 /* perf.exclusive_stream serialised by lrc_configure_all_contexts() */
3035 stream = READ_ONCE(engine->i915->perf.exclusive_stream);
3036 if (stream && GRAPHICS_VER(stream->perf->i915) < 12)
3037 gen8_update_reg_state_unlocked(ce, stream);
3041 * i915_perf_read - handles read() FOP for i915 perf stream FDs
3042 * @file: An i915 perf stream file
3043 * @buf: destination buffer given by userspace
3044 * @count: the number of bytes userspace wants to read
3045 * @ppos: (inout) file seek position (unused)
3047 * The entry point for handling a read() on a stream file descriptor from
3048 * userspace. Most of the work is left to the i915_perf_read_locked() and
3049 * &i915_perf_stream_ops->read but to save having stream implementations (of
3050 * which we might have multiple later) we handle blocking read here.
3052 * We can also consistently treat trying to read from a disabled stream
3053 * as an IO error so implementations can assume the stream is enabled
3056 * Returns: The number of bytes copied or a negative error code on failure.
3058 static ssize_t i915_perf_read(struct file *file,
3063 struct i915_perf_stream *stream = file->private_data;
3064 struct i915_perf *perf = stream->perf;
3068 /* To ensure it's handled consistently we simply treat all reads of a
3069 * disabled stream as an error. In particular it might otherwise lead
3070 * to a deadlock for blocking file descriptors...
3072 if (!stream->enabled || !(stream->sample_flags & SAMPLE_OA_REPORT))
3075 if (!(file->f_flags & O_NONBLOCK)) {
3076 /* There's the small chance of false positives from
3077 * stream->ops->wait_unlocked.
3079 * E.g. with single context filtering since we only wait until
3080 * oabuffer has >= 1 report we don't immediately know whether
3081 * any reports really belong to the current context
3084 ret = stream->ops->wait_unlocked(stream);
3088 mutex_lock(&perf->lock);
3089 ret = stream->ops->read(stream, buf, count, &offset);
3090 mutex_unlock(&perf->lock);
3091 } while (!offset && !ret);
3093 mutex_lock(&perf->lock);
3094 ret = stream->ops->read(stream, buf, count, &offset);
3095 mutex_unlock(&perf->lock);
3098 /* We allow the poll checking to sometimes report false positive EPOLLIN
3099 * events where we might actually report EAGAIN on read() if there's
3100 * not really any data available. In this situation though we don't
3101 * want to enter a busy loop between poll() reporting a EPOLLIN event
3102 * and read() returning -EAGAIN. Clearing the oa.pollin state here
3103 * effectively ensures we back off until the next hrtimer callback
3104 * before reporting another EPOLLIN event.
3105 * The exception to this is if ops->read() returned -ENOSPC which means
3106 * that more OA data is available than could fit in the user provided
3107 * buffer. In this case we want the next poll() call to not block.
3110 stream->pollin = false;
3112 /* Possible values for ret are 0, -EFAULT, -ENOSPC, -EIO, ... */
3113 return offset ?: (ret ?: -EAGAIN);
3116 static enum hrtimer_restart oa_poll_check_timer_cb(struct hrtimer *hrtimer)
3118 struct i915_perf_stream *stream =
3119 container_of(hrtimer, typeof(*stream), poll_check_timer);
3121 if (oa_buffer_check_unlocked(stream)) {
3122 stream->pollin = true;
3123 wake_up(&stream->poll_wq);
3126 hrtimer_forward_now(hrtimer,
3127 ns_to_ktime(stream->poll_oa_period));
3129 return HRTIMER_RESTART;
3133 * i915_perf_poll_locked - poll_wait() with a suitable wait queue for stream
3134 * @stream: An i915 perf stream
3135 * @file: An i915 perf stream file
3136 * @wait: poll() state table
3138 * For handling userspace polling on an i915 perf stream, this calls through to
3139 * &i915_perf_stream_ops->poll_wait to call poll_wait() with a wait queue that
3140 * will be woken for new stream data.
3142 * Note: The &perf->lock mutex has been taken to serialize
3143 * with any non-file-operation driver hooks.
3145 * Returns: any poll events that are ready without sleeping
3147 static __poll_t i915_perf_poll_locked(struct i915_perf_stream *stream,
3151 __poll_t events = 0;
3153 stream->ops->poll_wait(stream, file, wait);
3155 /* Note: we don't explicitly check whether there's something to read
3156 * here since this path may be very hot depending on what else
3157 * userspace is polling, or on the timeout in use. We rely solely on
3158 * the hrtimer/oa_poll_check_timer_cb to notify us when there are
3168 * i915_perf_poll - call poll_wait() with a suitable wait queue for stream
3169 * @file: An i915 perf stream file
3170 * @wait: poll() state table
3172 * For handling userspace polling on an i915 perf stream, this ensures
3173 * poll_wait() gets called with a wait queue that will be woken for new stream
3176 * Note: Implementation deferred to i915_perf_poll_locked()
3178 * Returns: any poll events that are ready without sleeping
3180 static __poll_t i915_perf_poll(struct file *file, poll_table *wait)
3182 struct i915_perf_stream *stream = file->private_data;
3183 struct i915_perf *perf = stream->perf;
3186 mutex_lock(&perf->lock);
3187 ret = i915_perf_poll_locked(stream, file, wait);
3188 mutex_unlock(&perf->lock);
3194 * i915_perf_enable_locked - handle `I915_PERF_IOCTL_ENABLE` ioctl
3195 * @stream: A disabled i915 perf stream
3197 * [Re]enables the associated capture of data for this stream.
3199 * If a stream was previously enabled then there's currently no intention
3200 * to provide userspace any guarantee about the preservation of previously
3203 static void i915_perf_enable_locked(struct i915_perf_stream *stream)
3205 if (stream->enabled)
3208 /* Allow stream->ops->enable() to refer to this */
3209 stream->enabled = true;
3211 if (stream->ops->enable)
3212 stream->ops->enable(stream);
3214 if (stream->hold_preemption)
3215 intel_context_set_nopreempt(stream->pinned_ctx);
3219 * i915_perf_disable_locked - handle `I915_PERF_IOCTL_DISABLE` ioctl
3220 * @stream: An enabled i915 perf stream
3222 * Disables the associated capture of data for this stream.
3224 * The intention is that disabling an re-enabling a stream will ideally be
3225 * cheaper than destroying and re-opening a stream with the same configuration,
3226 * though there are no formal guarantees about what state or buffered data
3227 * must be retained between disabling and re-enabling a stream.
3229 * Note: while a stream is disabled it's considered an error for userspace
3230 * to attempt to read from the stream (-EIO).
3232 static void i915_perf_disable_locked(struct i915_perf_stream *stream)
3234 if (!stream->enabled)
3237 /* Allow stream->ops->disable() to refer to this */
3238 stream->enabled = false;
3240 if (stream->hold_preemption)
3241 intel_context_clear_nopreempt(stream->pinned_ctx);
3243 if (stream->ops->disable)
3244 stream->ops->disable(stream);
3247 static long i915_perf_config_locked(struct i915_perf_stream *stream,
3248 unsigned long metrics_set)
3250 struct i915_oa_config *config;
3251 long ret = stream->oa_config->id;
3253 config = i915_perf_get_oa_config(stream->perf, metrics_set);
3257 if (config != stream->oa_config) {
3261 * If OA is bound to a specific context, emit the
3262 * reconfiguration inline from that context. The update
3263 * will then be ordered with respect to submission on that
3266 * When set globally, we use a low priority kernel context,
3267 * so it will effectively take effect when idle.
3269 err = emit_oa_config(stream, config, oa_context(stream), NULL);
3271 config = xchg(&stream->oa_config, config);
3276 i915_oa_config_put(config);
3282 * i915_perf_ioctl_locked - support ioctl() usage with i915 perf stream FDs
3283 * @stream: An i915 perf stream
3284 * @cmd: the ioctl request
3285 * @arg: the ioctl data
3287 * Note: The &perf->lock mutex has been taken to serialize
3288 * with any non-file-operation driver hooks.
3290 * Returns: zero on success or a negative error code. Returns -EINVAL for
3291 * an unknown ioctl request.
3293 static long i915_perf_ioctl_locked(struct i915_perf_stream *stream,
3298 case I915_PERF_IOCTL_ENABLE:
3299 i915_perf_enable_locked(stream);
3301 case I915_PERF_IOCTL_DISABLE:
3302 i915_perf_disable_locked(stream);
3304 case I915_PERF_IOCTL_CONFIG:
3305 return i915_perf_config_locked(stream, arg);
3312 * i915_perf_ioctl - support ioctl() usage with i915 perf stream FDs
3313 * @file: An i915 perf stream file
3314 * @cmd: the ioctl request
3315 * @arg: the ioctl data
3317 * Implementation deferred to i915_perf_ioctl_locked().
3319 * Returns: zero on success or a negative error code. Returns -EINVAL for
3320 * an unknown ioctl request.
3322 static long i915_perf_ioctl(struct file *file,
3326 struct i915_perf_stream *stream = file->private_data;
3327 struct i915_perf *perf = stream->perf;
3330 mutex_lock(&perf->lock);
3331 ret = i915_perf_ioctl_locked(stream, cmd, arg);
3332 mutex_unlock(&perf->lock);
3338 * i915_perf_destroy_locked - destroy an i915 perf stream
3339 * @stream: An i915 perf stream
3341 * Frees all resources associated with the given i915 perf @stream, disabling
3342 * any associated data capture in the process.
3344 * Note: The &perf->lock mutex has been taken to serialize
3345 * with any non-file-operation driver hooks.
3347 static void i915_perf_destroy_locked(struct i915_perf_stream *stream)
3349 if (stream->enabled)
3350 i915_perf_disable_locked(stream);
3352 if (stream->ops->destroy)
3353 stream->ops->destroy(stream);
3356 i915_gem_context_put(stream->ctx);
3362 * i915_perf_release - handles userspace close() of a stream file
3363 * @inode: anonymous inode associated with file
3364 * @file: An i915 perf stream file
3366 * Cleans up any resources associated with an open i915 perf stream file.
3368 * NB: close() can't really fail from the userspace point of view.
3370 * Returns: zero on success or a negative error code.
3372 static int i915_perf_release(struct inode *inode, struct file *file)
3374 struct i915_perf_stream *stream = file->private_data;
3375 struct i915_perf *perf = stream->perf;
3377 mutex_lock(&perf->lock);
3378 i915_perf_destroy_locked(stream);
3379 mutex_unlock(&perf->lock);
3381 /* Release the reference the perf stream kept on the driver. */
3382 drm_dev_put(&perf->i915->drm);
3388 static const struct file_operations fops = {
3389 .owner = THIS_MODULE,
3390 .llseek = no_llseek,
3391 .release = i915_perf_release,
3392 .poll = i915_perf_poll,
3393 .read = i915_perf_read,
3394 .unlocked_ioctl = i915_perf_ioctl,
3395 /* Our ioctl have no arguments, so it's safe to use the same function
3396 * to handle 32bits compatibility.
3398 .compat_ioctl = i915_perf_ioctl,
3403 * i915_perf_open_ioctl_locked - DRM ioctl() for userspace to open a stream FD
3404 * @perf: i915 perf instance
3405 * @param: The open parameters passed to 'DRM_I915_PERF_OPEN`
3406 * @props: individually validated u64 property value pairs
3409 * See i915_perf_ioctl_open() for interface details.
3411 * Implements further stream config validation and stream initialization on
3412 * behalf of i915_perf_open_ioctl() with the &perf->lock mutex
3413 * taken to serialize with any non-file-operation driver hooks.
3415 * Note: at this point the @props have only been validated in isolation and
3416 * it's still necessary to validate that the combination of properties makes
3419 * In the case where userspace is interested in OA unit metrics then further
3420 * config validation and stream initialization details will be handled by
3421 * i915_oa_stream_init(). The code here should only validate config state that
3422 * will be relevant to all stream types / backends.
3424 * Returns: zero on success or a negative error code.
3427 i915_perf_open_ioctl_locked(struct i915_perf *perf,
3428 struct drm_i915_perf_open_param *param,
3429 struct perf_open_properties *props,
3430 struct drm_file *file)
3432 struct i915_gem_context *specific_ctx = NULL;
3433 struct i915_perf_stream *stream = NULL;
3434 unsigned long f_flags = 0;
3435 bool privileged_op = true;
3439 if (props->single_context) {
3440 u32 ctx_handle = props->ctx_handle;
3441 struct drm_i915_file_private *file_priv = file->driver_priv;
3443 specific_ctx = i915_gem_context_lookup(file_priv, ctx_handle);
3444 if (IS_ERR(specific_ctx)) {
3445 drm_dbg(&perf->i915->drm,
3446 "Failed to look up context with ID %u for opening perf stream\n",
3448 ret = PTR_ERR(specific_ctx);
3454 * On Haswell the OA unit supports clock gating off for a specific
3455 * context and in this mode there's no visibility of metrics for the
3456 * rest of the system, which we consider acceptable for a
3457 * non-privileged client.
3459 * For Gen8->11 the OA unit no longer supports clock gating off for a
3460 * specific context and the kernel can't securely stop the counters
3461 * from updating as system-wide / global values. Even though we can
3462 * filter reports based on the included context ID we can't block
3463 * clients from seeing the raw / global counter values via
3464 * MI_REPORT_PERF_COUNT commands and so consider it a privileged op to
3465 * enable the OA unit by default.
3467 * For Gen12+ we gain a new OAR unit that only monitors the RCS on a
3468 * per context basis. So we can relax requirements there if the user
3469 * doesn't request global stream access (i.e. query based sampling
3470 * using MI_RECORD_PERF_COUNT.
3472 if (IS_HASWELL(perf->i915) && specific_ctx)
3473 privileged_op = false;
3474 else if (GRAPHICS_VER(perf->i915) == 12 && specific_ctx &&
3475 (props->sample_flags & SAMPLE_OA_REPORT) == 0)
3476 privileged_op = false;
3478 if (props->hold_preemption) {
3479 if (!props->single_context) {
3480 drm_dbg(&perf->i915->drm,
3481 "preemption disable with no context\n");
3485 privileged_op = true;
3489 * Asking for SSEU configuration is a priviliged operation.
3491 if (props->has_sseu)
3492 privileged_op = true;
3494 get_default_sseu_config(&props->sseu, props->engine);
3496 /* Similar to perf's kernel.perf_paranoid_cpu sysctl option
3497 * we check a dev.i915.perf_stream_paranoid sysctl option
3498 * to determine if it's ok to access system wide OA counters
3499 * without CAP_PERFMON or CAP_SYS_ADMIN privileges.
3501 if (privileged_op &&
3502 i915_perf_stream_paranoid && !perfmon_capable()) {
3503 drm_dbg(&perf->i915->drm,
3504 "Insufficient privileges to open i915 perf stream\n");
3509 stream = kzalloc(sizeof(*stream), GFP_KERNEL);
3515 stream->perf = perf;
3516 stream->ctx = specific_ctx;
3517 stream->poll_oa_period = props->poll_oa_period;
3519 ret = i915_oa_stream_init(stream, param, props);
3523 /* we avoid simply assigning stream->sample_flags = props->sample_flags
3524 * to have _stream_init check the combination of sample flags more
3525 * thoroughly, but still this is the expected result at this point.
3527 if (WARN_ON(stream->sample_flags != props->sample_flags)) {
3532 if (param->flags & I915_PERF_FLAG_FD_CLOEXEC)
3533 f_flags |= O_CLOEXEC;
3534 if (param->flags & I915_PERF_FLAG_FD_NONBLOCK)
3535 f_flags |= O_NONBLOCK;
3537 stream_fd = anon_inode_getfd("[i915_perf]", &fops, stream, f_flags);
3538 if (stream_fd < 0) {
3543 if (!(param->flags & I915_PERF_FLAG_DISABLED))
3544 i915_perf_enable_locked(stream);
3546 /* Take a reference on the driver that will be kept with stream_fd
3547 * until its release.
3549 drm_dev_get(&perf->i915->drm);
3554 if (stream->ops->destroy)
3555 stream->ops->destroy(stream);
3560 i915_gem_context_put(specific_ctx);
3565 static u64 oa_exponent_to_ns(struct i915_perf *perf, int exponent)
3567 return intel_gt_clock_interval_to_ns(to_gt(perf->i915),
3571 static __always_inline bool
3572 oa_format_valid(struct i915_perf *perf, enum drm_i915_oa_format format)
3574 return test_bit(format, perf->format_mask);
3577 static __always_inline void
3578 oa_format_add(struct i915_perf *perf, enum drm_i915_oa_format format)
3580 __set_bit(format, perf->format_mask);
3584 * read_properties_unlocked - validate + copy userspace stream open properties
3585 * @perf: i915 perf instance
3586 * @uprops: The array of u64 key value pairs given by userspace
3587 * @n_props: The number of key value pairs expected in @uprops
3588 * @props: The stream configuration built up while validating properties
3590 * Note this function only validates properties in isolation it doesn't
3591 * validate that the combination of properties makes sense or that all
3592 * properties necessary for a particular kind of stream have been set.
3594 * Note that there currently aren't any ordering requirements for properties so
3595 * we shouldn't validate or assume anything about ordering here. This doesn't
3596 * rule out defining new properties with ordering requirements in the future.
3598 static int read_properties_unlocked(struct i915_perf *perf,
3601 struct perf_open_properties *props)
3603 u64 __user *uprop = uprops;
3607 memset(props, 0, sizeof(struct perf_open_properties));
3608 props->poll_oa_period = DEFAULT_POLL_PERIOD_NS;
3611 drm_dbg(&perf->i915->drm,
3612 "No i915 perf properties given\n");
3616 /* At the moment we only support using i915-perf on the RCS. */
3617 props->engine = intel_engine_lookup_user(perf->i915,
3618 I915_ENGINE_CLASS_RENDER,
3620 if (!props->engine) {
3621 drm_dbg(&perf->i915->drm,
3622 "No RENDER-capable engines\n");
3626 /* Considering that ID = 0 is reserved and assuming that we don't
3627 * (currently) expect any configurations to ever specify duplicate
3628 * values for a particular property ID then the last _PROP_MAX value is
3629 * one greater than the maximum number of properties we expect to get
3632 if (n_props >= DRM_I915_PERF_PROP_MAX) {
3633 drm_dbg(&perf->i915->drm,
3634 "More i915 perf properties specified than exist\n");
3638 for (i = 0; i < n_props; i++) {
3639 u64 oa_period, oa_freq_hz;
3642 ret = get_user(id, uprop);
3646 ret = get_user(value, uprop + 1);
3650 if (id == 0 || id >= DRM_I915_PERF_PROP_MAX) {
3651 drm_dbg(&perf->i915->drm,
3652 "Unknown i915 perf property ID\n");
3656 switch ((enum drm_i915_perf_property_id)id) {
3657 case DRM_I915_PERF_PROP_CTX_HANDLE:
3658 props->single_context = 1;
3659 props->ctx_handle = value;
3661 case DRM_I915_PERF_PROP_SAMPLE_OA:
3663 props->sample_flags |= SAMPLE_OA_REPORT;
3665 case DRM_I915_PERF_PROP_OA_METRICS_SET:
3667 drm_dbg(&perf->i915->drm,
3668 "Unknown OA metric set ID\n");
3671 props->metrics_set = value;
3673 case DRM_I915_PERF_PROP_OA_FORMAT:
3674 if (value == 0 || value >= I915_OA_FORMAT_MAX) {
3675 drm_dbg(&perf->i915->drm,
3676 "Out-of-range OA report format %llu\n",
3680 if (!oa_format_valid(perf, value)) {
3681 drm_dbg(&perf->i915->drm,
3682 "Unsupported OA report format %llu\n",
3686 props->oa_format = value;
3688 case DRM_I915_PERF_PROP_OA_EXPONENT:
3689 if (value > OA_EXPONENT_MAX) {
3690 drm_dbg(&perf->i915->drm,
3691 "OA timer exponent too high (> %u)\n",
3696 /* Theoretically we can program the OA unit to sample
3697 * e.g. every 160ns for HSW, 167ns for BDW/SKL or 104ns
3698 * for BXT. We don't allow such high sampling
3699 * frequencies by default unless root.
3702 BUILD_BUG_ON(sizeof(oa_period) != 8);
3703 oa_period = oa_exponent_to_ns(perf, value);
3705 /* This check is primarily to ensure that oa_period <=
3706 * UINT32_MAX (before passing to do_div which only
3707 * accepts a u32 denominator), but we can also skip
3708 * checking anything < 1Hz which implicitly can't be
3709 * limited via an integer oa_max_sample_rate.
3711 if (oa_period <= NSEC_PER_SEC) {
3712 u64 tmp = NSEC_PER_SEC;
3713 do_div(tmp, oa_period);
3718 if (oa_freq_hz > i915_oa_max_sample_rate && !perfmon_capable()) {
3719 drm_dbg(&perf->i915->drm,
3720 "OA exponent would exceed the max sampling frequency (sysctl dev.i915.oa_max_sample_rate) %uHz without CAP_PERFMON or CAP_SYS_ADMIN privileges\n",
3721 i915_oa_max_sample_rate);
3725 props->oa_periodic = true;
3726 props->oa_period_exponent = value;
3728 case DRM_I915_PERF_PROP_HOLD_PREEMPTION:
3729 props->hold_preemption = !!value;
3731 case DRM_I915_PERF_PROP_GLOBAL_SSEU: {
3732 struct drm_i915_gem_context_param_sseu user_sseu;
3734 if (GRAPHICS_VER_FULL(perf->i915) >= IP_VER(12, 50)) {
3735 drm_dbg(&perf->i915->drm,
3736 "SSEU config not supported on gfx %x\n",
3737 GRAPHICS_VER_FULL(perf->i915));
3741 if (copy_from_user(&user_sseu,
3742 u64_to_user_ptr(value),
3743 sizeof(user_sseu))) {
3744 drm_dbg(&perf->i915->drm,
3745 "Unable to copy global sseu parameter\n");
3749 ret = get_sseu_config(&props->sseu, props->engine, &user_sseu);
3751 drm_dbg(&perf->i915->drm,
3752 "Invalid SSEU configuration\n");
3755 props->has_sseu = true;
3758 case DRM_I915_PERF_PROP_POLL_OA_PERIOD:
3759 if (value < 100000 /* 100us */) {
3760 drm_dbg(&perf->i915->drm,
3761 "OA availability timer too small (%lluns < 100us)\n",
3765 props->poll_oa_period = value;
3767 case DRM_I915_PERF_PROP_MAX:
3779 * i915_perf_open_ioctl - DRM ioctl() for userspace to open a stream FD
3781 * @data: ioctl data copied from userspace (unvalidated)
3784 * Validates the stream open parameters given by userspace including flags
3785 * and an array of u64 key, value pair properties.
3787 * Very little is assumed up front about the nature of the stream being
3788 * opened (for instance we don't assume it's for periodic OA unit metrics). An
3789 * i915-perf stream is expected to be a suitable interface for other forms of
3790 * buffered data written by the GPU besides periodic OA metrics.
3792 * Note we copy the properties from userspace outside of the i915 perf
3793 * mutex to avoid an awkward lockdep with mmap_lock.
3795 * Most of the implementation details are handled by
3796 * i915_perf_open_ioctl_locked() after taking the &perf->lock
3797 * mutex for serializing with any non-file-operation driver hooks.
3799 * Return: A newly opened i915 Perf stream file descriptor or negative
3800 * error code on failure.
3802 int i915_perf_open_ioctl(struct drm_device *dev, void *data,
3803 struct drm_file *file)
3805 struct i915_perf *perf = &to_i915(dev)->perf;
3806 struct drm_i915_perf_open_param *param = data;
3807 struct perf_open_properties props;
3808 u32 known_open_flags;
3812 drm_dbg(&perf->i915->drm,
3813 "i915 perf interface not available for this system\n");
3817 known_open_flags = I915_PERF_FLAG_FD_CLOEXEC |
3818 I915_PERF_FLAG_FD_NONBLOCK |
3819 I915_PERF_FLAG_DISABLED;
3820 if (param->flags & ~known_open_flags) {
3821 drm_dbg(&perf->i915->drm,
3822 "Unknown drm_i915_perf_open_param flag\n");
3826 ret = read_properties_unlocked(perf,
3827 u64_to_user_ptr(param->properties_ptr),
3828 param->num_properties,
3833 mutex_lock(&perf->lock);
3834 ret = i915_perf_open_ioctl_locked(perf, param, &props, file);
3835 mutex_unlock(&perf->lock);
3841 * i915_perf_register - exposes i915-perf to userspace
3842 * @i915: i915 device instance
3844 * In particular OA metric sets are advertised under a sysfs metrics/
3845 * directory allowing userspace to enumerate valid IDs that can be
3846 * used to open an i915-perf stream.
3848 void i915_perf_register(struct drm_i915_private *i915)
3850 struct i915_perf *perf = &i915->perf;
3855 /* To be sure we're synchronized with an attempted
3856 * i915_perf_open_ioctl(); considering that we register after
3857 * being exposed to userspace.
3859 mutex_lock(&perf->lock);
3861 perf->metrics_kobj =
3862 kobject_create_and_add("metrics",
3863 &i915->drm.primary->kdev->kobj);
3865 mutex_unlock(&perf->lock);
3869 * i915_perf_unregister - hide i915-perf from userspace
3870 * @i915: i915 device instance
3872 * i915-perf state cleanup is split up into an 'unregister' and
3873 * 'deinit' phase where the interface is first hidden from
3874 * userspace by i915_perf_unregister() before cleaning up
3875 * remaining state in i915_perf_fini().
3877 void i915_perf_unregister(struct drm_i915_private *i915)
3879 struct i915_perf *perf = &i915->perf;
3881 if (!perf->metrics_kobj)
3884 kobject_put(perf->metrics_kobj);
3885 perf->metrics_kobj = NULL;
3888 static bool gen8_is_valid_flex_addr(struct i915_perf *perf, u32 addr)
3890 static const i915_reg_t flex_eu_regs[] = {
3901 for (i = 0; i < ARRAY_SIZE(flex_eu_regs); i++) {
3902 if (i915_mmio_reg_offset(flex_eu_regs[i]) == addr)
3908 static bool reg_in_range_table(u32 addr, const struct i915_range *table)
3910 while (table->start || table->end) {
3911 if (addr >= table->start && addr <= table->end)
3920 #define REG_EQUAL(addr, mmio) \
3921 ((addr) == i915_mmio_reg_offset(mmio))
3923 static const struct i915_range gen7_oa_b_counters[] = {
3924 { .start = 0x2710, .end = 0x272c }, /* OASTARTTRIG[1-8] */
3925 { .start = 0x2740, .end = 0x275c }, /* OAREPORTTRIG[1-8] */
3926 { .start = 0x2770, .end = 0x27ac }, /* OACEC[0-7][0-1] */
3930 static const struct i915_range gen12_oa_b_counters[] = {
3931 { .start = 0x2b2c, .end = 0x2b2c }, /* GEN12_OAG_OA_PESS */
3932 { .start = 0xd900, .end = 0xd91c }, /* GEN12_OAG_OASTARTTRIG[1-8] */
3933 { .start = 0xd920, .end = 0xd93c }, /* GEN12_OAG_OAREPORTTRIG1[1-8] */
3934 { .start = 0xd940, .end = 0xd97c }, /* GEN12_OAG_CEC[0-7][0-1] */
3935 { .start = 0xdc00, .end = 0xdc3c }, /* GEN12_OAG_SCEC[0-7][0-1] */
3936 { .start = 0xdc40, .end = 0xdc40 }, /* GEN12_OAG_SPCTR_CNF */
3937 { .start = 0xdc44, .end = 0xdc44 }, /* GEN12_OAA_DBG_REG */
3941 static const struct i915_range gen7_oa_mux_regs[] = {
3942 { .start = 0x91b8, .end = 0x91cc }, /* OA_PERFCNT[1-2], OA_PERFMATRIX */
3943 { .start = 0x9800, .end = 0x9888 }, /* MICRO_BP0_0 - NOA_WRITE */
3944 { .start = 0xe180, .end = 0xe180 }, /* HALF_SLICE_CHICKEN2 */
3948 static const struct i915_range hsw_oa_mux_regs[] = {
3949 { .start = 0x09e80, .end = 0x09ea4 }, /* HSW_MBVID2_NOA[0-9] */
3950 { .start = 0x09ec0, .end = 0x09ec0 }, /* HSW_MBVID2_MISR0 */
3951 { .start = 0x25100, .end = 0x2ff90 },
3955 static const struct i915_range chv_oa_mux_regs[] = {
3956 { .start = 0x182300, .end = 0x1823a4 },
3960 static const struct i915_range gen8_oa_mux_regs[] = {
3961 { .start = 0x0d00, .end = 0x0d2c }, /* RPM_CONFIG[0-1], NOA_CONFIG[0-8] */
3962 { .start = 0x20cc, .end = 0x20cc }, /* WAIT_FOR_RC6_EXIT */
3966 static const struct i915_range gen11_oa_mux_regs[] = {
3967 { .start = 0x91c8, .end = 0x91dc }, /* OA_PERFCNT[3-4] */
3971 static const struct i915_range gen12_oa_mux_regs[] = {
3972 { .start = 0x0d00, .end = 0x0d04 }, /* RPM_CONFIG[0-1] */
3973 { .start = 0x0d0c, .end = 0x0d2c }, /* NOA_CONFIG[0-8] */
3974 { .start = 0x9840, .end = 0x9840 }, /* GDT_CHICKEN_BITS */
3975 { .start = 0x9884, .end = 0x9888 }, /* NOA_WRITE */
3976 { .start = 0x20cc, .end = 0x20cc }, /* WAIT_FOR_RC6_EXIT */
3980 static bool gen7_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
3982 return reg_in_range_table(addr, gen7_oa_b_counters);
3985 static bool gen8_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
3987 return reg_in_range_table(addr, gen7_oa_mux_regs) ||
3988 reg_in_range_table(addr, gen8_oa_mux_regs);
3991 static bool gen11_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
3993 return reg_in_range_table(addr, gen7_oa_mux_regs) ||
3994 reg_in_range_table(addr, gen8_oa_mux_regs) ||
3995 reg_in_range_table(addr, gen11_oa_mux_regs);
3998 static bool hsw_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
4000 return reg_in_range_table(addr, gen7_oa_mux_regs) ||
4001 reg_in_range_table(addr, hsw_oa_mux_regs);
4004 static bool chv_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
4006 return reg_in_range_table(addr, gen7_oa_mux_regs) ||
4007 reg_in_range_table(addr, chv_oa_mux_regs);
4010 static bool gen12_is_valid_b_counter_addr(struct i915_perf *perf, u32 addr)
4012 return reg_in_range_table(addr, gen12_oa_b_counters);
4015 static bool gen12_is_valid_mux_addr(struct i915_perf *perf, u32 addr)
4017 return reg_in_range_table(addr, gen12_oa_mux_regs);
4020 static u32 mask_reg_value(u32 reg, u32 val)
4022 /* HALF_SLICE_CHICKEN2 is programmed with a the
4023 * WaDisableSTUnitPowerOptimization workaround. Make sure the value
4024 * programmed by userspace doesn't change this.
4026 if (REG_EQUAL(reg, HALF_SLICE_CHICKEN2))
4027 val = val & ~_MASKED_BIT_ENABLE(GEN8_ST_PO_DISABLE);
4029 /* WAIT_FOR_RC6_EXIT has only one bit fullfilling the function
4030 * indicated by its name and a bunch of selection fields used by OA
4033 if (REG_EQUAL(reg, WAIT_FOR_RC6_EXIT))
4034 val = val & ~_MASKED_BIT_ENABLE(HSW_WAIT_FOR_RC6_EXIT_ENABLE);
4039 static struct i915_oa_reg *alloc_oa_regs(struct i915_perf *perf,
4040 bool (*is_valid)(struct i915_perf *perf, u32 addr),
4044 struct i915_oa_reg *oa_regs;
4051 /* No is_valid function means we're not allowing any register to be programmed. */
4052 GEM_BUG_ON(!is_valid);
4054 return ERR_PTR(-EINVAL);
4056 oa_regs = kmalloc_array(n_regs, sizeof(*oa_regs), GFP_KERNEL);
4058 return ERR_PTR(-ENOMEM);
4060 for (i = 0; i < n_regs; i++) {
4063 err = get_user(addr, regs);
4067 if (!is_valid(perf, addr)) {
4068 drm_dbg(&perf->i915->drm,
4069 "Invalid oa_reg address: %X\n", addr);
4074 err = get_user(value, regs + 1);
4078 oa_regs[i].addr = _MMIO(addr);
4079 oa_regs[i].value = mask_reg_value(addr, value);
4088 return ERR_PTR(err);
4091 static ssize_t show_dynamic_id(struct kobject *kobj,
4092 struct kobj_attribute *attr,
4095 struct i915_oa_config *oa_config =
4096 container_of(attr, typeof(*oa_config), sysfs_metric_id);
4098 return sprintf(buf, "%d\n", oa_config->id);
4101 static int create_dynamic_oa_sysfs_entry(struct i915_perf *perf,
4102 struct i915_oa_config *oa_config)
4104 sysfs_attr_init(&oa_config->sysfs_metric_id.attr);
4105 oa_config->sysfs_metric_id.attr.name = "id";
4106 oa_config->sysfs_metric_id.attr.mode = S_IRUGO;
4107 oa_config->sysfs_metric_id.show = show_dynamic_id;
4108 oa_config->sysfs_metric_id.store = NULL;
4110 oa_config->attrs[0] = &oa_config->sysfs_metric_id.attr;
4111 oa_config->attrs[1] = NULL;
4113 oa_config->sysfs_metric.name = oa_config->uuid;
4114 oa_config->sysfs_metric.attrs = oa_config->attrs;
4116 return sysfs_create_group(perf->metrics_kobj,
4117 &oa_config->sysfs_metric);
4121 * i915_perf_add_config_ioctl - DRM ioctl() for userspace to add a new OA config
4123 * @data: ioctl data (pointer to struct drm_i915_perf_oa_config) copied from
4124 * userspace (unvalidated)
4127 * Validates the submitted OA register to be saved into a new OA config that
4128 * can then be used for programming the OA unit and its NOA network.
4130 * Returns: A new allocated config number to be used with the perf open ioctl
4131 * or a negative error code on failure.
4133 int i915_perf_add_config_ioctl(struct drm_device *dev, void *data,
4134 struct drm_file *file)
4136 struct i915_perf *perf = &to_i915(dev)->perf;
4137 struct drm_i915_perf_oa_config *args = data;
4138 struct i915_oa_config *oa_config, *tmp;
4139 struct i915_oa_reg *regs;
4143 drm_dbg(&perf->i915->drm,
4144 "i915 perf interface not available for this system\n");
4148 if (!perf->metrics_kobj) {
4149 drm_dbg(&perf->i915->drm,
4150 "OA metrics weren't advertised via sysfs\n");
4154 if (i915_perf_stream_paranoid && !perfmon_capable()) {
4155 drm_dbg(&perf->i915->drm,
4156 "Insufficient privileges to add i915 OA config\n");
4160 if ((!args->mux_regs_ptr || !args->n_mux_regs) &&
4161 (!args->boolean_regs_ptr || !args->n_boolean_regs) &&
4162 (!args->flex_regs_ptr || !args->n_flex_regs)) {
4163 drm_dbg(&perf->i915->drm,
4164 "No OA registers given\n");
4168 oa_config = kzalloc(sizeof(*oa_config), GFP_KERNEL);
4170 drm_dbg(&perf->i915->drm,
4171 "Failed to allocate memory for the OA config\n");
4175 oa_config->perf = perf;
4176 kref_init(&oa_config->ref);
4178 if (!uuid_is_valid(args->uuid)) {
4179 drm_dbg(&perf->i915->drm,
4180 "Invalid uuid format for OA config\n");
4185 /* Last character in oa_config->uuid will be 0 because oa_config is
4188 memcpy(oa_config->uuid, args->uuid, sizeof(args->uuid));
4190 oa_config->mux_regs_len = args->n_mux_regs;
4191 regs = alloc_oa_regs(perf,
4192 perf->ops.is_valid_mux_reg,
4193 u64_to_user_ptr(args->mux_regs_ptr),
4197 drm_dbg(&perf->i915->drm,
4198 "Failed to create OA config for mux_regs\n");
4199 err = PTR_ERR(regs);
4202 oa_config->mux_regs = regs;
4204 oa_config->b_counter_regs_len = args->n_boolean_regs;
4205 regs = alloc_oa_regs(perf,
4206 perf->ops.is_valid_b_counter_reg,
4207 u64_to_user_ptr(args->boolean_regs_ptr),
4208 args->n_boolean_regs);
4211 drm_dbg(&perf->i915->drm,
4212 "Failed to create OA config for b_counter_regs\n");
4213 err = PTR_ERR(regs);
4216 oa_config->b_counter_regs = regs;
4218 if (GRAPHICS_VER(perf->i915) < 8) {
4219 if (args->n_flex_regs != 0) {
4224 oa_config->flex_regs_len = args->n_flex_regs;
4225 regs = alloc_oa_regs(perf,
4226 perf->ops.is_valid_flex_reg,
4227 u64_to_user_ptr(args->flex_regs_ptr),
4231 drm_dbg(&perf->i915->drm,
4232 "Failed to create OA config for flex_regs\n");
4233 err = PTR_ERR(regs);
4236 oa_config->flex_regs = regs;
4239 err = mutex_lock_interruptible(&perf->metrics_lock);
4243 /* We shouldn't have too many configs, so this iteration shouldn't be
4246 idr_for_each_entry(&perf->metrics_idr, tmp, id) {
4247 if (!strcmp(tmp->uuid, oa_config->uuid)) {
4248 drm_dbg(&perf->i915->drm,
4249 "OA config already exists with this uuid\n");
4255 err = create_dynamic_oa_sysfs_entry(perf, oa_config);
4257 drm_dbg(&perf->i915->drm,
4258 "Failed to create sysfs entry for OA config\n");
4262 /* Config id 0 is invalid, id 1 for kernel stored test config. */
4263 oa_config->id = idr_alloc(&perf->metrics_idr,
4266 if (oa_config->id < 0) {
4267 drm_dbg(&perf->i915->drm,
4268 "Failed to create sysfs entry for OA config\n");
4269 err = oa_config->id;
4273 mutex_unlock(&perf->metrics_lock);
4275 drm_dbg(&perf->i915->drm,
4276 "Added config %s id=%i\n", oa_config->uuid, oa_config->id);
4278 return oa_config->id;
4281 mutex_unlock(&perf->metrics_lock);
4283 i915_oa_config_put(oa_config);
4284 drm_dbg(&perf->i915->drm,
4285 "Failed to add new OA config\n");
4290 * i915_perf_remove_config_ioctl - DRM ioctl() for userspace to remove an OA config
4292 * @data: ioctl data (pointer to u64 integer) copied from userspace
4295 * Configs can be removed while being used, the will stop appearing in sysfs
4296 * and their content will be freed when the stream using the config is closed.
4298 * Returns: 0 on success or a negative error code on failure.
4300 int i915_perf_remove_config_ioctl(struct drm_device *dev, void *data,
4301 struct drm_file *file)
4303 struct i915_perf *perf = &to_i915(dev)->perf;
4305 struct i915_oa_config *oa_config;
4309 drm_dbg(&perf->i915->drm,
4310 "i915 perf interface not available for this system\n");
4314 if (i915_perf_stream_paranoid && !perfmon_capable()) {
4315 drm_dbg(&perf->i915->drm,
4316 "Insufficient privileges to remove i915 OA config\n");
4320 ret = mutex_lock_interruptible(&perf->metrics_lock);
4324 oa_config = idr_find(&perf->metrics_idr, *arg);
4326 drm_dbg(&perf->i915->drm,
4327 "Failed to remove unknown OA config\n");
4332 GEM_BUG_ON(*arg != oa_config->id);
4334 sysfs_remove_group(perf->metrics_kobj, &oa_config->sysfs_metric);
4336 idr_remove(&perf->metrics_idr, *arg);
4338 mutex_unlock(&perf->metrics_lock);
4340 drm_dbg(&perf->i915->drm,
4341 "Removed config %s id=%i\n", oa_config->uuid, oa_config->id);
4343 i915_oa_config_put(oa_config);
4348 mutex_unlock(&perf->metrics_lock);
4352 static struct ctl_table oa_table[] = {
4354 .procname = "perf_stream_paranoid",
4355 .data = &i915_perf_stream_paranoid,
4356 .maxlen = sizeof(i915_perf_stream_paranoid),
4358 .proc_handler = proc_dointvec_minmax,
4359 .extra1 = SYSCTL_ZERO,
4360 .extra2 = SYSCTL_ONE,
4363 .procname = "oa_max_sample_rate",
4364 .data = &i915_oa_max_sample_rate,
4365 .maxlen = sizeof(i915_oa_max_sample_rate),
4367 .proc_handler = proc_dointvec_minmax,
4368 .extra1 = SYSCTL_ZERO,
4369 .extra2 = &oa_sample_rate_hard_limit,
4374 static void oa_init_supported_formats(struct i915_perf *perf)
4376 struct drm_i915_private *i915 = perf->i915;
4377 enum intel_platform platform = INTEL_INFO(i915)->platform;
4381 oa_format_add(perf, I915_OA_FORMAT_A13);
4382 oa_format_add(perf, I915_OA_FORMAT_A13);
4383 oa_format_add(perf, I915_OA_FORMAT_A29);
4384 oa_format_add(perf, I915_OA_FORMAT_A13_B8_C8);
4385 oa_format_add(perf, I915_OA_FORMAT_B4_C8);
4386 oa_format_add(perf, I915_OA_FORMAT_A45_B8_C8);
4387 oa_format_add(perf, I915_OA_FORMAT_B4_C8_A16);
4388 oa_format_add(perf, I915_OA_FORMAT_C4_B8);
4391 case INTEL_BROADWELL:
4392 case INTEL_CHERRYVIEW:
4395 case INTEL_KABYLAKE:
4396 case INTEL_GEMINILAKE:
4397 case INTEL_COFFEELAKE:
4398 case INTEL_COMETLAKE:
4400 case INTEL_ELKHARTLAKE:
4401 case INTEL_JASPERLAKE:
4402 case INTEL_TIGERLAKE:
4403 case INTEL_ROCKETLAKE:
4405 case INTEL_ALDERLAKE_S:
4406 case INTEL_ALDERLAKE_P:
4407 oa_format_add(perf, I915_OA_FORMAT_A12);
4408 oa_format_add(perf, I915_OA_FORMAT_A12_B8_C8);
4409 oa_format_add(perf, I915_OA_FORMAT_A32u40_A4u32_B8_C8);
4410 oa_format_add(perf, I915_OA_FORMAT_C4_B8);
4414 MISSING_CASE(platform);
4419 * i915_perf_init - initialize i915-perf state on module bind
4420 * @i915: i915 device instance
4422 * Initializes i915-perf state without exposing anything to userspace.
4424 * Note: i915-perf initialization is split into an 'init' and 'register'
4425 * phase with the i915_perf_register() exposing state to userspace.
4427 void i915_perf_init(struct drm_i915_private *i915)
4429 struct i915_perf *perf = &i915->perf;
4431 /* XXX const struct i915_perf_ops! */
4433 /* i915_perf is not enabled for DG2 yet */
4437 perf->oa_formats = oa_formats;
4438 if (IS_HASWELL(i915)) {
4439 perf->ops.is_valid_b_counter_reg = gen7_is_valid_b_counter_addr;
4440 perf->ops.is_valid_mux_reg = hsw_is_valid_mux_addr;
4441 perf->ops.is_valid_flex_reg = NULL;
4442 perf->ops.enable_metric_set = hsw_enable_metric_set;
4443 perf->ops.disable_metric_set = hsw_disable_metric_set;
4444 perf->ops.oa_enable = gen7_oa_enable;
4445 perf->ops.oa_disable = gen7_oa_disable;
4446 perf->ops.read = gen7_oa_read;
4447 perf->ops.oa_hw_tail_read = gen7_oa_hw_tail_read;
4448 } else if (HAS_LOGICAL_RING_CONTEXTS(i915)) {
4449 /* Note: that although we could theoretically also support the
4450 * legacy ringbuffer mode on BDW (and earlier iterations of
4451 * this driver, before upstreaming did this) it didn't seem
4452 * worth the complexity to maintain now that BDW+ enable
4453 * execlist mode by default.
4455 perf->ops.read = gen8_oa_read;
4457 if (IS_GRAPHICS_VER(i915, 8, 9)) {
4458 perf->ops.is_valid_b_counter_reg =
4459 gen7_is_valid_b_counter_addr;
4460 perf->ops.is_valid_mux_reg =
4461 gen8_is_valid_mux_addr;
4462 perf->ops.is_valid_flex_reg =
4463 gen8_is_valid_flex_addr;
4465 if (IS_CHERRYVIEW(i915)) {
4466 perf->ops.is_valid_mux_reg =
4467 chv_is_valid_mux_addr;
4470 perf->ops.oa_enable = gen8_oa_enable;
4471 perf->ops.oa_disable = gen8_oa_disable;
4472 perf->ops.enable_metric_set = gen8_enable_metric_set;
4473 perf->ops.disable_metric_set = gen8_disable_metric_set;
4474 perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
4476 if (GRAPHICS_VER(i915) == 8) {
4477 perf->ctx_oactxctrl_offset = 0x120;
4478 perf->ctx_flexeu0_offset = 0x2ce;
4480 perf->gen8_valid_ctx_bit = BIT(25);
4482 perf->ctx_oactxctrl_offset = 0x128;
4483 perf->ctx_flexeu0_offset = 0x3de;
4485 perf->gen8_valid_ctx_bit = BIT(16);
4487 } else if (GRAPHICS_VER(i915) == 11) {
4488 perf->ops.is_valid_b_counter_reg =
4489 gen7_is_valid_b_counter_addr;
4490 perf->ops.is_valid_mux_reg =
4491 gen11_is_valid_mux_addr;
4492 perf->ops.is_valid_flex_reg =
4493 gen8_is_valid_flex_addr;
4495 perf->ops.oa_enable = gen8_oa_enable;
4496 perf->ops.oa_disable = gen8_oa_disable;
4497 perf->ops.enable_metric_set = gen8_enable_metric_set;
4498 perf->ops.disable_metric_set = gen11_disable_metric_set;
4499 perf->ops.oa_hw_tail_read = gen8_oa_hw_tail_read;
4501 perf->ctx_oactxctrl_offset = 0x124;
4502 perf->ctx_flexeu0_offset = 0x78e;
4504 perf->gen8_valid_ctx_bit = BIT(16);
4505 } else if (GRAPHICS_VER(i915) == 12) {
4506 perf->ops.is_valid_b_counter_reg =
4507 gen12_is_valid_b_counter_addr;
4508 perf->ops.is_valid_mux_reg =
4509 gen12_is_valid_mux_addr;
4510 perf->ops.is_valid_flex_reg =
4511 gen8_is_valid_flex_addr;
4513 perf->ops.oa_enable = gen12_oa_enable;
4514 perf->ops.oa_disable = gen12_oa_disable;
4515 perf->ops.enable_metric_set = gen12_enable_metric_set;
4516 perf->ops.disable_metric_set = gen12_disable_metric_set;
4517 perf->ops.oa_hw_tail_read = gen12_oa_hw_tail_read;
4519 perf->ctx_flexeu0_offset = 0;
4520 perf->ctx_oactxctrl_offset = 0x144;
4524 if (perf->ops.enable_metric_set) {
4525 mutex_init(&perf->lock);
4527 /* Choose a representative limit */
4528 oa_sample_rate_hard_limit = to_gt(i915)->clock_frequency / 2;
4530 mutex_init(&perf->metrics_lock);
4531 idr_init_base(&perf->metrics_idr, 1);
4533 /* We set up some ratelimit state to potentially throttle any
4534 * _NOTES about spurious, invalid OA reports which we don't
4535 * forward to userspace.
4537 * We print a _NOTE about any throttling when closing the
4538 * stream instead of waiting until driver _fini which no one
4541 * Using the same limiting factors as printk_ratelimit()
4543 ratelimit_state_init(&perf->spurious_report_rs, 5 * HZ, 10);
4544 /* Since we use a DRM_NOTE for spurious reports it would be
4545 * inconsistent to let __ratelimit() automatically print a
4546 * warning for throttling.
4548 ratelimit_set_flags(&perf->spurious_report_rs,
4549 RATELIMIT_MSG_ON_RELEASE);
4551 ratelimit_state_init(&perf->tail_pointer_race,
4553 ratelimit_set_flags(&perf->tail_pointer_race,
4554 RATELIMIT_MSG_ON_RELEASE);
4556 atomic64_set(&perf->noa_programming_delay,
4557 500 * 1000 /* 500us */);
4561 oa_init_supported_formats(perf);
4565 static int destroy_config(int id, void *p, void *data)
4567 i915_oa_config_put(p);
4571 int i915_perf_sysctl_register(void)
4573 sysctl_header = register_sysctl("dev/i915", oa_table);
4577 void i915_perf_sysctl_unregister(void)
4579 unregister_sysctl_table(sysctl_header);
4583 * i915_perf_fini - Counter part to i915_perf_init()
4584 * @i915: i915 device instance
4586 void i915_perf_fini(struct drm_i915_private *i915)
4588 struct i915_perf *perf = &i915->perf;
4593 idr_for_each(&perf->metrics_idr, destroy_config, perf);
4594 idr_destroy(&perf->metrics_idr);
4596 memset(&perf->ops, 0, sizeof(perf->ops));
4601 * i915_perf_ioctl_version - Version of the i915-perf subsystem
4603 * This version number is used by userspace to detect available features.
4605 int i915_perf_ioctl_version(void)
4608 * 1: Initial version
4609 * I915_PERF_IOCTL_ENABLE
4610 * I915_PERF_IOCTL_DISABLE
4612 * 2: Added runtime modification of OA config.
4613 * I915_PERF_IOCTL_CONFIG
4615 * 3: Add DRM_I915_PERF_PROP_HOLD_PREEMPTION parameter to hold
4616 * preemption on a particular context so that performance data is
4617 * accessible from a delta of MI_RPC reports without looking at the
4620 * 4: Add DRM_I915_PERF_PROP_ALLOWED_SSEU to limit what contexts can
4621 * be run for the duration of the performance recording based on
4622 * their SSEU configuration.
4624 * 5: Add DRM_I915_PERF_PROP_POLL_OA_PERIOD parameter that controls the
4625 * interval for the hrtimer used to check for OA data.
4630 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
4631 #include "selftests/i915_perf.c"