1 // SPDX-License-Identifier: MIT
3 * Copyright © 2014 Intel Corporation
6 #include "gem/i915_gem_lmem.h"
8 #include "gen8_engine_cs.h"
10 #include "i915_perf.h"
12 #include "intel_context.h"
13 #include "intel_engine.h"
14 #include "intel_engine_regs.h"
15 #include "intel_gpu_commands.h"
17 #include "intel_gt_regs.h"
18 #include "intel_lrc.h"
19 #include "intel_lrc_reg.h"
20 #include "intel_ring.h"
21 #include "shmem_utils.h"
23 static void set_offsets(u32 *regs,
25 const struct intel_engine_cs *engine,
27 #define NOP(x) (BIT(7) | (x))
28 #define LRI(count, flags) ((flags) << 6 | (count) | BUILD_BUG_ON_ZERO(count >= BIT(6)))
30 #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200))
32 (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x10000)), \
36 const u32 base = engine->mmio_base;
41 if (*data & BIT(7)) { /* skip */
42 count = *data++ & ~BIT(7);
51 *regs = MI_LOAD_REGISTER_IMM(count);
53 *regs |= MI_LRI_FORCE_POSTED;
54 if (GRAPHICS_VER(engine->i915) >= 11)
55 *regs |= MI_LRI_LRM_CS_MMIO;
66 offset |= v & ~BIT(7);
69 regs[0] = base + (offset << 2);
75 /* Close the batch; used mainly by live_lrc_layout() */
76 *regs = MI_BATCH_BUFFER_END;
77 if (GRAPHICS_VER(engine->i915) >= 11)
82 static const u8 gen8_xcs_offsets[] = {
117 static const u8 gen9_xcs_offsets[] = {
201 static const u8 gen12_xcs_offsets[] = {
233 static const u8 dg2_xcs_offsets[] = {
267 static const u8 gen8_rcs_offsets[] = {
304 static const u8 gen9_rcs_offsets[] = {
388 static const u8 gen11_rcs_offsets[] = {
429 static const u8 gen12_rcs_offsets[] = {
525 static const u8 xehp_rcs_offsets[] = {
566 static const u8 dg2_rcs_offsets[] = {
615 static const u8 *reg_offsets(const struct intel_engine_cs *engine)
618 * The gen12+ lists only have the registers we program in the basic
619 * default state. We rely on the context image using relative
620 * addressing to automatic fixup the register state between the
621 * physical engines for virtual engine.
623 GEM_BUG_ON(GRAPHICS_VER(engine->i915) >= 12 &&
624 !intel_engine_has_relative_mmio(engine));
626 if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
627 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
628 return dg2_rcs_offsets;
629 else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
630 return xehp_rcs_offsets;
631 else if (GRAPHICS_VER(engine->i915) >= 12)
632 return gen12_rcs_offsets;
633 else if (GRAPHICS_VER(engine->i915) >= 11)
634 return gen11_rcs_offsets;
635 else if (GRAPHICS_VER(engine->i915) >= 9)
636 return gen9_rcs_offsets;
638 return gen8_rcs_offsets;
640 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
641 return dg2_xcs_offsets;
642 else if (GRAPHICS_VER(engine->i915) >= 12)
643 return gen12_xcs_offsets;
644 else if (GRAPHICS_VER(engine->i915) >= 9)
645 return gen9_xcs_offsets;
647 return gen8_xcs_offsets;
651 static int lrc_ring_mi_mode(const struct intel_engine_cs *engine)
653 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
655 else if (GRAPHICS_VER(engine->i915) >= 12)
657 else if (GRAPHICS_VER(engine->i915) >= 9)
659 else if (engine->class == RENDER_CLASS)
665 static int lrc_ring_gpr0(const struct intel_engine_cs *engine)
667 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
669 else if (GRAPHICS_VER(engine->i915) >= 12)
671 else if (GRAPHICS_VER(engine->i915) >= 9)
673 else if (engine->class == RENDER_CLASS)
679 static int lrc_ring_wa_bb_per_ctx(const struct intel_engine_cs *engine)
681 if (GRAPHICS_VER(engine->i915) >= 12)
683 else if (GRAPHICS_VER(engine->i915) >= 9 || engine->class == RENDER_CLASS)
689 static int lrc_ring_indirect_ptr(const struct intel_engine_cs *engine)
693 x = lrc_ring_wa_bb_per_ctx(engine);
700 static int lrc_ring_indirect_offset(const struct intel_engine_cs *engine)
704 x = lrc_ring_indirect_ptr(engine);
711 static int lrc_ring_cmd_buf_cctl(const struct intel_engine_cs *engine)
714 if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
716 * Note that the CSFE context has a dummy slot for CMD_BUF_CCTL
717 * simply to match the RCS context image layout.
720 else if (engine->class != RENDER_CLASS)
722 else if (GRAPHICS_VER(engine->i915) >= 12)
724 else if (GRAPHICS_VER(engine->i915) >= 11)
731 lrc_ring_indirect_offset_default(const struct intel_engine_cs *engine)
733 switch (GRAPHICS_VER(engine->i915)) {
735 MISSING_CASE(GRAPHICS_VER(engine->i915));
738 return GEN12_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
740 return GEN11_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
742 return GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
744 return GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT;
749 lrc_setup_indirect_ctx(u32 *regs,
750 const struct intel_engine_cs *engine,
751 u32 ctx_bb_ggtt_addr,
755 GEM_BUG_ON(!IS_ALIGNED(size, CACHELINE_BYTES));
756 GEM_BUG_ON(lrc_ring_indirect_ptr(engine) == -1);
757 regs[lrc_ring_indirect_ptr(engine) + 1] =
758 ctx_bb_ggtt_addr | (size / CACHELINE_BYTES);
760 GEM_BUG_ON(lrc_ring_indirect_offset(engine) == -1);
761 regs[lrc_ring_indirect_offset(engine) + 1] =
762 lrc_ring_indirect_offset_default(engine) << 6;
765 static void init_common_regs(u32 * const regs,
766 const struct intel_context *ce,
767 const struct intel_engine_cs *engine,
772 ctl = _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH);
773 ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT);
775 ctl |= CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT;
776 if (GRAPHICS_VER(engine->i915) < 11)
777 ctl |= _MASKED_BIT_DISABLE(CTX_CTRL_ENGINE_CTX_SAVE_INHIBIT |
778 CTX_CTRL_RS_CTX_ENABLE);
779 regs[CTX_CONTEXT_CONTROL] = ctl;
781 regs[CTX_TIMESTAMP] = ce->stats.runtime.last;
784 static void init_wa_bb_regs(u32 * const regs,
785 const struct intel_engine_cs *engine)
787 const struct i915_ctx_workarounds * const wa_ctx = &engine->wa_ctx;
789 if (wa_ctx->per_ctx.size) {
790 const u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma);
792 GEM_BUG_ON(lrc_ring_wa_bb_per_ctx(engine) == -1);
793 regs[lrc_ring_wa_bb_per_ctx(engine) + 1] =
794 (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01;
797 if (wa_ctx->indirect_ctx.size) {
798 lrc_setup_indirect_ctx(regs, engine,
799 i915_ggtt_offset(wa_ctx->vma) +
800 wa_ctx->indirect_ctx.offset,
801 wa_ctx->indirect_ctx.size);
805 static void init_ppgtt_regs(u32 *regs, const struct i915_ppgtt *ppgtt)
807 if (i915_vm_is_4lvl(&ppgtt->vm)) {
808 /* 64b PPGTT (48bit canonical)
809 * PDP0_DESCRIPTOR contains the base address to PML4 and
810 * other PDP Descriptors are ignored.
812 ASSIGN_CTX_PML4(ppgtt, regs);
814 ASSIGN_CTX_PDP(ppgtt, regs, 3);
815 ASSIGN_CTX_PDP(ppgtt, regs, 2);
816 ASSIGN_CTX_PDP(ppgtt, regs, 1);
817 ASSIGN_CTX_PDP(ppgtt, regs, 0);
821 static struct i915_ppgtt *vm_alias(struct i915_address_space *vm)
823 if (i915_is_ggtt(vm))
824 return i915_vm_to_ggtt(vm)->alias;
826 return i915_vm_to_ppgtt(vm);
829 static void __reset_stop_ring(u32 *regs, const struct intel_engine_cs *engine)
833 x = lrc_ring_mi_mode(engine);
835 regs[x + 1] &= ~STOP_RING;
836 regs[x + 1] |= STOP_RING << 16;
840 static void __lrc_init_regs(u32 *regs,
841 const struct intel_context *ce,
842 const struct intel_engine_cs *engine,
846 * A context is actually a big batch buffer with several
847 * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The
848 * values we are setting here are only for the first context restore:
849 * on a subsequent save, the GPU will recreate this batchbuffer with new
850 * values (including all the missing MI_LOAD_REGISTER_IMM commands that
851 * we are not initializing here).
853 * Must keep consistent with virtual_update_register_offsets().
857 memset(regs, 0, PAGE_SIZE);
859 set_offsets(regs, reg_offsets(engine), engine, inhibit);
861 init_common_regs(regs, ce, engine, inhibit);
862 init_ppgtt_regs(regs, vm_alias(ce->vm));
864 init_wa_bb_regs(regs, engine);
866 __reset_stop_ring(regs, engine);
869 void lrc_init_regs(const struct intel_context *ce,
870 const struct intel_engine_cs *engine,
873 __lrc_init_regs(ce->lrc_reg_state, ce, engine, inhibit);
876 void lrc_reset_regs(const struct intel_context *ce,
877 const struct intel_engine_cs *engine)
879 __reset_stop_ring(ce->lrc_reg_state, engine);
883 set_redzone(void *vaddr, const struct intel_engine_cs *engine)
885 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
888 vaddr += engine->context_size;
890 memset(vaddr, CONTEXT_REDZONE, I915_GTT_PAGE_SIZE);
894 check_redzone(const void *vaddr, const struct intel_engine_cs *engine)
896 if (!IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
899 vaddr += engine->context_size;
901 if (memchr_inv(vaddr, CONTEXT_REDZONE, I915_GTT_PAGE_SIZE))
902 drm_err_once(&engine->i915->drm,
903 "%s context redzone overwritten!\n",
907 static u32 context_wa_bb_offset(const struct intel_context *ce)
909 return PAGE_SIZE * ce->wa_bb_page;
912 static u32 *context_indirect_bb(const struct intel_context *ce)
916 GEM_BUG_ON(!ce->wa_bb_page);
918 ptr = ce->lrc_reg_state;
919 ptr -= LRC_STATE_OFFSET; /* back to start of context image */
920 ptr += context_wa_bb_offset(ce);
925 void lrc_init_state(struct intel_context *ce,
926 struct intel_engine_cs *engine,
931 set_redzone(state, engine);
933 if (engine->default_state) {
934 shmem_read(engine->default_state, 0,
935 state, engine->context_size);
936 __set_bit(CONTEXT_VALID_BIT, &ce->flags);
940 /* Clear the ppHWSP (inc. per-context counters) */
941 memset(state, 0, PAGE_SIZE);
943 /* Clear the indirect wa and storage */
945 memset(state + context_wa_bb_offset(ce), 0, PAGE_SIZE);
948 * The second page of the context object contains some registers which
949 * must be set up prior to the first execution.
951 __lrc_init_regs(state + LRC_STATE_OFFSET, ce, engine, inhibit);
954 u32 lrc_indirect_bb(const struct intel_context *ce)
956 return i915_ggtt_offset(ce->state) + context_wa_bb_offset(ce);
959 static u32 *setup_predicate_disable_wa(const struct intel_context *ce, u32 *cs)
961 /* If predication is active, this will be noop'ed */
962 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT | (4 - 2);
963 *cs++ = lrc_indirect_bb(ce) + DG2_PREDICATE_RESULT_WA;
965 *cs++ = 0; /* No predication */
967 /* predicated end, only terminates if SET_PREDICATE_RESULT:0 is clear */
968 *cs++ = MI_BATCH_BUFFER_END | BIT(15);
969 *cs++ = MI_SET_PREDICATE | MI_SET_PREDICATE_DISABLE;
971 /* Instructions are no longer predicated (disabled), we can proceed */
972 *cs++ = MI_STORE_DWORD_IMM_GEN4 | MI_USE_GGTT | (4 - 2);
973 *cs++ = lrc_indirect_bb(ce) + DG2_PREDICATE_RESULT_WA;
975 *cs++ = 1; /* enable predication before the next BB */
977 *cs++ = MI_BATCH_BUFFER_END;
978 GEM_BUG_ON(offset_in_page(cs) > DG2_PREDICATE_RESULT_WA);
983 static struct i915_vma *
984 __lrc_alloc_state(struct intel_context *ce, struct intel_engine_cs *engine)
986 struct drm_i915_gem_object *obj;
987 struct i915_vma *vma;
990 context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE);
992 if (IS_ENABLED(CONFIG_DRM_I915_DEBUG_GEM))
993 context_size += I915_GTT_PAGE_SIZE; /* for redzone */
995 if (GRAPHICS_VER(engine->i915) == 12) {
996 ce->wa_bb_page = context_size / PAGE_SIZE;
997 context_size += PAGE_SIZE;
1000 if (intel_context_is_parent(ce) && intel_engine_uses_guc(engine)) {
1001 ce->parallel.guc.parent_page = context_size / PAGE_SIZE;
1002 context_size += PARENT_SCRATCH_SIZE;
1005 obj = i915_gem_object_create_lmem(engine->i915, context_size,
1006 I915_BO_ALLOC_PM_VOLATILE);
1008 obj = i915_gem_object_create_shmem(engine->i915, context_size);
1010 return ERR_CAST(obj);
1012 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
1014 i915_gem_object_put(obj);
1021 static struct intel_timeline *
1022 pinned_timeline(struct intel_context *ce, struct intel_engine_cs *engine)
1024 struct intel_timeline *tl = fetch_and_zero(&ce->timeline);
1026 return intel_timeline_create_from_engine(engine, page_unmask_bits(tl));
1029 int lrc_alloc(struct intel_context *ce, struct intel_engine_cs *engine)
1031 struct intel_ring *ring;
1032 struct i915_vma *vma;
1035 GEM_BUG_ON(ce->state);
1037 vma = __lrc_alloc_state(ce, engine);
1039 return PTR_ERR(vma);
1041 ring = intel_engine_create_ring(engine, ce->ring_size);
1043 err = PTR_ERR(ring);
1047 if (!page_mask_bits(ce->timeline)) {
1048 struct intel_timeline *tl;
1051 * Use the static global HWSP for the kernel context, and
1052 * a dynamically allocated cacheline for everyone else.
1054 if (unlikely(ce->timeline))
1055 tl = pinned_timeline(ce, engine);
1057 tl = intel_timeline_create(engine->gt);
1072 intel_ring_put(ring);
1078 void lrc_reset(struct intel_context *ce)
1080 GEM_BUG_ON(!intel_context_is_pinned(ce));
1082 intel_ring_reset(ce->ring, ce->ring->emit);
1084 /* Scrub away the garbage */
1085 lrc_init_regs(ce, ce->engine, true);
1086 ce->lrc.lrca = lrc_update_regs(ce, ce->engine, ce->ring->tail);
1090 lrc_pre_pin(struct intel_context *ce,
1091 struct intel_engine_cs *engine,
1092 struct i915_gem_ww_ctx *ww,
1095 GEM_BUG_ON(!ce->state);
1096 GEM_BUG_ON(!i915_vma_is_pinned(ce->state));
1098 *vaddr = i915_gem_object_pin_map(ce->state->obj,
1099 i915_coherent_map_type(ce->engine->i915,
1104 return PTR_ERR_OR_ZERO(*vaddr);
1108 lrc_pin(struct intel_context *ce,
1109 struct intel_engine_cs *engine,
1112 ce->lrc_reg_state = vaddr + LRC_STATE_OFFSET;
1114 if (!__test_and_set_bit(CONTEXT_INIT_BIT, &ce->flags))
1115 lrc_init_state(ce, engine, vaddr);
1117 ce->lrc.lrca = lrc_update_regs(ce, engine, ce->ring->tail);
1121 void lrc_unpin(struct intel_context *ce)
1123 if (unlikely(ce->parallel.last_rq)) {
1124 i915_request_put(ce->parallel.last_rq);
1125 ce->parallel.last_rq = NULL;
1127 check_redzone((void *)ce->lrc_reg_state - LRC_STATE_OFFSET,
1131 void lrc_post_unpin(struct intel_context *ce)
1133 i915_gem_object_unpin_map(ce->state->obj);
1136 void lrc_fini(struct intel_context *ce)
1141 intel_ring_put(fetch_and_zero(&ce->ring));
1142 i915_vma_put(fetch_and_zero(&ce->state));
1145 void lrc_destroy(struct kref *kref)
1147 struct intel_context *ce = container_of(kref, typeof(*ce), ref);
1149 GEM_BUG_ON(!i915_active_is_idle(&ce->active));
1150 GEM_BUG_ON(intel_context_is_pinned(ce));
1154 intel_context_fini(ce);
1155 intel_context_free(ce);
1159 gen12_emit_timestamp_wa(const struct intel_context *ce, u32 *cs)
1161 *cs++ = MI_LOAD_REGISTER_MEM_GEN8 |
1162 MI_SRM_LRM_GLOBAL_GTT |
1164 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));
1165 *cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET +
1166 CTX_TIMESTAMP * sizeof(u32);
1169 *cs++ = MI_LOAD_REGISTER_REG |
1170 MI_LRR_SOURCE_CS_MMIO |
1172 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));
1173 *cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0));
1175 *cs++ = MI_LOAD_REGISTER_REG |
1176 MI_LRR_SOURCE_CS_MMIO |
1178 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));
1179 *cs++ = i915_mmio_reg_offset(RING_CTX_TIMESTAMP(0));
1185 gen12_emit_restore_scratch(const struct intel_context *ce, u32 *cs)
1187 GEM_BUG_ON(lrc_ring_gpr0(ce->engine) == -1);
1189 *cs++ = MI_LOAD_REGISTER_MEM_GEN8 |
1190 MI_SRM_LRM_GLOBAL_GTT |
1192 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));
1193 *cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET +
1194 (lrc_ring_gpr0(ce->engine) + 1) * sizeof(u32);
1201 gen12_emit_cmd_buf_wa(const struct intel_context *ce, u32 *cs)
1203 GEM_BUG_ON(lrc_ring_cmd_buf_cctl(ce->engine) == -1);
1205 *cs++ = MI_LOAD_REGISTER_MEM_GEN8 |
1206 MI_SRM_LRM_GLOBAL_GTT |
1208 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));
1209 *cs++ = i915_ggtt_offset(ce->state) + LRC_STATE_OFFSET +
1210 (lrc_ring_cmd_buf_cctl(ce->engine) + 1) * sizeof(u32);
1213 *cs++ = MI_LOAD_REGISTER_REG |
1214 MI_LRR_SOURCE_CS_MMIO |
1216 *cs++ = i915_mmio_reg_offset(GEN8_RING_CS_GPR(0, 0));
1217 *cs++ = i915_mmio_reg_offset(RING_CMD_BUF_CCTL(0));
1223 * On DG2 during context restore of a preempted context in GPGPU mode,
1224 * RCS restore hang is detected. This is extremely timing dependent.
1225 * To address this below sw wabb is implemented for DG2 A steppings.
1228 dg2_emit_rcs_hang_wabb(const struct intel_context *ce, u32 *cs)
1230 *cs++ = MI_LOAD_REGISTER_IMM(1);
1231 *cs++ = i915_mmio_reg_offset(GEN12_STATE_ACK_DEBUG);
1234 *cs++ = MI_LOAD_REGISTER_REG;
1235 *cs++ = i915_mmio_reg_offset(RING_NOPID(ce->engine->mmio_base));
1236 *cs++ = i915_mmio_reg_offset(GEN12_CULLBIT1);
1238 *cs++ = MI_LOAD_REGISTER_REG;
1239 *cs++ = i915_mmio_reg_offset(RING_NOPID(ce->engine->mmio_base));
1240 *cs++ = i915_mmio_reg_offset(GEN12_CULLBIT2);
1246 gen12_emit_indirect_ctx_rcs(const struct intel_context *ce, u32 *cs)
1248 cs = gen12_emit_timestamp_wa(ce, cs);
1249 cs = gen12_emit_cmd_buf_wa(ce, cs);
1250 cs = gen12_emit_restore_scratch(ce, cs);
1252 /* Wa_22011450934:dg2 */
1253 if (IS_DG2_GRAPHICS_STEP(ce->engine->i915, G10, STEP_A0, STEP_B0) ||
1254 IS_DG2_GRAPHICS_STEP(ce->engine->i915, G11, STEP_A0, STEP_B0))
1255 cs = dg2_emit_rcs_hang_wabb(ce, cs);
1257 /* Wa_16013000631:dg2 */
1258 if (IS_DG2_GRAPHICS_STEP(ce->engine->i915, G10, STEP_B0, STEP_C0) ||
1259 IS_DG2_G11(ce->engine->i915))
1260 cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE, 0);
1262 /* hsdes: 1809175790 */
1263 if (!HAS_FLAT_CCS(ce->engine->i915))
1264 cs = gen12_emit_aux_table_inv(cs, GEN12_GFX_CCS_AUX_NV);
1270 gen12_emit_indirect_ctx_xcs(const struct intel_context *ce, u32 *cs)
1272 cs = gen12_emit_timestamp_wa(ce, cs);
1273 cs = gen12_emit_restore_scratch(ce, cs);
1275 /* Wa_16013000631:dg2 */
1276 if (IS_DG2_GRAPHICS_STEP(ce->engine->i915, G10, STEP_B0, STEP_C0) ||
1277 IS_DG2_G11(ce->engine->i915))
1278 if (ce->engine->class == COMPUTE_CLASS)
1279 cs = gen8_emit_pipe_control(cs,
1280 PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE,
1283 /* hsdes: 1809175790 */
1284 if (!HAS_FLAT_CCS(ce->engine->i915)) {
1285 if (ce->engine->class == VIDEO_DECODE_CLASS)
1286 cs = gen12_emit_aux_table_inv(cs, GEN12_VD0_AUX_NV);
1287 else if (ce->engine->class == VIDEO_ENHANCEMENT_CLASS)
1288 cs = gen12_emit_aux_table_inv(cs, GEN12_VE0_AUX_NV);
1295 setup_indirect_ctx_bb(const struct intel_context *ce,
1296 const struct intel_engine_cs *engine,
1297 u32 *(*emit)(const struct intel_context *, u32 *))
1299 u32 * const start = context_indirect_bb(ce);
1302 cs = emit(ce, start);
1303 GEM_BUG_ON(cs - start > I915_GTT_PAGE_SIZE / sizeof(*cs));
1304 while ((unsigned long)cs % CACHELINE_BYTES)
1307 GEM_BUG_ON(cs - start > DG2_PREDICATE_RESULT_BB / sizeof(*start));
1308 setup_predicate_disable_wa(ce, start + DG2_PREDICATE_RESULT_BB / sizeof(*start));
1310 lrc_setup_indirect_ctx(ce->lrc_reg_state, engine,
1311 lrc_indirect_bb(ce),
1312 (cs - start) * sizeof(*cs));
1316 * The context descriptor encodes various attributes of a context,
1317 * including its GTT address and some flags. Because it's fairly
1318 * expensive to calculate, we'll just do it once and cache the result,
1319 * which remains valid until the context is unpinned.
1321 * This is what a descriptor looks like, from LSB to MSB::
1323 * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template)
1324 * bits 12-31: LRCA, GTT address of (the HWSP of) this context
1325 * bits 32-52: ctx ID, a globally unique tag (highest bit used by GuC)
1326 * bits 53-54: mbz, reserved for use by hardware
1327 * bits 55-63: group ID, currently unused and set to 0
1329 * Starting from Gen11, the upper dword of the descriptor has a new format:
1331 * bits 32-36: reserved
1332 * bits 37-47: SW context ID
1333 * bits 48:53: engine instance
1334 * bit 54: mbz, reserved for use by hardware
1335 * bits 55-60: SW counter
1336 * bits 61-63: engine class
1338 * On Xe_HP, the upper dword of the descriptor has a new format:
1340 * bits 32-37: virtual function number
1341 * bit 38: mbz, reserved for use by hardware
1342 * bits 39-54: SW context ID
1343 * bits 55-57: reserved
1344 * bits 58-63: SW counter
1346 * engine info, SW context ID and SW counter need to form a unique number
1347 * (Context ID) per lrc.
1349 static u32 lrc_descriptor(const struct intel_context *ce)
1353 desc = INTEL_LEGACY_32B_CONTEXT;
1354 if (i915_vm_is_4lvl(ce->vm))
1355 desc = INTEL_LEGACY_64B_CONTEXT;
1356 desc <<= GEN8_CTX_ADDRESSING_MODE_SHIFT;
1358 desc |= GEN8_CTX_VALID | GEN8_CTX_PRIVILEGE;
1359 if (GRAPHICS_VER(ce->vm->i915) == 8)
1360 desc |= GEN8_CTX_L3LLC_COHERENT;
1362 return i915_ggtt_offset(ce->state) | desc;
1365 u32 lrc_update_regs(const struct intel_context *ce,
1366 const struct intel_engine_cs *engine,
1369 struct intel_ring *ring = ce->ring;
1370 u32 *regs = ce->lrc_reg_state;
1372 GEM_BUG_ON(!intel_ring_offset_valid(ring, head));
1373 GEM_BUG_ON(!intel_ring_offset_valid(ring, ring->tail));
1375 regs[CTX_RING_START] = i915_ggtt_offset(ring->vma);
1376 regs[CTX_RING_HEAD] = head;
1377 regs[CTX_RING_TAIL] = ring->tail;
1378 regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID;
1381 if (engine->class == RENDER_CLASS) {
1382 regs[CTX_R_PWR_CLK_STATE] =
1383 intel_sseu_make_rpcs(engine->gt, &ce->sseu);
1385 i915_oa_init_reg_state(ce, engine);
1388 if (ce->wa_bb_page) {
1389 u32 *(*fn)(const struct intel_context *ce, u32 *cs);
1391 fn = gen12_emit_indirect_ctx_xcs;
1392 if (ce->engine->class == RENDER_CLASS)
1393 fn = gen12_emit_indirect_ctx_rcs;
1395 /* Mutually exclusive wrt to global indirect bb */
1396 GEM_BUG_ON(engine->wa_ctx.indirect_ctx.size);
1397 setup_indirect_ctx_bb(ce, engine, fn);
1400 return lrc_descriptor(ce) | CTX_DESC_FORCE_RESTORE;
1403 void lrc_update_offsets(struct intel_context *ce,
1404 struct intel_engine_cs *engine)
1406 set_offsets(ce->lrc_reg_state, reg_offsets(engine), engine, false);
1409 void lrc_check_regs(const struct intel_context *ce,
1410 const struct intel_engine_cs *engine,
1413 const struct intel_ring *ring = ce->ring;
1414 u32 *regs = ce->lrc_reg_state;
1418 if (regs[CTX_RING_START] != i915_ggtt_offset(ring->vma)) {
1419 pr_err("%s: context submitted with incorrect RING_START [%08x], expected %08x\n",
1421 regs[CTX_RING_START],
1422 i915_ggtt_offset(ring->vma));
1423 regs[CTX_RING_START] = i915_ggtt_offset(ring->vma);
1427 if ((regs[CTX_RING_CTL] & ~(RING_WAIT | RING_WAIT_SEMAPHORE)) !=
1428 (RING_CTL_SIZE(ring->size) | RING_VALID)) {
1429 pr_err("%s: context submitted with incorrect RING_CTL [%08x], expected %08x\n",
1432 (u32)(RING_CTL_SIZE(ring->size) | RING_VALID));
1433 regs[CTX_RING_CTL] = RING_CTL_SIZE(ring->size) | RING_VALID;
1437 x = lrc_ring_mi_mode(engine);
1438 if (x != -1 && regs[x + 1] & (regs[x + 1] >> 16) & STOP_RING) {
1439 pr_err("%s: context submitted with STOP_RING [%08x] in RING_MI_MODE\n",
1440 engine->name, regs[x + 1]);
1441 regs[x + 1] &= ~STOP_RING;
1442 regs[x + 1] |= STOP_RING << 16;
1446 WARN_ONCE(!valid, "Invalid lrc state found %s submission\n", when);
1450 * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after
1451 * PIPE_CONTROL instruction. This is required for the flush to happen correctly
1452 * but there is a slight complication as this is applied in WA batch where the
1453 * values are only initialized once so we cannot take register value at the
1454 * beginning and reuse it further; hence we save its value to memory, upload a
1455 * constant value with bit21 set and then we restore it back with the saved value.
1456 * To simplify the WA, a constant value is formed by using the default value
1457 * of this register. This shouldn't be a problem because we are only modifying
1458 * it for a short period and this batch in non-premptible. We can ofcourse
1459 * use additional instructions that read the actual value of the register
1460 * at that time and set our bit of interest but it makes the WA complicated.
1462 * This WA is also required for Gen9 so extracting as a function avoids
1466 gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch)
1468 /* NB no one else is allowed to scribble over scratch + 256! */
1469 *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
1470 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1471 *batch++ = intel_gt_scratch_offset(engine->gt,
1472 INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA);
1475 *batch++ = MI_LOAD_REGISTER_IMM(1);
1476 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1477 *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES;
1479 batch = gen8_emit_pipe_control(batch,
1480 PIPE_CONTROL_CS_STALL |
1481 PIPE_CONTROL_DC_FLUSH_ENABLE,
1484 *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT;
1485 *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4);
1486 *batch++ = intel_gt_scratch_offset(engine->gt,
1487 INTEL_GT_SCRATCH_FIELD_COHERENTL3_WA);
1494 * Typically we only have one indirect_ctx and per_ctx batch buffer which are
1495 * initialized at the beginning and shared across all contexts but this field
1496 * helps us to have multiple batches at different offsets and select them based
1497 * on a criteria. At the moment this batch always start at the beginning of the page
1498 * and at this point we don't have multiple wa_ctx batch buffers.
1500 * The number of WA applied are not known at the beginning; we use this field
1501 * to return the no of DWORDS written.
1503 * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END
1504 * so it adds NOOPs as padding to make it cacheline aligned.
1505 * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together
1506 * makes a complete batch buffer.
1508 static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1510 /* WaDisableCtxRestoreArbitration:bdw,chv */
1511 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1513 /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */
1514 if (IS_BROADWELL(engine->i915))
1515 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
1517 /* WaClearSlmSpaceAtContextSwitch:bdw,chv */
1518 /* Actual scratch location is at 128 bytes offset */
1519 batch = gen8_emit_pipe_control(batch,
1520 PIPE_CONTROL_FLUSH_L3 |
1521 PIPE_CONTROL_STORE_DATA_INDEX |
1522 PIPE_CONTROL_CS_STALL |
1523 PIPE_CONTROL_QW_WRITE,
1524 LRC_PPHWSP_SCRATCH_ADDR);
1526 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1528 /* Pad to end of cacheline */
1529 while ((unsigned long)batch % CACHELINE_BYTES)
1533 * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because
1534 * execution depends on the length specified in terms of cache lines
1535 * in the register CTX_RCS_INDIRECT_CTX
1546 static u32 *emit_lri(u32 *batch, const struct lri *lri, unsigned int count)
1548 GEM_BUG_ON(!count || count > 63);
1550 *batch++ = MI_LOAD_REGISTER_IMM(count);
1552 *batch++ = i915_mmio_reg_offset(lri->reg);
1553 *batch++ = lri->value;
1554 } while (lri++, --count);
1560 static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch)
1562 static const struct lri lri[] = {
1563 /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */
1565 COMMON_SLICE_CHICKEN2,
1566 __MASKED_FIELD(GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE,
1573 __MASKED_FIELD(FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX,
1574 FF_SLICE_CHICKEN_CL_PROVOKING_VERTEX_FIX),
1580 __MASKED_FIELD(_3D_CHICKEN_SF_PROVOKING_VERTEX_FIX,
1581 _3D_CHICKEN_SF_PROVOKING_VERTEX_FIX),
1585 *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE;
1587 /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */
1588 batch = gen8_emit_flush_coherentl3_wa(engine, batch);
1590 /* WaClearSlmSpaceAtContextSwitch:skl,bxt,kbl,glk,cfl */
1591 batch = gen8_emit_pipe_control(batch,
1592 PIPE_CONTROL_FLUSH_L3 |
1593 PIPE_CONTROL_STORE_DATA_INDEX |
1594 PIPE_CONTROL_CS_STALL |
1595 PIPE_CONTROL_QW_WRITE,
1596 LRC_PPHWSP_SCRATCH_ADDR);
1598 batch = emit_lri(batch, lri, ARRAY_SIZE(lri));
1600 /* WaMediaPoolStateCmdInWABB:bxt,glk */
1601 if (HAS_POOLED_EU(engine->i915)) {
1603 * EU pool configuration is setup along with golden context
1604 * during context initialization. This value depends on
1605 * device type (2x6 or 3x6) and needs to be updated based
1606 * on which subslice is disabled especially for 2x6
1607 * devices, however it is safe to load default
1608 * configuration of 3x6 device instead of masking off
1609 * corresponding bits because HW ignores bits of a disabled
1610 * subslice and drops down to appropriate config. Please
1611 * see render_state_setup() in i915_gem_render_state.c for
1612 * possible configurations, to avoid duplication they are
1613 * not shown here again.
1615 *batch++ = GEN9_MEDIA_POOL_STATE;
1616 *batch++ = GEN9_MEDIA_POOL_ENABLE;
1617 *batch++ = 0x00777000;
1623 *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE;
1625 /* Pad to end of cacheline */
1626 while ((unsigned long)batch % CACHELINE_BYTES)
1632 #define CTX_WA_BB_SIZE (PAGE_SIZE)
1634 static int lrc_create_wa_ctx(struct intel_engine_cs *engine)
1636 struct drm_i915_gem_object *obj;
1637 struct i915_vma *vma;
1640 obj = i915_gem_object_create_shmem(engine->i915, CTX_WA_BB_SIZE);
1642 return PTR_ERR(obj);
1644 vma = i915_vma_instance(obj, &engine->gt->ggtt->vm, NULL);
1650 engine->wa_ctx.vma = vma;
1654 i915_gem_object_put(obj);
1658 void lrc_fini_wa_ctx(struct intel_engine_cs *engine)
1660 i915_vma_unpin_and_release(&engine->wa_ctx.vma, 0);
1663 typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch);
1665 void lrc_init_wa_ctx(struct intel_engine_cs *engine)
1667 struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx;
1668 struct i915_wa_ctx_bb *wa_bb[] = {
1669 &wa_ctx->indirect_ctx, &wa_ctx->per_ctx
1671 wa_bb_func_t wa_bb_fn[ARRAY_SIZE(wa_bb)];
1672 struct i915_gem_ww_ctx ww;
1673 void *batch, *batch_ptr;
1677 if (!(engine->flags & I915_ENGINE_HAS_RCS_REG_STATE))
1680 switch (GRAPHICS_VER(engine->i915)) {
1685 wa_bb_fn[0] = gen9_init_indirectctx_bb;
1689 wa_bb_fn[0] = gen8_init_indirectctx_bb;
1693 MISSING_CASE(GRAPHICS_VER(engine->i915));
1697 err = lrc_create_wa_ctx(engine);
1700 * We continue even if we fail to initialize WA batch
1701 * because we only expect rare glitches but nothing
1702 * critical to prevent us from using GPU
1704 drm_err(&engine->i915->drm,
1705 "Ignoring context switch w/a allocation error:%d\n",
1710 if (!engine->wa_ctx.vma)
1713 i915_gem_ww_ctx_init(&ww, true);
1715 err = i915_gem_object_lock(wa_ctx->vma->obj, &ww);
1717 err = i915_ggtt_pin(wa_ctx->vma, &ww, 0, PIN_HIGH);
1721 batch = i915_gem_object_pin_map(wa_ctx->vma->obj, I915_MAP_WB);
1722 if (IS_ERR(batch)) {
1723 err = PTR_ERR(batch);
1728 * Emit the two workaround batch buffers, recording the offset from the
1729 * start of the workaround batch buffer object for each and their
1733 for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) {
1734 wa_bb[i]->offset = batch_ptr - batch;
1735 if (GEM_DEBUG_WARN_ON(!IS_ALIGNED(wa_bb[i]->offset,
1736 CACHELINE_BYTES))) {
1741 batch_ptr = wa_bb_fn[i](engine, batch_ptr);
1742 wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset);
1744 GEM_BUG_ON(batch_ptr - batch > CTX_WA_BB_SIZE);
1746 __i915_gem_object_flush_map(wa_ctx->vma->obj, 0, batch_ptr - batch);
1747 __i915_gem_object_release_map(wa_ctx->vma->obj);
1749 /* Verify that we can handle failure to setup the wa_ctx */
1751 err = i915_inject_probe_error(engine->i915, -ENODEV);
1755 i915_vma_unpin(wa_ctx->vma);
1757 if (err == -EDEADLK) {
1758 err = i915_gem_ww_ctx_backoff(&ww);
1762 i915_gem_ww_ctx_fini(&ww);
1765 i915_vma_put(engine->wa_ctx.vma);
1767 /* Clear all flags to prevent further use */
1768 memset(wa_ctx, 0, sizeof(*wa_ctx));
1772 static void st_runtime_underflow(struct intel_context_stats *stats, s32 dt)
1774 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1775 stats->runtime.num_underflow++;
1776 stats->runtime.max_underflow =
1777 max_t(u32, stats->runtime.max_underflow, -dt);
1781 static u32 lrc_get_runtime(const struct intel_context *ce)
1784 * We can use either ppHWSP[16] which is recorded before the context
1785 * switch (and so excludes the cost of context switches) or use the
1786 * value from the context image itself, which is saved/restored earlier
1787 * and so includes the cost of the save.
1789 return READ_ONCE(ce->lrc_reg_state[CTX_TIMESTAMP]);
1792 void lrc_update_runtime(struct intel_context *ce)
1794 struct intel_context_stats *stats = &ce->stats;
1798 old = stats->runtime.last;
1799 stats->runtime.last = lrc_get_runtime(ce);
1800 dt = stats->runtime.last - old;
1804 if (unlikely(dt < 0)) {
1805 CE_TRACE(ce, "runtime underflow: last=%u, new=%u, delta=%d\n",
1806 old, stats->runtime.last, dt);
1807 st_runtime_underflow(stats, dt);
1811 ewma_runtime_add(&stats->runtime.avg, dt);
1812 stats->runtime.total += dt;
1815 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
1816 #include "selftest_lrc.c"