1 // SPDX-License-Identifier: MIT
3 * Copyright © 2019 Intel Corporation
6 #include <linux/string_helpers.h>
7 #include <linux/suspend.h>
10 #include "i915_params.h"
11 #include "intel_context.h"
12 #include "intel_engine_pm.h"
14 #include "intel_gt_clock_utils.h"
15 #include "intel_gt_pm.h"
16 #include "intel_gt_requests.h"
17 #include "intel_llc.h"
19 #include "intel_rc6.h"
20 #include "intel_rps.h"
21 #include "intel_wakeref.h"
22 #include "pxp/intel_pxp_pm.h"
24 #define I915_GT_SUSPEND_IDLE_TIMEOUT (HZ / 2)
26 static void user_forcewake(struct intel_gt *gt, bool suspend)
28 int count = atomic_read(>->user_wakeref);
30 /* Inside suspend/resume so single threaded, no races to worry about. */
36 GEM_BUG_ON(count > atomic_read(>->wakeref.count));
37 atomic_sub(count, >->wakeref.count);
39 atomic_add(count, >->wakeref.count);
44 static void runtime_begin(struct intel_gt *gt)
47 write_seqcount_begin(>->stats.lock);
48 gt->stats.start = ktime_get();
49 gt->stats.active = true;
50 write_seqcount_end(>->stats.lock);
54 static void runtime_end(struct intel_gt *gt)
57 write_seqcount_begin(>->stats.lock);
58 gt->stats.active = false;
60 ktime_add(gt->stats.total,
61 ktime_sub(ktime_get(), gt->stats.start));
62 write_seqcount_end(>->stats.lock);
66 static int __gt_unpark(struct intel_wakeref *wf)
68 struct intel_gt *gt = container_of(wf, typeof(*gt), wakeref);
69 struct drm_i915_private *i915 = gt->i915;
74 * It seems that the DMC likes to transition between the DC states a lot
75 * when there are no connected displays (no active power domains) during
78 * This activity has negative impact on the performance of the chip with
79 * huge latencies observed in the interrupt handler and elsewhere.
81 * Work around it by grabbing a GT IRQ power domain whilst there is any
82 * GT activity, preventing any DC state transitions.
84 gt->awake = intel_display_power_get(i915, POWER_DOMAIN_GT_IRQ);
85 GEM_BUG_ON(!gt->awake);
87 intel_rc6_unpark(>->rc6);
88 intel_rps_unpark(>->rps);
89 i915_pmu_gt_unparked(i915);
90 intel_guc_busyness_unpark(gt);
92 intel_gt_unpark_requests(gt);
98 static int __gt_park(struct intel_wakeref *wf)
100 struct intel_gt *gt = container_of(wf, typeof(*gt), wakeref);
101 intel_wakeref_t wakeref = fetch_and_zero(>->awake);
102 struct drm_i915_private *i915 = gt->i915;
107 intel_gt_park_requests(gt);
109 intel_guc_busyness_park(gt);
111 i915_pmu_gt_parked(i915);
112 intel_rps_park(>->rps);
113 intel_rc6_park(>->rc6);
115 /* Everything switched off, flush any residual interrupt just in case */
116 intel_synchronize_irq(i915);
118 /* Defer dropping the display power well for 100ms, it's slow! */
119 GEM_BUG_ON(!wakeref);
120 intel_display_power_put_async(i915, POWER_DOMAIN_GT_IRQ, wakeref);
125 static const struct intel_wakeref_ops wf_ops = {
130 void intel_gt_pm_init_early(struct intel_gt *gt)
133 * We access the runtime_pm structure via gt->i915 here rather than
134 * gt->uncore as we do elsewhere in the file because gt->uncore is not
135 * yet initialized for all tiles at this point in the driver startup.
136 * runtime_pm is per-device rather than per-tile, so this is still the
139 intel_wakeref_init(>->wakeref, >->i915->runtime_pm, &wf_ops);
140 seqcount_mutex_init(>->stats.lock, >->wakeref.mutex);
143 void intel_gt_pm_init(struct intel_gt *gt)
146 * Enabling power-management should be "self-healing". If we cannot
147 * enable a feature, simply leave it disabled with a notice to the
150 intel_rc6_init(>->rc6);
151 intel_rps_init(>->rps);
154 static bool reset_engines(struct intel_gt *gt)
156 if (INTEL_INFO(gt->i915)->gpu_reset_clobbers_display)
159 return __intel_gt_reset(gt, ALL_ENGINES) == 0;
162 static void gt_sanitize(struct intel_gt *gt, bool force)
164 struct intel_engine_cs *engine;
165 enum intel_engine_id id;
166 intel_wakeref_t wakeref;
168 GT_TRACE(gt, "force:%s", str_yes_no(force));
170 /* Use a raw wakeref to avoid calling intel_display_power_get early */
171 wakeref = intel_runtime_pm_get(gt->uncore->rpm);
172 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
174 intel_gt_check_clock_frequency(gt);
177 * As we have just resumed the machine and woken the device up from
178 * deep PCI sleep (presumably D3_cold), assume the HW has been reset
179 * back to defaults, recovering from whatever wedged state we left it
180 * in and so worth trying to use the device once more.
182 if (intel_gt_is_wedged(gt))
183 intel_gt_unset_wedged(gt);
185 /* For GuC mode, ensure submission is disabled before stopping ring */
186 intel_uc_reset_prepare(>->uc);
188 for_each_engine(engine, gt, id) {
189 if (engine->reset.prepare)
190 engine->reset.prepare(engine);
192 if (engine->sanitize)
193 engine->sanitize(engine);
196 if (reset_engines(gt) || force) {
197 for_each_engine(engine, gt, id)
198 __intel_engine_reset(engine, false);
201 intel_uc_reset(>->uc, false);
203 for_each_engine(engine, gt, id)
204 if (engine->reset.finish)
205 engine->reset.finish(engine);
207 intel_rps_sanitize(>->rps);
209 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
210 intel_runtime_pm_put(gt->uncore->rpm, wakeref);
213 void intel_gt_pm_fini(struct intel_gt *gt)
215 intel_rc6_fini(>->rc6);
218 int intel_gt_resume(struct intel_gt *gt)
220 struct intel_engine_cs *engine;
221 enum intel_engine_id id;
224 err = intel_gt_has_unrecoverable_error(gt);
231 * After resume, we may need to poke into the pinned kernel
232 * contexts to paper over any damage caused by the sudden suspend.
233 * Only the kernel contexts should remain pinned over suspend,
234 * allowing us to fixup the user contexts on their first pin.
236 gt_sanitize(gt, true);
240 intel_uncore_forcewake_get(gt->uncore, FORCEWAKE_ALL);
241 intel_rc6_sanitize(>->rc6);
242 if (intel_gt_is_wedged(gt)) {
247 /* Only when the HW is re-initialised, can we replay the requests */
248 err = intel_gt_init_hw(gt);
250 i915_probe_error(gt->i915,
251 "Failed to initialize GPU, declaring it wedged!\n");
255 intel_uc_reset_finish(>->uc);
257 intel_rps_enable(>->rps);
258 intel_llc_enable(>->llc);
260 for_each_engine(engine, gt, id) {
261 intel_engine_pm_get(engine);
263 engine->serial++; /* kernel context lost */
264 err = intel_engine_resume(engine);
266 intel_engine_pm_put(engine);
268 drm_err(>->i915->drm,
269 "Failed to restart %s (%d)\n",
275 intel_rc6_enable(>->rc6);
277 intel_uc_resume(>->uc);
279 intel_pxp_resume(>->pxp);
281 user_forcewake(gt, false);
284 intel_uncore_forcewake_put(gt->uncore, FORCEWAKE_ALL);
289 intel_gt_set_wedged(gt);
293 static void wait_for_suspend(struct intel_gt *gt)
295 if (!intel_gt_pm_is_awake(gt))
298 if (intel_gt_wait_for_idle(gt, I915_GT_SUSPEND_IDLE_TIMEOUT) == -ETIME) {
300 * Forcibly cancel outstanding work and leave
303 intel_gt_set_wedged(gt);
304 intel_gt_retire_requests(gt);
307 intel_gt_pm_wait_for_idle(gt);
310 void intel_gt_suspend_prepare(struct intel_gt *gt)
312 user_forcewake(gt, true);
313 wait_for_suspend(gt);
315 intel_pxp_suspend_prepare(>->pxp);
318 static suspend_state_t pm_suspend_target(void)
320 #if IS_ENABLED(CONFIG_SUSPEND) && IS_ENABLED(CONFIG_PM_SLEEP)
321 return pm_suspend_target_state;
323 return PM_SUSPEND_TO_IDLE;
327 void intel_gt_suspend_late(struct intel_gt *gt)
329 intel_wakeref_t wakeref;
331 /* We expect to be idle already; but also want to be independent */
332 wait_for_suspend(gt);
337 GEM_BUG_ON(gt->awake);
339 intel_uc_suspend(>->uc);
340 intel_pxp_suspend(>->pxp);
343 * On disabling the device, we want to turn off HW access to memory
344 * that we no longer own.
346 * However, not all suspend-states disable the device. S0 (s2idle)
347 * is effectively runtime-suspend, the device is left powered on
348 * but needs to be put into a low power state. We need to keep
349 * powermanagement enabled, but we also retain system state and so
350 * it remains safe to keep on using our allocated memory.
352 if (pm_suspend_target() == PM_SUSPEND_TO_IDLE)
355 with_intel_runtime_pm(gt->uncore->rpm, wakeref) {
356 intel_rps_disable(>->rps);
357 intel_rc6_disable(>->rc6);
358 intel_llc_disable(>->llc);
361 gt_sanitize(gt, false);
366 void intel_gt_runtime_suspend(struct intel_gt *gt)
368 intel_pxp_runtime_suspend(>->pxp);
369 intel_uc_runtime_suspend(>->uc);
374 int intel_gt_runtime_resume(struct intel_gt *gt)
379 intel_gt_init_swizzling(gt);
380 intel_ggtt_restore_fences(gt->ggtt);
382 ret = intel_uc_runtime_resume(>->uc);
386 intel_pxp_runtime_resume(>->pxp);
391 static ktime_t __intel_gt_get_awake_time(const struct intel_gt *gt)
393 ktime_t total = gt->stats.total;
395 if (gt->stats.active)
396 total = ktime_add(total,
397 ktime_sub(ktime_get(), gt->stats.start));
402 ktime_t intel_gt_get_awake_time(const struct intel_gt *gt)
408 seq = read_seqcount_begin(>->stats.lock);
409 total = __intel_gt_get_awake_time(gt);
410 } while (read_seqcount_retry(>->stats.lock, seq));
415 #if IS_ENABLED(CONFIG_DRM_I915_SELFTEST)
416 #include "selftest_gt_pm.c"