drivers/gpu/drm/amd/pm/swsmu/amdgpu_smu.c

   1 /*
   2  * Copyright 2019 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  */
  22
  23 #define SWSMU_CODE_LAYER_L1
  24
  25 #include <linux/firmware.h>
  26 #include <linux/pci.h>
  27
  28 #include "amdgpu.h"
  29 #include "amdgpu_smu.h"
  30 #include "smu_internal.h"
  31 #include "atom.h"
  32 #include "arcturus_ppt.h"
  33 #include "navi10_ppt.h"
  34 #include "sienna_cichlid_ppt.h"
  35 #include "renoir_ppt.h"
  36 #include "vangogh_ppt.h"
  37 #include "aldebaran_ppt.h"
  38 #include "yellow_carp_ppt.h"
  39 #include "cyan_skillfish_ppt.h"
  40 #include "smu_v13_0_0_ppt.h"
  41 #include "smu_v13_0_4_ppt.h"
  42 #include "smu_v13_0_5_ppt.h"
  43 #include "smu_v13_0_7_ppt.h"
  44 #include "amd_pcie.h"
  45
  46 /*
  47  * DO NOT use these for err/warn/info/debug messages.
  48  * Use dev_err, dev_warn, dev_info and dev_dbg instead.
  49  * They are more MGPU friendly.
  50  */
  51 #undef pr_err
  52 #undef pr_warn
  53 #undef pr_info
  54 #undef pr_debug
  55
  56 static const struct amd_pm_funcs swsmu_pm_funcs;
  57 static int smu_force_smuclk_levels(struct smu_context *smu,
  58                                    enum smu_clk_type clk_type,
  59                                    uint32_t mask);
  60 static int smu_handle_task(struct smu_context *smu,
  61                            enum amd_dpm_forced_level level,
  62                            enum amd_pp_task task_id);
  63 static int smu_reset(struct smu_context *smu);
  64 static int smu_set_fan_speed_pwm(void *handle, u32 speed);
  65 static int smu_set_fan_control_mode(void *handle, u32 value);
  66 static int smu_set_power_limit(void *handle, uint32_t limit);
  67 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed);
  68 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled);
  69 static int smu_set_mp1_state(void *handle, enum pp_mp1_state mp1_state);
  70
  71 static int smu_sys_get_pp_feature_mask(void *handle,
  72                                        char *buf)
  73 {
  74         struct smu_context *smu = handle;
  75
  76         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
  77                 return -EOPNOTSUPP;
  78
  79         return smu_get_pp_feature_mask(smu, buf);
  80 }
  81
  82 static int smu_sys_set_pp_feature_mask(void *handle,
  83                                        uint64_t new_mask)
  84 {
  85         struct smu_context *smu = handle;
  86
  87         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
  88                 return -EOPNOTSUPP;
  89
  90         return smu_set_pp_feature_mask(smu, new_mask);
  91 }
  92
  93 int smu_get_status_gfxoff(struct smu_context *smu, uint32_t *value)
  94 {
  95         if (!smu->ppt_funcs->get_gfx_off_status)
  96                 return -EINVAL;
  97
  98         *value = smu_get_gfx_off_status(smu);
  99
 100         return 0;
 101 }
 102
 103 int smu_set_soft_freq_range(struct smu_context *smu,
 104                             enum smu_clk_type clk_type,
 105                             uint32_t min,
 106                             uint32_t max)
 107 {
 108         int ret = 0;
 109
 110         if (smu->ppt_funcs->set_soft_freq_limited_range)
 111                 ret = smu->ppt_funcs->set_soft_freq_limited_range(smu,
 112                                                                   clk_type,
 113                                                                   min,
 114                                                                   max);
 115
 116         return ret;
 117 }
 118
 119 int smu_get_dpm_freq_range(struct smu_context *smu,
 120                            enum smu_clk_type clk_type,
 121                            uint32_t *min,
 122                            uint32_t *max)
 123 {
 124         int ret = -ENOTSUPP;
 125
 126         if (!min && !max)
 127                 return -EINVAL;
 128
 129         if (smu->ppt_funcs->get_dpm_ultimate_freq)
 130                 ret = smu->ppt_funcs->get_dpm_ultimate_freq(smu,
 131                                                             clk_type,
 132                                                             min,
 133                                                             max);
 134
 135         return ret;
 136 }
 137
 138 int smu_set_gfx_power_up_by_imu(struct smu_context *smu)
 139 {
 140         if (!smu->ppt_funcs && !smu->ppt_funcs->set_gfx_power_up_by_imu)
 141                 return -EOPNOTSUPP;
 142
 143         return smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
 144 }
 145
 146 static u32 smu_get_mclk(void *handle, bool low)
 147 {
 148         struct smu_context *smu = handle;
 149         uint32_t clk_freq;
 150         int ret = 0;
 151
 152         ret = smu_get_dpm_freq_range(smu, SMU_UCLK,
 153                                      low ? &clk_freq : NULL,
 154                                      !low ? &clk_freq : NULL);
 155         if (ret)
 156                 return 0;
 157         return clk_freq * 100;
 158 }
 159
 160 static u32 smu_get_sclk(void *handle, bool low)
 161 {
 162         struct smu_context *smu = handle;
 163         uint32_t clk_freq;
 164         int ret = 0;
 165
 166         ret = smu_get_dpm_freq_range(smu, SMU_GFXCLK,
 167                                      low ? &clk_freq : NULL,
 168                                      !low ? &clk_freq : NULL);
 169         if (ret)
 170                 return 0;
 171         return clk_freq * 100;
 172 }
 173
 174 static int smu_dpm_set_vcn_enable(struct smu_context *smu,
 175                                   bool enable)
 176 {
 177         struct smu_power_context *smu_power = &smu->smu_power;
 178         struct smu_power_gate *power_gate = &smu_power->power_gate;
 179         int ret = 0;
 180
 181         if (!smu->ppt_funcs->dpm_set_vcn_enable)
 182                 return 0;
 183
 184         if (atomic_read(&power_gate->vcn_gated) ^ enable)
 185                 return 0;
 186
 187         ret = smu->ppt_funcs->dpm_set_vcn_enable(smu, enable);
 188         if (!ret)
 189                 atomic_set(&power_gate->vcn_gated, !enable);
 190
 191         return ret;
 192 }
 193
 194 static int smu_dpm_set_jpeg_enable(struct smu_context *smu,
 195                                    bool enable)
 196 {
 197         struct smu_power_context *smu_power = &smu->smu_power;
 198         struct smu_power_gate *power_gate = &smu_power->power_gate;
 199         int ret = 0;
 200
 201         if (!smu->ppt_funcs->dpm_set_jpeg_enable)
 202                 return 0;
 203
 204         if (atomic_read(&power_gate->jpeg_gated) ^ enable)
 205                 return 0;
 206
 207         ret = smu->ppt_funcs->dpm_set_jpeg_enable(smu, enable);
 208         if (!ret)
 209                 atomic_set(&power_gate->jpeg_gated, !enable);
 210
 211         return ret;
 212 }
 213
 214 /**
 215  * smu_dpm_set_power_gate - power gate/ungate the specific IP block
 216  *
 217  * @handle:        smu_context pointer
 218  * @block_type: the IP block to power gate/ungate
 219  * @gate:       to power gate if true, ungate otherwise
 220  *
 221  * This API uses no smu->mutex lock protection due to:
 222  * 1. It is either called by other IP block(gfx/sdma/vcn/uvd/vce).
 223  *    This is guarded to be race condition free by the caller.
 224  * 2. Or get called on user setting request of power_dpm_force_performance_level.
 225  *    Under this case, the smu->mutex lock protection is already enforced on
 226  *    the parent API smu_force_performance_level of the call path.
 227  */
 228 static int smu_dpm_set_power_gate(void *handle,
 229                                   uint32_t block_type,
 230                                   bool gate)
 231 {
 232         struct smu_context *smu = handle;
 233         int ret = 0;
 234
 235         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled) {
 236                 dev_WARN(smu->adev->dev,
 237                          "SMU uninitialized but power %s requested for %u!\n",
 238                          gate ? "gate" : "ungate", block_type);
 239                 return -EOPNOTSUPP;
 240         }
 241
 242         switch (block_type) {
 243         /*
 244          * Some legacy code of amdgpu_vcn.c and vcn_v2*.c still uses
 245          * AMD_IP_BLOCK_TYPE_UVD for VCN. So, here both of them are kept.
 246          */
 247         case AMD_IP_BLOCK_TYPE_UVD:
 248         case AMD_IP_BLOCK_TYPE_VCN:
 249                 ret = smu_dpm_set_vcn_enable(smu, !gate);
 250                 if (ret)
 251                         dev_err(smu->adev->dev, "Failed to power %s VCN!\n",
 252                                 gate ? "gate" : "ungate");
 253                 break;
 254         case AMD_IP_BLOCK_TYPE_GFX:
 255                 ret = smu_gfx_off_control(smu, gate);
 256                 if (ret)
 257                         dev_err(smu->adev->dev, "Failed to %s gfxoff!\n",
 258                                 gate ? "enable" : "disable");
 259                 break;
 260         case AMD_IP_BLOCK_TYPE_SDMA:
 261                 ret = smu_powergate_sdma(smu, gate);
 262                 if (ret)
 263                         dev_err(smu->adev->dev, "Failed to power %s SDMA!\n",
 264                                 gate ? "gate" : "ungate");
 265                 break;
 266         case AMD_IP_BLOCK_TYPE_JPEG:
 267                 ret = smu_dpm_set_jpeg_enable(smu, !gate);
 268                 if (ret)
 269                         dev_err(smu->adev->dev, "Failed to power %s JPEG!\n",
 270                                 gate ? "gate" : "ungate");
 271                 break;
 272         default:
 273                 dev_err(smu->adev->dev, "Unsupported block type!\n");
 274                 return -EINVAL;
 275         }
 276
 277         return ret;
 278 }
 279
 280 /**
 281  * smu_set_user_clk_dependencies - set user profile clock dependencies
 282  *
 283  * @smu:        smu_context pointer
 284  * @clk:        enum smu_clk_type type
 285  *
 286  * Enable/Disable the clock dependency for the @clk type.
 287  */
 288 static void smu_set_user_clk_dependencies(struct smu_context *smu, enum smu_clk_type clk)
 289 {
 290         if (smu->adev->in_suspend)
 291                 return;
 292
 293         if (clk == SMU_MCLK) {
 294                 smu->user_dpm_profile.clk_dependency = 0;
 295                 smu->user_dpm_profile.clk_dependency = BIT(SMU_FCLK) | BIT(SMU_SOCCLK);
 296         } else if (clk == SMU_FCLK) {
 297                 /* MCLK takes precedence over FCLK */
 298                 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
 299                         return;
 300
 301                 smu->user_dpm_profile.clk_dependency = 0;
 302                 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_SOCCLK);
 303         } else if (clk == SMU_SOCCLK) {
 304                 /* MCLK takes precedence over SOCCLK */
 305                 if (smu->user_dpm_profile.clk_dependency == (BIT(SMU_FCLK) | BIT(SMU_SOCCLK)))
 306                         return;
 307
 308                 smu->user_dpm_profile.clk_dependency = 0;
 309                 smu->user_dpm_profile.clk_dependency = BIT(SMU_MCLK) | BIT(SMU_FCLK);
 310         } else
 311                 /* Add clk dependencies here, if any */
 312                 return;
 313 }
 314
 315 /**
 316  * smu_restore_dpm_user_profile - reinstate user dpm profile
 317  *
 318  * @smu:        smu_context pointer
 319  *
 320  * Restore the saved user power configurations include power limit,
 321  * clock frequencies, fan control mode and fan speed.
 322  */
 323 static void smu_restore_dpm_user_profile(struct smu_context *smu)
 324 {
 325         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
 326         int ret = 0;
 327
 328         if (!smu->adev->in_suspend)
 329                 return;
 330
 331         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 332                 return;
 333
 334         /* Enable restore flag */
 335         smu->user_dpm_profile.flags |= SMU_DPM_USER_PROFILE_RESTORE;
 336
 337         /* set the user dpm power limit */
 338         if (smu->user_dpm_profile.power_limit) {
 339                 ret = smu_set_power_limit(smu, smu->user_dpm_profile.power_limit);
 340                 if (ret)
 341                         dev_err(smu->adev->dev, "Failed to set power limit value\n");
 342         }
 343
 344         /* set the user dpm clock configurations */
 345         if (smu_dpm_ctx->dpm_level == AMD_DPM_FORCED_LEVEL_MANUAL) {
 346                 enum smu_clk_type clk_type;
 347
 348                 for (clk_type = 0; clk_type < SMU_CLK_COUNT; clk_type++) {
 349                         /*
 350                          * Iterate over smu clk type and force the saved user clk
 351                          * configs, skip if clock dependency is enabled
 352                          */
 353                         if (!(smu->user_dpm_profile.clk_dependency & BIT(clk_type)) &&
 354                                         smu->user_dpm_profile.clk_mask[clk_type]) {
 355                                 ret = smu_force_smuclk_levels(smu, clk_type,
 356                                                 smu->user_dpm_profile.clk_mask[clk_type]);
 357                                 if (ret)
 358                                         dev_err(smu->adev->dev,
 359                                                 "Failed to set clock type = %d\n", clk_type);
 360                         }
 361                 }
 362         }
 363
 364         /* set the user dpm fan configurations */
 365         if (smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_MANUAL ||
 366             smu->user_dpm_profile.fan_mode == AMD_FAN_CTRL_NONE) {
 367                 ret = smu_set_fan_control_mode(smu, smu->user_dpm_profile.fan_mode);
 368                 if (ret != -EOPNOTSUPP) {
 369                         smu->user_dpm_profile.fan_speed_pwm = 0;
 370                         smu->user_dpm_profile.fan_speed_rpm = 0;
 371                         smu->user_dpm_profile.fan_mode = AMD_FAN_CTRL_AUTO;
 372                         dev_err(smu->adev->dev, "Failed to set manual fan control mode\n");
 373                 }
 374
 375                 if (smu->user_dpm_profile.fan_speed_pwm) {
 376                         ret = smu_set_fan_speed_pwm(smu, smu->user_dpm_profile.fan_speed_pwm);
 377                         if (ret != -EOPNOTSUPP)
 378                                 dev_err(smu->adev->dev, "Failed to set manual fan speed in pwm\n");
 379                 }
 380
 381                 if (smu->user_dpm_profile.fan_speed_rpm) {
 382                         ret = smu_set_fan_speed_rpm(smu, smu->user_dpm_profile.fan_speed_rpm);
 383                         if (ret != -EOPNOTSUPP)
 384                                 dev_err(smu->adev->dev, "Failed to set manual fan speed in rpm\n");
 385                 }
 386         }
 387
 388         /* Restore user customized OD settings */
 389         if (smu->user_dpm_profile.user_od) {
 390                 if (smu->ppt_funcs->restore_user_od_settings) {
 391                         ret = smu->ppt_funcs->restore_user_od_settings(smu);
 392                         if (ret)
 393                                 dev_err(smu->adev->dev, "Failed to upload customized OD settings\n");
 394                 }
 395         }
 396
 397         /* Disable restore flag */
 398         smu->user_dpm_profile.flags &= ~SMU_DPM_USER_PROFILE_RESTORE;
 399 }
 400
 401 static int smu_get_power_num_states(void *handle,
 402                                     struct pp_states_info *state_info)
 403 {
 404         if (!state_info)
 405                 return -EINVAL;
 406
 407         /* not support power state */
 408         memset(state_info, 0, sizeof(struct pp_states_info));
 409         state_info->nums = 1;
 410         state_info->states[0] = POWER_STATE_TYPE_DEFAULT;
 411
 412         return 0;
 413 }
 414
 415 bool is_support_sw_smu(struct amdgpu_device *adev)
 416 {
 417         /* vega20 is 11.0.2, but it's supported via the powerplay code */
 418         if (adev->asic_type == CHIP_VEGA20)
 419                 return false;
 420
 421         if (adev->ip_versions[MP1_HWIP][0] >= IP_VERSION(11, 0, 0))
 422                 return true;
 423
 424         return false;
 425 }
 426
 427 bool is_support_cclk_dpm(struct amdgpu_device *adev)
 428 {
 429         struct smu_context *smu = adev->powerplay.pp_handle;
 430
 431         if (!smu_feature_is_enabled(smu, SMU_FEATURE_CCLK_DPM_BIT))
 432                 return false;
 433
 434         return true;
 435 }
 436
 437
 438 static int smu_sys_get_pp_table(void *handle,
 439                                 char **table)
 440 {
 441         struct smu_context *smu = handle;
 442         struct smu_table_context *smu_table = &smu->smu_table;
 443
 444         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 445                 return -EOPNOTSUPP;
 446
 447         if (!smu_table->power_play_table && !smu_table->hardcode_pptable)
 448                 return -EINVAL;
 449
 450         if (smu_table->hardcode_pptable)
 451                 *table = smu_table->hardcode_pptable;
 452         else
 453                 *table = smu_table->power_play_table;
 454
 455         return smu_table->power_play_table_size;
 456 }
 457
 458 static int smu_sys_set_pp_table(void *handle,
 459                                 const char *buf,
 460                                 size_t size)
 461 {
 462         struct smu_context *smu = handle;
 463         struct smu_table_context *smu_table = &smu->smu_table;
 464         ATOM_COMMON_TABLE_HEADER *header = (ATOM_COMMON_TABLE_HEADER *)buf;
 465         int ret = 0;
 466
 467         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
 468                 return -EOPNOTSUPP;
 469
 470         if (header->usStructureSize != size) {
 471                 dev_err(smu->adev->dev, "pp table size not matched !\n");
 472                 return -EIO;
 473         }
 474
 475         if (!smu_table->hardcode_pptable) {
 476                 smu_table->hardcode_pptable = kzalloc(size, GFP_KERNEL);
 477                 if (!smu_table->hardcode_pptable)
 478                         return -ENOMEM;
 479         }
 480
 481         memcpy(smu_table->hardcode_pptable, buf, size);
 482         smu_table->power_play_table = smu_table->hardcode_pptable;
 483         smu_table->power_play_table_size = size;
 484
 485         /*
 486          * Special hw_fini action(for Navi1x, the DPMs disablement will be
 487          * skipped) may be needed for custom pptable uploading.
 488          */
 489         smu->uploading_custom_pp_table = true;
 490
 491         ret = smu_reset(smu);
 492         if (ret)
 493                 dev_info(smu->adev->dev, "smu reset failed, ret = %d\n", ret);
 494
 495         smu->uploading_custom_pp_table = false;
 496
 497         return ret;
 498 }
 499
 500 static int smu_get_driver_allowed_feature_mask(struct smu_context *smu)
 501 {
 502         struct smu_feature *feature = &smu->smu_feature;
 503         uint32_t allowed_feature_mask[SMU_FEATURE_MAX/32];
 504         int ret = 0;
 505
 506         /*
 507          * With SCPM enabled, the allowed featuremasks setting(via
 508          * PPSMC_MSG_SetAllowedFeaturesMaskLow/High) is not permitted.
 509          * That means there is no way to let PMFW knows the settings below.
 510          * Thus, we just assume all the features are allowed under
 511          * such scenario.
 512          */
 513         if (smu->adev->scpm_enabled) {
 514                 bitmap_fill(feature->allowed, SMU_FEATURE_MAX);
 515                 return 0;
 516         }
 517
 518         bitmap_zero(feature->allowed, SMU_FEATURE_MAX);
 519
 520         ret = smu_get_allowed_feature_mask(smu, allowed_feature_mask,
 521                                              SMU_FEATURE_MAX/32);
 522         if (ret)
 523                 return ret;
 524
 525         bitmap_or(feature->allowed, feature->allowed,
 526                       (unsigned long *)allowed_feature_mask,
 527                       feature->feature_num);
 528
 529         return ret;
 530 }
 531
 532 static int smu_set_funcs(struct amdgpu_device *adev)
 533 {
 534         struct smu_context *smu = adev->powerplay.pp_handle;
 535
 536         if (adev->pm.pp_feature & PP_OVERDRIVE_MASK)
 537                 smu->od_enabled = true;
 538
 539         switch (adev->ip_versions[MP1_HWIP][0]) {
 540         case IP_VERSION(11, 0, 0):
 541         case IP_VERSION(11, 0, 5):
 542         case IP_VERSION(11, 0, 9):
 543                 navi10_set_ppt_funcs(smu);
 544                 break;
 545         case IP_VERSION(11, 0, 7):
 546         case IP_VERSION(11, 0, 11):
 547         case IP_VERSION(11, 0, 12):
 548         case IP_VERSION(11, 0, 13):
 549                 sienna_cichlid_set_ppt_funcs(smu);
 550                 break;
 551         case IP_VERSION(12, 0, 0):
 552         case IP_VERSION(12, 0, 1):
 553                 renoir_set_ppt_funcs(smu);
 554                 break;
 555         case IP_VERSION(11, 5, 0):
 556                 vangogh_set_ppt_funcs(smu);
 557                 break;
 558         case IP_VERSION(13, 0, 1):
 559         case IP_VERSION(13, 0, 3):
 560         case IP_VERSION(13, 0, 8):
 561                 yellow_carp_set_ppt_funcs(smu);
 562                 break;
 563         case IP_VERSION(13, 0, 4):
 564                 smu_v13_0_4_set_ppt_funcs(smu);
 565                 break;
 566         case IP_VERSION(13, 0, 5):
 567                 smu_v13_0_5_set_ppt_funcs(smu);
 568                 break;
 569         case IP_VERSION(11, 0, 8):
 570                 cyan_skillfish_set_ppt_funcs(smu);
 571                 break;
 572         case IP_VERSION(11, 0, 2):
 573                 adev->pm.pp_feature &= ~PP_GFXOFF_MASK;
 574                 arcturus_set_ppt_funcs(smu);
 575                 /* OD is not supported on Arcturus */
 576                 smu->od_enabled =false;
 577                 break;
 578         case IP_VERSION(13, 0, 2):
 579                 aldebaran_set_ppt_funcs(smu);
 580                 /* Enable pp_od_clk_voltage node */
 581                 smu->od_enabled = true;
 582                 break;
 583         case IP_VERSION(13, 0, 0):
 584                 smu_v13_0_0_set_ppt_funcs(smu);
 585                 break;
 586         case IP_VERSION(13, 0, 7):
 587                 smu_v13_0_7_set_ppt_funcs(smu);
 588                 break;
 589         default:
 590                 return -EINVAL;
 591         }
 592
 593         return 0;
 594 }
 595
 596 static int smu_early_init(void *handle)
 597 {
 598         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 599         struct smu_context *smu;
 600
 601         smu = kzalloc(sizeof(struct smu_context), GFP_KERNEL);
 602         if (!smu)
 603                 return -ENOMEM;
 604
 605         smu->adev = adev;
 606         smu->pm_enabled = !!amdgpu_dpm;
 607         smu->is_apu = false;
 608         smu->smu_baco.state = SMU_BACO_STATE_EXIT;
 609         smu->smu_baco.platform_support = false;
 610         smu->user_dpm_profile.fan_mode = -1;
 611
 612         mutex_init(&smu->message_lock);
 613
 614         adev->powerplay.pp_handle = smu;
 615         adev->powerplay.pp_funcs = &swsmu_pm_funcs;
 616
 617         return smu_set_funcs(adev);
 618 }
 619
 620 static int smu_set_default_dpm_table(struct smu_context *smu)
 621 {
 622         struct smu_power_context *smu_power = &smu->smu_power;
 623         struct smu_power_gate *power_gate = &smu_power->power_gate;
 624         int vcn_gate, jpeg_gate;
 625         int ret = 0;
 626
 627         if (!smu->ppt_funcs->set_default_dpm_table)
 628                 return 0;
 629
 630         vcn_gate = atomic_read(&power_gate->vcn_gated);
 631         jpeg_gate = atomic_read(&power_gate->jpeg_gated);
 632
 633         ret = smu_dpm_set_vcn_enable(smu, true);
 634         if (ret)
 635                 return ret;
 636
 637         ret = smu_dpm_set_jpeg_enable(smu, true);
 638         if (ret)
 639                 goto err_out;
 640
 641         ret = smu->ppt_funcs->set_default_dpm_table(smu);
 642         if (ret)
 643                 dev_err(smu->adev->dev,
 644                         "Failed to setup default dpm clock tables!\n");
 645
 646         smu_dpm_set_jpeg_enable(smu, !jpeg_gate);
 647 err_out:
 648         smu_dpm_set_vcn_enable(smu, !vcn_gate);
 649         return ret;
 650 }
 651
 652 static int smu_apply_default_config_table_settings(struct smu_context *smu)
 653 {
 654         struct amdgpu_device *adev = smu->adev;
 655         int ret = 0;
 656
 657         ret = smu_get_default_config_table_settings(smu,
 658                                                     &adev->pm.config_table);
 659         if (ret)
 660                 return ret;
 661
 662         return smu_set_config_table(smu, &adev->pm.config_table);
 663 }
 664
 665 static int smu_late_init(void *handle)
 666 {
 667         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 668         struct smu_context *smu = adev->powerplay.pp_handle;
 669         int ret = 0;
 670
 671         smu_set_fine_grain_gfx_freq_parameters(smu);
 672
 673         if (!smu->pm_enabled)
 674                 return 0;
 675
 676         ret = smu_post_init(smu);
 677         if (ret) {
 678                 dev_err(adev->dev, "Failed to post smu init!\n");
 679                 return ret;
 680         }
 681
 682         if ((adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 1)) ||
 683             (adev->ip_versions[MP1_HWIP][0] == IP_VERSION(13, 0, 3)))
 684                 return 0;
 685
 686         if (!amdgpu_sriov_vf(adev) || smu->od_enabled) {
 687                 ret = smu_set_default_od_settings(smu);
 688                 if (ret) {
 689                         dev_err(adev->dev, "Failed to setup default OD settings!\n");
 690                         return ret;
 691                 }
 692         }
 693
 694         ret = smu_populate_umd_state_clk(smu);
 695         if (ret) {
 696                 dev_err(adev->dev, "Failed to populate UMD state clocks!\n");
 697                 return ret;
 698         }
 699
 700         ret = smu_get_asic_power_limits(smu,
 701                                         &smu->current_power_limit,
 702                                         &smu->default_power_limit,
 703                                         &smu->max_power_limit);
 704         if (ret) {
 705                 dev_err(adev->dev, "Failed to get asic power limits!\n");
 706                 return ret;
 707         }
 708
 709         if (!amdgpu_sriov_vf(adev))
 710                 smu_get_unique_id(smu);
 711
 712         smu_get_fan_parameters(smu);
 713
 714         smu_handle_task(smu,
 715                         smu->smu_dpm.dpm_level,
 716                         AMD_PP_TASK_COMPLETE_INIT);
 717
 718         ret = smu_apply_default_config_table_settings(smu);
 719         if (ret && (ret != -EOPNOTSUPP)) {
 720                 dev_err(adev->dev, "Failed to apply default DriverSmuConfig settings!\n");
 721                 return ret;
 722         }
 723
 724         smu_restore_dpm_user_profile(smu);
 725
 726         return 0;
 727 }
 728
 729 static int smu_init_fb_allocations(struct smu_context *smu)
 730 {
 731         struct amdgpu_device *adev = smu->adev;
 732         struct smu_table_context *smu_table = &smu->smu_table;
 733         struct smu_table *tables = smu_table->tables;
 734         struct smu_table *driver_table = &(smu_table->driver_table);
 735         uint32_t max_table_size = 0;
 736         int ret, i;
 737
 738         /* VRAM allocation for tool table */
 739         if (tables[SMU_TABLE_PMSTATUSLOG].size) {
 740                 ret = amdgpu_bo_create_kernel(adev,
 741                                               tables[SMU_TABLE_PMSTATUSLOG].size,
 742                                               tables[SMU_TABLE_PMSTATUSLOG].align,
 743                                               tables[SMU_TABLE_PMSTATUSLOG].domain,
 744                                               &tables[SMU_TABLE_PMSTATUSLOG].bo,
 745                                               &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 746                                               &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 747                 if (ret) {
 748                         dev_err(adev->dev, "VRAM allocation for tool table failed!\n");
 749                         return ret;
 750                 }
 751         }
 752
 753         /* VRAM allocation for driver table */
 754         for (i = 0; i < SMU_TABLE_COUNT; i++) {
 755                 if (tables[i].size == 0)
 756                         continue;
 757
 758                 if (i == SMU_TABLE_PMSTATUSLOG)
 759                         continue;
 760
 761                 if (max_table_size < tables[i].size)
 762                         max_table_size = tables[i].size;
 763         }
 764
 765         driver_table->size = max_table_size;
 766         driver_table->align = PAGE_SIZE;
 767         driver_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
 768
 769         ret = amdgpu_bo_create_kernel(adev,
 770                                       driver_table->size,
 771                                       driver_table->align,
 772                                       driver_table->domain,
 773                                       &driver_table->bo,
 774                                       &driver_table->mc_address,
 775                                       &driver_table->cpu_addr);
 776         if (ret) {
 777                 dev_err(adev->dev, "VRAM allocation for driver table failed!\n");
 778                 if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
 779                         amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
 780                                               &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 781                                               &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 782         }
 783
 784         return ret;
 785 }
 786
 787 static int smu_fini_fb_allocations(struct smu_context *smu)
 788 {
 789         struct smu_table_context *smu_table = &smu->smu_table;
 790         struct smu_table *tables = smu_table->tables;
 791         struct smu_table *driver_table = &(smu_table->driver_table);
 792
 793         if (tables[SMU_TABLE_PMSTATUSLOG].mc_address)
 794                 amdgpu_bo_free_kernel(&tables[SMU_TABLE_PMSTATUSLOG].bo,
 795                                       &tables[SMU_TABLE_PMSTATUSLOG].mc_address,
 796                                       &tables[SMU_TABLE_PMSTATUSLOG].cpu_addr);
 797
 798         amdgpu_bo_free_kernel(&driver_table->bo,
 799                               &driver_table->mc_address,
 800                               &driver_table->cpu_addr);
 801
 802         return 0;
 803 }
 804
 805 /**
 806  * smu_alloc_memory_pool - allocate memory pool in the system memory
 807  *
 808  * @smu: amdgpu_device pointer
 809  *
 810  * This memory pool will be used for SMC use and msg SetSystemVirtualDramAddr
 811  * and DramLogSetDramAddr can notify it changed.
 812  *
 813  * Returns 0 on success, error on failure.
 814  */
 815 static int smu_alloc_memory_pool(struct smu_context *smu)
 816 {
 817         struct amdgpu_device *adev = smu->adev;
 818         struct smu_table_context *smu_table = &smu->smu_table;
 819         struct smu_table *memory_pool = &smu_table->memory_pool;
 820         uint64_t pool_size = smu->pool_size;
 821         int ret = 0;
 822
 823         if (pool_size == SMU_MEMORY_POOL_SIZE_ZERO)
 824                 return ret;
 825
 826         memory_pool->size = pool_size;
 827         memory_pool->align = PAGE_SIZE;
 828         memory_pool->domain = AMDGPU_GEM_DOMAIN_GTT;
 829
 830         switch (pool_size) {
 831         case SMU_MEMORY_POOL_SIZE_256_MB:
 832         case SMU_MEMORY_POOL_SIZE_512_MB:
 833         case SMU_MEMORY_POOL_SIZE_1_GB:
 834         case SMU_MEMORY_POOL_SIZE_2_GB:
 835                 ret = amdgpu_bo_create_kernel(adev,
 836                                               memory_pool->size,
 837                                               memory_pool->align,
 838                                               memory_pool->domain,
 839                                               &memory_pool->bo,
 840                                               &memory_pool->mc_address,
 841                                               &memory_pool->cpu_addr);
 842                 if (ret)
 843                         dev_err(adev->dev, "VRAM allocation for dramlog failed!\n");
 844                 break;
 845         default:
 846                 break;
 847         }
 848
 849         return ret;
 850 }
 851
 852 static int smu_free_memory_pool(struct smu_context *smu)
 853 {
 854         struct smu_table_context *smu_table = &smu->smu_table;
 855         struct smu_table *memory_pool = &smu_table->memory_pool;
 856
 857         if (memory_pool->size == SMU_MEMORY_POOL_SIZE_ZERO)
 858                 return 0;
 859
 860         amdgpu_bo_free_kernel(&memory_pool->bo,
 861                               &memory_pool->mc_address,
 862                               &memory_pool->cpu_addr);
 863
 864         memset(memory_pool, 0, sizeof(struct smu_table));
 865
 866         return 0;
 867 }
 868
 869 static int smu_alloc_dummy_read_table(struct smu_context *smu)
 870 {
 871         struct smu_table_context *smu_table = &smu->smu_table;
 872         struct smu_table *dummy_read_1_table =
 873                         &smu_table->dummy_read_1_table;
 874         struct amdgpu_device *adev = smu->adev;
 875         int ret = 0;
 876
 877         dummy_read_1_table->size = 0x40000;
 878         dummy_read_1_table->align = PAGE_SIZE;
 879         dummy_read_1_table->domain = AMDGPU_GEM_DOMAIN_VRAM;
 880
 881         ret = amdgpu_bo_create_kernel(adev,
 882                                       dummy_read_1_table->size,
 883                                       dummy_read_1_table->align,
 884                                       dummy_read_1_table->domain,
 885                                       &dummy_read_1_table->bo,
 886                                       &dummy_read_1_table->mc_address,
 887                                       &dummy_read_1_table->cpu_addr);
 888         if (ret)
 889                 dev_err(adev->dev, "VRAM allocation for dummy read table failed!\n");
 890
 891         return ret;
 892 }
 893
 894 static void smu_free_dummy_read_table(struct smu_context *smu)
 895 {
 896         struct smu_table_context *smu_table = &smu->smu_table;
 897         struct smu_table *dummy_read_1_table =
 898                         &smu_table->dummy_read_1_table;
 899
 900
 901         amdgpu_bo_free_kernel(&dummy_read_1_table->bo,
 902                               &dummy_read_1_table->mc_address,
 903                               &dummy_read_1_table->cpu_addr);
 904
 905         memset(dummy_read_1_table, 0, sizeof(struct smu_table));
 906 }
 907
 908 static int smu_smc_table_sw_init(struct smu_context *smu)
 909 {
 910         int ret;
 911
 912         /**
 913          * Create smu_table structure, and init smc tables such as
 914          * TABLE_PPTABLE, TABLE_WATERMARKS, TABLE_SMU_METRICS, and etc.
 915          */
 916         ret = smu_init_smc_tables(smu);
 917         if (ret) {
 918                 dev_err(smu->adev->dev, "Failed to init smc tables!\n");
 919                 return ret;
 920         }
 921
 922         /**
 923          * Create smu_power_context structure, and allocate smu_dpm_context and
 924          * context size to fill the smu_power_context data.
 925          */
 926         ret = smu_init_power(smu);
 927         if (ret) {
 928                 dev_err(smu->adev->dev, "Failed to init smu_init_power!\n");
 929                 return ret;
 930         }
 931
 932         /*
 933          * allocate vram bos to store smc table contents.
 934          */
 935         ret = smu_init_fb_allocations(smu);
 936         if (ret)
 937                 return ret;
 938
 939         ret = smu_alloc_memory_pool(smu);
 940         if (ret)
 941                 return ret;
 942
 943         ret = smu_alloc_dummy_read_table(smu);
 944         if (ret)
 945                 return ret;
 946
 947         ret = smu_i2c_init(smu);
 948         if (ret)
 949                 return ret;
 950
 951         return 0;
 952 }
 953
 954 static int smu_smc_table_sw_fini(struct smu_context *smu)
 955 {
 956         int ret;
 957
 958         smu_i2c_fini(smu);
 959
 960         smu_free_dummy_read_table(smu);
 961
 962         ret = smu_free_memory_pool(smu);
 963         if (ret)
 964                 return ret;
 965
 966         ret = smu_fini_fb_allocations(smu);
 967         if (ret)
 968                 return ret;
 969
 970         ret = smu_fini_power(smu);
 971         if (ret) {
 972                 dev_err(smu->adev->dev, "Failed to init smu_fini_power!\n");
 973                 return ret;
 974         }
 975
 976         ret = smu_fini_smc_tables(smu);
 977         if (ret) {
 978                 dev_err(smu->adev->dev, "Failed to smu_fini_smc_tables!\n");
 979                 return ret;
 980         }
 981
 982         return 0;
 983 }
 984
 985 static void smu_throttling_logging_work_fn(struct work_struct *work)
 986 {
 987         struct smu_context *smu = container_of(work, struct smu_context,
 988                                                throttling_logging_work);
 989
 990         smu_log_thermal_throttling(smu);
 991 }
 992
 993 static void smu_interrupt_work_fn(struct work_struct *work)
 994 {
 995         struct smu_context *smu = container_of(work, struct smu_context,
 996                                                interrupt_work);
 997
 998         if (smu->ppt_funcs && smu->ppt_funcs->interrupt_work)
 999                 smu->ppt_funcs->interrupt_work(smu);
1000 }
1001
1002 static int smu_sw_init(void *handle)
1003 {
1004         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1005         struct smu_context *smu = adev->powerplay.pp_handle;
1006         int ret;
1007
1008         smu->pool_size = adev->pm.smu_prv_buffer_size;
1009         smu->smu_feature.feature_num = SMU_FEATURE_MAX;
1010         bitmap_zero(smu->smu_feature.supported, SMU_FEATURE_MAX);
1011         bitmap_zero(smu->smu_feature.allowed, SMU_FEATURE_MAX);
1012
1013         INIT_WORK(&smu->throttling_logging_work, smu_throttling_logging_work_fn);
1014         INIT_WORK(&smu->interrupt_work, smu_interrupt_work_fn);
1015         atomic64_set(&smu->throttle_int_counter, 0);
1016         smu->watermarks_bitmap = 0;
1017         smu->power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1018         smu->default_power_profile_mode = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1019
1020         atomic_set(&smu->smu_power.power_gate.vcn_gated, 1);
1021         atomic_set(&smu->smu_power.power_gate.jpeg_gated, 1);
1022
1023         smu->workload_mask = 1 << smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT];
1024         smu->workload_prority[PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT] = 0;
1025         smu->workload_prority[PP_SMC_POWER_PROFILE_FULLSCREEN3D] = 1;
1026         smu->workload_prority[PP_SMC_POWER_PROFILE_POWERSAVING] = 2;
1027         smu->workload_prority[PP_SMC_POWER_PROFILE_VIDEO] = 3;
1028         smu->workload_prority[PP_SMC_POWER_PROFILE_VR] = 4;
1029         smu->workload_prority[PP_SMC_POWER_PROFILE_COMPUTE] = 5;
1030         smu->workload_prority[PP_SMC_POWER_PROFILE_CUSTOM] = 6;
1031
1032         smu->workload_setting[0] = PP_SMC_POWER_PROFILE_BOOTUP_DEFAULT;
1033         smu->workload_setting[1] = PP_SMC_POWER_PROFILE_FULLSCREEN3D;
1034         smu->workload_setting[2] = PP_SMC_POWER_PROFILE_POWERSAVING;
1035         smu->workload_setting[3] = PP_SMC_POWER_PROFILE_VIDEO;
1036         smu->workload_setting[4] = PP_SMC_POWER_PROFILE_VR;
1037         smu->workload_setting[5] = PP_SMC_POWER_PROFILE_COMPUTE;
1038         smu->workload_setting[6] = PP_SMC_POWER_PROFILE_CUSTOM;
1039         smu->display_config = &adev->pm.pm_display_cfg;
1040
1041         smu->smu_dpm.dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1042         smu->smu_dpm.requested_dpm_level = AMD_DPM_FORCED_LEVEL_AUTO;
1043
1044         ret = smu_init_microcode(smu);
1045         if (ret) {
1046                 dev_err(adev->dev, "Failed to load smu firmware!\n");
1047                 return ret;
1048         }
1049
1050         ret = smu_smc_table_sw_init(smu);
1051         if (ret) {
1052                 dev_err(adev->dev, "Failed to sw init smc table!\n");
1053                 return ret;
1054         }
1055
1056         /* get boot_values from vbios to set revision, gfxclk, and etc. */
1057         ret = smu_get_vbios_bootup_values(smu);
1058         if (ret) {
1059                 dev_err(adev->dev, "Failed to get VBIOS boot clock values!\n");
1060                 return ret;
1061         }
1062
1063         ret = smu_init_pptable_microcode(smu);
1064         if (ret) {
1065                 dev_err(adev->dev, "Failed to setup pptable firmware!\n");
1066                 return ret;
1067         }
1068
1069         ret = smu_register_irq_handler(smu);
1070         if (ret) {
1071                 dev_err(adev->dev, "Failed to register smc irq handler!\n");
1072                 return ret;
1073         }
1074
1075         /* If there is no way to query fan control mode, fan control is not supported */
1076         if (!smu->ppt_funcs->get_fan_control_mode)
1077                 smu->adev->pm.no_fan = true;
1078
1079         return 0;
1080 }
1081
1082 static int smu_sw_fini(void *handle)
1083 {
1084         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1085         struct smu_context *smu = adev->powerplay.pp_handle;
1086         int ret;
1087
1088         ret = smu_smc_table_sw_fini(smu);
1089         if (ret) {
1090                 dev_err(adev->dev, "Failed to sw fini smc table!\n");
1091                 return ret;
1092         }
1093
1094         smu_fini_microcode(smu);
1095
1096         return 0;
1097 }
1098
1099 static int smu_get_thermal_temperature_range(struct smu_context *smu)
1100 {
1101         struct amdgpu_device *adev = smu->adev;
1102         struct smu_temperature_range *range =
1103                                 &smu->thermal_range;
1104         int ret = 0;
1105
1106         if (!smu->ppt_funcs->get_thermal_temperature_range)
1107                 return 0;
1108
1109         ret = smu->ppt_funcs->get_thermal_temperature_range(smu, range);
1110         if (ret)
1111                 return ret;
1112
1113         adev->pm.dpm.thermal.min_temp = range->min;
1114         adev->pm.dpm.thermal.max_temp = range->max;
1115         adev->pm.dpm.thermal.max_edge_emergency_temp = range->edge_emergency_max;
1116         adev->pm.dpm.thermal.min_hotspot_temp = range->hotspot_min;
1117         adev->pm.dpm.thermal.max_hotspot_crit_temp = range->hotspot_crit_max;
1118         adev->pm.dpm.thermal.max_hotspot_emergency_temp = range->hotspot_emergency_max;
1119         adev->pm.dpm.thermal.min_mem_temp = range->mem_min;
1120         adev->pm.dpm.thermal.max_mem_crit_temp = range->mem_crit_max;
1121         adev->pm.dpm.thermal.max_mem_emergency_temp = range->mem_emergency_max;
1122
1123         return ret;
1124 }
1125
1126 static int smu_smc_hw_setup(struct smu_context *smu)
1127 {
1128         struct smu_feature *feature = &smu->smu_feature;
1129         struct amdgpu_device *adev = smu->adev;
1130         uint32_t pcie_gen = 0, pcie_width = 0;
1131         uint64_t features_supported;
1132         int ret = 0;
1133
1134         if (adev->in_suspend && smu_is_dpm_running(smu)) {
1135                 dev_info(adev->dev, "dpm has been enabled\n");
1136                 /* this is needed specifically */
1137                 switch (adev->ip_versions[MP1_HWIP][0]) {
1138                 case IP_VERSION(11, 0, 7):
1139                 case IP_VERSION(11, 0, 11):
1140                 case IP_VERSION(11, 5, 0):
1141                 case IP_VERSION(11, 0, 12):
1142                         ret = smu_system_features_control(smu, true);
1143                         if (ret)
1144                                 dev_err(adev->dev, "Failed system features control!\n");
1145                         break;
1146                 default:
1147                         break;
1148                 }
1149                 return ret;
1150         }
1151
1152         ret = smu_init_display_count(smu, 0);
1153         if (ret) {
1154                 dev_info(adev->dev, "Failed to pre-set display count as 0!\n");
1155                 return ret;
1156         }
1157
1158         ret = smu_set_driver_table_location(smu);
1159         if (ret) {
1160                 dev_err(adev->dev, "Failed to SetDriverDramAddr!\n");
1161                 return ret;
1162         }
1163
1164         /*
1165          * Set PMSTATUSLOG table bo address with SetToolsDramAddr MSG for tools.
1166          */
1167         ret = smu_set_tool_table_location(smu);
1168         if (ret) {
1169                 dev_err(adev->dev, "Failed to SetToolsDramAddr!\n");
1170                 return ret;
1171         }
1172
1173         /*
1174          * Use msg SetSystemVirtualDramAddr and DramLogSetDramAddr can notify
1175          * pool location.
1176          */
1177         ret = smu_notify_memory_pool_location(smu);
1178         if (ret) {
1179                 dev_err(adev->dev, "Failed to SetDramLogDramAddr!\n");
1180                 return ret;
1181         }
1182
1183         ret = smu_setup_pptable(smu);
1184         if (ret) {
1185                 dev_err(adev->dev, "Failed to setup pptable!\n");
1186                 return ret;
1187         }
1188
1189         /* smu_dump_pptable(smu); */
1190
1191         /*
1192          * With SCPM enabled, PSP is responsible for the PPTable transferring
1193          * (to SMU). Driver involvement is not needed and permitted.
1194          */
1195         if (!adev->scpm_enabled) {
1196                 /*
1197                  * Copy pptable bo in the vram to smc with SMU MSGs such as
1198                  * SetDriverDramAddr and TransferTableDram2Smu.
1199                  */
1200                 ret = smu_write_pptable(smu);
1201                 if (ret) {
1202                         dev_err(adev->dev, "Failed to transfer pptable to SMC!\n");
1203                         return ret;
1204                 }
1205         }
1206
1207         /* issue Run*Btc msg */
1208         ret = smu_run_btc(smu);
1209         if (ret)
1210                 return ret;
1211
1212         /*
1213          * With SCPM enabled, these actions(and relevant messages) are
1214          * not needed and permitted.
1215          */
1216         if (!adev->scpm_enabled) {
1217                 ret = smu_feature_set_allowed_mask(smu);
1218                 if (ret) {
1219                         dev_err(adev->dev, "Failed to set driver allowed features mask!\n");
1220                         return ret;
1221                 }
1222         }
1223
1224         ret = smu_system_features_control(smu, true);
1225         if (ret) {
1226                 dev_err(adev->dev, "Failed to enable requested dpm features!\n");
1227                 return ret;
1228         }
1229
1230         ret = smu_feature_get_enabled_mask(smu, &features_supported);
1231         if (ret) {
1232                 dev_err(adev->dev, "Failed to retrieve supported dpm features!\n");
1233                 return ret;
1234         }
1235         bitmap_copy(feature->supported,
1236                     (unsigned long *)&features_supported,
1237                     feature->feature_num);
1238
1239         if (!smu_is_dpm_running(smu))
1240                 dev_info(adev->dev, "dpm has been disabled\n");
1241
1242         /*
1243          * Set initialized values (get from vbios) to dpm tables context such as
1244          * gfxclk, memclk, dcefclk, and etc. And enable the DPM feature for each
1245          * type of clks.
1246          */
1247         ret = smu_set_default_dpm_table(smu);
1248         if (ret) {
1249                 dev_err(adev->dev, "Failed to setup default dpm clock tables!\n");
1250                 return ret;
1251         }
1252
1253         if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4)
1254                 pcie_gen = 3;
1255         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3)
1256                 pcie_gen = 2;
1257         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2)
1258                 pcie_gen = 1;
1259         else if (adev->pm.pcie_gen_mask & CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1)
1260                 pcie_gen = 0;
1261
1262         /* Bit 31:16: LCLK DPM level. 0 is DPM0, and 1 is DPM1
1263          * Bit 15:8:  PCIE GEN, 0 to 3 corresponds to GEN1 to GEN4
1264          * Bit 7:0:   PCIE lane width, 1 to 7 corresponds is x1 to x32
1265          */
1266         if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X16)
1267                 pcie_width = 6;
1268         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X12)
1269                 pcie_width = 5;
1270         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X8)
1271                 pcie_width = 4;
1272         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X4)
1273                 pcie_width = 3;
1274         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X2)
1275                 pcie_width = 2;
1276         else if (adev->pm.pcie_mlw_mask & CAIL_PCIE_LINK_WIDTH_SUPPORT_X1)
1277                 pcie_width = 1;
1278         ret = smu_update_pcie_parameters(smu, pcie_gen, pcie_width);
1279         if (ret) {
1280                 dev_err(adev->dev, "Attempt to override pcie params failed!\n");
1281                 return ret;
1282         }
1283
1284         ret = smu_get_thermal_temperature_range(smu);
1285         if (ret) {
1286                 dev_err(adev->dev, "Failed to get thermal temperature ranges!\n");
1287                 return ret;
1288         }
1289
1290         ret = smu_enable_thermal_alert(smu);
1291         if (ret) {
1292                 dev_err(adev->dev, "Failed to enable thermal alert!\n");
1293                 return ret;
1294         }
1295
1296         ret = smu_notify_display_change(smu);
1297         if (ret) {
1298                 dev_err(adev->dev, "Failed to notify display change!\n");
1299                 return ret;
1300         }
1301
1302         /*
1303          * Set min deep sleep dce fclk with bootup value from vbios via
1304          * SetMinDeepSleepDcefclk MSG.
1305          */
1306         ret = smu_set_min_dcef_deep_sleep(smu,
1307                                           smu->smu_table.boot_values.dcefclk / 100);
1308
1309         return ret;
1310 }
1311
1312 static int smu_start_smc_engine(struct smu_context *smu)
1313 {
1314         struct amdgpu_device *adev = smu->adev;
1315         int ret = 0;
1316
1317         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
1318                 if (adev->ip_versions[MP1_HWIP][0] < IP_VERSION(11, 0, 0)) {
1319                         if (smu->ppt_funcs->load_microcode) {
1320                                 ret = smu->ppt_funcs->load_microcode(smu);
1321                                 if (ret)
1322                                         return ret;
1323                         }
1324                 }
1325         }
1326
1327         if (smu->ppt_funcs->check_fw_status) {
1328                 ret = smu->ppt_funcs->check_fw_status(smu);
1329                 if (ret) {
1330                         dev_err(adev->dev, "SMC is not ready\n");
1331                         return ret;
1332                 }
1333         }
1334
1335         /*
1336          * Send msg GetDriverIfVersion to check if the return value is equal
1337          * with DRIVER_IF_VERSION of smc header.
1338          */
1339         ret = smu_check_fw_version(smu);
1340         if (ret)
1341                 return ret;
1342
1343         return ret;
1344 }
1345
1346 static int smu_hw_init(void *handle)
1347 {
1348         int ret;
1349         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1350         struct smu_context *smu = adev->powerplay.pp_handle;
1351
1352         if (amdgpu_sriov_vf(adev) && !amdgpu_sriov_is_pp_one_vf(adev)) {
1353                 smu->pm_enabled = false;
1354                 return 0;
1355         }
1356
1357         ret = smu_start_smc_engine(smu);
1358         if (ret) {
1359                 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1360                 return ret;
1361         }
1362
1363         if (smu->is_apu) {
1364                 if ((smu->ppt_funcs->set_gfx_power_up_by_imu) &&
1365                                 likely(adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
1366                         ret = smu->ppt_funcs->set_gfx_power_up_by_imu(smu);
1367                         if (ret) {
1368                                 dev_err(adev->dev, "Failed to Enable gfx imu!\n");
1369                                 return ret;
1370                         }
1371                 }
1372
1373                 smu_dpm_set_vcn_enable(smu, true);
1374                 smu_dpm_set_jpeg_enable(smu, true);
1375                 smu_set_gfx_cgpg(smu, true);
1376         }
1377
1378         if (!smu->pm_enabled)
1379                 return 0;
1380
1381         ret = smu_get_driver_allowed_feature_mask(smu);
1382         if (ret)
1383                 return ret;
1384
1385         ret = smu_smc_hw_setup(smu);
1386         if (ret) {
1387                 dev_err(adev->dev, "Failed to setup smc hw!\n");
1388                 return ret;
1389         }
1390
1391         /*
1392          * Move maximum sustainable clock retrieving here considering
1393          * 1. It is not needed on resume(from S3).
1394          * 2. DAL settings come between .hw_init and .late_init of SMU.
1395          *    And DAL needs to know the maximum sustainable clocks. Thus
1396          *    it cannot be put in .late_init().
1397          */
1398         ret = smu_init_max_sustainable_clocks(smu);
1399         if (ret) {
1400                 dev_err(adev->dev, "Failed to init max sustainable clocks!\n");
1401                 return ret;
1402         }
1403
1404         adev->pm.dpm_enabled = true;
1405
1406         dev_info(adev->dev, "SMU is initialized successfully!\n");
1407
1408         return 0;
1409 }
1410
1411 static int smu_disable_dpms(struct smu_context *smu)
1412 {
1413         struct amdgpu_device *adev = smu->adev;
1414         int ret = 0;
1415         bool use_baco = !smu->is_apu &&
1416                 ((amdgpu_in_reset(adev) &&
1417                   (amdgpu_asic_reset_method(adev) == AMD_RESET_METHOD_BACO)) ||
1418                  ((adev->in_runpm || adev->in_s4) && amdgpu_asic_supports_baco(adev)));
1419
1420         /*
1421          * For SMU 13.0.0 and 13.0.7, PMFW will handle the DPM features(disablement or others)
1422          * properly on suspend/reset/unload. Driver involvement may cause some unexpected issues.
1423          */
1424         switch (adev->ip_versions[MP1_HWIP][0]) {
1425         case IP_VERSION(13, 0, 0):
1426         case IP_VERSION(13, 0, 7):
1427                 return 0;
1428         default:
1429                 break;
1430         }
1431
1432         /*
1433          * For custom pptable uploading, skip the DPM features
1434          * disable process on Navi1x ASICs.
1435          *   - As the gfx related features are under control of
1436          *     RLC on those ASICs. RLC reinitialization will be
1437          *     needed to reenable them. That will cost much more
1438          *     efforts.
1439          *
1440          *   - SMU firmware can handle the DPM reenablement
1441          *     properly.
1442          */
1443         if (smu->uploading_custom_pp_table) {
1444                 switch (adev->ip_versions[MP1_HWIP][0]) {
1445                 case IP_VERSION(11, 0, 0):
1446                 case IP_VERSION(11, 0, 5):
1447                 case IP_VERSION(11, 0, 9):
1448                 case IP_VERSION(11, 0, 7):
1449                 case IP_VERSION(11, 0, 11):
1450                 case IP_VERSION(11, 5, 0):
1451                 case IP_VERSION(11, 0, 12):
1452                 case IP_VERSION(11, 0, 13):
1453                         return 0;
1454                 default:
1455                         break;
1456                 }
1457         }
1458
1459         /*
1460          * For Sienna_Cichlid, PMFW will handle the features disablement properly
1461          * on BACO in. Driver involvement is unnecessary.
1462          */
1463         if (use_baco) {
1464                 switch (adev->ip_versions[MP1_HWIP][0]) {
1465                 case IP_VERSION(11, 0, 7):
1466                 case IP_VERSION(11, 0, 0):
1467                 case IP_VERSION(11, 0, 5):
1468                 case IP_VERSION(11, 0, 9):
1469                 case IP_VERSION(13, 0, 7):
1470                         return 0;
1471                 default:
1472                         break;
1473                 }
1474         }
1475
1476         /*
1477          * For gpu reset, runpm and hibernation through BACO,
1478          * BACO feature has to be kept enabled.
1479          */
1480         if (use_baco && smu_feature_is_enabled(smu, SMU_FEATURE_BACO_BIT)) {
1481                 ret = smu_disable_all_features_with_exception(smu,
1482                                                               SMU_FEATURE_BACO_BIT);
1483                 if (ret)
1484                         dev_err(adev->dev, "Failed to disable smu features except BACO.\n");
1485         } else {
1486                 /* DisableAllSmuFeatures message is not permitted with SCPM enabled */
1487                 if (!adev->scpm_enabled) {
1488                         ret = smu_system_features_control(smu, false);
1489                         if (ret)
1490                                 dev_err(adev->dev, "Failed to disable smu features.\n");
1491                 }
1492         }
1493
1494         if (adev->ip_versions[GC_HWIP][0] >= IP_VERSION(9, 4, 2) &&
1495             adev->gfx.rlc.funcs->stop)
1496                 adev->gfx.rlc.funcs->stop(adev);
1497
1498         return ret;
1499 }
1500
1501 static int smu_smc_hw_cleanup(struct smu_context *smu)
1502 {
1503         struct amdgpu_device *adev = smu->adev;
1504         int ret = 0;
1505
1506         cancel_work_sync(&smu->throttling_logging_work);
1507         cancel_work_sync(&smu->interrupt_work);
1508
1509         ret = smu_disable_thermal_alert(smu);
1510         if (ret) {
1511                 dev_err(adev->dev, "Fail to disable thermal alert!\n");
1512                 return ret;
1513         }
1514
1515         ret = smu_disable_dpms(smu);
1516         if (ret) {
1517                 dev_err(adev->dev, "Fail to disable dpm features!\n");
1518                 return ret;
1519         }
1520
1521         return 0;
1522 }
1523
1524 static int smu_hw_fini(void *handle)
1525 {
1526         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1527         struct smu_context *smu = adev->powerplay.pp_handle;
1528
1529         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1530                 return 0;
1531
1532         smu_dpm_set_vcn_enable(smu, false);
1533         smu_dpm_set_jpeg_enable(smu, false);
1534
1535         adev->vcn.cur_state = AMD_PG_STATE_GATE;
1536         adev->jpeg.cur_state = AMD_PG_STATE_GATE;
1537
1538         if (!smu->pm_enabled)
1539                 return 0;
1540
1541         adev->pm.dpm_enabled = false;
1542
1543         return smu_smc_hw_cleanup(smu);
1544 }
1545
1546 static void smu_late_fini(void *handle)
1547 {
1548         struct amdgpu_device *adev = handle;
1549         struct smu_context *smu = adev->powerplay.pp_handle;
1550
1551         kfree(smu);
1552 }
1553
1554 static int smu_reset(struct smu_context *smu)
1555 {
1556         struct amdgpu_device *adev = smu->adev;
1557         int ret;
1558
1559         ret = smu_hw_fini(adev);
1560         if (ret)
1561                 return ret;
1562
1563         ret = smu_hw_init(adev);
1564         if (ret)
1565                 return ret;
1566
1567         ret = smu_late_init(adev);
1568         if (ret)
1569                 return ret;
1570
1571         return 0;
1572 }
1573
1574 static int smu_suspend(void *handle)
1575 {
1576         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1577         struct smu_context *smu = adev->powerplay.pp_handle;
1578         int ret;
1579
1580         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1581                 return 0;
1582
1583         if (!smu->pm_enabled)
1584                 return 0;
1585
1586         adev->pm.dpm_enabled = false;
1587
1588         ret = smu_smc_hw_cleanup(smu);
1589         if (ret)
1590                 return ret;
1591
1592         smu->watermarks_bitmap &= ~(WATERMARKS_LOADED);
1593
1594         smu_set_gfx_cgpg(smu, false);
1595
1596         return 0;
1597 }
1598
1599 static int smu_resume(void *handle)
1600 {
1601         int ret;
1602         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1603         struct smu_context *smu = adev->powerplay.pp_handle;
1604
1605         if (amdgpu_sriov_vf(adev)&& !amdgpu_sriov_is_pp_one_vf(adev))
1606                 return 0;
1607
1608         if (!smu->pm_enabled)
1609                 return 0;
1610
1611         dev_info(adev->dev, "SMU is resuming...\n");
1612
1613         ret = smu_start_smc_engine(smu);
1614         if (ret) {
1615                 dev_err(adev->dev, "SMC engine is not correctly up!\n");
1616                 return ret;
1617         }
1618
1619         ret = smu_smc_hw_setup(smu);
1620         if (ret) {
1621                 dev_err(adev->dev, "Failed to setup smc hw!\n");
1622                 return ret;
1623         }
1624
1625         smu_set_gfx_cgpg(smu, true);
1626
1627         smu->disable_uclk_switch = 0;
1628
1629         adev->pm.dpm_enabled = true;
1630
1631         dev_info(adev->dev, "SMU is resumed successfully!\n");
1632
1633         return 0;
1634 }
1635
1636 static int smu_display_configuration_change(void *handle,
1637                                             const struct amd_pp_display_configuration *display_config)
1638 {
1639         struct smu_context *smu = handle;
1640         int index = 0;
1641         int num_of_active_display = 0;
1642
1643         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1644                 return -EOPNOTSUPP;
1645
1646         if (!display_config)
1647                 return -EINVAL;
1648
1649         smu_set_min_dcef_deep_sleep(smu,
1650                                     display_config->min_dcef_deep_sleep_set_clk / 100);
1651
1652         for (index = 0; index < display_config->num_path_including_non_display; index++) {
1653                 if (display_config->displays[index].controller_id != 0)
1654                         num_of_active_display++;
1655         }
1656
1657         return 0;
1658 }
1659
1660 static int smu_set_clockgating_state(void *handle,
1661                                      enum amd_clockgating_state state)
1662 {
1663         return 0;
1664 }
1665
1666 static int smu_set_powergating_state(void *handle,
1667                                      enum amd_powergating_state state)
1668 {
1669         return 0;
1670 }
1671
1672 static int smu_enable_umd_pstate(void *handle,
1673                       enum amd_dpm_forced_level *level)
1674 {
1675         uint32_t profile_mode_mask = AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD |
1676                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK |
1677                                         AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK |
1678                                         AMD_DPM_FORCED_LEVEL_PROFILE_PEAK;
1679
1680         struct smu_context *smu = (struct smu_context*)(handle);
1681         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1682
1683         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1684                 return -EINVAL;
1685
1686         if (!(smu_dpm_ctx->dpm_level & profile_mode_mask)) {
1687                 /* enter umd pstate, save current level, disable gfx cg*/
1688                 if (*level & profile_mode_mask) {
1689                         smu_dpm_ctx->saved_dpm_level = smu_dpm_ctx->dpm_level;
1690                         smu_gpo_control(smu, false);
1691                         smu_gfx_ulv_control(smu, false);
1692                         smu_deep_sleep_control(smu, false);
1693                         amdgpu_asic_update_umd_stable_pstate(smu->adev, true);
1694                 }
1695         } else {
1696                 /* exit umd pstate, restore level, enable gfx cg*/
1697                 if (!(*level & profile_mode_mask)) {
1698                         if (*level == AMD_DPM_FORCED_LEVEL_PROFILE_EXIT)
1699                                 *level = smu_dpm_ctx->saved_dpm_level;
1700                         amdgpu_asic_update_umd_stable_pstate(smu->adev, false);
1701                         smu_deep_sleep_control(smu, true);
1702                         smu_gfx_ulv_control(smu, true);
1703                         smu_gpo_control(smu, true);
1704                 }
1705         }
1706
1707         return 0;
1708 }
1709
1710 static int smu_bump_power_profile_mode(struct smu_context *smu,
1711                                            long *param,
1712                                            uint32_t param_size)
1713 {
1714         int ret = 0;
1715
1716         if (smu->ppt_funcs->set_power_profile_mode)
1717                 ret = smu->ppt_funcs->set_power_profile_mode(smu, param, param_size);
1718
1719         return ret;
1720 }
1721
1722 static int smu_adjust_power_state_dynamic(struct smu_context *smu,
1723                                    enum amd_dpm_forced_level level,
1724                                    bool skip_display_settings)
1725 {
1726         int ret = 0;
1727         int index = 0;
1728         long workload;
1729         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1730
1731         if (!skip_display_settings) {
1732                 ret = smu_display_config_changed(smu);
1733                 if (ret) {
1734                         dev_err(smu->adev->dev, "Failed to change display config!");
1735                         return ret;
1736                 }
1737         }
1738
1739         ret = smu_apply_clocks_adjust_rules(smu);
1740         if (ret) {
1741                 dev_err(smu->adev->dev, "Failed to apply clocks adjust rules!");
1742                 return ret;
1743         }
1744
1745         if (!skip_display_settings) {
1746                 ret = smu_notify_smc_display_config(smu);
1747                 if (ret) {
1748                         dev_err(smu->adev->dev, "Failed to notify smc display config!");
1749                         return ret;
1750                 }
1751         }
1752
1753         if (smu_dpm_ctx->dpm_level != level) {
1754                 ret = smu_asic_set_performance_level(smu, level);
1755                 if (ret) {
1756                         dev_err(smu->adev->dev, "Failed to set performance level!");
1757                         return ret;
1758                 }
1759
1760                 /* update the saved copy */
1761                 smu_dpm_ctx->dpm_level = level;
1762         }
1763
1764         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
1765                 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM) {
1766                 index = fls(smu->workload_mask);
1767                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1768                 workload = smu->workload_setting[index];
1769
1770                 if (smu->power_profile_mode != workload)
1771                         smu_bump_power_profile_mode(smu, &workload, 0);
1772         }
1773
1774         return ret;
1775 }
1776
1777 static int smu_handle_task(struct smu_context *smu,
1778                            enum amd_dpm_forced_level level,
1779                            enum amd_pp_task task_id)
1780 {
1781         int ret = 0;
1782
1783         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1784                 return -EOPNOTSUPP;
1785
1786         switch (task_id) {
1787         case AMD_PP_TASK_DISPLAY_CONFIG_CHANGE:
1788                 ret = smu_pre_display_config_changed(smu);
1789                 if (ret)
1790                         return ret;
1791                 ret = smu_adjust_power_state_dynamic(smu, level, false);
1792                 break;
1793         case AMD_PP_TASK_COMPLETE_INIT:
1794         case AMD_PP_TASK_READJUST_POWER_STATE:
1795                 ret = smu_adjust_power_state_dynamic(smu, level, true);
1796                 break;
1797         default:
1798                 break;
1799         }
1800
1801         return ret;
1802 }
1803
1804 static int smu_handle_dpm_task(void *handle,
1805                                enum amd_pp_task task_id,
1806                                enum amd_pm_state_type *user_state)
1807 {
1808         struct smu_context *smu = handle;
1809         struct smu_dpm_context *smu_dpm = &smu->smu_dpm;
1810
1811         return smu_handle_task(smu, smu_dpm->dpm_level, task_id);
1812
1813 }
1814
1815 static int smu_switch_power_profile(void *handle,
1816                                     enum PP_SMC_POWER_PROFILE type,
1817                                     bool en)
1818 {
1819         struct smu_context *smu = handle;
1820         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1821         long workload;
1822         uint32_t index;
1823
1824         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1825                 return -EOPNOTSUPP;
1826
1827         if (!(type < PP_SMC_POWER_PROFILE_CUSTOM))
1828                 return -EINVAL;
1829
1830         if (!en) {
1831                 smu->workload_mask &= ~(1 << smu->workload_prority[type]);
1832                 index = fls(smu->workload_mask);
1833                 index = index > 0 && index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1834                 workload = smu->workload_setting[index];
1835         } else {
1836                 smu->workload_mask |= (1 << smu->workload_prority[type]);
1837                 index = fls(smu->workload_mask);
1838                 index = index <= WORKLOAD_POLICY_MAX ? index - 1 : 0;
1839                 workload = smu->workload_setting[index];
1840         }
1841
1842         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL &&
1843                 smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_PERF_DETERMINISM)
1844                 smu_bump_power_profile_mode(smu, &workload, 0);
1845
1846         return 0;
1847 }
1848
1849 static enum amd_dpm_forced_level smu_get_performance_level(void *handle)
1850 {
1851         struct smu_context *smu = handle;
1852         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1853
1854         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1855                 return -EOPNOTSUPP;
1856
1857         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1858                 return -EINVAL;
1859
1860         return smu_dpm_ctx->dpm_level;
1861 }
1862
1863 static int smu_force_performance_level(void *handle,
1864                                        enum amd_dpm_forced_level level)
1865 {
1866         struct smu_context *smu = handle;
1867         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1868         int ret = 0;
1869
1870         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1871                 return -EOPNOTSUPP;
1872
1873         if (!smu->is_apu && !smu_dpm_ctx->dpm_context)
1874                 return -EINVAL;
1875
1876         ret = smu_enable_umd_pstate(smu, &level);
1877         if (ret)
1878                 return ret;
1879
1880         ret = smu_handle_task(smu, level,
1881                               AMD_PP_TASK_READJUST_POWER_STATE);
1882
1883         /* reset user dpm clock state */
1884         if (!ret && smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1885                 memset(smu->user_dpm_profile.clk_mask, 0, sizeof(smu->user_dpm_profile.clk_mask));
1886                 smu->user_dpm_profile.clk_dependency = 0;
1887         }
1888
1889         return ret;
1890 }
1891
1892 static int smu_set_display_count(void *handle, uint32_t count)
1893 {
1894         struct smu_context *smu = handle;
1895
1896         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1897                 return -EOPNOTSUPP;
1898
1899         return smu_init_display_count(smu, count);
1900 }
1901
1902 static int smu_force_smuclk_levels(struct smu_context *smu,
1903                          enum smu_clk_type clk_type,
1904                          uint32_t mask)
1905 {
1906         struct smu_dpm_context *smu_dpm_ctx = &(smu->smu_dpm);
1907         int ret = 0;
1908
1909         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1910                 return -EOPNOTSUPP;
1911
1912         if (smu_dpm_ctx->dpm_level != AMD_DPM_FORCED_LEVEL_MANUAL) {
1913                 dev_dbg(smu->adev->dev, "force clock level is for dpm manual mode only.\n");
1914                 return -EINVAL;
1915         }
1916
1917         if (smu->ppt_funcs && smu->ppt_funcs->force_clk_levels) {
1918                 ret = smu->ppt_funcs->force_clk_levels(smu, clk_type, mask);
1919                 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
1920                         smu->user_dpm_profile.clk_mask[clk_type] = mask;
1921                         smu_set_user_clk_dependencies(smu, clk_type);
1922                 }
1923         }
1924
1925         return ret;
1926 }
1927
1928 static int smu_force_ppclk_levels(void *handle,
1929                                   enum pp_clock_type type,
1930                                   uint32_t mask)
1931 {
1932         struct smu_context *smu = handle;
1933         enum smu_clk_type clk_type;
1934
1935         switch (type) {
1936         case PP_SCLK:
1937                 clk_type = SMU_SCLK; break;
1938         case PP_MCLK:
1939                 clk_type = SMU_MCLK; break;
1940         case PP_PCIE:
1941                 clk_type = SMU_PCIE; break;
1942         case PP_SOCCLK:
1943                 clk_type = SMU_SOCCLK; break;
1944         case PP_FCLK:
1945                 clk_type = SMU_FCLK; break;
1946         case PP_DCEFCLK:
1947                 clk_type = SMU_DCEFCLK; break;
1948         case PP_VCLK:
1949                 clk_type = SMU_VCLK; break;
1950         case PP_DCLK:
1951                 clk_type = SMU_DCLK; break;
1952         case OD_SCLK:
1953                 clk_type = SMU_OD_SCLK; break;
1954         case OD_MCLK:
1955                 clk_type = SMU_OD_MCLK; break;
1956         case OD_VDDC_CURVE:
1957                 clk_type = SMU_OD_VDDC_CURVE; break;
1958         case OD_RANGE:
1959                 clk_type = SMU_OD_RANGE; break;
1960         default:
1961                 return -EINVAL;
1962         }
1963
1964         return smu_force_smuclk_levels(smu, clk_type, mask);
1965 }
1966
1967 /*
1968  * On system suspending or resetting, the dpm_enabled
1969  * flag will be cleared. So that those SMU services which
1970  * are not supported will be gated.
1971  * However, the mp1 state setting should still be granted
1972  * even if the dpm_enabled cleared.
1973  */
1974 static int smu_set_mp1_state(void *handle,
1975                              enum pp_mp1_state mp1_state)
1976 {
1977         struct smu_context *smu = handle;
1978         int ret = 0;
1979
1980         if (!smu->pm_enabled)
1981                 return -EOPNOTSUPP;
1982
1983         if (smu->ppt_funcs &&
1984             smu->ppt_funcs->set_mp1_state)
1985                 ret = smu->ppt_funcs->set_mp1_state(smu, mp1_state);
1986
1987         return ret;
1988 }
1989
1990 static int smu_set_df_cstate(void *handle,
1991                              enum pp_df_cstate state)
1992 {
1993         struct smu_context *smu = handle;
1994         int ret = 0;
1995
1996         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
1997                 return -EOPNOTSUPP;
1998
1999         if (!smu->ppt_funcs || !smu->ppt_funcs->set_df_cstate)
2000                 return 0;
2001
2002         ret = smu->ppt_funcs->set_df_cstate(smu, state);
2003         if (ret)
2004                 dev_err(smu->adev->dev, "[SetDfCstate] failed!\n");
2005
2006         return ret;
2007 }
2008
2009 int smu_allow_xgmi_power_down(struct smu_context *smu, bool en)
2010 {
2011         int ret = 0;
2012
2013         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2014                 return -EOPNOTSUPP;
2015
2016         if (!smu->ppt_funcs || !smu->ppt_funcs->allow_xgmi_power_down)
2017                 return 0;
2018
2019         ret = smu->ppt_funcs->allow_xgmi_power_down(smu, en);
2020         if (ret)
2021                 dev_err(smu->adev->dev, "[AllowXgmiPowerDown] failed!\n");
2022
2023         return ret;
2024 }
2025
2026 int smu_write_watermarks_table(struct smu_context *smu)
2027 {
2028         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2029                 return -EOPNOTSUPP;
2030
2031         return smu_set_watermarks_table(smu, NULL);
2032 }
2033
2034 static int smu_set_watermarks_for_clock_ranges(void *handle,
2035                                                struct pp_smu_wm_range_sets *clock_ranges)
2036 {
2037         struct smu_context *smu = handle;
2038
2039         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2040                 return -EOPNOTSUPP;
2041
2042         if (smu->disable_watermark)
2043                 return 0;
2044
2045         return smu_set_watermarks_table(smu, clock_ranges);
2046 }
2047
2048 int smu_set_ac_dc(struct smu_context *smu)
2049 {
2050         int ret = 0;
2051
2052         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2053                 return -EOPNOTSUPP;
2054
2055         /* controlled by firmware */
2056         if (smu->dc_controlled_by_gpio)
2057                 return 0;
2058
2059         ret = smu_set_power_source(smu,
2060                                    smu->adev->pm.ac_power ? SMU_POWER_SOURCE_AC :
2061                                    SMU_POWER_SOURCE_DC);
2062         if (ret)
2063                 dev_err(smu->adev->dev, "Failed to switch to %s mode!\n",
2064                        smu->adev->pm.ac_power ? "AC" : "DC");
2065
2066         return ret;
2067 }
2068
2069 const struct amd_ip_funcs smu_ip_funcs = {
2070         .name = "smu",
2071         .early_init = smu_early_init,
2072         .late_init = smu_late_init,
2073         .sw_init = smu_sw_init,
2074         .sw_fini = smu_sw_fini,
2075         .hw_init = smu_hw_init,
2076         .hw_fini = smu_hw_fini,
2077         .late_fini = smu_late_fini,
2078         .suspend = smu_suspend,
2079         .resume = smu_resume,
2080         .is_idle = NULL,
2081         .check_soft_reset = NULL,
2082         .wait_for_idle = NULL,
2083         .soft_reset = NULL,
2084         .set_clockgating_state = smu_set_clockgating_state,
2085         .set_powergating_state = smu_set_powergating_state,
2086 };
2087
2088 const struct amdgpu_ip_block_version smu_v11_0_ip_block =
2089 {
2090         .type = AMD_IP_BLOCK_TYPE_SMC,
2091         .major = 11,
2092         .minor = 0,
2093         .rev = 0,
2094         .funcs = &smu_ip_funcs,
2095 };
2096
2097 const struct amdgpu_ip_block_version smu_v12_0_ip_block =
2098 {
2099         .type = AMD_IP_BLOCK_TYPE_SMC,
2100         .major = 12,
2101         .minor = 0,
2102         .rev = 0,
2103         .funcs = &smu_ip_funcs,
2104 };
2105
2106 const struct amdgpu_ip_block_version smu_v13_0_ip_block =
2107 {
2108         .type = AMD_IP_BLOCK_TYPE_SMC,
2109         .major = 13,
2110         .minor = 0,
2111         .rev = 0,
2112         .funcs = &smu_ip_funcs,
2113 };
2114
2115 static int smu_load_microcode(void *handle)
2116 {
2117         struct smu_context *smu = handle;
2118         struct amdgpu_device *adev = smu->adev;
2119         int ret = 0;
2120
2121         if (!smu->pm_enabled)
2122                 return -EOPNOTSUPP;
2123
2124         /* This should be used for non PSP loading */
2125         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
2126                 return 0;
2127
2128         if (smu->ppt_funcs->load_microcode) {
2129                 ret = smu->ppt_funcs->load_microcode(smu);
2130                 if (ret) {
2131                         dev_err(adev->dev, "Load microcode failed\n");
2132                         return ret;
2133                 }
2134         }
2135
2136         if (smu->ppt_funcs->check_fw_status) {
2137                 ret = smu->ppt_funcs->check_fw_status(smu);
2138                 if (ret) {
2139                         dev_err(adev->dev, "SMC is not ready\n");
2140                         return ret;
2141                 }
2142         }
2143
2144         return ret;
2145 }
2146
2147 static int smu_set_gfx_cgpg(struct smu_context *smu, bool enabled)
2148 {
2149         int ret = 0;
2150
2151         if (smu->ppt_funcs->set_gfx_cgpg)
2152                 ret = smu->ppt_funcs->set_gfx_cgpg(smu, enabled);
2153
2154         return ret;
2155 }
2156
2157 static int smu_set_fan_speed_rpm(void *handle, uint32_t speed)
2158 {
2159         struct smu_context *smu = handle;
2160         int ret = 0;
2161
2162         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2163                 return -EOPNOTSUPP;
2164
2165         if (!smu->ppt_funcs->set_fan_speed_rpm)
2166                 return -EOPNOTSUPP;
2167
2168         if (speed == U32_MAX)
2169                 return -EINVAL;
2170
2171         ret = smu->ppt_funcs->set_fan_speed_rpm(smu, speed);
2172         if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2173                 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_RPM;
2174                 smu->user_dpm_profile.fan_speed_rpm = speed;
2175
2176                 /* Override custom PWM setting as they cannot co-exist */
2177                 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_PWM;
2178                 smu->user_dpm_profile.fan_speed_pwm = 0;
2179         }
2180
2181         return ret;
2182 }
2183
2184 /**
2185  * smu_get_power_limit - Request one of the SMU Power Limits
2186  *
2187  * @handle: pointer to smu context
2188  * @limit: requested limit is written back to this variable
2189  * @pp_limit_level: &pp_power_limit_level which limit of the power to return
2190  * @pp_power_type: &pp_power_type type of power
2191  * Return:  0 on success, <0 on error
2192  *
2193  */
2194 int smu_get_power_limit(void *handle,
2195                         uint32_t *limit,
2196                         enum pp_power_limit_level pp_limit_level,
2197                         enum pp_power_type pp_power_type)
2198 {
2199         struct smu_context *smu = handle;
2200         struct amdgpu_device *adev = smu->adev;
2201         enum smu_ppt_limit_level limit_level;
2202         uint32_t limit_type;
2203         int ret = 0;
2204
2205         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2206                 return -EOPNOTSUPP;
2207
2208         switch(pp_power_type) {
2209         case PP_PWR_TYPE_SUSTAINED:
2210                 limit_type = SMU_DEFAULT_PPT_LIMIT;
2211                 break;
2212         case PP_PWR_TYPE_FAST:
2213                 limit_type = SMU_FAST_PPT_LIMIT;
2214                 break;
2215         default:
2216                 return -EOPNOTSUPP;
2217                 break;
2218         }
2219
2220         switch(pp_limit_level){
2221         case PP_PWR_LIMIT_CURRENT:
2222                 limit_level = SMU_PPT_LIMIT_CURRENT;
2223                 break;
2224         case PP_PWR_LIMIT_DEFAULT:
2225                 limit_level = SMU_PPT_LIMIT_DEFAULT;
2226                 break;
2227         case PP_PWR_LIMIT_MAX:
2228                 limit_level = SMU_PPT_LIMIT_MAX;
2229                 break;
2230         case PP_PWR_LIMIT_MIN:
2231         default:
2232                 return -EOPNOTSUPP;
2233                 break;
2234         }
2235
2236         if (limit_type != SMU_DEFAULT_PPT_LIMIT) {
2237                 if (smu->ppt_funcs->get_ppt_limit)
2238                         ret = smu->ppt_funcs->get_ppt_limit(smu, limit, limit_type, limit_level);
2239         } else {
2240                 switch (limit_level) {
2241                 case SMU_PPT_LIMIT_CURRENT:
2242                         switch (adev->ip_versions[MP1_HWIP][0]) {
2243                         case IP_VERSION(13, 0, 2):
2244                         case IP_VERSION(11, 0, 7):
2245                         case IP_VERSION(11, 0, 11):
2246                         case IP_VERSION(11, 0, 12):
2247                         case IP_VERSION(11, 0, 13):
2248                                 ret = smu_get_asic_power_limits(smu,
2249                                                                 &smu->current_power_limit,
2250                                                                 NULL,
2251                                                                 NULL);
2252                                 break;
2253                         default:
2254                                 break;
2255                         }
2256                         *limit = smu->current_power_limit;
2257                         break;
2258                 case SMU_PPT_LIMIT_DEFAULT:
2259                         *limit = smu->default_power_limit;
2260                         break;
2261                 case SMU_PPT_LIMIT_MAX:
2262                         *limit = smu->max_power_limit;
2263                         break;
2264                 default:
2265                         break;
2266                 }
2267         }
2268
2269         return ret;
2270 }
2271
2272 static int smu_set_power_limit(void *handle, uint32_t limit)
2273 {
2274         struct smu_context *smu = handle;
2275         uint32_t limit_type = limit >> 24;
2276         int ret = 0;
2277
2278         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2279                 return -EOPNOTSUPP;
2280
2281         limit &= (1<<24)-1;
2282         if (limit_type != SMU_DEFAULT_PPT_LIMIT)
2283                 if (smu->ppt_funcs->set_power_limit)
2284                         return smu->ppt_funcs->set_power_limit(smu, limit_type, limit);
2285
2286         if (limit > smu->max_power_limit) {
2287                 dev_err(smu->adev->dev,
2288                         "New power limit (%d) is over the max allowed %d\n",
2289                         limit, smu->max_power_limit);
2290                 return -EINVAL;
2291         }
2292
2293         if (!limit)
2294                 limit = smu->current_power_limit;
2295
2296         if (smu->ppt_funcs->set_power_limit) {
2297                 ret = smu->ppt_funcs->set_power_limit(smu, limit_type, limit);
2298                 if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE))
2299                         smu->user_dpm_profile.power_limit = limit;
2300         }
2301
2302         return ret;
2303 }
2304
2305 static int smu_print_smuclk_levels(struct smu_context *smu, enum smu_clk_type clk_type, char *buf)
2306 {
2307         int ret = 0;
2308
2309         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2310                 return -EOPNOTSUPP;
2311
2312         if (smu->ppt_funcs->print_clk_levels)
2313                 ret = smu->ppt_funcs->print_clk_levels(smu, clk_type, buf);
2314
2315         return ret;
2316 }
2317
2318 static enum smu_clk_type smu_convert_to_smuclk(enum pp_clock_type type)
2319 {
2320         enum smu_clk_type clk_type;
2321
2322         switch (type) {
2323         case PP_SCLK:
2324                 clk_type = SMU_SCLK; break;
2325         case PP_MCLK:
2326                 clk_type = SMU_MCLK; break;
2327         case PP_PCIE:
2328                 clk_type = SMU_PCIE; break;
2329         case PP_SOCCLK:
2330                 clk_type = SMU_SOCCLK; break;
2331         case PP_FCLK:
2332                 clk_type = SMU_FCLK; break;
2333         case PP_DCEFCLK:
2334                 clk_type = SMU_DCEFCLK; break;
2335         case PP_VCLK:
2336                 clk_type = SMU_VCLK; break;
2337         case PP_DCLK:
2338                 clk_type = SMU_DCLK; break;
2339         case OD_SCLK:
2340                 clk_type = SMU_OD_SCLK; break;
2341         case OD_MCLK:
2342                 clk_type = SMU_OD_MCLK; break;
2343         case OD_VDDC_CURVE:
2344                 clk_type = SMU_OD_VDDC_CURVE; break;
2345         case OD_RANGE:
2346                 clk_type = SMU_OD_RANGE; break;
2347         case OD_VDDGFX_OFFSET:
2348                 clk_type = SMU_OD_VDDGFX_OFFSET; break;
2349         case OD_CCLK:
2350                 clk_type = SMU_OD_CCLK; break;
2351         default:
2352                 clk_type = SMU_CLK_COUNT; break;
2353         }
2354
2355         return clk_type;
2356 }
2357
2358 static int smu_print_ppclk_levels(void *handle,
2359                                   enum pp_clock_type type,
2360                                   char *buf)
2361 {
2362         struct smu_context *smu = handle;
2363         enum smu_clk_type clk_type;
2364
2365         clk_type = smu_convert_to_smuclk(type);
2366         if (clk_type == SMU_CLK_COUNT)
2367                 return -EINVAL;
2368
2369         return smu_print_smuclk_levels(smu, clk_type, buf);
2370 }
2371
2372 static int smu_emit_ppclk_levels(void *handle, enum pp_clock_type type, char *buf, int *offset)
2373 {
2374         struct smu_context *smu = handle;
2375         enum smu_clk_type clk_type;
2376
2377         clk_type = smu_convert_to_smuclk(type);
2378         if (clk_type == SMU_CLK_COUNT)
2379                 return -EINVAL;
2380
2381         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2382                 return -EOPNOTSUPP;
2383
2384         if (!smu->ppt_funcs->emit_clk_levels)
2385                 return -ENOENT;
2386
2387         return smu->ppt_funcs->emit_clk_levels(smu, clk_type, buf, offset);
2388
2389 }
2390
2391 static int smu_od_edit_dpm_table(void *handle,
2392                                  enum PP_OD_DPM_TABLE_COMMAND type,
2393                                  long *input, uint32_t size)
2394 {
2395         struct smu_context *smu = handle;
2396         int ret = 0;
2397
2398         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2399                 return -EOPNOTSUPP;
2400
2401         if (smu->ppt_funcs->od_edit_dpm_table) {
2402                 ret = smu->ppt_funcs->od_edit_dpm_table(smu, type, input, size);
2403         }
2404
2405         return ret;
2406 }
2407
2408 static int smu_read_sensor(void *handle,
2409                            int sensor,
2410                            void *data,
2411                            int *size_arg)
2412 {
2413         struct smu_context *smu = handle;
2414         struct smu_umd_pstate_table *pstate_table =
2415                                 &smu->pstate_table;
2416         int ret = 0;
2417         uint32_t *size, size_val;
2418
2419         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2420                 return -EOPNOTSUPP;
2421
2422         if (!data || !size_arg)
2423                 return -EINVAL;
2424
2425         size_val = *size_arg;
2426         size = &size_val;
2427
2428         if (smu->ppt_funcs->read_sensor)
2429                 if (!smu->ppt_funcs->read_sensor(smu, sensor, data, size))
2430                         goto unlock;
2431
2432         switch (sensor) {
2433         case AMDGPU_PP_SENSOR_STABLE_PSTATE_SCLK:
2434                 *((uint32_t *)data) = pstate_table->gfxclk_pstate.standard * 100;
2435                 *size = 4;
2436                 break;
2437         case AMDGPU_PP_SENSOR_STABLE_PSTATE_MCLK:
2438                 *((uint32_t *)data) = pstate_table->uclk_pstate.standard * 100;
2439                 *size = 4;
2440                 break;
2441         case AMDGPU_PP_SENSOR_ENABLED_SMC_FEATURES_MASK:
2442                 ret = smu_feature_get_enabled_mask(smu, (uint64_t *)data);
2443                 *size = 8;
2444                 break;
2445         case AMDGPU_PP_SENSOR_UVD_POWER:
2446                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_UVD_BIT) ? 1 : 0;
2447                 *size = 4;
2448                 break;
2449         case AMDGPU_PP_SENSOR_VCE_POWER:
2450                 *(uint32_t *)data = smu_feature_is_enabled(smu, SMU_FEATURE_DPM_VCE_BIT) ? 1 : 0;
2451                 *size = 4;
2452                 break;
2453         case AMDGPU_PP_SENSOR_VCN_POWER_STATE:
2454                 *(uint32_t *)data = atomic_read(&smu->smu_power.power_gate.vcn_gated) ? 0: 1;
2455                 *size = 4;
2456                 break;
2457         case AMDGPU_PP_SENSOR_MIN_FAN_RPM:
2458                 *(uint32_t *)data = 0;
2459                 *size = 4;
2460                 break;
2461         default:
2462                 *size = 0;
2463                 ret = -EOPNOTSUPP;
2464                 break;
2465         }
2466
2467 unlock:
2468         // assign uint32_t to int
2469         *size_arg = size_val;
2470
2471         return ret;
2472 }
2473
2474 static int smu_get_power_profile_mode(void *handle, char *buf)
2475 {
2476         struct smu_context *smu = handle;
2477
2478         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled ||
2479             !smu->ppt_funcs->get_power_profile_mode)
2480                 return -EOPNOTSUPP;
2481         if (!buf)
2482                 return -EINVAL;
2483
2484         return smu->ppt_funcs->get_power_profile_mode(smu, buf);
2485 }
2486
2487 static int smu_set_power_profile_mode(void *handle,
2488                                       long *param,
2489                                       uint32_t param_size)
2490 {
2491         struct smu_context *smu = handle;
2492
2493         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled ||
2494             !smu->ppt_funcs->set_power_profile_mode)
2495                 return -EOPNOTSUPP;
2496
2497         return smu_bump_power_profile_mode(smu, param, param_size);
2498 }
2499
2500 static int smu_get_fan_control_mode(void *handle, u32 *fan_mode)
2501 {
2502         struct smu_context *smu = handle;
2503
2504         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2505                 return -EOPNOTSUPP;
2506
2507         if (!smu->ppt_funcs->get_fan_control_mode)
2508                 return -EOPNOTSUPP;
2509
2510         if (!fan_mode)
2511                 return -EINVAL;
2512
2513         *fan_mode = smu->ppt_funcs->get_fan_control_mode(smu);
2514
2515         return 0;
2516 }
2517
2518 static int smu_set_fan_control_mode(void *handle, u32 value)
2519 {
2520         struct smu_context *smu = handle;
2521         int ret = 0;
2522
2523         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2524                 return -EOPNOTSUPP;
2525
2526         if (!smu->ppt_funcs->set_fan_control_mode)
2527                 return -EOPNOTSUPP;
2528
2529         if (value == U32_MAX)
2530                 return -EINVAL;
2531
2532         ret = smu->ppt_funcs->set_fan_control_mode(smu, value);
2533         if (ret)
2534                 goto out;
2535
2536         if (!(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2537                 smu->user_dpm_profile.fan_mode = value;
2538
2539                 /* reset user dpm fan speed */
2540                 if (value != AMD_FAN_CTRL_MANUAL) {
2541                         smu->user_dpm_profile.fan_speed_pwm = 0;
2542                         smu->user_dpm_profile.fan_speed_rpm = 0;
2543                         smu->user_dpm_profile.flags &= ~(SMU_CUSTOM_FAN_SPEED_RPM | SMU_CUSTOM_FAN_SPEED_PWM);
2544                 }
2545         }
2546
2547 out:
2548         return ret;
2549 }
2550
2551 static int smu_get_fan_speed_pwm(void *handle, u32 *speed)
2552 {
2553         struct smu_context *smu = handle;
2554         int ret = 0;
2555
2556         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2557                 return -EOPNOTSUPP;
2558
2559         if (!smu->ppt_funcs->get_fan_speed_pwm)
2560                 return -EOPNOTSUPP;
2561
2562         if (!speed)
2563                 return -EINVAL;
2564
2565         ret = smu->ppt_funcs->get_fan_speed_pwm(smu, speed);
2566
2567         return ret;
2568 }
2569
2570 static int smu_set_fan_speed_pwm(void *handle, u32 speed)
2571 {
2572         struct smu_context *smu = handle;
2573         int ret = 0;
2574
2575         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2576                 return -EOPNOTSUPP;
2577
2578         if (!smu->ppt_funcs->set_fan_speed_pwm)
2579                 return -EOPNOTSUPP;
2580
2581         if (speed == U32_MAX)
2582                 return -EINVAL;
2583
2584         ret = smu->ppt_funcs->set_fan_speed_pwm(smu, speed);
2585         if (!ret && !(smu->user_dpm_profile.flags & SMU_DPM_USER_PROFILE_RESTORE)) {
2586                 smu->user_dpm_profile.flags |= SMU_CUSTOM_FAN_SPEED_PWM;
2587                 smu->user_dpm_profile.fan_speed_pwm = speed;
2588
2589                 /* Override custom RPM setting as they cannot co-exist */
2590                 smu->user_dpm_profile.flags &= ~SMU_CUSTOM_FAN_SPEED_RPM;
2591                 smu->user_dpm_profile.fan_speed_rpm = 0;
2592         }
2593
2594         return ret;
2595 }
2596
2597 static int smu_get_fan_speed_rpm(void *handle, uint32_t *speed)
2598 {
2599         struct smu_context *smu = handle;
2600         int ret = 0;
2601
2602         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2603                 return -EOPNOTSUPP;
2604
2605         if (!smu->ppt_funcs->get_fan_speed_rpm)
2606                 return -EOPNOTSUPP;
2607
2608         if (!speed)
2609                 return -EINVAL;
2610
2611         ret = smu->ppt_funcs->get_fan_speed_rpm(smu, speed);
2612
2613         return ret;
2614 }
2615
2616 static int smu_set_deep_sleep_dcefclk(void *handle, uint32_t clk)
2617 {
2618         struct smu_context *smu = handle;
2619
2620         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2621                 return -EOPNOTSUPP;
2622
2623         return smu_set_min_dcef_deep_sleep(smu, clk);
2624 }
2625
2626 static int smu_get_clock_by_type_with_latency(void *handle,
2627                                               enum amd_pp_clock_type type,
2628                                               struct pp_clock_levels_with_latency *clocks)
2629 {
2630         struct smu_context *smu = handle;
2631         enum smu_clk_type clk_type;
2632         int ret = 0;
2633
2634         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2635                 return -EOPNOTSUPP;
2636
2637         if (smu->ppt_funcs->get_clock_by_type_with_latency) {
2638                 switch (type) {
2639                 case amd_pp_sys_clock:
2640                         clk_type = SMU_GFXCLK;
2641                         break;
2642                 case amd_pp_mem_clock:
2643                         clk_type = SMU_MCLK;
2644                         break;
2645                 case amd_pp_dcef_clock:
2646                         clk_type = SMU_DCEFCLK;
2647                         break;
2648                 case amd_pp_disp_clock:
2649                         clk_type = SMU_DISPCLK;
2650                         break;
2651                 default:
2652                         dev_err(smu->adev->dev, "Invalid clock type!\n");
2653                         return -EINVAL;
2654                 }
2655
2656                 ret = smu->ppt_funcs->get_clock_by_type_with_latency(smu, clk_type, clocks);
2657         }
2658
2659         return ret;
2660 }
2661
2662 static int smu_display_clock_voltage_request(void *handle,
2663                                              struct pp_display_clock_request *clock_req)
2664 {
2665         struct smu_context *smu = handle;
2666         int ret = 0;
2667
2668         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2669                 return -EOPNOTSUPP;
2670
2671         if (smu->ppt_funcs->display_clock_voltage_request)
2672                 ret = smu->ppt_funcs->display_clock_voltage_request(smu, clock_req);
2673
2674         return ret;
2675 }
2676
2677
2678 static int smu_display_disable_memory_clock_switch(void *handle,
2679                                                    bool disable_memory_clock_switch)
2680 {
2681         struct smu_context *smu = handle;
2682         int ret = -EINVAL;
2683
2684         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2685                 return -EOPNOTSUPP;
2686
2687         if (smu->ppt_funcs->display_disable_memory_clock_switch)
2688                 ret = smu->ppt_funcs->display_disable_memory_clock_switch(smu, disable_memory_clock_switch);
2689
2690         return ret;
2691 }
2692
2693 static int smu_set_xgmi_pstate(void *handle,
2694                                uint32_t pstate)
2695 {
2696         struct smu_context *smu = handle;
2697         int ret = 0;
2698
2699         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2700                 return -EOPNOTSUPP;
2701
2702         if (smu->ppt_funcs->set_xgmi_pstate)
2703                 ret = smu->ppt_funcs->set_xgmi_pstate(smu, pstate);
2704
2705         if(ret)
2706                 dev_err(smu->adev->dev, "Failed to set XGMI pstate!\n");
2707
2708         return ret;
2709 }
2710
2711 static int smu_get_baco_capability(void *handle, bool *cap)
2712 {
2713         struct smu_context *smu = handle;
2714
2715         *cap = false;
2716
2717         if (!smu->pm_enabled)
2718                 return 0;
2719
2720         if (smu->ppt_funcs && smu->ppt_funcs->baco_is_support)
2721                 *cap = smu->ppt_funcs->baco_is_support(smu);
2722
2723         return 0;
2724 }
2725
2726 static int smu_baco_set_state(void *handle, int state)
2727 {
2728         struct smu_context *smu = handle;
2729         int ret = 0;
2730
2731         if (!smu->pm_enabled)
2732                 return -EOPNOTSUPP;
2733
2734         if (state == 0) {
2735                 if (smu->ppt_funcs->baco_exit)
2736                         ret = smu->ppt_funcs->baco_exit(smu);
2737         } else if (state == 1) {
2738                 if (smu->ppt_funcs->baco_enter)
2739                         ret = smu->ppt_funcs->baco_enter(smu);
2740         } else {
2741                 return -EINVAL;
2742         }
2743
2744         if (ret)
2745                 dev_err(smu->adev->dev, "Failed to %s BACO state!\n",
2746                                 (state)?"enter":"exit");
2747
2748         return ret;
2749 }
2750
2751 bool smu_mode1_reset_is_support(struct smu_context *smu)
2752 {
2753         bool ret = false;
2754
2755         if (!smu->pm_enabled)
2756                 return false;
2757
2758         if (smu->ppt_funcs && smu->ppt_funcs->mode1_reset_is_support)
2759                 ret = smu->ppt_funcs->mode1_reset_is_support(smu);
2760
2761         return ret;
2762 }
2763
2764 bool smu_mode2_reset_is_support(struct smu_context *smu)
2765 {
2766         bool ret = false;
2767
2768         if (!smu->pm_enabled)
2769                 return false;
2770
2771         if (smu->ppt_funcs && smu->ppt_funcs->mode2_reset_is_support)
2772                 ret = smu->ppt_funcs->mode2_reset_is_support(smu);
2773
2774         return ret;
2775 }
2776
2777 int smu_mode1_reset(struct smu_context *smu)
2778 {
2779         int ret = 0;
2780
2781         if (!smu->pm_enabled)
2782                 return -EOPNOTSUPP;
2783
2784         if (smu->ppt_funcs->mode1_reset)
2785                 ret = smu->ppt_funcs->mode1_reset(smu);
2786
2787         return ret;
2788 }
2789
2790 static int smu_mode2_reset(void *handle)
2791 {
2792         struct smu_context *smu = handle;
2793         int ret = 0;
2794
2795         if (!smu->pm_enabled)
2796                 return -EOPNOTSUPP;
2797
2798         if (smu->ppt_funcs->mode2_reset)
2799                 ret = smu->ppt_funcs->mode2_reset(smu);
2800
2801         if (ret)
2802                 dev_err(smu->adev->dev, "Mode2 reset failed!\n");
2803
2804         return ret;
2805 }
2806
2807 static int smu_get_max_sustainable_clocks_by_dc(void *handle,
2808                                                 struct pp_smu_nv_clock_table *max_clocks)
2809 {
2810         struct smu_context *smu = handle;
2811         int ret = 0;
2812
2813         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2814                 return -EOPNOTSUPP;
2815
2816         if (smu->ppt_funcs->get_max_sustainable_clocks_by_dc)
2817                 ret = smu->ppt_funcs->get_max_sustainable_clocks_by_dc(smu, max_clocks);
2818
2819         return ret;
2820 }
2821
2822 static int smu_get_uclk_dpm_states(void *handle,
2823                                    unsigned int *clock_values_in_khz,
2824                                    unsigned int *num_states)
2825 {
2826         struct smu_context *smu = handle;
2827         int ret = 0;
2828
2829         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2830                 return -EOPNOTSUPP;
2831
2832         if (smu->ppt_funcs->get_uclk_dpm_states)
2833                 ret = smu->ppt_funcs->get_uclk_dpm_states(smu, clock_values_in_khz, num_states);
2834
2835         return ret;
2836 }
2837
2838 static enum amd_pm_state_type smu_get_current_power_state(void *handle)
2839 {
2840         struct smu_context *smu = handle;
2841         enum amd_pm_state_type pm_state = POWER_STATE_TYPE_DEFAULT;
2842
2843         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2844                 return -EOPNOTSUPP;
2845
2846         if (smu->ppt_funcs->get_current_power_state)
2847                 pm_state = smu->ppt_funcs->get_current_power_state(smu);
2848
2849         return pm_state;
2850 }
2851
2852 static int smu_get_dpm_clock_table(void *handle,
2853                                    struct dpm_clocks *clock_table)
2854 {
2855         struct smu_context *smu = handle;
2856         int ret = 0;
2857
2858         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2859                 return -EOPNOTSUPP;
2860
2861         if (smu->ppt_funcs->get_dpm_clock_table)
2862                 ret = smu->ppt_funcs->get_dpm_clock_table(smu, clock_table);
2863
2864         return ret;
2865 }
2866
2867 static ssize_t smu_sys_get_gpu_metrics(void *handle, void **table)
2868 {
2869         struct smu_context *smu = handle;
2870
2871         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2872                 return -EOPNOTSUPP;
2873
2874         if (!smu->ppt_funcs->get_gpu_metrics)
2875                 return -EOPNOTSUPP;
2876
2877         return smu->ppt_funcs->get_gpu_metrics(smu, table);
2878 }
2879
2880 static int smu_enable_mgpu_fan_boost(void *handle)
2881 {
2882         struct smu_context *smu = handle;
2883         int ret = 0;
2884
2885         if (!smu->pm_enabled || !smu->adev->pm.dpm_enabled)
2886                 return -EOPNOTSUPP;
2887
2888         if (smu->ppt_funcs->enable_mgpu_fan_boost)
2889                 ret = smu->ppt_funcs->enable_mgpu_fan_boost(smu);
2890
2891         return ret;
2892 }
2893
2894 static int smu_gfx_state_change_set(void *handle,
2895                                     uint32_t state)
2896 {
2897         struct smu_context *smu = handle;
2898         int ret = 0;
2899
2900         if (smu->ppt_funcs->gfx_state_change_set)
2901                 ret = smu->ppt_funcs->gfx_state_change_set(smu, state);
2902
2903         return ret;
2904 }
2905
2906 int smu_handle_passthrough_sbr(struct smu_context *smu, bool enable)
2907 {
2908         int ret = 0;
2909
2910         if (smu->ppt_funcs->smu_handle_passthrough_sbr)
2911                 ret = smu->ppt_funcs->smu_handle_passthrough_sbr(smu, enable);
2912
2913         return ret;
2914 }
2915
2916 int smu_get_ecc_info(struct smu_context *smu, void *umc_ecc)
2917 {
2918         int ret = -EOPNOTSUPP;
2919
2920         if (smu->ppt_funcs &&
2921                 smu->ppt_funcs->get_ecc_info)
2922                 ret = smu->ppt_funcs->get_ecc_info(smu, umc_ecc);
2923
2924         return ret;
2925
2926 }
2927
2928 static int smu_get_prv_buffer_details(void *handle, void **addr, size_t *size)
2929 {
2930         struct smu_context *smu = handle;
2931         struct smu_table_context *smu_table = &smu->smu_table;
2932         struct smu_table *memory_pool = &smu_table->memory_pool;
2933
2934         if (!addr || !size)
2935                 return -EINVAL;
2936
2937         *addr = NULL;
2938         *size = 0;
2939         if (memory_pool->bo) {
2940                 *addr = memory_pool->cpu_addr;
2941                 *size = memory_pool->size;
2942         }
2943
2944         return 0;
2945 }
2946
2947 static const struct amd_pm_funcs swsmu_pm_funcs = {
2948         /* export for sysfs */
2949         .set_fan_control_mode    = smu_set_fan_control_mode,
2950         .get_fan_control_mode    = smu_get_fan_control_mode,
2951         .set_fan_speed_pwm   = smu_set_fan_speed_pwm,
2952         .get_fan_speed_pwm   = smu_get_fan_speed_pwm,
2953         .force_clock_level       = smu_force_ppclk_levels,
2954         .print_clock_levels      = smu_print_ppclk_levels,
2955         .emit_clock_levels       = smu_emit_ppclk_levels,
2956         .force_performance_level = smu_force_performance_level,
2957         .read_sensor             = smu_read_sensor,
2958         .get_performance_level   = smu_get_performance_level,
2959         .get_current_power_state = smu_get_current_power_state,
2960         .get_fan_speed_rpm       = smu_get_fan_speed_rpm,
2961         .set_fan_speed_rpm       = smu_set_fan_speed_rpm,
2962         .get_pp_num_states       = smu_get_power_num_states,
2963         .get_pp_table            = smu_sys_get_pp_table,
2964         .set_pp_table            = smu_sys_set_pp_table,
2965         .switch_power_profile    = smu_switch_power_profile,
2966         /* export to amdgpu */
2967         .dispatch_tasks          = smu_handle_dpm_task,
2968         .load_firmware           = smu_load_microcode,
2969         .set_powergating_by_smu  = smu_dpm_set_power_gate,
2970         .set_power_limit         = smu_set_power_limit,
2971         .get_power_limit         = smu_get_power_limit,
2972         .get_power_profile_mode  = smu_get_power_profile_mode,
2973         .set_power_profile_mode  = smu_set_power_profile_mode,
2974         .odn_edit_dpm_table      = smu_od_edit_dpm_table,
2975         .set_mp1_state           = smu_set_mp1_state,
2976         .gfx_state_change_set    = smu_gfx_state_change_set,
2977         /* export to DC */
2978         .get_sclk                         = smu_get_sclk,
2979         .get_mclk                         = smu_get_mclk,
2980         .display_configuration_change     = smu_display_configuration_change,
2981         .get_clock_by_type_with_latency   = smu_get_clock_by_type_with_latency,
2982         .display_clock_voltage_request    = smu_display_clock_voltage_request,
2983         .enable_mgpu_fan_boost            = smu_enable_mgpu_fan_boost,
2984         .set_active_display_count         = smu_set_display_count,
2985         .set_min_deep_sleep_dcefclk       = smu_set_deep_sleep_dcefclk,
2986         .get_asic_baco_capability         = smu_get_baco_capability,
2987         .set_asic_baco_state              = smu_baco_set_state,
2988         .get_ppfeature_status             = smu_sys_get_pp_feature_mask,
2989         .set_ppfeature_status             = smu_sys_set_pp_feature_mask,
2990         .asic_reset_mode_2                = smu_mode2_reset,
2991         .set_df_cstate                    = smu_set_df_cstate,
2992         .set_xgmi_pstate                  = smu_set_xgmi_pstate,
2993         .get_gpu_metrics                  = smu_sys_get_gpu_metrics,
2994         .set_watermarks_for_clock_ranges     = smu_set_watermarks_for_clock_ranges,
2995         .display_disable_memory_clock_switch = smu_display_disable_memory_clock_switch,
2996         .get_max_sustainable_clocks_by_dc    = smu_get_max_sustainable_clocks_by_dc,
2997         .get_uclk_dpm_states              = smu_get_uclk_dpm_states,
2998         .get_dpm_clock_table              = smu_get_dpm_clock_table,
2999         .get_smu_prv_buf_details = smu_get_prv_buffer_details,
3000 };
3001
3002 int smu_wait_for_event(struct smu_context *smu, enum smu_event_type event,
3003                        uint64_t event_arg)
3004 {
3005         int ret = -EINVAL;
3006
3007         if (smu->ppt_funcs->wait_for_event)
3008                 ret = smu->ppt_funcs->wait_for_event(smu, event, event_arg);
3009
3010         return ret;
3011 }
3012
3013 int smu_stb_collect_info(struct smu_context *smu, void *buf, uint32_t size)
3014 {
3015
3016         if (!smu->ppt_funcs->stb_collect_info || !smu->stb_context.enabled)
3017                 return -EOPNOTSUPP;
3018
3019         /* Confirm the buffer allocated is of correct size */
3020         if (size != smu->stb_context.stb_buf_size)
3021                 return -EINVAL;
3022
3023         /*
3024          * No need to lock smu mutex as we access STB directly through MMIO
3025          * and not going through SMU messaging route (for now at least).
3026          * For registers access rely on implementation internal locking.
3027          */
3028         return smu->ppt_funcs->stb_collect_info(smu, buf, size);
3029 }
3030
3031 #if defined(CONFIG_DEBUG_FS)
3032
3033 static int smu_stb_debugfs_open(struct inode *inode, struct file *filp)
3034 {
3035         struct amdgpu_device *adev = filp->f_inode->i_private;
3036         struct smu_context *smu = adev->powerplay.pp_handle;
3037         unsigned char *buf;
3038         int r;
3039
3040         buf = kvmalloc_array(smu->stb_context.stb_buf_size, sizeof(*buf), GFP_KERNEL);
3041         if (!buf)
3042                 return -ENOMEM;
3043
3044         r = smu_stb_collect_info(smu, buf, smu->stb_context.stb_buf_size);
3045         if (r)
3046                 goto out;
3047
3048         filp->private_data = buf;
3049
3050         return 0;
3051
3052 out:
3053         kvfree(buf);
3054         return r;
3055 }
3056
3057 static ssize_t smu_stb_debugfs_read(struct file *filp, char __user *buf, size_t size,
3058                                 loff_t *pos)
3059 {
3060         struct amdgpu_device *adev = filp->f_inode->i_private;
3061         struct smu_context *smu = adev->powerplay.pp_handle;
3062
3063
3064         if (!filp->private_data)
3065                 return -EINVAL;
3066
3067         return simple_read_from_buffer(buf,
3068                                        size,
3069                                        pos, filp->private_data,
3070                                        smu->stb_context.stb_buf_size);
3071 }
3072
3073 static int smu_stb_debugfs_release(struct inode *inode, struct file *filp)
3074 {
3075         kvfree(filp->private_data);
3076         filp->private_data = NULL;
3077
3078         return 0;
3079 }
3080
3081 /*
3082  * We have to define not only read method but also
3083  * open and release because .read takes up to PAGE_SIZE
3084  * data each time so and so is invoked multiple times.
3085  *  We allocate the STB buffer in .open and release it
3086  *  in .release
3087  */
3088 static const struct file_operations smu_stb_debugfs_fops = {
3089         .owner = THIS_MODULE,
3090         .open = smu_stb_debugfs_open,
3091         .read = smu_stb_debugfs_read,
3092         .release = smu_stb_debugfs_release,
3093         .llseek = default_llseek,
3094 };
3095
3096 #endif
3097
3098 void amdgpu_smu_stb_debug_fs_init(struct amdgpu_device *adev)
3099 {
3100 #if defined(CONFIG_DEBUG_FS)
3101
3102         struct smu_context *smu = adev->powerplay.pp_handle;
3103
3104         if (!smu || (!smu->stb_context.stb_buf_size))
3105                 return;
3106
3107         debugfs_create_file_size("amdgpu_smu_stb_dump",
3108                             S_IRUSR,
3109                             adev_to_drm(adev)->primary->debugfs_root,
3110                             adev,
3111                             &smu_stb_debugfs_fops,
3112                             smu->stb_context.stb_buf_size);
3113 #endif
3114 }
3115
3116 int smu_send_hbm_bad_pages_num(struct smu_context *smu, uint32_t size)
3117 {
3118         int ret = 0;
3119
3120         if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_pages_num)
3121                 ret = smu->ppt_funcs->send_hbm_bad_pages_num(smu, size);
3122
3123         return ret;
3124 }
3125
3126 int smu_send_hbm_bad_channel_flag(struct smu_context *smu, uint32_t size)
3127 {
3128         int ret = 0;
3129
3130         if (smu->ppt_funcs && smu->ppt_funcs->send_hbm_bad_channel_flag)
3131                 ret = smu->ppt_funcs->send_hbm_bad_channel_flag(smu, size);
3132
3133         return ret;
3134 }