drivers/spi/spi-bcm63xx.c

   1 /*
   2  * Broadcom BCM63xx SPI controller support
   3  *
   4  * Copyright (C) 2009-2012 Florian Fainelli <[email protected]>
   5  * Copyright (C) 2010 Tanguy Bouzeloc <[email protected]>
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License
   9  * as published by the Free Software Foundation; either version 2
  10  * of the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  */
  17
  18 #include <linux/kernel.h>
  19 #include <linux/clk.h>
  20 #include <linux/io.h>
  21 #include <linux/module.h>
  22 #include <linux/platform_device.h>
  23 #include <linux/delay.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/spi/spi.h>
  26 #include <linux/completion.h>
  27 #include <linux/err.h>
  28 #include <linux/pm_runtime.h>
  29 #include <linux/of.h>
  30
  31 /* BCM 6338/6348 SPI core */
  32 #define SPI_6348_RSET_SIZE              64
  33 #define SPI_6348_CMD                    0x00    /* 16-bits register */
  34 #define SPI_6348_INT_STATUS             0x02
  35 #define SPI_6348_INT_MASK_ST            0x03
  36 #define SPI_6348_INT_MASK               0x04
  37 #define SPI_6348_ST                     0x05
  38 #define SPI_6348_CLK_CFG                0x06
  39 #define SPI_6348_FILL_BYTE              0x07
  40 #define SPI_6348_MSG_TAIL               0x09
  41 #define SPI_6348_RX_TAIL                0x0b
  42 #define SPI_6348_MSG_CTL                0x40    /* 8-bits register */
  43 #define SPI_6348_MSG_CTL_WIDTH          8
  44 #define SPI_6348_MSG_DATA               0x41
  45 #define SPI_6348_MSG_DATA_SIZE          0x3f
  46 #define SPI_6348_RX_DATA                0x80
  47 #define SPI_6348_RX_DATA_SIZE           0x3f
  48
  49 /* BCM 3368/6358/6262/6368 SPI core */
  50 #define SPI_6358_RSET_SIZE              1804
  51 #define SPI_6358_MSG_CTL                0x00    /* 16-bits register */
  52 #define SPI_6358_MSG_CTL_WIDTH          16
  53 #define SPI_6358_MSG_DATA               0x02
  54 #define SPI_6358_MSG_DATA_SIZE          0x21e
  55 #define SPI_6358_RX_DATA                0x400
  56 #define SPI_6358_RX_DATA_SIZE           0x220
  57 #define SPI_6358_CMD                    0x700   /* 16-bits register */
  58 #define SPI_6358_INT_STATUS             0x702
  59 #define SPI_6358_INT_MASK_ST            0x703
  60 #define SPI_6358_INT_MASK               0x704
  61 #define SPI_6358_ST                     0x705
  62 #define SPI_6358_CLK_CFG                0x706
  63 #define SPI_6358_FILL_BYTE              0x707
  64 #define SPI_6358_MSG_TAIL               0x709
  65 #define SPI_6358_RX_TAIL                0x70B
  66
  67 /* Shared SPI definitions */
  68
  69 /* Message configuration */
  70 #define SPI_FD_RW                       0x00
  71 #define SPI_HD_W                        0x01
  72 #define SPI_HD_R                        0x02
  73 #define SPI_BYTE_CNT_SHIFT              0
  74 #define SPI_6348_MSG_TYPE_SHIFT         6
  75 #define SPI_6358_MSG_TYPE_SHIFT         14
  76
  77 /* Command */
  78 #define SPI_CMD_NOOP                    0x00
  79 #define SPI_CMD_SOFT_RESET              0x01
  80 #define SPI_CMD_HARD_RESET              0x02
  81 #define SPI_CMD_START_IMMEDIATE         0x03
  82 #define SPI_CMD_COMMAND_SHIFT           0
  83 #define SPI_CMD_COMMAND_MASK            0x000f
  84 #define SPI_CMD_DEVICE_ID_SHIFT         4
  85 #define SPI_CMD_PREPEND_BYTE_CNT_SHIFT  8
  86 #define SPI_CMD_ONE_BYTE_SHIFT          11
  87 #define SPI_CMD_ONE_WIRE_SHIFT          12
  88 #define SPI_DEV_ID_0                    0
  89 #define SPI_DEV_ID_1                    1
  90 #define SPI_DEV_ID_2                    2
  91 #define SPI_DEV_ID_3                    3
  92
  93 /* Interrupt mask */
  94 #define SPI_INTR_CMD_DONE               0x01
  95 #define SPI_INTR_RX_OVERFLOW            0x02
  96 #define SPI_INTR_TX_UNDERFLOW           0x04
  97 #define SPI_INTR_TX_OVERFLOW            0x08
  98 #define SPI_INTR_RX_UNDERFLOW           0x10
  99 #define SPI_INTR_CLEAR_ALL              0x1f
 100
 101 /* Status */
 102 #define SPI_RX_EMPTY                    0x02
 103 #define SPI_CMD_BUSY                    0x04
 104 #define SPI_SERIAL_BUSY                 0x08
 105
 106 /* Clock configuration */
 107 #define SPI_CLK_20MHZ                   0x00
 108 #define SPI_CLK_0_391MHZ                0x01
 109 #define SPI_CLK_0_781MHZ                0x02    /* default */
 110 #define SPI_CLK_1_563MHZ                0x03
 111 #define SPI_CLK_3_125MHZ                0x04
 112 #define SPI_CLK_6_250MHZ                0x05
 113 #define SPI_CLK_12_50MHZ                0x06
 114 #define SPI_CLK_MASK                    0x07
 115 #define SPI_SSOFFTIME_MASK              0x38
 116 #define SPI_SSOFFTIME_SHIFT             3
 117 #define SPI_BYTE_SWAP                   0x80
 118
 119 enum bcm63xx_regs_spi {
 120         SPI_CMD,
 121         SPI_INT_STATUS,
 122         SPI_INT_MASK_ST,
 123         SPI_INT_MASK,
 124         SPI_ST,
 125         SPI_CLK_CFG,
 126         SPI_FILL_BYTE,
 127         SPI_MSG_TAIL,
 128         SPI_RX_TAIL,
 129         SPI_MSG_CTL,
 130         SPI_MSG_DATA,
 131         SPI_RX_DATA,
 132         SPI_MSG_TYPE_SHIFT,
 133         SPI_MSG_CTL_WIDTH,
 134         SPI_MSG_DATA_SIZE,
 135 };
 136
 137 #define BCM63XX_SPI_MAX_PREPEND         15
 138
 139 #define BCM63XX_SPI_MAX_CS              8
 140 #define BCM63XX_SPI_BUS_NUM             0
 141
 142 struct bcm63xx_spi {
 143         struct completion       done;
 144
 145         void __iomem            *regs;
 146         int                     irq;
 147
 148         /* Platform data */
 149         const unsigned long     *reg_offsets;
 150         unsigned int            fifo_size;
 151         unsigned int            msg_type_shift;
 152         unsigned int            msg_ctl_width;
 153
 154         /* data iomem */
 155         u8 __iomem              *tx_io;
 156         const u8 __iomem        *rx_io;
 157
 158         struct clk              *clk;
 159         struct platform_device  *pdev;
 160 };
 161
 162 static inline u8 bcm_spi_readb(struct bcm63xx_spi *bs,
 163                                unsigned int offset)
 164 {
 165         return readb(bs->regs + bs->reg_offsets[offset]);
 166 }
 167
 168 static inline u16 bcm_spi_readw(struct bcm63xx_spi *bs,
 169                                 unsigned int offset)
 170 {
 171 #ifdef CONFIG_CPU_BIG_ENDIAN
 172         return ioread16be(bs->regs + bs->reg_offsets[offset]);
 173 #else
 174         return readw(bs->regs + bs->reg_offsets[offset]);
 175 #endif
 176 }
 177
 178 static inline void bcm_spi_writeb(struct bcm63xx_spi *bs,
 179                                   u8 value, unsigned int offset)
 180 {
 181         writeb(value, bs->regs + bs->reg_offsets[offset]);
 182 }
 183
 184 static inline void bcm_spi_writew(struct bcm63xx_spi *bs,
 185                                   u16 value, unsigned int offset)
 186 {
 187 #ifdef CONFIG_CPU_BIG_ENDIAN
 188         iowrite16be(value, bs->regs + bs->reg_offsets[offset]);
 189 #else
 190         writew(value, bs->regs + bs->reg_offsets[offset]);
 191 #endif
 192 }
 193
 194 static const unsigned int bcm63xx_spi_freq_table[SPI_CLK_MASK][2] = {
 195         { 20000000, SPI_CLK_20MHZ },
 196         { 12500000, SPI_CLK_12_50MHZ },
 197         {  6250000, SPI_CLK_6_250MHZ },
 198         {  3125000, SPI_CLK_3_125MHZ },
 199         {  1563000, SPI_CLK_1_563MHZ },
 200         {   781000, SPI_CLK_0_781MHZ },
 201         {   391000, SPI_CLK_0_391MHZ }
 202 };
 203
 204 static void bcm63xx_spi_setup_transfer(struct spi_device *spi,
 205                                       struct spi_transfer *t)
 206 {
 207         struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
 208         u8 clk_cfg, reg;
 209         int i;
 210
 211         /* Default to lowest clock configuration */
 212         clk_cfg = SPI_CLK_0_391MHZ;
 213
 214         /* Find the closest clock configuration */
 215         for (i = 0; i < SPI_CLK_MASK; i++) {
 216                 if (t->speed_hz >= bcm63xx_spi_freq_table[i][0]) {
 217                         clk_cfg = bcm63xx_spi_freq_table[i][1];
 218                         break;
 219                 }
 220         }
 221
 222         /* clear existing clock configuration bits of the register */
 223         reg = bcm_spi_readb(bs, SPI_CLK_CFG);
 224         reg &= ~SPI_CLK_MASK;
 225         reg |= clk_cfg;
 226
 227         bcm_spi_writeb(bs, reg, SPI_CLK_CFG);
 228         dev_dbg(&spi->dev, "Setting clock register to %02x (hz %d)\n",
 229                 clk_cfg, t->speed_hz);
 230 }
 231
 232 /* the spi->mode bits understood by this driver: */
 233 #define MODEBITS (SPI_CPOL | SPI_CPHA)
 234
 235 static int bcm63xx_txrx_bufs(struct spi_device *spi, struct spi_transfer *first,
 236                                 unsigned int num_transfers)
 237 {
 238         struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
 239         u16 msg_ctl;
 240         u16 cmd;
 241         unsigned int i, timeout = 0, prepend_len = 0, len = 0;
 242         struct spi_transfer *t = first;
 243         bool do_rx = false;
 244         bool do_tx = false;
 245
 246         /* Disable the CMD_DONE interrupt */
 247         bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 248
 249         dev_dbg(&spi->dev, "txrx: tx %p, rx %p, len %d\n",
 250                 t->tx_buf, t->rx_buf, t->len);
 251
 252         if (num_transfers > 1 && t->tx_buf && t->len <= BCM63XX_SPI_MAX_PREPEND)
 253                 prepend_len = t->len;
 254
 255         /* prepare the buffer */
 256         for (i = 0; i < num_transfers; i++) {
 257                 if (t->tx_buf) {
 258                         do_tx = true;
 259                         memcpy_toio(bs->tx_io + len, t->tx_buf, t->len);
 260
 261                         /* don't prepend more than one tx */
 262                         if (t != first)
 263                                 prepend_len = 0;
 264                 }
 265
 266                 if (t->rx_buf) {
 267                         do_rx = true;
 268                         /* prepend is half-duplex write only */
 269                         if (t == first)
 270                                 prepend_len = 0;
 271                 }
 272
 273                 len += t->len;
 274
 275                 t = list_entry(t->transfer_list.next, struct spi_transfer,
 276                                transfer_list);
 277         }
 278
 279         reinit_completion(&bs->done);
 280
 281         /* Fill in the Message control register */
 282         msg_ctl = (len << SPI_BYTE_CNT_SHIFT);
 283
 284         if (do_rx && do_tx && prepend_len == 0)
 285                 msg_ctl |= (SPI_FD_RW << bs->msg_type_shift);
 286         else if (do_rx)
 287                 msg_ctl |= (SPI_HD_R << bs->msg_type_shift);
 288         else if (do_tx)
 289                 msg_ctl |= (SPI_HD_W << bs->msg_type_shift);
 290
 291         switch (bs->msg_ctl_width) {
 292         case 8:
 293                 bcm_spi_writeb(bs, msg_ctl, SPI_MSG_CTL);
 294                 break;
 295         case 16:
 296                 bcm_spi_writew(bs, msg_ctl, SPI_MSG_CTL);
 297                 break;
 298         }
 299
 300         /* Issue the transfer */
 301         cmd = SPI_CMD_START_IMMEDIATE;
 302         cmd |= (prepend_len << SPI_CMD_PREPEND_BYTE_CNT_SHIFT);
 303         cmd |= (spi->chip_select << SPI_CMD_DEVICE_ID_SHIFT);
 304         bcm_spi_writew(bs, cmd, SPI_CMD);
 305
 306         /* Enable the CMD_DONE interrupt */
 307         bcm_spi_writeb(bs, SPI_INTR_CMD_DONE, SPI_INT_MASK);
 308
 309         timeout = wait_for_completion_timeout(&bs->done, HZ);
 310         if (!timeout)
 311                 return -ETIMEDOUT;
 312
 313         if (!do_rx)
 314                 return 0;
 315
 316         len = 0;
 317         t = first;
 318         /* Read out all the data */
 319         for (i = 0; i < num_transfers; i++) {
 320                 if (t->rx_buf)
 321                         memcpy_fromio(t->rx_buf, bs->rx_io + len, t->len);
 322
 323                 if (t != first || prepend_len == 0)
 324                         len += t->len;
 325
 326                 t = list_entry(t->transfer_list.next, struct spi_transfer,
 327                                transfer_list);
 328         }
 329
 330         return 0;
 331 }
 332
 333 static int bcm63xx_spi_transfer_one(struct spi_master *master,
 334                                         struct spi_message *m)
 335 {
 336         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 337         struct spi_transfer *t, *first = NULL;
 338         struct spi_device *spi = m->spi;
 339         int status = 0;
 340         unsigned int n_transfers = 0, total_len = 0;
 341         bool can_use_prepend = false;
 342
 343         /*
 344          * This SPI controller does not support keeping CS active after a
 345          * transfer.
 346          * Work around this by merging as many transfers we can into one big
 347          * full-duplex transfers.
 348          */
 349         list_for_each_entry(t, &m->transfers, transfer_list) {
 350                 if (!first)
 351                         first = t;
 352
 353                 n_transfers++;
 354                 total_len += t->len;
 355
 356                 if (n_transfers == 2 && !first->rx_buf && !t->tx_buf &&
 357                     first->len <= BCM63XX_SPI_MAX_PREPEND)
 358                         can_use_prepend = true;
 359                 else if (can_use_prepend && t->tx_buf)
 360                         can_use_prepend = false;
 361
 362                 /* we can only transfer one fifo worth of data */
 363                 if ((can_use_prepend &&
 364                      total_len > (bs->fifo_size + BCM63XX_SPI_MAX_PREPEND)) ||
 365                     (!can_use_prepend && total_len > bs->fifo_size)) {
 366                         dev_err(&spi->dev, "unable to do transfers larger than FIFO size (%i > %i)\n",
 367                                 total_len, bs->fifo_size);
 368                         status = -EINVAL;
 369                         goto exit;
 370                 }
 371
 372                 /* all combined transfers have to have the same speed */
 373                 if (t->speed_hz != first->speed_hz) {
 374                         dev_err(&spi->dev, "unable to change speed between transfers\n");
 375                         status = -EINVAL;
 376                         goto exit;
 377                 }
 378
 379                 /* CS will be deasserted directly after transfer */
 380                 if (t->delay_usecs) {
 381                         dev_err(&spi->dev, "unable to keep CS asserted after transfer\n");
 382                         status = -EINVAL;
 383                         goto exit;
 384                 }
 385
 386                 if (t->cs_change ||
 387                     list_is_last(&t->transfer_list, &m->transfers)) {
 388                         /* configure adapter for a new transfer */
 389                         bcm63xx_spi_setup_transfer(spi, first);
 390
 391                         /* send the data */
 392                         status = bcm63xx_txrx_bufs(spi, first, n_transfers);
 393                         if (status)
 394                                 goto exit;
 395
 396                         m->actual_length += total_len;
 397
 398                         first = NULL;
 399                         n_transfers = 0;
 400                         total_len = 0;
 401                         can_use_prepend = false;
 402                 }
 403         }
 404 exit:
 405         m->status = status;
 406         spi_finalize_current_message(master);
 407
 408         return 0;
 409 }
 410
 411 /* This driver supports single master mode only. Hence
 412  * CMD_DONE is the only interrupt we care about
 413  */
 414 static irqreturn_t bcm63xx_spi_interrupt(int irq, void *dev_id)
 415 {
 416         struct spi_master *master = (struct spi_master *)dev_id;
 417         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 418         u8 intr;
 419
 420         /* Read interupts and clear them immediately */
 421         intr = bcm_spi_readb(bs, SPI_INT_STATUS);
 422         bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
 423         bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 424
 425         /* A transfer completed */
 426         if (intr & SPI_INTR_CMD_DONE)
 427                 complete(&bs->done);
 428
 429         return IRQ_HANDLED;
 430 }
 431
 432 static size_t bcm63xx_spi_max_length(struct spi_device *spi)
 433 {
 434         struct bcm63xx_spi *bs = spi_master_get_devdata(spi->master);
 435
 436         return bs->fifo_size;
 437 }
 438
 439 static const unsigned long bcm6348_spi_reg_offsets[] = {
 440         [SPI_CMD]               = SPI_6348_CMD,
 441         [SPI_INT_STATUS]        = SPI_6348_INT_STATUS,
 442         [SPI_INT_MASK_ST]       = SPI_6348_INT_MASK_ST,
 443         [SPI_INT_MASK]          = SPI_6348_INT_MASK,
 444         [SPI_ST]                = SPI_6348_ST,
 445         [SPI_CLK_CFG]           = SPI_6348_CLK_CFG,
 446         [SPI_FILL_BYTE]         = SPI_6348_FILL_BYTE,
 447         [SPI_MSG_TAIL]          = SPI_6348_MSG_TAIL,
 448         [SPI_RX_TAIL]           = SPI_6348_RX_TAIL,
 449         [SPI_MSG_CTL]           = SPI_6348_MSG_CTL,
 450         [SPI_MSG_DATA]          = SPI_6348_MSG_DATA,
 451         [SPI_RX_DATA]           = SPI_6348_RX_DATA,
 452         [SPI_MSG_TYPE_SHIFT]    = SPI_6348_MSG_TYPE_SHIFT,
 453         [SPI_MSG_CTL_WIDTH]     = SPI_6348_MSG_CTL_WIDTH,
 454         [SPI_MSG_DATA_SIZE]     = SPI_6348_MSG_DATA_SIZE,
 455 };
 456
 457 static const unsigned long bcm6358_spi_reg_offsets[] = {
 458         [SPI_CMD]               = SPI_6358_CMD,
 459         [SPI_INT_STATUS]        = SPI_6358_INT_STATUS,
 460         [SPI_INT_MASK_ST]       = SPI_6358_INT_MASK_ST,
 461         [SPI_INT_MASK]          = SPI_6358_INT_MASK,
 462         [SPI_ST]                = SPI_6358_ST,
 463         [SPI_CLK_CFG]           = SPI_6358_CLK_CFG,
 464         [SPI_FILL_BYTE]         = SPI_6358_FILL_BYTE,
 465         [SPI_MSG_TAIL]          = SPI_6358_MSG_TAIL,
 466         [SPI_RX_TAIL]           = SPI_6358_RX_TAIL,
 467         [SPI_MSG_CTL]           = SPI_6358_MSG_CTL,
 468         [SPI_MSG_DATA]          = SPI_6358_MSG_DATA,
 469         [SPI_RX_DATA]           = SPI_6358_RX_DATA,
 470         [SPI_MSG_TYPE_SHIFT]    = SPI_6358_MSG_TYPE_SHIFT,
 471         [SPI_MSG_CTL_WIDTH]     = SPI_6358_MSG_CTL_WIDTH,
 472         [SPI_MSG_DATA_SIZE]     = SPI_6358_MSG_DATA_SIZE,
 473 };
 474
 475 static const struct platform_device_id bcm63xx_spi_dev_match[] = {
 476         {
 477                 .name = "bcm6348-spi",
 478                 .driver_data = (unsigned long)bcm6348_spi_reg_offsets,
 479         },
 480         {
 481                 .name = "bcm6358-spi",
 482                 .driver_data = (unsigned long)bcm6358_spi_reg_offsets,
 483         },
 484         {
 485         },
 486 };
 487
 488 static const struct of_device_id bcm63xx_spi_of_match[] = {
 489         { .compatible = "brcm,bcm6348-spi", .data = &bcm6348_spi_reg_offsets },
 490         { .compatible = "brcm,bcm6358-spi", .data = &bcm6358_spi_reg_offsets },
 491         { },
 492 };
 493
 494 static int bcm63xx_spi_probe(struct platform_device *pdev)
 495 {
 496         struct resource *r;
 497         const unsigned long *bcm63xx_spireg;
 498         struct device *dev = &pdev->dev;
 499         int irq, bus_num;
 500         struct spi_master *master;
 501         struct clk *clk;
 502         struct bcm63xx_spi *bs;
 503         int ret;
 504         u32 num_cs = BCM63XX_SPI_MAX_CS;
 505
 506         if (dev->of_node) {
 507                 const struct of_device_id *match;
 508
 509                 match = of_match_node(bcm63xx_spi_of_match, dev->of_node);
 510                 if (!match)
 511                         return -EINVAL;
 512                 bcm63xx_spireg = match->data;
 513
 514                 of_property_read_u32(dev->of_node, "num-cs", &num_cs);
 515                 if (num_cs > BCM63XX_SPI_MAX_CS) {
 516                         dev_warn(dev, "unsupported number of cs (%i), reducing to 8\n",
 517                                  num_cs);
 518                         num_cs = BCM63XX_SPI_MAX_CS;
 519                 }
 520
 521                 bus_num = -1;
 522         } else if (pdev->id_entry->driver_data) {
 523                 const struct platform_device_id *match = pdev->id_entry;
 524
 525                 bcm63xx_spireg = (const unsigned long *)match->driver_data;
 526                 bus_num = BCM63XX_SPI_BUS_NUM;
 527         } else {
 528                 return -EINVAL;
 529         }
 530
 531         irq = platform_get_irq(pdev, 0);
 532         if (irq < 0) {
 533                 dev_err(dev, "no irq: %d\n", irq);
 534                 return irq;
 535         }
 536
 537         clk = devm_clk_get(dev, "spi");
 538         if (IS_ERR(clk)) {
 539                 dev_err(dev, "no clock for device\n");
 540                 return PTR_ERR(clk);
 541         }
 542
 543         master = spi_alloc_master(dev, sizeof(*bs));
 544         if (!master) {
 545                 dev_err(dev, "out of memory\n");
 546                 return -ENOMEM;
 547         }
 548
 549         bs = spi_master_get_devdata(master);
 550         init_completion(&bs->done);
 551
 552         platform_set_drvdata(pdev, master);
 553         bs->pdev = pdev;
 554
 555         r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 556         bs->regs = devm_ioremap_resource(&pdev->dev, r);
 557         if (IS_ERR(bs->regs)) {
 558                 ret = PTR_ERR(bs->regs);
 559                 goto out_err;
 560         }
 561
 562         bs->irq = irq;
 563         bs->clk = clk;
 564         bs->reg_offsets = bcm63xx_spireg;
 565         bs->fifo_size = bs->reg_offsets[SPI_MSG_DATA_SIZE];
 566
 567         ret = devm_request_irq(&pdev->dev, irq, bcm63xx_spi_interrupt, 0,
 568                                                         pdev->name, master);
 569         if (ret) {
 570                 dev_err(dev, "unable to request irq\n");
 571                 goto out_err;
 572         }
 573
 574         master->dev.of_node = dev->of_node;
 575         master->bus_num = bus_num;
 576         master->num_chipselect = num_cs;
 577         master->transfer_one_message = bcm63xx_spi_transfer_one;
 578         master->mode_bits = MODEBITS;
 579         master->bits_per_word_mask = SPI_BPW_MASK(8);
 580         master->max_transfer_size = bcm63xx_spi_max_length;
 581         master->max_message_size = bcm63xx_spi_max_length;
 582         master->auto_runtime_pm = true;
 583         bs->msg_type_shift = bs->reg_offsets[SPI_MSG_TYPE_SHIFT];
 584         bs->msg_ctl_width = bs->reg_offsets[SPI_MSG_CTL_WIDTH];
 585         bs->tx_io = (u8 *)(bs->regs + bs->reg_offsets[SPI_MSG_DATA]);
 586         bs->rx_io = (const u8 *)(bs->regs + bs->reg_offsets[SPI_RX_DATA]);
 587
 588         /* Initialize hardware */
 589         ret = clk_prepare_enable(bs->clk);
 590         if (ret)
 591                 goto out_err;
 592
 593         bcm_spi_writeb(bs, SPI_INTR_CLEAR_ALL, SPI_INT_STATUS);
 594
 595         /* register and we are done */
 596         ret = devm_spi_register_master(dev, master);
 597         if (ret) {
 598                 dev_err(dev, "spi register failed\n");
 599                 goto out_clk_disable;
 600         }
 601
 602         dev_info(dev, "at %pr (irq %d, FIFOs size %d)\n",
 603                  r, irq, bs->fifo_size);
 604
 605         return 0;
 606
 607 out_clk_disable:
 608         clk_disable_unprepare(clk);
 609 out_err:
 610         spi_master_put(master);
 611         return ret;
 612 }
 613
 614 static int bcm63xx_spi_remove(struct platform_device *pdev)
 615 {
 616         struct spi_master *master = platform_get_drvdata(pdev);
 617         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 618
 619         /* reset spi block */
 620         bcm_spi_writeb(bs, 0, SPI_INT_MASK);
 621
 622         /* HW shutdown */
 623         clk_disable_unprepare(bs->clk);
 624
 625         return 0;
 626 }
 627
 628 #ifdef CONFIG_PM_SLEEP
 629 static int bcm63xx_spi_suspend(struct device *dev)
 630 {
 631         struct spi_master *master = dev_get_drvdata(dev);
 632         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 633
 634         spi_master_suspend(master);
 635
 636         clk_disable_unprepare(bs->clk);
 637
 638         return 0;
 639 }
 640
 641 static int bcm63xx_spi_resume(struct device *dev)
 642 {
 643         struct spi_master *master = dev_get_drvdata(dev);
 644         struct bcm63xx_spi *bs = spi_master_get_devdata(master);
 645         int ret;
 646
 647         ret = clk_prepare_enable(bs->clk);
 648         if (ret)
 649                 return ret;
 650
 651         spi_master_resume(master);
 652
 653         return 0;
 654 }
 655 #endif
 656
 657 static const struct dev_pm_ops bcm63xx_spi_pm_ops = {
 658         SET_SYSTEM_SLEEP_PM_OPS(bcm63xx_spi_suspend, bcm63xx_spi_resume)
 659 };
 660
 661 static struct platform_driver bcm63xx_spi_driver = {
 662         .driver = {
 663                 .name   = "bcm63xx-spi",
 664                 .pm     = &bcm63xx_spi_pm_ops,
 665                 .of_match_table = bcm63xx_spi_of_match,
 666         },
 667         .id_table       = bcm63xx_spi_dev_match,
 668         .probe          = bcm63xx_spi_probe,
 669         .remove         = bcm63xx_spi_remove,
 670 };
 671
 672 module_platform_driver(bcm63xx_spi_driver);
 673
 674 MODULE_ALIAS("platform:bcm63xx_spi");
 675 MODULE_AUTHOR("Florian Fainelli <[email protected]>");
 676 MODULE_AUTHOR("Tanguy Bouzeloc <[email protected]>");
 677 MODULE_DESCRIPTION("Broadcom BCM63xx SPI Controller driver");
 678 MODULE_LICENSE("GPL");