drivers/iio/trigger/stm32-timer-trigger.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) STMicroelectronics 2016
   4  *
   5  * Author: Benjamin Gaignard <[email protected]>
   6  *
   7  */
   8
   9 #include <linux/iio/iio.h>
  10 #include <linux/iio/sysfs.h>
  11 #include <linux/iio/timer/stm32-timer-trigger.h>
  12 #include <linux/iio/trigger.h>
  13 #include <linux/mfd/stm32-timers.h>
  14 #include <linux/module.h>
  15 #include <linux/platform_device.h>
  16 #include <linux/of_device.h>
  17
  18 #define MAX_TRIGGERS 7
  19 #define MAX_VALIDS 5
  20
  21 /* List the triggers created by each timer */
  22 static const void *triggers_table[][MAX_TRIGGERS] = {
  23         { TIM1_TRGO, TIM1_TRGO2, TIM1_CH1, TIM1_CH2, TIM1_CH3, TIM1_CH4,},
  24         { TIM2_TRGO, TIM2_CH1, TIM2_CH2, TIM2_CH3, TIM2_CH4,},
  25         { TIM3_TRGO, TIM3_CH1, TIM3_CH2, TIM3_CH3, TIM3_CH4,},
  26         { TIM4_TRGO, TIM4_CH1, TIM4_CH2, TIM4_CH3, TIM4_CH4,},
  27         { TIM5_TRGO, TIM5_CH1, TIM5_CH2, TIM5_CH3, TIM5_CH4,},
  28         { TIM6_TRGO,},
  29         { TIM7_TRGO,},
  30         { TIM8_TRGO, TIM8_TRGO2, TIM8_CH1, TIM8_CH2, TIM8_CH3, TIM8_CH4,},
  31         { TIM9_TRGO, TIM9_CH1, TIM9_CH2,},
  32         { TIM10_OC1,},
  33         { TIM11_OC1,},
  34         { TIM12_TRGO, TIM12_CH1, TIM12_CH2,},
  35         { TIM13_OC1,},
  36         { TIM14_OC1,},
  37         { TIM15_TRGO,},
  38         { TIM16_OC1,},
  39         { TIM17_OC1,},
  40 };
  41
  42 /* List the triggers accepted by each timer */
  43 static const void *valids_table[][MAX_VALIDS] = {
  44         { TIM5_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,},
  45         { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
  46         { TIM1_TRGO, TIM2_TRGO, TIM5_TRGO, TIM4_TRGO,},
  47         { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,},
  48         { TIM2_TRGO, TIM3_TRGO, TIM4_TRGO, TIM8_TRGO,},
  49         { }, /* timer 6 */
  50         { }, /* timer 7 */
  51         { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,},
  52         { TIM2_TRGO, TIM3_TRGO, TIM10_OC1, TIM11_OC1,},
  53         { }, /* timer 10 */
  54         { }, /* timer 11 */
  55         { TIM4_TRGO, TIM5_TRGO, TIM13_OC1, TIM14_OC1,},
  56 };
  57
  58 static const void *stm32h7_valids_table[][MAX_VALIDS] = {
  59         { TIM15_TRGO, TIM2_TRGO, TIM3_TRGO, TIM4_TRGO,},
  60         { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
  61         { TIM1_TRGO, TIM2_TRGO, TIM15_TRGO, TIM4_TRGO,},
  62         { TIM1_TRGO, TIM2_TRGO, TIM3_TRGO, TIM8_TRGO,},
  63         { TIM1_TRGO, TIM8_TRGO, TIM3_TRGO, TIM4_TRGO,},
  64         { }, /* timer 6 */
  65         { }, /* timer 7 */
  66         { TIM1_TRGO, TIM2_TRGO, TIM4_TRGO, TIM5_TRGO,},
  67         { }, /* timer 9 */
  68         { }, /* timer 10 */
  69         { }, /* timer 11 */
  70         { TIM4_TRGO, TIM5_TRGO, TIM13_OC1, TIM14_OC1,},
  71         { }, /* timer 13 */
  72         { }, /* timer 14 */
  73         { TIM1_TRGO, TIM3_TRGO, TIM16_OC1, TIM17_OC1,},
  74         { }, /* timer 16 */
  75         { }, /* timer 17 */
  76 };
  77
  78 struct stm32_timer_trigger {
  79         struct device *dev;
  80         struct regmap *regmap;
  81         struct clk *clk;
  82         u32 max_arr;
  83         const void *triggers;
  84         const void *valids;
  85         bool has_trgo2;
  86 };
  87
  88 struct stm32_timer_trigger_cfg {
  89         const void *(*valids_table)[MAX_VALIDS];
  90         const unsigned int num_valids_table;
  91 };
  92
  93 static bool stm32_timer_is_trgo2_name(const char *name)
  94 {
  95         return !!strstr(name, "trgo2");
  96 }
  97
  98 static bool stm32_timer_is_trgo_name(const char *name)
  99 {
 100         return (!!strstr(name, "trgo") && !strstr(name, "trgo2"));
 101 }
 102
 103 static int stm32_timer_start(struct stm32_timer_trigger *priv,
 104                              struct iio_trigger *trig,
 105                              unsigned int frequency)
 106 {
 107         unsigned long long prd, div;
 108         int prescaler = 0;
 109         u32 ccer, cr1;
 110
 111         /* Period and prescaler values depends of clock rate */
 112         div = (unsigned long long)clk_get_rate(priv->clk);
 113
 114         do_div(div, frequency);
 115
 116         prd = div;
 117
 118         /*
 119          * Increase prescaler value until we get a result that fit
 120          * with auto reload register maximum value.
 121          */
 122         while (div > priv->max_arr) {
 123                 prescaler++;
 124                 div = prd;
 125                 do_div(div, (prescaler + 1));
 126         }
 127         prd = div;
 128
 129         if (prescaler > MAX_TIM_PSC) {
 130                 dev_err(priv->dev, "prescaler exceeds the maximum value\n");
 131                 return -EINVAL;
 132         }
 133
 134         /* Check if nobody else use the timer */
 135         regmap_read(priv->regmap, TIM_CCER, &ccer);
 136         if (ccer & TIM_CCER_CCXE)
 137                 return -EBUSY;
 138
 139         regmap_read(priv->regmap, TIM_CR1, &cr1);
 140         if (!(cr1 & TIM_CR1_CEN))
 141                 clk_enable(priv->clk);
 142
 143         regmap_write(priv->regmap, TIM_PSC, prescaler);
 144         regmap_write(priv->regmap, TIM_ARR, prd - 1);
 145         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE);
 146
 147         /* Force master mode to update mode */
 148         if (stm32_timer_is_trgo2_name(trig->name))
 149                 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2,
 150                                    0x2 << TIM_CR2_MMS2_SHIFT);
 151         else
 152                 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS,
 153                                    0x2 << TIM_CR2_MMS_SHIFT);
 154
 155         /* Make sure that registers are updated */
 156         regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
 157
 158         /* Enable controller */
 159         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN);
 160
 161         return 0;
 162 }
 163
 164 static void stm32_timer_stop(struct stm32_timer_trigger *priv)
 165 {
 166         u32 ccer, cr1;
 167
 168         regmap_read(priv->regmap, TIM_CCER, &ccer);
 169         if (ccer & TIM_CCER_CCXE)
 170                 return;
 171
 172         regmap_read(priv->regmap, TIM_CR1, &cr1);
 173         if (cr1 & TIM_CR1_CEN)
 174                 clk_disable(priv->clk);
 175
 176         /* Stop timer */
 177         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
 178         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0);
 179         regmap_write(priv->regmap, TIM_PSC, 0);
 180         regmap_write(priv->regmap, TIM_ARR, 0);
 181
 182         /* Make sure that registers are updated */
 183         regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG);
 184 }
 185
 186 static ssize_t stm32_tt_store_frequency(struct device *dev,
 187                                         struct device_attribute *attr,
 188                                         const char *buf, size_t len)
 189 {
 190         struct iio_trigger *trig = to_iio_trigger(dev);
 191         struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
 192         unsigned int freq;
 193         int ret;
 194
 195         ret = kstrtouint(buf, 10, &freq);
 196         if (ret)
 197                 return ret;
 198
 199         if (freq == 0) {
 200                 stm32_timer_stop(priv);
 201         } else {
 202                 ret = stm32_timer_start(priv, trig, freq);
 203                 if (ret)
 204                         return ret;
 205         }
 206
 207         return len;
 208 }
 209
 210 static ssize_t stm32_tt_read_frequency(struct device *dev,
 211                                        struct device_attribute *attr, char *buf)
 212 {
 213         struct iio_trigger *trig = to_iio_trigger(dev);
 214         struct stm32_timer_trigger *priv = iio_trigger_get_drvdata(trig);
 215         u32 psc, arr, cr1;
 216         unsigned long long freq = 0;
 217
 218         regmap_read(priv->regmap, TIM_CR1, &cr1);
 219         regmap_read(priv->regmap, TIM_PSC, &psc);
 220         regmap_read(priv->regmap, TIM_ARR, &arr);
 221
 222         if (cr1 & TIM_CR1_CEN) {
 223                 freq = (unsigned long long)clk_get_rate(priv->clk);
 224                 do_div(freq, psc + 1);
 225                 do_div(freq, arr + 1);
 226         }
 227
 228         return sprintf(buf, "%d\n", (unsigned int)freq);
 229 }
 230
 231 static IIO_DEV_ATTR_SAMP_FREQ(0660,
 232                               stm32_tt_read_frequency,
 233                               stm32_tt_store_frequency);
 234
 235 #define MASTER_MODE_MAX         7
 236 #define MASTER_MODE2_MAX        15
 237
 238 static char *master_mode_table[] = {
 239         "reset",
 240         "enable",
 241         "update",
 242         "compare_pulse",
 243         "OC1REF",
 244         "OC2REF",
 245         "OC3REF",
 246         "OC4REF",
 247         /* Master mode selection 2 only */
 248         "OC5REF",
 249         "OC6REF",
 250         "compare_pulse_OC4REF",
 251         "compare_pulse_OC6REF",
 252         "compare_pulse_OC4REF_r_or_OC6REF_r",
 253         "compare_pulse_OC4REF_r_or_OC6REF_f",
 254         "compare_pulse_OC5REF_r_or_OC6REF_r",
 255         "compare_pulse_OC5REF_r_or_OC6REF_f",
 256 };
 257
 258 static ssize_t stm32_tt_show_master_mode(struct device *dev,
 259                                          struct device_attribute *attr,
 260                                          char *buf)
 261 {
 262         struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
 263         struct iio_trigger *trig = to_iio_trigger(dev);
 264         u32 cr2;
 265
 266         regmap_read(priv->regmap, TIM_CR2, &cr2);
 267
 268         if (stm32_timer_is_trgo2_name(trig->name))
 269                 cr2 = (cr2 & TIM_CR2_MMS2) >> TIM_CR2_MMS2_SHIFT;
 270         else
 271                 cr2 = (cr2 & TIM_CR2_MMS) >> TIM_CR2_MMS_SHIFT;
 272
 273         return snprintf(buf, PAGE_SIZE, "%s\n", master_mode_table[cr2]);
 274 }
 275
 276 static ssize_t stm32_tt_store_master_mode(struct device *dev,
 277                                           struct device_attribute *attr,
 278                                           const char *buf, size_t len)
 279 {
 280         struct stm32_timer_trigger *priv = dev_get_drvdata(dev);
 281         struct iio_trigger *trig = to_iio_trigger(dev);
 282         u32 mask, shift, master_mode_max;
 283         int i;
 284
 285         if (stm32_timer_is_trgo2_name(trig->name)) {
 286                 mask = TIM_CR2_MMS2;
 287                 shift = TIM_CR2_MMS2_SHIFT;
 288                 master_mode_max = MASTER_MODE2_MAX;
 289         } else {
 290                 mask = TIM_CR2_MMS;
 291                 shift = TIM_CR2_MMS_SHIFT;
 292                 master_mode_max = MASTER_MODE_MAX;
 293         }
 294
 295         for (i = 0; i <= master_mode_max; i++) {
 296                 if (!strncmp(master_mode_table[i], buf,
 297                              strlen(master_mode_table[i]))) {
 298                         regmap_update_bits(priv->regmap, TIM_CR2, mask,
 299                                            i << shift);
 300                         return len;
 301                 }
 302         }
 303
 304         return -EINVAL;
 305 }
 306
 307 static ssize_t stm32_tt_show_master_mode_avail(struct device *dev,
 308                                                struct device_attribute *attr,
 309                                                char *buf)
 310 {
 311         struct iio_trigger *trig = to_iio_trigger(dev);
 312         unsigned int i, master_mode_max;
 313         size_t len = 0;
 314
 315         if (stm32_timer_is_trgo2_name(trig->name))
 316                 master_mode_max = MASTER_MODE2_MAX;
 317         else
 318                 master_mode_max = MASTER_MODE_MAX;
 319
 320         for (i = 0; i <= master_mode_max; i++)
 321                 len += scnprintf(buf + len, PAGE_SIZE - len,
 322                         "%s ", master_mode_table[i]);
 323
 324         /* replace trailing space by newline */
 325         buf[len - 1] = '\n';
 326
 327         return len;
 328 }
 329
 330 static IIO_DEVICE_ATTR(master_mode_available, 0444,
 331                        stm32_tt_show_master_mode_avail, NULL, 0);
 332
 333 static IIO_DEVICE_ATTR(master_mode, 0660,
 334                        stm32_tt_show_master_mode,
 335                        stm32_tt_store_master_mode,
 336                        0);
 337
 338 static struct attribute *stm32_trigger_attrs[] = {
 339         &iio_dev_attr_sampling_frequency.dev_attr.attr,
 340         &iio_dev_attr_master_mode.dev_attr.attr,
 341         &iio_dev_attr_master_mode_available.dev_attr.attr,
 342         NULL,
 343 };
 344
 345 static const struct attribute_group stm32_trigger_attr_group = {
 346         .attrs = stm32_trigger_attrs,
 347 };
 348
 349 static const struct attribute_group *stm32_trigger_attr_groups[] = {
 350         &stm32_trigger_attr_group,
 351         NULL,
 352 };
 353
 354 static const struct iio_trigger_ops timer_trigger_ops = {
 355 };
 356
 357 static int stm32_setup_iio_triggers(struct stm32_timer_trigger *priv)
 358 {
 359         int ret;
 360         const char * const *cur = priv->triggers;
 361
 362         while (cur && *cur) {
 363                 struct iio_trigger *trig;
 364                 bool cur_is_trgo = stm32_timer_is_trgo_name(*cur);
 365                 bool cur_is_trgo2 = stm32_timer_is_trgo2_name(*cur);
 366
 367                 if (cur_is_trgo2 && !priv->has_trgo2) {
 368                         cur++;
 369                         continue;
 370                 }
 371
 372                 trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur);
 373                 if  (!trig)
 374                         return -ENOMEM;
 375
 376                 trig->dev.parent = priv->dev->parent;
 377                 trig->ops = &timer_trigger_ops;
 378
 379                 /*
 380                  * sampling frequency and master mode attributes
 381                  * should only be available on trgo/trgo2 triggers
 382                  */
 383                 if (cur_is_trgo || cur_is_trgo2)
 384                         trig->dev.groups = stm32_trigger_attr_groups;
 385
 386                 iio_trigger_set_drvdata(trig, priv);
 387
 388                 ret = devm_iio_trigger_register(priv->dev, trig);
 389                 if (ret)
 390                         return ret;
 391                 cur++;
 392         }
 393
 394         return 0;
 395 }
 396
 397 static int stm32_counter_read_raw(struct iio_dev *indio_dev,
 398                                   struct iio_chan_spec const *chan,
 399                                   int *val, int *val2, long mask)
 400 {
 401         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 402         u32 dat;
 403
 404         switch (mask) {
 405         case IIO_CHAN_INFO_RAW:
 406                 regmap_read(priv->regmap, TIM_CNT, &dat);
 407                 *val = dat;
 408                 return IIO_VAL_INT;
 409
 410         case IIO_CHAN_INFO_ENABLE:
 411                 regmap_read(priv->regmap, TIM_CR1, &dat);
 412                 *val = (dat & TIM_CR1_CEN) ? 1 : 0;
 413                 return IIO_VAL_INT;
 414
 415         case IIO_CHAN_INFO_SCALE:
 416                 regmap_read(priv->regmap, TIM_SMCR, &dat);
 417                 dat &= TIM_SMCR_SMS;
 418
 419                 *val = 1;
 420                 *val2 = 0;
 421
 422                 /* in quadrature case scale = 0.25 */
 423                 if (dat == 3)
 424                         *val2 = 2;
 425
 426                 return IIO_VAL_FRACTIONAL_LOG2;
 427         }
 428
 429         return -EINVAL;
 430 }
 431
 432 static int stm32_counter_write_raw(struct iio_dev *indio_dev,
 433                                    struct iio_chan_spec const *chan,
 434                                    int val, int val2, long mask)
 435 {
 436         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 437         u32 dat;
 438
 439         switch (mask) {
 440         case IIO_CHAN_INFO_RAW:
 441                 return regmap_write(priv->regmap, TIM_CNT, val);
 442
 443         case IIO_CHAN_INFO_SCALE:
 444                 /* fixed scale */
 445                 return -EINVAL;
 446
 447         case IIO_CHAN_INFO_ENABLE:
 448                 if (val) {
 449                         regmap_read(priv->regmap, TIM_CR1, &dat);
 450                         if (!(dat & TIM_CR1_CEN))
 451                                 clk_enable(priv->clk);
 452                         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
 453                                            TIM_CR1_CEN);
 454                 } else {
 455                         regmap_read(priv->regmap, TIM_CR1, &dat);
 456                         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN,
 457                                            0);
 458                         if (dat & TIM_CR1_CEN)
 459                                 clk_disable(priv->clk);
 460                 }
 461                 return 0;
 462         }
 463
 464         return -EINVAL;
 465 }
 466
 467 static int stm32_counter_validate_trigger(struct iio_dev *indio_dev,
 468                                           struct iio_trigger *trig)
 469 {
 470         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 471         const char * const *cur = priv->valids;
 472         unsigned int i = 0;
 473
 474         if (!is_stm32_timer_trigger(trig))
 475                 return -EINVAL;
 476
 477         while (cur && *cur) {
 478                 if (!strncmp(trig->name, *cur, strlen(trig->name))) {
 479                         regmap_update_bits(priv->regmap,
 480                                            TIM_SMCR, TIM_SMCR_TS,
 481                                            i << TIM_SMCR_TS_SHIFT);
 482                         return 0;
 483                 }
 484                 cur++;
 485                 i++;
 486         }
 487
 488         return -EINVAL;
 489 }
 490
 491 static const struct iio_info stm32_trigger_info = {
 492         .validate_trigger = stm32_counter_validate_trigger,
 493         .read_raw = stm32_counter_read_raw,
 494         .write_raw = stm32_counter_write_raw
 495 };
 496
 497 static const char *const stm32_trigger_modes[] = {
 498         "trigger",
 499 };
 500
 501 static int stm32_set_trigger_mode(struct iio_dev *indio_dev,
 502                                   const struct iio_chan_spec *chan,
 503                                   unsigned int mode)
 504 {
 505         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 506
 507         regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, TIM_SMCR_SMS);
 508
 509         return 0;
 510 }
 511
 512 static int stm32_get_trigger_mode(struct iio_dev *indio_dev,
 513                                   const struct iio_chan_spec *chan)
 514 {
 515         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 516         u32 smcr;
 517
 518         regmap_read(priv->regmap, TIM_SMCR, &smcr);
 519
 520         return (smcr & TIM_SMCR_SMS) == TIM_SMCR_SMS ? 0 : -EINVAL;
 521 }
 522
 523 static const struct iio_enum stm32_trigger_mode_enum = {
 524         .items = stm32_trigger_modes,
 525         .num_items = ARRAY_SIZE(stm32_trigger_modes),
 526         .set = stm32_set_trigger_mode,
 527         .get = stm32_get_trigger_mode
 528 };
 529
 530 static const char *const stm32_enable_modes[] = {
 531         "always",
 532         "gated",
 533         "triggered",
 534 };
 535
 536 static int stm32_enable_mode2sms(int mode)
 537 {
 538         switch (mode) {
 539         case 0:
 540                 return 0;
 541         case 1:
 542                 return 5;
 543         case 2:
 544                 return 6;
 545         }
 546
 547         return -EINVAL;
 548 }
 549
 550 static int stm32_set_enable_mode(struct iio_dev *indio_dev,
 551                                  const struct iio_chan_spec *chan,
 552                                  unsigned int mode)
 553 {
 554         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 555         int sms = stm32_enable_mode2sms(mode);
 556         u32 val;
 557
 558         if (sms < 0)
 559                 return sms;
 560         /*
 561          * Triggered mode sets CEN bit automatically by hardware. So, first
 562          * enable counter clock, so it can use it. Keeps it in sync with CEN.
 563          */
 564         if (sms == 6) {
 565                 regmap_read(priv->regmap, TIM_CR1, &val);
 566                 if (!(val & TIM_CR1_CEN))
 567                         clk_enable(priv->clk);
 568         }
 569
 570         regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms);
 571
 572         return 0;
 573 }
 574
 575 static int stm32_sms2enable_mode(int mode)
 576 {
 577         switch (mode) {
 578         case 0:
 579                 return 0;
 580         case 5:
 581                 return 1;
 582         case 6:
 583                 return 2;
 584         }
 585
 586         return -EINVAL;
 587 }
 588
 589 static int stm32_get_enable_mode(struct iio_dev *indio_dev,
 590                                  const struct iio_chan_spec *chan)
 591 {
 592         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 593         u32 smcr;
 594
 595         regmap_read(priv->regmap, TIM_SMCR, &smcr);
 596         smcr &= TIM_SMCR_SMS;
 597
 598         return stm32_sms2enable_mode(smcr);
 599 }
 600
 601 static const struct iio_enum stm32_enable_mode_enum = {
 602         .items = stm32_enable_modes,
 603         .num_items = ARRAY_SIZE(stm32_enable_modes),
 604         .set = stm32_set_enable_mode,
 605         .get = stm32_get_enable_mode
 606 };
 607
 608 static ssize_t stm32_count_get_preset(struct iio_dev *indio_dev,
 609                                       uintptr_t private,
 610                                       const struct iio_chan_spec *chan,
 611                                       char *buf)
 612 {
 613         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 614         u32 arr;
 615
 616         regmap_read(priv->regmap, TIM_ARR, &arr);
 617
 618         return snprintf(buf, PAGE_SIZE, "%u\n", arr);
 619 }
 620
 621 static ssize_t stm32_count_set_preset(struct iio_dev *indio_dev,
 622                                       uintptr_t private,
 623                                       const struct iio_chan_spec *chan,
 624                                       const char *buf, size_t len)
 625 {
 626         struct stm32_timer_trigger *priv = iio_priv(indio_dev);
 627         unsigned int preset;
 628         int ret;
 629
 630         ret = kstrtouint(buf, 0, &preset);
 631         if (ret)
 632                 return ret;
 633
 634         /* TIMx_ARR register shouldn't be buffered (ARPE=0) */
 635         regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0);
 636         regmap_write(priv->regmap, TIM_ARR, preset);
 637
 638         return len;
 639 }
 640
 641 static const struct iio_chan_spec_ext_info stm32_trigger_count_info[] = {
 642         {
 643                 .name = "preset",
 644                 .shared = IIO_SEPARATE,
 645                 .read = stm32_count_get_preset,
 646                 .write = stm32_count_set_preset
 647         },
 648         IIO_ENUM("enable_mode", IIO_SEPARATE, &stm32_enable_mode_enum),
 649         IIO_ENUM_AVAILABLE("enable_mode", &stm32_enable_mode_enum),
 650         IIO_ENUM("trigger_mode", IIO_SEPARATE, &stm32_trigger_mode_enum),
 651         IIO_ENUM_AVAILABLE("trigger_mode", &stm32_trigger_mode_enum),
 652         {}
 653 };
 654
 655 static const struct iio_chan_spec stm32_trigger_channel = {
 656         .type = IIO_COUNT,
 657         .channel = 0,
 658         .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) |
 659                               BIT(IIO_CHAN_INFO_ENABLE) |
 660                               BIT(IIO_CHAN_INFO_SCALE),
 661         .ext_info = stm32_trigger_count_info,
 662         .indexed = 1
 663 };
 664
 665 static struct stm32_timer_trigger *stm32_setup_counter_device(struct device *dev)
 666 {
 667         struct iio_dev *indio_dev;
 668         int ret;
 669
 670         indio_dev = devm_iio_device_alloc(dev,
 671                                           sizeof(struct stm32_timer_trigger));
 672         if (!indio_dev)
 673                 return NULL;
 674
 675         indio_dev->name = dev_name(dev);
 676         indio_dev->dev.parent = dev;
 677         indio_dev->info = &stm32_trigger_info;
 678         indio_dev->modes = INDIO_HARDWARE_TRIGGERED;
 679         indio_dev->num_channels = 1;
 680         indio_dev->channels = &stm32_trigger_channel;
 681         indio_dev->dev.of_node = dev->of_node;
 682
 683         ret = devm_iio_device_register(dev, indio_dev);
 684         if (ret)
 685                 return NULL;
 686
 687         return iio_priv(indio_dev);
 688 }
 689
 690 /**
 691  * is_stm32_timer_trigger
 692  * @trig: trigger to be checked
 693  *
 694  * return true if the trigger is a valid stm32 iio timer trigger
 695  * either return false
 696  */
 697 bool is_stm32_timer_trigger(struct iio_trigger *trig)
 698 {
 699         return (trig->ops == &timer_trigger_ops);
 700 }
 701 EXPORT_SYMBOL(is_stm32_timer_trigger);
 702
 703 static void stm32_timer_detect_trgo2(struct stm32_timer_trigger *priv)
 704 {
 705         u32 val;
 706
 707         /*
 708          * Master mode selection 2 bits can only be written and read back when
 709          * timer supports it.
 710          */
 711         regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, TIM_CR2_MMS2);
 712         regmap_read(priv->regmap, TIM_CR2, &val);
 713         regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0);
 714         priv->has_trgo2 = !!val;
 715 }
 716
 717 static int stm32_timer_trigger_probe(struct platform_device *pdev)
 718 {
 719         struct device *dev = &pdev->dev;
 720         struct stm32_timer_trigger *priv;
 721         struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent);
 722         const struct stm32_timer_trigger_cfg *cfg;
 723         unsigned int index;
 724         int ret;
 725
 726         if (of_property_read_u32(dev->of_node, "reg", &index))
 727                 return -EINVAL;
 728
 729         cfg = (const struct stm32_timer_trigger_cfg *)
 730                 of_match_device(dev->driver->of_match_table, dev)->data;
 731
 732         if (index >= ARRAY_SIZE(triggers_table) ||
 733             index >= cfg->num_valids_table)
 734                 return -EINVAL;
 735
 736         /* Create an IIO device only if we have triggers to be validated */
 737         if (*cfg->valids_table[index])
 738                 priv = stm32_setup_counter_device(dev);
 739         else
 740                 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 741
 742         if (!priv)
 743                 return -ENOMEM;
 744
 745         priv->dev = dev;
 746         priv->regmap = ddata->regmap;
 747         priv->clk = ddata->clk;
 748         priv->max_arr = ddata->max_arr;
 749         priv->triggers = triggers_table[index];
 750         priv->valids = cfg->valids_table[index];
 751         stm32_timer_detect_trgo2(priv);
 752
 753         ret = stm32_setup_iio_triggers(priv);
 754         if (ret)
 755                 return ret;
 756
 757         platform_set_drvdata(pdev, priv);
 758
 759         return 0;
 760 }
 761
 762 static const struct stm32_timer_trigger_cfg stm32_timer_trg_cfg = {
 763         .valids_table = valids_table,
 764         .num_valids_table = ARRAY_SIZE(valids_table),
 765 };
 766
 767 static const struct stm32_timer_trigger_cfg stm32h7_timer_trg_cfg = {
 768         .valids_table = stm32h7_valids_table,
 769         .num_valids_table = ARRAY_SIZE(stm32h7_valids_table),
 770 };
 771
 772 static const struct of_device_id stm32_trig_of_match[] = {
 773         {
 774                 .compatible = "st,stm32-timer-trigger",
 775                 .data = (void *)&stm32_timer_trg_cfg,
 776         }, {
 777                 .compatible = "st,stm32h7-timer-trigger",
 778                 .data = (void *)&stm32h7_timer_trg_cfg,
 779         },
 780         { /* end node */ },
 781 };
 782 MODULE_DEVICE_TABLE(of, stm32_trig_of_match);
 783
 784 static struct platform_driver stm32_timer_trigger_driver = {
 785         .probe = stm32_timer_trigger_probe,
 786         .driver = {
 787                 .name = "stm32-timer-trigger",
 788                 .of_match_table = stm32_trig_of_match,
 789         },
 790 };
 791 module_platform_driver(stm32_timer_trigger_driver);
 792
 793 MODULE_ALIAS("platform: stm32-timer-trigger");
 794 MODULE_DESCRIPTION("STMicroelectronics STM32 Timer Trigger driver");
 795 MODULE_LICENSE("GPL v2");