drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c

   1 /*
   2  * Copyright 2014 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24
  25 #include <linux/delay.h>
  26 #include <linux/firmware.h>
  27 #include <linux/module.h>
  28
  29 #include "amdgpu.h"
  30 #include "amdgpu_ucode.h"
  31 #include "amdgpu_trace.h"
  32 #include "vi.h"
  33 #include "vid.h"
  34
  35 #include "oss/oss_3_0_d.h"
  36 #include "oss/oss_3_0_sh_mask.h"
  37
  38 #include "gmc/gmc_8_1_d.h"
  39 #include "gmc/gmc_8_1_sh_mask.h"
  40
  41 #include "gca/gfx_8_0_d.h"
  42 #include "gca/gfx_8_0_enum.h"
  43 #include "gca/gfx_8_0_sh_mask.h"
  44
  45 #include "bif/bif_5_0_d.h"
  46 #include "bif/bif_5_0_sh_mask.h"
  47
  48 #include "tonga_sdma_pkt_open.h"
  49
  50 #include "ivsrcid/ivsrcid_vislands30.h"
  51
  52 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev);
  53 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev);
  54 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev);
  55 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev);
  56
  57 MODULE_FIRMWARE("amdgpu/tonga_sdma.bin");
  58 MODULE_FIRMWARE("amdgpu/tonga_sdma1.bin");
  59 MODULE_FIRMWARE("amdgpu/carrizo_sdma.bin");
  60 MODULE_FIRMWARE("amdgpu/carrizo_sdma1.bin");
  61 MODULE_FIRMWARE("amdgpu/fiji_sdma.bin");
  62 MODULE_FIRMWARE("amdgpu/fiji_sdma1.bin");
  63 MODULE_FIRMWARE("amdgpu/stoney_sdma.bin");
  64 MODULE_FIRMWARE("amdgpu/polaris10_sdma.bin");
  65 MODULE_FIRMWARE("amdgpu/polaris10_sdma1.bin");
  66 MODULE_FIRMWARE("amdgpu/polaris11_sdma.bin");
  67 MODULE_FIRMWARE("amdgpu/polaris11_sdma1.bin");
  68 MODULE_FIRMWARE("amdgpu/polaris12_sdma.bin");
  69 MODULE_FIRMWARE("amdgpu/polaris12_sdma1.bin");
  70 MODULE_FIRMWARE("amdgpu/vegam_sdma.bin");
  71 MODULE_FIRMWARE("amdgpu/vegam_sdma1.bin");
  72
  73
  74 static const u32 sdma_offsets[SDMA_MAX_INSTANCE] =
  75 {
  76         SDMA0_REGISTER_OFFSET,
  77         SDMA1_REGISTER_OFFSET
  78 };
  79
  80 static const u32 golden_settings_tonga_a11[] =
  81 {
  82         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
  83         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
  84         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  85         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  86         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  87         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
  88         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
  89         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
  90         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
  91         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
  92 };
  93
  94 static const u32 tonga_mgcg_cgcg_init[] =
  95 {
  96         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
  97         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
  98 };
  99
 100 static const u32 golden_settings_fiji_a10[] =
 101 {
 102         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 103         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 104         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 105         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 106         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 107         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 108         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 109         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 110 };
 111
 112 static const u32 fiji_mgcg_cgcg_init[] =
 113 {
 114         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
 115         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
 116 };
 117
 118 static const u32 golden_settings_polaris11_a11[] =
 119 {
 120         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 121         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 122         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 123         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 124         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 125         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 126         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 127         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 128         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 129         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 130 };
 131
 132 static const u32 golden_settings_polaris10_a11[] =
 133 {
 134         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 135         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 136         mmSDMA0_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 137         mmSDMA0_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 138         mmSDMA0_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 139         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 140         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 141         mmSDMA1_GFX_IB_CNTL, 0x800f0111, 0x00000100,
 142         mmSDMA1_RLC0_IB_CNTL, 0x800f0111, 0x00000100,
 143         mmSDMA1_RLC1_IB_CNTL, 0x800f0111, 0x00000100,
 144 };
 145
 146 static const u32 cz_golden_settings_a11[] =
 147 {
 148         mmSDMA0_CHICKEN_BITS, 0xfc910007, 0x00810007,
 149         mmSDMA0_CLK_CTRL, 0xff000fff, 0x00000000,
 150         mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
 151         mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
 152         mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 153         mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 154         mmSDMA1_CHICKEN_BITS, 0xfc910007, 0x00810007,
 155         mmSDMA1_CLK_CTRL, 0xff000fff, 0x00000000,
 156         mmSDMA1_GFX_IB_CNTL, 0x00000100, 0x00000100,
 157         mmSDMA1_POWER_CNTL, 0x00000800, 0x0003c800,
 158         mmSDMA1_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 159         mmSDMA1_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 160 };
 161
 162 static const u32 cz_mgcg_cgcg_init[] =
 163 {
 164         mmSDMA0_CLK_CTRL, 0xff000ff0, 0x00000100,
 165         mmSDMA1_CLK_CTRL, 0xff000ff0, 0x00000100
 166 };
 167
 168 static const u32 stoney_golden_settings_a11[] =
 169 {
 170         mmSDMA0_GFX_IB_CNTL, 0x00000100, 0x00000100,
 171         mmSDMA0_POWER_CNTL, 0x00000800, 0x0003c800,
 172         mmSDMA0_RLC0_IB_CNTL, 0x00000100, 0x00000100,
 173         mmSDMA0_RLC1_IB_CNTL, 0x00000100, 0x00000100,
 174 };
 175
 176 static const u32 stoney_mgcg_cgcg_init[] =
 177 {
 178         mmSDMA0_CLK_CTRL, 0xffffffff, 0x00000100,
 179 };
 180
 181 /*
 182  * sDMA - System DMA
 183  * Starting with CIK, the GPU has new asynchronous
 184  * DMA engines.  These engines are used for compute
 185  * and gfx.  There are two DMA engines (SDMA0, SDMA1)
 186  * and each one supports 1 ring buffer used for gfx
 187  * and 2 queues used for compute.
 188  *
 189  * The programming model is very similar to the CP
 190  * (ring buffer, IBs, etc.), but sDMA has it's own
 191  * packet format that is different from the PM4 format
 192  * used by the CP. sDMA supports copying data, writing
 193  * embedded data, solid fills, and a number of other
 194  * things.  It also has support for tiling/detiling of
 195  * buffers.
 196  */
 197
 198 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev)
 199 {
 200         switch (adev->asic_type) {
 201         case CHIP_FIJI:
 202                 amdgpu_device_program_register_sequence(adev,
 203                                                         fiji_mgcg_cgcg_init,
 204                                                         ARRAY_SIZE(fiji_mgcg_cgcg_init));
 205                 amdgpu_device_program_register_sequence(adev,
 206                                                         golden_settings_fiji_a10,
 207                                                         ARRAY_SIZE(golden_settings_fiji_a10));
 208                 break;
 209         case CHIP_TONGA:
 210                 amdgpu_device_program_register_sequence(adev,
 211                                                         tonga_mgcg_cgcg_init,
 212                                                         ARRAY_SIZE(tonga_mgcg_cgcg_init));
 213                 amdgpu_device_program_register_sequence(adev,
 214                                                         golden_settings_tonga_a11,
 215                                                         ARRAY_SIZE(golden_settings_tonga_a11));
 216                 break;
 217         case CHIP_POLARIS11:
 218         case CHIP_POLARIS12:
 219         case CHIP_VEGAM:
 220                 amdgpu_device_program_register_sequence(adev,
 221                                                         golden_settings_polaris11_a11,
 222                                                         ARRAY_SIZE(golden_settings_polaris11_a11));
 223                 break;
 224         case CHIP_POLARIS10:
 225                 amdgpu_device_program_register_sequence(adev,
 226                                                         golden_settings_polaris10_a11,
 227                                                         ARRAY_SIZE(golden_settings_polaris10_a11));
 228                 break;
 229         case CHIP_CARRIZO:
 230                 amdgpu_device_program_register_sequence(adev,
 231                                                         cz_mgcg_cgcg_init,
 232                                                         ARRAY_SIZE(cz_mgcg_cgcg_init));
 233                 amdgpu_device_program_register_sequence(adev,
 234                                                         cz_golden_settings_a11,
 235                                                         ARRAY_SIZE(cz_golden_settings_a11));
 236                 break;
 237         case CHIP_STONEY:
 238                 amdgpu_device_program_register_sequence(adev,
 239                                                         stoney_mgcg_cgcg_init,
 240                                                         ARRAY_SIZE(stoney_mgcg_cgcg_init));
 241                 amdgpu_device_program_register_sequence(adev,
 242                                                         stoney_golden_settings_a11,
 243                                                         ARRAY_SIZE(stoney_golden_settings_a11));
 244                 break;
 245         default:
 246                 break;
 247         }
 248 }
 249
 250 static void sdma_v3_0_free_microcode(struct amdgpu_device *adev)
 251 {
 252         int i;
 253
 254         for (i = 0; i < adev->sdma.num_instances; i++)
 255                 amdgpu_ucode_release(&adev->sdma.instance[i].fw);
 256 }
 257
 258 /**
 259  * sdma_v3_0_init_microcode - load ucode images from disk
 260  *
 261  * @adev: amdgpu_device pointer
 262  *
 263  * Use the firmware interface to load the ucode images into
 264  * the driver (not loaded into hw).
 265  * Returns 0 on success, error on failure.
 266  */
 267 static int sdma_v3_0_init_microcode(struct amdgpu_device *adev)
 268 {
 269         const char *chip_name;
 270         char fw_name[30];
 271         int err = 0, i;
 272         struct amdgpu_firmware_info *info = NULL;
 273         const struct common_firmware_header *header = NULL;
 274         const struct sdma_firmware_header_v1_0 *hdr;
 275
 276         DRM_DEBUG("\n");
 277
 278         switch (adev->asic_type) {
 279         case CHIP_TONGA:
 280                 chip_name = "tonga";
 281                 break;
 282         case CHIP_FIJI:
 283                 chip_name = "fiji";
 284                 break;
 285         case CHIP_POLARIS10:
 286                 chip_name = "polaris10";
 287                 break;
 288         case CHIP_POLARIS11:
 289                 chip_name = "polaris11";
 290                 break;
 291         case CHIP_POLARIS12:
 292                 chip_name = "polaris12";
 293                 break;
 294         case CHIP_VEGAM:
 295                 chip_name = "vegam";
 296                 break;
 297         case CHIP_CARRIZO:
 298                 chip_name = "carrizo";
 299                 break;
 300         case CHIP_STONEY:
 301                 chip_name = "stoney";
 302                 break;
 303         default: BUG();
 304         }
 305
 306         for (i = 0; i < adev->sdma.num_instances; i++) {
 307                 if (i == 0)
 308                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma.bin", chip_name);
 309                 else
 310                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_sdma1.bin", chip_name);
 311                 err = amdgpu_ucode_request(adev, &adev->sdma.instance[i].fw, fw_name);
 312                 if (err)
 313                         goto out;
 314                 hdr = (const struct sdma_firmware_header_v1_0 *)adev->sdma.instance[i].fw->data;
 315                 adev->sdma.instance[i].fw_version = le32_to_cpu(hdr->header.ucode_version);
 316                 adev->sdma.instance[i].feature_version = le32_to_cpu(hdr->ucode_feature_version);
 317                 if (adev->sdma.instance[i].feature_version >= 20)
 318                         adev->sdma.instance[i].burst_nop = true;
 319
 320                 info = &adev->firmware.ucode[AMDGPU_UCODE_ID_SDMA0 + i];
 321                 info->ucode_id = AMDGPU_UCODE_ID_SDMA0 + i;
 322                 info->fw = adev->sdma.instance[i].fw;
 323                 header = (const struct common_firmware_header *)info->fw->data;
 324                 adev->firmware.fw_size +=
 325                         ALIGN(le32_to_cpu(header->ucode_size_bytes), PAGE_SIZE);
 326
 327         }
 328 out:
 329         if (err) {
 330                 pr_err("sdma_v3_0: Failed to load firmware \"%s\"\n", fw_name);
 331                 for (i = 0; i < adev->sdma.num_instances; i++)
 332                         amdgpu_ucode_release(&adev->sdma.instance[i].fw);
 333         }
 334         return err;
 335 }
 336
 337 /**
 338  * sdma_v3_0_ring_get_rptr - get the current read pointer
 339  *
 340  * @ring: amdgpu ring pointer
 341  *
 342  * Get the current rptr from the hardware (VI+).
 343  */
 344 static uint64_t sdma_v3_0_ring_get_rptr(struct amdgpu_ring *ring)
 345 {
 346         /* XXX check if swapping is necessary on BE */
 347         return *ring->rptr_cpu_addr >> 2;
 348 }
 349
 350 /**
 351  * sdma_v3_0_ring_get_wptr - get the current write pointer
 352  *
 353  * @ring: amdgpu ring pointer
 354  *
 355  * Get the current wptr from the hardware (VI+).
 356  */
 357 static uint64_t sdma_v3_0_ring_get_wptr(struct amdgpu_ring *ring)
 358 {
 359         struct amdgpu_device *adev = ring->adev;
 360         u32 wptr;
 361
 362         if (ring->use_doorbell || ring->use_pollmem) {
 363                 /* XXX check if swapping is necessary on BE */
 364                 wptr = *ring->wptr_cpu_addr >> 2;
 365         } else {
 366                 wptr = RREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me]) >> 2;
 367         }
 368
 369         return wptr;
 370 }
 371
 372 /**
 373  * sdma_v3_0_ring_set_wptr - commit the write pointer
 374  *
 375  * @ring: amdgpu ring pointer
 376  *
 377  * Write the wptr back to the hardware (VI+).
 378  */
 379 static void sdma_v3_0_ring_set_wptr(struct amdgpu_ring *ring)
 380 {
 381         struct amdgpu_device *adev = ring->adev;
 382
 383         if (ring->use_doorbell) {
 384                 u32 *wb = (u32 *)ring->wptr_cpu_addr;
 385                 /* XXX check if swapping is necessary on BE */
 386                 WRITE_ONCE(*wb, ring->wptr << 2);
 387                 WDOORBELL32(ring->doorbell_index, ring->wptr << 2);
 388         } else if (ring->use_pollmem) {
 389                 u32 *wb = (u32 *)ring->wptr_cpu_addr;
 390
 391                 WRITE_ONCE(*wb, ring->wptr << 2);
 392         } else {
 393                 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], ring->wptr << 2);
 394         }
 395 }
 396
 397 static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
 398 {
 399         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
 400         int i;
 401
 402         for (i = 0; i < count; i++)
 403                 if (sdma && sdma->burst_nop && (i == 0))
 404                         amdgpu_ring_write(ring, ring->funcs->nop |
 405                                 SDMA_PKT_NOP_HEADER_COUNT(count - 1));
 406                 else
 407                         amdgpu_ring_write(ring, ring->funcs->nop);
 408 }
 409
 410 /**
 411  * sdma_v3_0_ring_emit_ib - Schedule an IB on the DMA engine
 412  *
 413  * @ring: amdgpu ring pointer
 414  * @job: job to retrieve vmid from
 415  * @ib: IB object to schedule
 416  * @flags: unused
 417  *
 418  * Schedule an IB in the DMA ring (VI).
 419  */
 420 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
 421                                    struct amdgpu_job *job,
 422                                    struct amdgpu_ib *ib,
 423                                    uint32_t flags)
 424 {
 425         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
 426
 427         /* IB packet must end on a 8 DW boundary */
 428         sdma_v3_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7);
 429
 430         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
 431                           SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
 432         /* base must be 32 byte aligned */
 433         amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
 434         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
 435         amdgpu_ring_write(ring, ib->length_dw);
 436         amdgpu_ring_write(ring, 0);
 437         amdgpu_ring_write(ring, 0);
 438
 439 }
 440
 441 /**
 442  * sdma_v3_0_ring_emit_hdp_flush - emit an hdp flush on the DMA ring
 443  *
 444  * @ring: amdgpu ring pointer
 445  *
 446  * Emit an hdp flush packet on the requested DMA ring.
 447  */
 448 static void sdma_v3_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
 449 {
 450         u32 ref_and_mask = 0;
 451
 452         if (ring->me == 0)
 453                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA0, 1);
 454         else
 455                 ref_and_mask = REG_SET_FIELD(ref_and_mask, GPU_HDP_FLUSH_DONE, SDMA1, 1);
 456
 457         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
 458                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(1) |
 459                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* == */
 460         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_DONE << 2);
 461         amdgpu_ring_write(ring, mmGPU_HDP_FLUSH_REQ << 2);
 462         amdgpu_ring_write(ring, ref_and_mask); /* reference */
 463         amdgpu_ring_write(ring, ref_and_mask); /* mask */
 464         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
 465                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
 466 }
 467
 468 /**
 469  * sdma_v3_0_ring_emit_fence - emit a fence on the DMA ring
 470  *
 471  * @ring: amdgpu ring pointer
 472  * @addr: address
 473  * @seq: sequence number
 474  * @flags: fence related flags
 475  *
 476  * Add a DMA fence packet to the ring to write
 477  * the fence seq number and DMA trap packet to generate
 478  * an interrupt if needed (VI).
 479  */
 480 static void sdma_v3_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
 481                                       unsigned flags)
 482 {
 483         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
 484         /* write the fence */
 485         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 486         amdgpu_ring_write(ring, lower_32_bits(addr));
 487         amdgpu_ring_write(ring, upper_32_bits(addr));
 488         amdgpu_ring_write(ring, lower_32_bits(seq));
 489
 490         /* optionally write high bits as well */
 491         if (write64bit) {
 492                 addr += 4;
 493                 amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_FENCE));
 494                 amdgpu_ring_write(ring, lower_32_bits(addr));
 495                 amdgpu_ring_write(ring, upper_32_bits(addr));
 496                 amdgpu_ring_write(ring, upper_32_bits(seq));
 497         }
 498
 499         /* generate an interrupt */
 500         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_TRAP));
 501         amdgpu_ring_write(ring, SDMA_PKT_TRAP_INT_CONTEXT_INT_CONTEXT(0));
 502 }
 503
 504 /**
 505  * sdma_v3_0_gfx_stop - stop the gfx async dma engines
 506  *
 507  * @adev: amdgpu_device pointer
 508  *
 509  * Stop the gfx async dma ring buffers (VI).
 510  */
 511 static void sdma_v3_0_gfx_stop(struct amdgpu_device *adev)
 512 {
 513         u32 rb_cntl, ib_cntl;
 514         int i;
 515
 516         amdgpu_sdma_unset_buffer_funcs_helper(adev);
 517
 518         for (i = 0; i < adev->sdma.num_instances; i++) {
 519                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 520                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 0);
 521                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 522                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 523                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 0);
 524                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 525         }
 526 }
 527
 528 /**
 529  * sdma_v3_0_rlc_stop - stop the compute async dma engines
 530  *
 531  * @adev: amdgpu_device pointer
 532  *
 533  * Stop the compute async dma queues (VI).
 534  */
 535 static void sdma_v3_0_rlc_stop(struct amdgpu_device *adev)
 536 {
 537         /* XXX todo */
 538 }
 539
 540 /**
 541  * sdma_v3_0_ctx_switch_enable - stop the async dma engines context switch
 542  *
 543  * @adev: amdgpu_device pointer
 544  * @enable: enable/disable the DMA MEs context switch.
 545  *
 546  * Halt or unhalt the async dma engines context switch (VI).
 547  */
 548 static void sdma_v3_0_ctx_switch_enable(struct amdgpu_device *adev, bool enable)
 549 {
 550         u32 f32_cntl, phase_quantum = 0;
 551         int i;
 552
 553         if (amdgpu_sdma_phase_quantum) {
 554                 unsigned value = amdgpu_sdma_phase_quantum;
 555                 unsigned unit = 0;
 556
 557                 while (value > (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 558                                 SDMA0_PHASE0_QUANTUM__VALUE__SHIFT)) {
 559                         value = (value + 1) >> 1;
 560                         unit++;
 561                 }
 562                 if (unit > (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 563                             SDMA0_PHASE0_QUANTUM__UNIT__SHIFT)) {
 564                         value = (SDMA0_PHASE0_QUANTUM__VALUE_MASK >>
 565                                  SDMA0_PHASE0_QUANTUM__VALUE__SHIFT);
 566                         unit = (SDMA0_PHASE0_QUANTUM__UNIT_MASK >>
 567                                 SDMA0_PHASE0_QUANTUM__UNIT__SHIFT);
 568                         WARN_ONCE(1,
 569                         "clamping sdma_phase_quantum to %uK clock cycles\n",
 570                                   value << unit);
 571                 }
 572                 phase_quantum =
 573                         value << SDMA0_PHASE0_QUANTUM__VALUE__SHIFT |
 574                         unit  << SDMA0_PHASE0_QUANTUM__UNIT__SHIFT;
 575         }
 576
 577         for (i = 0; i < adev->sdma.num_instances; i++) {
 578                 f32_cntl = RREG32(mmSDMA0_CNTL + sdma_offsets[i]);
 579                 if (enable) {
 580                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 581                                         AUTO_CTXSW_ENABLE, 1);
 582                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 583                                         ATC_L1_ENABLE, 1);
 584                         if (amdgpu_sdma_phase_quantum) {
 585                                 WREG32(mmSDMA0_PHASE0_QUANTUM + sdma_offsets[i],
 586                                        phase_quantum);
 587                                 WREG32(mmSDMA0_PHASE1_QUANTUM + sdma_offsets[i],
 588                                        phase_quantum);
 589                         }
 590                 } else {
 591                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 592                                         AUTO_CTXSW_ENABLE, 0);
 593                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_CNTL,
 594                                         ATC_L1_ENABLE, 1);
 595                 }
 596
 597                 WREG32(mmSDMA0_CNTL + sdma_offsets[i], f32_cntl);
 598         }
 599 }
 600
 601 /**
 602  * sdma_v3_0_enable - stop the async dma engines
 603  *
 604  * @adev: amdgpu_device pointer
 605  * @enable: enable/disable the DMA MEs.
 606  *
 607  * Halt or unhalt the async dma engines (VI).
 608  */
 609 static void sdma_v3_0_enable(struct amdgpu_device *adev, bool enable)
 610 {
 611         u32 f32_cntl;
 612         int i;
 613
 614         if (!enable) {
 615                 sdma_v3_0_gfx_stop(adev);
 616                 sdma_v3_0_rlc_stop(adev);
 617         }
 618
 619         for (i = 0; i < adev->sdma.num_instances; i++) {
 620                 f32_cntl = RREG32(mmSDMA0_F32_CNTL + sdma_offsets[i]);
 621                 if (enable)
 622                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 0);
 623                 else
 624                         f32_cntl = REG_SET_FIELD(f32_cntl, SDMA0_F32_CNTL, HALT, 1);
 625                 WREG32(mmSDMA0_F32_CNTL + sdma_offsets[i], f32_cntl);
 626         }
 627 }
 628
 629 /**
 630  * sdma_v3_0_gfx_resume - setup and start the async dma engines
 631  *
 632  * @adev: amdgpu_device pointer
 633  *
 634  * Set up the gfx DMA ring buffers and enable them (VI).
 635  * Returns 0 for success, error for failure.
 636  */
 637 static int sdma_v3_0_gfx_resume(struct amdgpu_device *adev)
 638 {
 639         struct amdgpu_ring *ring;
 640         u32 rb_cntl, ib_cntl, wptr_poll_cntl;
 641         u32 rb_bufsz;
 642         u32 doorbell;
 643         u64 wptr_gpu_addr;
 644         int i, j, r;
 645
 646         for (i = 0; i < adev->sdma.num_instances; i++) {
 647                 ring = &adev->sdma.instance[i].ring;
 648                 amdgpu_ring_clear_ring(ring);
 649
 650                 mutex_lock(&adev->srbm_mutex);
 651                 for (j = 0; j < 16; j++) {
 652                         vi_srbm_select(adev, 0, 0, 0, j);
 653                         /* SDMA GFX */
 654                         WREG32(mmSDMA0_GFX_VIRTUAL_ADDR + sdma_offsets[i], 0);
 655                         WREG32(mmSDMA0_GFX_APE1_CNTL + sdma_offsets[i], 0);
 656                 }
 657                 vi_srbm_select(adev, 0, 0, 0, 0);
 658                 mutex_unlock(&adev->srbm_mutex);
 659
 660                 WREG32(mmSDMA0_TILING_CONFIG + sdma_offsets[i],
 661                        adev->gfx.config.gb_addr_config & 0x70);
 662
 663                 WREG32(mmSDMA0_SEM_WAIT_FAIL_TIMER_CNTL + sdma_offsets[i], 0);
 664
 665                 /* Set ring buffer size in dwords */
 666                 rb_bufsz = order_base_2(ring->ring_size / 4);
 667                 rb_cntl = RREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i]);
 668                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SIZE, rb_bufsz);
 669 #ifdef __BIG_ENDIAN
 670                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_SWAP_ENABLE, 1);
 671                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL,
 672                                         RPTR_WRITEBACK_SWAP_ENABLE, 1);
 673 #endif
 674                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 675
 676                 /* Initialize the ring buffer's read and write pointers */
 677                 ring->wptr = 0;
 678                 WREG32(mmSDMA0_GFX_RB_RPTR + sdma_offsets[i], 0);
 679                 sdma_v3_0_ring_set_wptr(ring);
 680                 WREG32(mmSDMA0_GFX_IB_RPTR + sdma_offsets[i], 0);
 681                 WREG32(mmSDMA0_GFX_IB_OFFSET + sdma_offsets[i], 0);
 682
 683                 /* set the wb address whether it's enabled or not */
 684                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_HI + sdma_offsets[i],
 685                        upper_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFF);
 686                 WREG32(mmSDMA0_GFX_RB_RPTR_ADDR_LO + sdma_offsets[i],
 687                        lower_32_bits(ring->rptr_gpu_addr) & 0xFFFFFFFC);
 688
 689                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RPTR_WRITEBACK_ENABLE, 1);
 690
 691                 WREG32(mmSDMA0_GFX_RB_BASE + sdma_offsets[i], ring->gpu_addr >> 8);
 692                 WREG32(mmSDMA0_GFX_RB_BASE_HI + sdma_offsets[i], ring->gpu_addr >> 40);
 693
 694                 doorbell = RREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i]);
 695
 696                 if (ring->use_doorbell) {
 697                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL,
 698                                                  OFFSET, ring->doorbell_index);
 699                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 1);
 700                 } else {
 701                         doorbell = REG_SET_FIELD(doorbell, SDMA0_GFX_DOORBELL, ENABLE, 0);
 702                 }
 703                 WREG32(mmSDMA0_GFX_DOORBELL + sdma_offsets[i], doorbell);
 704
 705                 /* setup the wptr shadow polling */
 706                 wptr_gpu_addr = ring->wptr_gpu_addr;
 707
 708                 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_LO + sdma_offsets[i],
 709                        lower_32_bits(wptr_gpu_addr));
 710                 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_ADDR_HI + sdma_offsets[i],
 711                        upper_32_bits(wptr_gpu_addr));
 712                 wptr_poll_cntl = RREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i]);
 713                 if (ring->use_pollmem) {
 714                         /*wptr polling is not enogh fast, directly clean the wptr register */
 715                         WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], 0);
 716                         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 717                                                        SDMA0_GFX_RB_WPTR_POLL_CNTL,
 718                                                        ENABLE, 1);
 719                 } else {
 720                         wptr_poll_cntl = REG_SET_FIELD(wptr_poll_cntl,
 721                                                        SDMA0_GFX_RB_WPTR_POLL_CNTL,
 722                                                        ENABLE, 0);
 723                 }
 724                 WREG32(mmSDMA0_GFX_RB_WPTR_POLL_CNTL + sdma_offsets[i], wptr_poll_cntl);
 725
 726                 /* enable DMA RB */
 727                 rb_cntl = REG_SET_FIELD(rb_cntl, SDMA0_GFX_RB_CNTL, RB_ENABLE, 1);
 728                 WREG32(mmSDMA0_GFX_RB_CNTL + sdma_offsets[i], rb_cntl);
 729
 730                 ib_cntl = RREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i]);
 731                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_ENABLE, 1);
 732 #ifdef __BIG_ENDIAN
 733                 ib_cntl = REG_SET_FIELD(ib_cntl, SDMA0_GFX_IB_CNTL, IB_SWAP_ENABLE, 1);
 734 #endif
 735                 /* enable DMA IBs */
 736                 WREG32(mmSDMA0_GFX_IB_CNTL + sdma_offsets[i], ib_cntl);
 737         }
 738
 739         /* unhalt the MEs */
 740         sdma_v3_0_enable(adev, true);
 741         /* enable sdma ring preemption */
 742         sdma_v3_0_ctx_switch_enable(adev, true);
 743
 744         for (i = 0; i < adev->sdma.num_instances; i++) {
 745                 ring = &adev->sdma.instance[i].ring;
 746                 r = amdgpu_ring_test_helper(ring);
 747                 if (r)
 748                         return r;
 749
 750                 if (adev->mman.buffer_funcs_ring == ring)
 751                         amdgpu_ttm_set_buffer_funcs_status(adev, true);
 752         }
 753
 754         return 0;
 755 }
 756
 757 /**
 758  * sdma_v3_0_rlc_resume - setup and start the async dma engines
 759  *
 760  * @adev: amdgpu_device pointer
 761  *
 762  * Set up the compute DMA queues and enable them (VI).
 763  * Returns 0 for success, error for failure.
 764  */
 765 static int sdma_v3_0_rlc_resume(struct amdgpu_device *adev)
 766 {
 767         /* XXX todo */
 768         return 0;
 769 }
 770
 771 /**
 772  * sdma_v3_0_start - setup and start the async dma engines
 773  *
 774  * @adev: amdgpu_device pointer
 775  *
 776  * Set up the DMA engines and enable them (VI).
 777  * Returns 0 for success, error for failure.
 778  */
 779 static int sdma_v3_0_start(struct amdgpu_device *adev)
 780 {
 781         int r;
 782
 783         /* disable sdma engine before programing it */
 784         sdma_v3_0_ctx_switch_enable(adev, false);
 785         sdma_v3_0_enable(adev, false);
 786
 787         /* start the gfx rings and rlc compute queues */
 788         r = sdma_v3_0_gfx_resume(adev);
 789         if (r)
 790                 return r;
 791         r = sdma_v3_0_rlc_resume(adev);
 792         if (r)
 793                 return r;
 794
 795         return 0;
 796 }
 797
 798 /**
 799  * sdma_v3_0_ring_test_ring - simple async dma engine test
 800  *
 801  * @ring: amdgpu_ring structure holding ring information
 802  *
 803  * Test the DMA engine by writing using it to write an
 804  * value to memory. (VI).
 805  * Returns 0 for success, error for failure.
 806  */
 807 static int sdma_v3_0_ring_test_ring(struct amdgpu_ring *ring)
 808 {
 809         struct amdgpu_device *adev = ring->adev;
 810         unsigned i;
 811         unsigned index;
 812         int r;
 813         u32 tmp;
 814         u64 gpu_addr;
 815
 816         r = amdgpu_device_wb_get(adev, &index);
 817         if (r)
 818                 return r;
 819
 820         gpu_addr = adev->wb.gpu_addr + (index * 4);
 821         tmp = 0xCAFEDEAD;
 822         adev->wb.wb[index] = cpu_to_le32(tmp);
 823
 824         r = amdgpu_ring_alloc(ring, 5);
 825         if (r)
 826                 goto error_free_wb;
 827
 828         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 829                           SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR));
 830         amdgpu_ring_write(ring, lower_32_bits(gpu_addr));
 831         amdgpu_ring_write(ring, upper_32_bits(gpu_addr));
 832         amdgpu_ring_write(ring, SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1));
 833         amdgpu_ring_write(ring, 0xDEADBEEF);
 834         amdgpu_ring_commit(ring);
 835
 836         for (i = 0; i < adev->usec_timeout; i++) {
 837                 tmp = le32_to_cpu(adev->wb.wb[index]);
 838                 if (tmp == 0xDEADBEEF)
 839                         break;
 840                 udelay(1);
 841         }
 842
 843         if (i >= adev->usec_timeout)
 844                 r = -ETIMEDOUT;
 845
 846 error_free_wb:
 847         amdgpu_device_wb_free(adev, index);
 848         return r;
 849 }
 850
 851 /**
 852  * sdma_v3_0_ring_test_ib - test an IB on the DMA engine
 853  *
 854  * @ring: amdgpu_ring structure holding ring information
 855  * @timeout: timeout value in jiffies, or MAX_SCHEDULE_TIMEOUT
 856  *
 857  * Test a simple IB in the DMA ring (VI).
 858  * Returns 0 on success, error on failure.
 859  */
 860 static int sdma_v3_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 861 {
 862         struct amdgpu_device *adev = ring->adev;
 863         struct amdgpu_ib ib;
 864         struct dma_fence *f = NULL;
 865         unsigned index;
 866         u32 tmp = 0;
 867         u64 gpu_addr;
 868         long r;
 869
 870         r = amdgpu_device_wb_get(adev, &index);
 871         if (r)
 872                 return r;
 873
 874         gpu_addr = adev->wb.gpu_addr + (index * 4);
 875         tmp = 0xCAFEDEAD;
 876         adev->wb.wb[index] = cpu_to_le32(tmp);
 877         memset(&ib, 0, sizeof(ib));
 878         r = amdgpu_ib_get(adev, NULL, 256,
 879                                         AMDGPU_IB_POOL_DIRECT, &ib);
 880         if (r)
 881                 goto err0;
 882
 883         ib.ptr[0] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 884                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 885         ib.ptr[1] = lower_32_bits(gpu_addr);
 886         ib.ptr[2] = upper_32_bits(gpu_addr);
 887         ib.ptr[3] = SDMA_PKT_WRITE_UNTILED_DW_3_COUNT(1);
 888         ib.ptr[4] = 0xDEADBEEF;
 889         ib.ptr[5] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 890         ib.ptr[6] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 891         ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
 892         ib.length_dw = 8;
 893
 894         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 895         if (r)
 896                 goto err1;
 897
 898         r = dma_fence_wait_timeout(f, false, timeout);
 899         if (r == 0) {
 900                 r = -ETIMEDOUT;
 901                 goto err1;
 902         } else if (r < 0) {
 903                 goto err1;
 904         }
 905         tmp = le32_to_cpu(adev->wb.wb[index]);
 906         if (tmp == 0xDEADBEEF)
 907                 r = 0;
 908         else
 909                 r = -EINVAL;
 910 err1:
 911         amdgpu_ib_free(adev, &ib, NULL);
 912         dma_fence_put(f);
 913 err0:
 914         amdgpu_device_wb_free(adev, index);
 915         return r;
 916 }
 917
 918 /**
 919  * sdma_v3_0_vm_copy_pte - update PTEs by copying them from the GART
 920  *
 921  * @ib: indirect buffer to fill with commands
 922  * @pe: addr of the page entry
 923  * @src: src addr to copy from
 924  * @count: number of page entries to update
 925  *
 926  * Update PTEs by copying them from the GART using sDMA (CIK).
 927  */
 928 static void sdma_v3_0_vm_copy_pte(struct amdgpu_ib *ib,
 929                                   uint64_t pe, uint64_t src,
 930                                   unsigned count)
 931 {
 932         unsigned bytes = count * 8;
 933
 934         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
 935                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
 936         ib->ptr[ib->length_dw++] = bytes;
 937         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
 938         ib->ptr[ib->length_dw++] = lower_32_bits(src);
 939         ib->ptr[ib->length_dw++] = upper_32_bits(src);
 940         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 941         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 942 }
 943
 944 /**
 945  * sdma_v3_0_vm_write_pte - update PTEs by writing them manually
 946  *
 947  * @ib: indirect buffer to fill with commands
 948  * @pe: addr of the page entry
 949  * @value: dst addr to write into pe
 950  * @count: number of page entries to update
 951  * @incr: increase next addr by incr bytes
 952  *
 953  * Update PTEs by writing them manually using sDMA (CIK).
 954  */
 955 static void sdma_v3_0_vm_write_pte(struct amdgpu_ib *ib, uint64_t pe,
 956                                    uint64_t value, unsigned count,
 957                                    uint32_t incr)
 958 {
 959         unsigned ndw = count * 2;
 960
 961         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_WRITE) |
 962                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_WRITE_LINEAR);
 963         ib->ptr[ib->length_dw++] = lower_32_bits(pe);
 964         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 965         ib->ptr[ib->length_dw++] = ndw;
 966         for (; ndw > 0; ndw -= 2) {
 967                 ib->ptr[ib->length_dw++] = lower_32_bits(value);
 968                 ib->ptr[ib->length_dw++] = upper_32_bits(value);
 969                 value += incr;
 970         }
 971 }
 972
 973 /**
 974  * sdma_v3_0_vm_set_pte_pde - update the page tables using sDMA
 975  *
 976  * @ib: indirect buffer to fill with commands
 977  * @pe: addr of the page entry
 978  * @addr: dst addr to write into pe
 979  * @count: number of page entries to update
 980  * @incr: increase next addr by incr bytes
 981  * @flags: access flags
 982  *
 983  * Update the page tables using sDMA (CIK).
 984  */
 985 static void sdma_v3_0_vm_set_pte_pde(struct amdgpu_ib *ib, uint64_t pe,
 986                                      uint64_t addr, unsigned count,
 987                                      uint32_t incr, uint64_t flags)
 988 {
 989         /* for physically contiguous pages (vram) */
 990         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_GEN_PTEPDE);
 991         ib->ptr[ib->length_dw++] = lower_32_bits(pe); /* dst addr */
 992         ib->ptr[ib->length_dw++] = upper_32_bits(pe);
 993         ib->ptr[ib->length_dw++] = lower_32_bits(flags); /* mask */
 994         ib->ptr[ib->length_dw++] = upper_32_bits(flags);
 995         ib->ptr[ib->length_dw++] = lower_32_bits(addr); /* value */
 996         ib->ptr[ib->length_dw++] = upper_32_bits(addr);
 997         ib->ptr[ib->length_dw++] = incr; /* increment size */
 998         ib->ptr[ib->length_dw++] = 0;
 999         ib->ptr[ib->length_dw++] = count; /* number of entries */
1000 }
1001
1002 /**
1003  * sdma_v3_0_ring_pad_ib - pad the IB to the required number of dw
1004  *
1005  * @ring: amdgpu_ring structure holding ring information
1006  * @ib: indirect buffer to fill with padding
1007  *
1008  */
1009 static void sdma_v3_0_ring_pad_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib)
1010 {
1011         struct amdgpu_sdma_instance *sdma = amdgpu_sdma_get_instance_from_ring(ring);
1012         u32 pad_count;
1013         int i;
1014
1015         pad_count = (-ib->length_dw) & 7;
1016         for (i = 0; i < pad_count; i++)
1017                 if (sdma && sdma->burst_nop && (i == 0))
1018                         ib->ptr[ib->length_dw++] =
1019                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP) |
1020                                 SDMA_PKT_NOP_HEADER_COUNT(pad_count - 1);
1021                 else
1022                         ib->ptr[ib->length_dw++] =
1023                                 SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
1024 }
1025
1026 /**
1027  * sdma_v3_0_ring_emit_pipeline_sync - sync the pipeline
1028  *
1029  * @ring: amdgpu_ring pointer
1030  *
1031  * Make sure all previous operations are completed (CIK).
1032  */
1033 static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
1034 {
1035         uint32_t seq = ring->fence_drv.sync_seq;
1036         uint64_t addr = ring->fence_drv.gpu_addr;
1037
1038         /* wait for idle */
1039         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1040                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1041                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3) | /* equal */
1042                           SDMA_PKT_POLL_REGMEM_HEADER_MEM_POLL(1));
1043         amdgpu_ring_write(ring, addr & 0xfffffffc);
1044         amdgpu_ring_write(ring, upper_32_bits(addr) & 0xffffffff);
1045         amdgpu_ring_write(ring, seq); /* reference */
1046         amdgpu_ring_write(ring, 0xffffffff); /* mask */
1047         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1048                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(4)); /* retry count, poll interval */
1049 }
1050
1051 /**
1052  * sdma_v3_0_ring_emit_vm_flush - cik vm flush using sDMA
1053  *
1054  * @ring: amdgpu_ring pointer
1055  * @vmid: vmid number to use
1056  * @pd_addr: address
1057  *
1058  * Update the page table base and flush the VM TLB
1059  * using sDMA (VI).
1060  */
1061 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
1062                                          unsigned vmid, uint64_t pd_addr)
1063 {
1064         amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
1065
1066         /* wait for flush */
1067         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |
1068                           SDMA_PKT_POLL_REGMEM_HEADER_HDP_FLUSH(0) |
1069                           SDMA_PKT_POLL_REGMEM_HEADER_FUNC(0)); /* always */
1070         amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
1071         amdgpu_ring_write(ring, 0);
1072         amdgpu_ring_write(ring, 0); /* reference */
1073         amdgpu_ring_write(ring, 0); /* mask */
1074         amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
1075                           SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10)); /* retry count, poll interval */
1076 }
1077
1078 static void sdma_v3_0_ring_emit_wreg(struct amdgpu_ring *ring,
1079                                      uint32_t reg, uint32_t val)
1080 {
1081         amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
1082                           SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
1083         amdgpu_ring_write(ring, reg);
1084         amdgpu_ring_write(ring, val);
1085 }
1086
1087 static int sdma_v3_0_early_init(void *handle)
1088 {
1089         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1090
1091         switch (adev->asic_type) {
1092         case CHIP_STONEY:
1093                 adev->sdma.num_instances = 1;
1094                 break;
1095         default:
1096                 adev->sdma.num_instances = SDMA_MAX_INSTANCE;
1097                 break;
1098         }
1099
1100         sdma_v3_0_set_ring_funcs(adev);
1101         sdma_v3_0_set_buffer_funcs(adev);
1102         sdma_v3_0_set_vm_pte_funcs(adev);
1103         sdma_v3_0_set_irq_funcs(adev);
1104
1105         return 0;
1106 }
1107
1108 static int sdma_v3_0_sw_init(void *handle)
1109 {
1110         struct amdgpu_ring *ring;
1111         int r, i;
1112         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1113
1114         /* SDMA trap event */
1115         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP,
1116                               &adev->sdma.trap_irq);
1117         if (r)
1118                 return r;
1119
1120         /* SDMA Privileged inst */
1121         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 241,
1122                               &adev->sdma.illegal_inst_irq);
1123         if (r)
1124                 return r;
1125
1126         /* SDMA Privileged inst */
1127         r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE,
1128                               &adev->sdma.illegal_inst_irq);
1129         if (r)
1130                 return r;
1131
1132         r = sdma_v3_0_init_microcode(adev);
1133         if (r) {
1134                 DRM_ERROR("Failed to load sdma firmware!\n");
1135                 return r;
1136         }
1137
1138         for (i = 0; i < adev->sdma.num_instances; i++) {
1139                 ring = &adev->sdma.instance[i].ring;
1140                 ring->ring_obj = NULL;
1141                 if (!amdgpu_sriov_vf(adev)) {
1142                         ring->use_doorbell = true;
1143                         ring->doorbell_index = adev->doorbell_index.sdma_engine[i];
1144                 } else {
1145                         ring->use_pollmem = true;
1146                 }
1147
1148                 sprintf(ring->name, "sdma%d", i);
1149                 r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq,
1150                                      (i == 0) ? AMDGPU_SDMA_IRQ_INSTANCE0 :
1151                                      AMDGPU_SDMA_IRQ_INSTANCE1,
1152                                      AMDGPU_RING_PRIO_DEFAULT, NULL);
1153                 if (r)
1154                         return r;
1155         }
1156
1157         return r;
1158 }
1159
1160 static int sdma_v3_0_sw_fini(void *handle)
1161 {
1162         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1163         int i;
1164
1165         for (i = 0; i < adev->sdma.num_instances; i++)
1166                 amdgpu_ring_fini(&adev->sdma.instance[i].ring);
1167
1168         sdma_v3_0_free_microcode(adev);
1169         return 0;
1170 }
1171
1172 static int sdma_v3_0_hw_init(void *handle)
1173 {
1174         int r;
1175         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1176
1177         sdma_v3_0_init_golden_registers(adev);
1178
1179         r = sdma_v3_0_start(adev);
1180         if (r)
1181                 return r;
1182
1183         return r;
1184 }
1185
1186 static int sdma_v3_0_hw_fini(void *handle)
1187 {
1188         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1189
1190         sdma_v3_0_ctx_switch_enable(adev, false);
1191         sdma_v3_0_enable(adev, false);
1192
1193         return 0;
1194 }
1195
1196 static int sdma_v3_0_suspend(void *handle)
1197 {
1198         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1199
1200         return sdma_v3_0_hw_fini(adev);
1201 }
1202
1203 static int sdma_v3_0_resume(void *handle)
1204 {
1205         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1206
1207         return sdma_v3_0_hw_init(adev);
1208 }
1209
1210 static bool sdma_v3_0_is_idle(void *handle)
1211 {
1212         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1213         u32 tmp = RREG32(mmSRBM_STATUS2);
1214
1215         if (tmp & (SRBM_STATUS2__SDMA_BUSY_MASK |
1216                    SRBM_STATUS2__SDMA1_BUSY_MASK))
1217             return false;
1218
1219         return true;
1220 }
1221
1222 static int sdma_v3_0_wait_for_idle(void *handle)
1223 {
1224         unsigned i;
1225         u32 tmp;
1226         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1227
1228         for (i = 0; i < adev->usec_timeout; i++) {
1229                 tmp = RREG32(mmSRBM_STATUS2) & (SRBM_STATUS2__SDMA_BUSY_MASK |
1230                                 SRBM_STATUS2__SDMA1_BUSY_MASK);
1231
1232                 if (!tmp)
1233                         return 0;
1234                 udelay(1);
1235         }
1236         return -ETIMEDOUT;
1237 }
1238
1239 static bool sdma_v3_0_check_soft_reset(void *handle)
1240 {
1241         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1242         u32 srbm_soft_reset = 0;
1243         u32 tmp = RREG32(mmSRBM_STATUS2);
1244
1245         if ((tmp & SRBM_STATUS2__SDMA_BUSY_MASK) ||
1246             (tmp & SRBM_STATUS2__SDMA1_BUSY_MASK)) {
1247                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA_MASK;
1248                 srbm_soft_reset |= SRBM_SOFT_RESET__SOFT_RESET_SDMA1_MASK;
1249         }
1250
1251         if (srbm_soft_reset) {
1252                 adev->sdma.srbm_soft_reset = srbm_soft_reset;
1253                 return true;
1254         } else {
1255                 adev->sdma.srbm_soft_reset = 0;
1256                 return false;
1257         }
1258 }
1259
1260 static int sdma_v3_0_pre_soft_reset(void *handle)
1261 {
1262         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1263         u32 srbm_soft_reset = 0;
1264
1265         if (!adev->sdma.srbm_soft_reset)
1266                 return 0;
1267
1268         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1269
1270         if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1271             REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1272                 sdma_v3_0_ctx_switch_enable(adev, false);
1273                 sdma_v3_0_enable(adev, false);
1274         }
1275
1276         return 0;
1277 }
1278
1279 static int sdma_v3_0_post_soft_reset(void *handle)
1280 {
1281         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1282         u32 srbm_soft_reset = 0;
1283
1284         if (!adev->sdma.srbm_soft_reset)
1285                 return 0;
1286
1287         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1288
1289         if (REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA) ||
1290             REG_GET_FIELD(srbm_soft_reset, SRBM_SOFT_RESET, SOFT_RESET_SDMA1)) {
1291                 sdma_v3_0_gfx_resume(adev);
1292                 sdma_v3_0_rlc_resume(adev);
1293         }
1294
1295         return 0;
1296 }
1297
1298 static int sdma_v3_0_soft_reset(void *handle)
1299 {
1300         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1301         u32 srbm_soft_reset = 0;
1302         u32 tmp;
1303
1304         if (!adev->sdma.srbm_soft_reset)
1305                 return 0;
1306
1307         srbm_soft_reset = adev->sdma.srbm_soft_reset;
1308
1309         if (srbm_soft_reset) {
1310                 tmp = RREG32(mmSRBM_SOFT_RESET);
1311                 tmp |= srbm_soft_reset;
1312                 dev_info(adev->dev, "SRBM_SOFT_RESET=0x%08X\n", tmp);
1313                 WREG32(mmSRBM_SOFT_RESET, tmp);
1314                 tmp = RREG32(mmSRBM_SOFT_RESET);
1315
1316                 udelay(50);
1317
1318                 tmp &= ~srbm_soft_reset;
1319                 WREG32(mmSRBM_SOFT_RESET, tmp);
1320                 tmp = RREG32(mmSRBM_SOFT_RESET);
1321
1322                 /* Wait a little for things to settle down */
1323                 udelay(50);
1324         }
1325
1326         return 0;
1327 }
1328
1329 static int sdma_v3_0_set_trap_irq_state(struct amdgpu_device *adev,
1330                                         struct amdgpu_irq_src *source,
1331                                         unsigned type,
1332                                         enum amdgpu_interrupt_state state)
1333 {
1334         u32 sdma_cntl;
1335
1336         switch (type) {
1337         case AMDGPU_SDMA_IRQ_INSTANCE0:
1338                 switch (state) {
1339                 case AMDGPU_IRQ_STATE_DISABLE:
1340                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1341                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1342                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1343                         break;
1344                 case AMDGPU_IRQ_STATE_ENABLE:
1345                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET);
1346                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1347                         WREG32(mmSDMA0_CNTL + SDMA0_REGISTER_OFFSET, sdma_cntl);
1348                         break;
1349                 default:
1350                         break;
1351                 }
1352                 break;
1353         case AMDGPU_SDMA_IRQ_INSTANCE1:
1354                 switch (state) {
1355                 case AMDGPU_IRQ_STATE_DISABLE:
1356                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1357                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 0);
1358                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1359                         break;
1360                 case AMDGPU_IRQ_STATE_ENABLE:
1361                         sdma_cntl = RREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET);
1362                         sdma_cntl = REG_SET_FIELD(sdma_cntl, SDMA0_CNTL, TRAP_ENABLE, 1);
1363                         WREG32(mmSDMA0_CNTL + SDMA1_REGISTER_OFFSET, sdma_cntl);
1364                         break;
1365                 default:
1366                         break;
1367                 }
1368                 break;
1369         default:
1370                 break;
1371         }
1372         return 0;
1373 }
1374
1375 static int sdma_v3_0_process_trap_irq(struct amdgpu_device *adev,
1376                                       struct amdgpu_irq_src *source,
1377                                       struct amdgpu_iv_entry *entry)
1378 {
1379         u8 instance_id, queue_id;
1380
1381         instance_id = (entry->ring_id & 0x3) >> 0;
1382         queue_id = (entry->ring_id & 0xc) >> 2;
1383         DRM_DEBUG("IH: SDMA trap\n");
1384         switch (instance_id) {
1385         case 0:
1386                 switch (queue_id) {
1387                 case 0:
1388                         amdgpu_fence_process(&adev->sdma.instance[0].ring);
1389                         break;
1390                 case 1:
1391                         /* XXX compute */
1392                         break;
1393                 case 2:
1394                         /* XXX compute */
1395                         break;
1396                 }
1397                 break;
1398         case 1:
1399                 switch (queue_id) {
1400                 case 0:
1401                         amdgpu_fence_process(&adev->sdma.instance[1].ring);
1402                         break;
1403                 case 1:
1404                         /* XXX compute */
1405                         break;
1406                 case 2:
1407                         /* XXX compute */
1408                         break;
1409                 }
1410                 break;
1411         }
1412         return 0;
1413 }
1414
1415 static int sdma_v3_0_process_illegal_inst_irq(struct amdgpu_device *adev,
1416                                               struct amdgpu_irq_src *source,
1417                                               struct amdgpu_iv_entry *entry)
1418 {
1419         u8 instance_id, queue_id;
1420
1421         DRM_ERROR("Illegal instruction in SDMA command stream\n");
1422         instance_id = (entry->ring_id & 0x3) >> 0;
1423         queue_id = (entry->ring_id & 0xc) >> 2;
1424
1425         if (instance_id <= 1 && queue_id == 0)
1426                 drm_sched_fault(&adev->sdma.instance[instance_id].ring.sched);
1427         return 0;
1428 }
1429
1430 static void sdma_v3_0_update_sdma_medium_grain_clock_gating(
1431                 struct amdgpu_device *adev,
1432                 bool enable)
1433 {
1434         uint32_t temp, data;
1435         int i;
1436
1437         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_MGCG)) {
1438                 for (i = 0; i < adev->sdma.num_instances; i++) {
1439                         temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1440                         data &= ~(SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1441                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1442                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1443                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1444                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1445                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1446                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1447                                   SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK);
1448                         if (data != temp)
1449                                 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1450                 }
1451         } else {
1452                 for (i = 0; i < adev->sdma.num_instances; i++) {
1453                         temp = data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i]);
1454                         data |= SDMA0_CLK_CTRL__SOFT_OVERRIDE7_MASK |
1455                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE6_MASK |
1456                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE5_MASK |
1457                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE4_MASK |
1458                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE3_MASK |
1459                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE2_MASK |
1460                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE1_MASK |
1461                                 SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK;
1462
1463                         if (data != temp)
1464                                 WREG32(mmSDMA0_CLK_CTRL + sdma_offsets[i], data);
1465                 }
1466         }
1467 }
1468
1469 static void sdma_v3_0_update_sdma_medium_grain_light_sleep(
1470                 struct amdgpu_device *adev,
1471                 bool enable)
1472 {
1473         uint32_t temp, data;
1474         int i;
1475
1476         if (enable && (adev->cg_flags & AMD_CG_SUPPORT_SDMA_LS)) {
1477                 for (i = 0; i < adev->sdma.num_instances; i++) {
1478                         temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1479                         data |= SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1480
1481                         if (temp != data)
1482                                 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1483                 }
1484         } else {
1485                 for (i = 0; i < adev->sdma.num_instances; i++) {
1486                         temp = data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i]);
1487                         data &= ~SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK;
1488
1489                         if (temp != data)
1490                                 WREG32(mmSDMA0_POWER_CNTL + sdma_offsets[i], data);
1491                 }
1492         }
1493 }
1494
1495 static int sdma_v3_0_set_clockgating_state(void *handle,
1496                                           enum amd_clockgating_state state)
1497 {
1498         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1499
1500         if (amdgpu_sriov_vf(adev))
1501                 return 0;
1502
1503         switch (adev->asic_type) {
1504         case CHIP_FIJI:
1505         case CHIP_CARRIZO:
1506         case CHIP_STONEY:
1507                 sdma_v3_0_update_sdma_medium_grain_clock_gating(adev,
1508                                 state == AMD_CG_STATE_GATE);
1509                 sdma_v3_0_update_sdma_medium_grain_light_sleep(adev,
1510                                 state == AMD_CG_STATE_GATE);
1511                 break;
1512         default:
1513                 break;
1514         }
1515         return 0;
1516 }
1517
1518 static int sdma_v3_0_set_powergating_state(void *handle,
1519                                           enum amd_powergating_state state)
1520 {
1521         return 0;
1522 }
1523
1524 static void sdma_v3_0_get_clockgating_state(void *handle, u64 *flags)
1525 {
1526         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1527         int data;
1528
1529         if (amdgpu_sriov_vf(adev))
1530                 *flags = 0;
1531
1532         /* AMD_CG_SUPPORT_SDMA_MGCG */
1533         data = RREG32(mmSDMA0_CLK_CTRL + sdma_offsets[0]);
1534         if (!(data & SDMA0_CLK_CTRL__SOFT_OVERRIDE0_MASK))
1535                 *flags |= AMD_CG_SUPPORT_SDMA_MGCG;
1536
1537         /* AMD_CG_SUPPORT_SDMA_LS */
1538         data = RREG32(mmSDMA0_POWER_CNTL + sdma_offsets[0]);
1539         if (data & SDMA0_POWER_CNTL__MEM_POWER_OVERRIDE_MASK)
1540                 *flags |= AMD_CG_SUPPORT_SDMA_LS;
1541 }
1542
1543 static const struct amd_ip_funcs sdma_v3_0_ip_funcs = {
1544         .name = "sdma_v3_0",
1545         .early_init = sdma_v3_0_early_init,
1546         .late_init = NULL,
1547         .sw_init = sdma_v3_0_sw_init,
1548         .sw_fini = sdma_v3_0_sw_fini,
1549         .hw_init = sdma_v3_0_hw_init,
1550         .hw_fini = sdma_v3_0_hw_fini,
1551         .suspend = sdma_v3_0_suspend,
1552         .resume = sdma_v3_0_resume,
1553         .is_idle = sdma_v3_0_is_idle,
1554         .wait_for_idle = sdma_v3_0_wait_for_idle,
1555         .check_soft_reset = sdma_v3_0_check_soft_reset,
1556         .pre_soft_reset = sdma_v3_0_pre_soft_reset,
1557         .post_soft_reset = sdma_v3_0_post_soft_reset,
1558         .soft_reset = sdma_v3_0_soft_reset,
1559         .set_clockgating_state = sdma_v3_0_set_clockgating_state,
1560         .set_powergating_state = sdma_v3_0_set_powergating_state,
1561         .get_clockgating_state = sdma_v3_0_get_clockgating_state,
1562 };
1563
1564 static const struct amdgpu_ring_funcs sdma_v3_0_ring_funcs = {
1565         .type = AMDGPU_RING_TYPE_SDMA,
1566         .align_mask = 0xf,
1567         .nop = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP),
1568         .support_64bit_ptrs = false,
1569         .secure_submission_supported = true,
1570         .get_rptr = sdma_v3_0_ring_get_rptr,
1571         .get_wptr = sdma_v3_0_ring_get_wptr,
1572         .set_wptr = sdma_v3_0_ring_set_wptr,
1573         .emit_frame_size =
1574                 6 + /* sdma_v3_0_ring_emit_hdp_flush */
1575                 3 + /* hdp invalidate */
1576                 6 + /* sdma_v3_0_ring_emit_pipeline_sync */
1577                 VI_FLUSH_GPU_TLB_NUM_WREG * 3 + 6 + /* sdma_v3_0_ring_emit_vm_flush */
1578                 10 + 10 + 10, /* sdma_v3_0_ring_emit_fence x3 for user fence, vm fence */
1579         .emit_ib_size = 7 + 6, /* sdma_v3_0_ring_emit_ib */
1580         .emit_ib = sdma_v3_0_ring_emit_ib,
1581         .emit_fence = sdma_v3_0_ring_emit_fence,
1582         .emit_pipeline_sync = sdma_v3_0_ring_emit_pipeline_sync,
1583         .emit_vm_flush = sdma_v3_0_ring_emit_vm_flush,
1584         .emit_hdp_flush = sdma_v3_0_ring_emit_hdp_flush,
1585         .test_ring = sdma_v3_0_ring_test_ring,
1586         .test_ib = sdma_v3_0_ring_test_ib,
1587         .insert_nop = sdma_v3_0_ring_insert_nop,
1588         .pad_ib = sdma_v3_0_ring_pad_ib,
1589         .emit_wreg = sdma_v3_0_ring_emit_wreg,
1590 };
1591
1592 static void sdma_v3_0_set_ring_funcs(struct amdgpu_device *adev)
1593 {
1594         int i;
1595
1596         for (i = 0; i < adev->sdma.num_instances; i++) {
1597                 adev->sdma.instance[i].ring.funcs = &sdma_v3_0_ring_funcs;
1598                 adev->sdma.instance[i].ring.me = i;
1599         }
1600 }
1601
1602 static const struct amdgpu_irq_src_funcs sdma_v3_0_trap_irq_funcs = {
1603         .set = sdma_v3_0_set_trap_irq_state,
1604         .process = sdma_v3_0_process_trap_irq,
1605 };
1606
1607 static const struct amdgpu_irq_src_funcs sdma_v3_0_illegal_inst_irq_funcs = {
1608         .process = sdma_v3_0_process_illegal_inst_irq,
1609 };
1610
1611 static void sdma_v3_0_set_irq_funcs(struct amdgpu_device *adev)
1612 {
1613         adev->sdma.trap_irq.num_types = AMDGPU_SDMA_IRQ_LAST;
1614         adev->sdma.trap_irq.funcs = &sdma_v3_0_trap_irq_funcs;
1615         adev->sdma.illegal_inst_irq.funcs = &sdma_v3_0_illegal_inst_irq_funcs;
1616 }
1617
1618 /**
1619  * sdma_v3_0_emit_copy_buffer - copy buffer using the sDMA engine
1620  *
1621  * @ib: indirect buffer to copy to
1622  * @src_offset: src GPU address
1623  * @dst_offset: dst GPU address
1624  * @byte_count: number of bytes to xfer
1625  * @tmz: unused
1626  *
1627  * Copy GPU buffers using the DMA engine (VI).
1628  * Used by the amdgpu ttm implementation to move pages if
1629  * registered as the asic copy callback.
1630  */
1631 static void sdma_v3_0_emit_copy_buffer(struct amdgpu_ib *ib,
1632                                        uint64_t src_offset,
1633                                        uint64_t dst_offset,
1634                                        uint32_t byte_count,
1635                                        bool tmz)
1636 {
1637         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_COPY) |
1638                 SDMA_PKT_HEADER_SUB_OP(SDMA_SUBOP_COPY_LINEAR);
1639         ib->ptr[ib->length_dw++] = byte_count;
1640         ib->ptr[ib->length_dw++] = 0; /* src/dst endian swap */
1641         ib->ptr[ib->length_dw++] = lower_32_bits(src_offset);
1642         ib->ptr[ib->length_dw++] = upper_32_bits(src_offset);
1643         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1644         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1645 }
1646
1647 /**
1648  * sdma_v3_0_emit_fill_buffer - fill buffer using the sDMA engine
1649  *
1650  * @ib: indirect buffer to copy to
1651  * @src_data: value to write to buffer
1652  * @dst_offset: dst GPU address
1653  * @byte_count: number of bytes to xfer
1654  *
1655  * Fill GPU buffers using the DMA engine (VI).
1656  */
1657 static void sdma_v3_0_emit_fill_buffer(struct amdgpu_ib *ib,
1658                                        uint32_t src_data,
1659                                        uint64_t dst_offset,
1660                                        uint32_t byte_count)
1661 {
1662         ib->ptr[ib->length_dw++] = SDMA_PKT_HEADER_OP(SDMA_OP_CONST_FILL);
1663         ib->ptr[ib->length_dw++] = lower_32_bits(dst_offset);
1664         ib->ptr[ib->length_dw++] = upper_32_bits(dst_offset);
1665         ib->ptr[ib->length_dw++] = src_data;
1666         ib->ptr[ib->length_dw++] = byte_count;
1667 }
1668
1669 static const struct amdgpu_buffer_funcs sdma_v3_0_buffer_funcs = {
1670         .copy_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */
1671         .copy_num_dw = 7,
1672         .emit_copy_buffer = sdma_v3_0_emit_copy_buffer,
1673
1674         .fill_max_bytes = 0x3fffe0, /* not 0x3fffff due to HW limitation */
1675         .fill_num_dw = 5,
1676         .emit_fill_buffer = sdma_v3_0_emit_fill_buffer,
1677 };
1678
1679 static void sdma_v3_0_set_buffer_funcs(struct amdgpu_device *adev)
1680 {
1681         adev->mman.buffer_funcs = &sdma_v3_0_buffer_funcs;
1682         adev->mman.buffer_funcs_ring = &adev->sdma.instance[0].ring;
1683 }
1684
1685 static const struct amdgpu_vm_pte_funcs sdma_v3_0_vm_pte_funcs = {
1686         .copy_pte_num_dw = 7,
1687         .copy_pte = sdma_v3_0_vm_copy_pte,
1688
1689         .write_pte = sdma_v3_0_vm_write_pte,
1690         .set_pte_pde = sdma_v3_0_vm_set_pte_pde,
1691 };
1692
1693 static void sdma_v3_0_set_vm_pte_funcs(struct amdgpu_device *adev)
1694 {
1695         unsigned i;
1696
1697         adev->vm_manager.vm_pte_funcs = &sdma_v3_0_vm_pte_funcs;
1698         for (i = 0; i < adev->sdma.num_instances; i++) {
1699                 adev->vm_manager.vm_pte_scheds[i] =
1700                          &adev->sdma.instance[i].ring.sched;
1701         }
1702         adev->vm_manager.vm_pte_num_scheds = adev->sdma.num_instances;
1703 }
1704
1705 const struct amdgpu_ip_block_version sdma_v3_0_ip_block =
1706 {
1707         .type = AMD_IP_BLOCK_TYPE_SDMA,
1708         .major = 3,
1709         .minor = 0,
1710         .rev = 0,
1711         .funcs = &sdma_v3_0_ip_funcs,
1712 };
1713
1714 const struct amdgpu_ip_block_version sdma_v3_1_ip_block =
1715 {
1716         .type = AMD_IP_BLOCK_TYPE_SDMA,
1717         .major = 3,
1718         .minor = 1,
1719         .rev = 0,
1720         .funcs = &sdma_v3_0_ip_funcs,
1721 };