drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c

   1 /*
   2  * Copyright 2016 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Author: Huang Rui
  23  *
  24  */
  25
  26 #include <linux/firmware.h>
  27 #include <drm/drmP.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_psp.h"
  30 #include "amdgpu_ucode.h"
  31 #include "soc15_common.h"
  32 #include "psp_v3_1.h"
  33 #include "psp_v10_0.h"
  34
  35 static void psp_set_funcs(struct amdgpu_device *adev);
  36
  37 static int psp_early_init(void *handle)
  38 {
  39         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  40
  41         psp_set_funcs(adev);
  42
  43         return 0;
  44 }
  45
  46 static int psp_sw_init(void *handle)
  47 {
  48         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  49         struct psp_context *psp = &adev->psp;
  50         int ret;
  51
  52         switch (adev->asic_type) {
  53         case CHIP_VEGA10:
  54         case CHIP_VEGA12:
  55         case CHIP_VEGA20:
  56                 psp_v3_1_set_psp_funcs(psp);
  57                 break;
  58         case CHIP_RAVEN:
  59                 psp_v10_0_set_psp_funcs(psp);
  60                 break;
  61         default:
  62                 return -EINVAL;
  63         }
  64
  65         psp->adev = adev;
  66
  67         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
  68                 return 0;
  69
  70         ret = psp_init_microcode(psp);
  71         if (ret) {
  72                 DRM_ERROR("Failed to load psp firmware!\n");
  73                 return ret;
  74         }
  75
  76         return 0;
  77 }
  78
  79 static int psp_sw_fini(void *handle)
  80 {
  81         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
  82
  83         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
  84                 return 0;
  85
  86         release_firmware(adev->psp.sos_fw);
  87         adev->psp.sos_fw = NULL;
  88         release_firmware(adev->psp.asd_fw);
  89         adev->psp.asd_fw = NULL;
  90         return 0;
  91 }
  92
  93 int psp_wait_for(struct psp_context *psp, uint32_t reg_index,
  94                  uint32_t reg_val, uint32_t mask, bool check_changed)
  95 {
  96         uint32_t val;
  97         int i;
  98         struct amdgpu_device *adev = psp->adev;
  99
 100         for (i = 0; i < adev->usec_timeout; i++) {
 101                 val = RREG32(reg_index);
 102                 if (check_changed) {
 103                         if (val != reg_val)
 104                                 return 0;
 105                 } else {
 106                         if ((val & mask) == reg_val)
 107                                 return 0;
 108                 }
 109                 udelay(1);
 110         }
 111
 112         return -ETIME;
 113 }
 114
 115 static int
 116 psp_cmd_submit_buf(struct psp_context *psp,
 117                    struct amdgpu_firmware_info *ucode,
 118                    struct psp_gfx_cmd_resp *cmd, uint64_t fence_mc_addr,
 119                    int index)
 120 {
 121         int ret;
 122
 123         memset(psp->cmd_buf_mem, 0, PSP_CMD_BUFFER_SIZE);
 124
 125         memcpy(psp->cmd_buf_mem, cmd, sizeof(struct psp_gfx_cmd_resp));
 126
 127         ret = psp_cmd_submit(psp, ucode, psp->cmd_buf_mc_addr,
 128                              fence_mc_addr, index);
 129
 130         while (*((unsigned int *)psp->fence_buf) != index) {
 131                 msleep(1);
 132         }
 133
 134         if (ucode) {
 135                 ucode->tmr_mc_addr_lo = psp->cmd_buf_mem->resp.fw_addr_lo;
 136                 ucode->tmr_mc_addr_hi = psp->cmd_buf_mem->resp.fw_addr_hi;
 137         }
 138
 139         return ret;
 140 }
 141
 142 static void psp_prep_tmr_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 143                                  uint64_t tmr_mc, uint32_t size)
 144 {
 145         cmd->cmd_id = GFX_CMD_ID_SETUP_TMR;
 146         cmd->cmd.cmd_setup_tmr.buf_phy_addr_lo = lower_32_bits(tmr_mc);
 147         cmd->cmd.cmd_setup_tmr.buf_phy_addr_hi = upper_32_bits(tmr_mc);
 148         cmd->cmd.cmd_setup_tmr.buf_size = size;
 149 }
 150
 151 /* Set up Trusted Memory Region */
 152 static int psp_tmr_init(struct psp_context *psp)
 153 {
 154         int ret;
 155
 156         /*
 157          * Allocate 3M memory aligned to 1M from Frame Buffer (local
 158          * physical).
 159          *
 160          * Note: this memory need be reserved till the driver
 161          * uninitializes.
 162          */
 163         ret = amdgpu_bo_create_kernel(psp->adev, 0x300000, 0x100000,
 164                                       AMDGPU_GEM_DOMAIN_VRAM,
 165                                       &psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
 166
 167         return ret;
 168 }
 169
 170 static int psp_tmr_load(struct psp_context *psp)
 171 {
 172         int ret;
 173         struct psp_gfx_cmd_resp *cmd;
 174
 175         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 176         if (!cmd)
 177                 return -ENOMEM;
 178
 179         psp_prep_tmr_cmd_buf(cmd, psp->tmr_mc_addr, 0x300000);
 180
 181         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 182                                  psp->fence_buf_mc_addr, 1);
 183         if (ret)
 184                 goto failed;
 185
 186         kfree(cmd);
 187
 188         return 0;
 189
 190 failed:
 191         kfree(cmd);
 192         return ret;
 193 }
 194
 195 static void psp_prep_asd_cmd_buf(struct psp_gfx_cmd_resp *cmd,
 196                                  uint64_t asd_mc, uint64_t asd_mc_shared,
 197                                  uint32_t size, uint32_t shared_size)
 198 {
 199         cmd->cmd_id = GFX_CMD_ID_LOAD_ASD;
 200         cmd->cmd.cmd_load_ta.app_phy_addr_lo = lower_32_bits(asd_mc);
 201         cmd->cmd.cmd_load_ta.app_phy_addr_hi = upper_32_bits(asd_mc);
 202         cmd->cmd.cmd_load_ta.app_len = size;
 203
 204         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_lo = lower_32_bits(asd_mc_shared);
 205         cmd->cmd.cmd_load_ta.cmd_buf_phy_addr_hi = upper_32_bits(asd_mc_shared);
 206         cmd->cmd.cmd_load_ta.cmd_buf_len = shared_size;
 207 }
 208
 209 static int psp_asd_init(struct psp_context *psp)
 210 {
 211         int ret;
 212
 213         /*
 214          * Allocate 16k memory aligned to 4k from Frame Buffer (local
 215          * physical) for shared ASD <-> Driver
 216          */
 217         ret = amdgpu_bo_create_kernel(psp->adev, PSP_ASD_SHARED_MEM_SIZE,
 218                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM,
 219                                       &psp->asd_shared_bo,
 220                                       &psp->asd_shared_mc_addr,
 221                                       &psp->asd_shared_buf);
 222
 223         return ret;
 224 }
 225
 226 static int psp_asd_load(struct psp_context *psp)
 227 {
 228         int ret;
 229         struct psp_gfx_cmd_resp *cmd;
 230
 231         /* If PSP version doesn't match ASD version, asd loading will be failed.
 232          * add workaround to bypass it for sriov now.
 233          * TODO: add version check to make it common
 234          */
 235         if (amdgpu_sriov_vf(psp->adev))
 236                 return 0;
 237
 238         cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 239         if (!cmd)
 240                 return -ENOMEM;
 241
 242         memset(psp->fw_pri_buf, 0, PSP_1_MEG);
 243         memcpy(psp->fw_pri_buf, psp->asd_start_addr, psp->asd_ucode_size);
 244
 245         psp_prep_asd_cmd_buf(cmd, psp->fw_pri_mc_addr, psp->asd_shared_mc_addr,
 246                              psp->asd_ucode_size, PSP_ASD_SHARED_MEM_SIZE);
 247
 248         ret = psp_cmd_submit_buf(psp, NULL, cmd,
 249                                  psp->fence_buf_mc_addr, 2);
 250
 251         kfree(cmd);
 252
 253         return ret;
 254 }
 255
 256 static int psp_hw_start(struct psp_context *psp)
 257 {
 258         struct amdgpu_device *adev = psp->adev;
 259         int ret;
 260
 261         if (!amdgpu_sriov_vf(adev) || !adev->in_gpu_reset) {
 262                 ret = psp_bootloader_load_sysdrv(psp);
 263                 if (ret)
 264                         return ret;
 265
 266                 ret = psp_bootloader_load_sos(psp);
 267                 if (ret)
 268                         return ret;
 269         }
 270
 271         ret = psp_ring_create(psp, PSP_RING_TYPE__KM);
 272         if (ret)
 273                 return ret;
 274
 275         ret = psp_tmr_load(psp);
 276         if (ret)
 277                 return ret;
 278
 279         ret = psp_asd_load(psp);
 280         if (ret)
 281                 return ret;
 282
 283         return 0;
 284 }
 285
 286 static int psp_np_fw_load(struct psp_context *psp)
 287 {
 288         int i, ret;
 289         struct amdgpu_firmware_info *ucode;
 290         struct amdgpu_device* adev = psp->adev;
 291
 292         for (i = 0; i < adev->firmware.max_ucodes; i++) {
 293                 ucode = &adev->firmware.ucode[i];
 294                 if (!ucode->fw)
 295                         continue;
 296
 297                 if (ucode->ucode_id == AMDGPU_UCODE_ID_SMC &&
 298                     psp_smu_reload_quirk(psp))
 299                         continue;
 300                 if (amdgpu_sriov_vf(adev) &&
 301                    (ucode->ucode_id == AMDGPU_UCODE_ID_SDMA0
 302                     || ucode->ucode_id == AMDGPU_UCODE_ID_SDMA1
 303                     || ucode->ucode_id == AMDGPU_UCODE_ID_RLC_G))
 304                         /*skip ucode loading in SRIOV VF */
 305                         continue;
 306
 307                 ret = psp_prep_cmd_buf(ucode, psp->cmd);
 308                 if (ret)
 309                         return ret;
 310
 311                 ret = psp_cmd_submit_buf(psp, ucode, psp->cmd,
 312                                          psp->fence_buf_mc_addr, i + 3);
 313                 if (ret)
 314                         return ret;
 315
 316 #if 0
 317                 /* check if firmware loaded sucessfully */
 318                 if (!amdgpu_psp_check_fw_loading_status(adev, i))
 319                         return -EINVAL;
 320 #endif
 321         }
 322
 323         return 0;
 324 }
 325
 326 static int psp_load_fw(struct amdgpu_device *adev)
 327 {
 328         int ret;
 329         struct psp_context *psp = &adev->psp;
 330
 331         if (amdgpu_sriov_vf(adev) && adev->in_gpu_reset != 0)
 332                 goto skip_memalloc;
 333
 334         psp->cmd = kzalloc(sizeof(struct psp_gfx_cmd_resp), GFP_KERNEL);
 335         if (!psp->cmd)
 336                 return -ENOMEM;
 337
 338         ret = amdgpu_bo_create_kernel(adev, PSP_1_MEG, PSP_1_MEG,
 339                                         AMDGPU_GEM_DOMAIN_GTT,
 340                                         &psp->fw_pri_bo,
 341                                         &psp->fw_pri_mc_addr,
 342                                         &psp->fw_pri_buf);
 343         if (ret)
 344                 goto failed;
 345
 346         ret = amdgpu_bo_create_kernel(adev, PSP_FENCE_BUFFER_SIZE, PAGE_SIZE,
 347                                         AMDGPU_GEM_DOMAIN_VRAM,
 348                                         &psp->fence_buf_bo,
 349                                         &psp->fence_buf_mc_addr,
 350                                         &psp->fence_buf);
 351         if (ret)
 352                 goto failed_mem2;
 353
 354         ret = amdgpu_bo_create_kernel(adev, PSP_CMD_BUFFER_SIZE, PAGE_SIZE,
 355                                       AMDGPU_GEM_DOMAIN_VRAM,
 356                                       &psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 357                                       (void **)&psp->cmd_buf_mem);
 358         if (ret)
 359                 goto failed_mem1;
 360
 361         memset(psp->fence_buf, 0, PSP_FENCE_BUFFER_SIZE);
 362
 363         ret = psp_ring_init(psp, PSP_RING_TYPE__KM);
 364         if (ret)
 365                 goto failed_mem;
 366
 367         ret = psp_tmr_init(psp);
 368         if (ret)
 369                 goto failed_mem;
 370
 371         ret = psp_asd_init(psp);
 372         if (ret)
 373                 goto failed_mem;
 374
 375 skip_memalloc:
 376         ret = psp_hw_start(psp);
 377         if (ret)
 378                 goto failed_mem;
 379
 380         ret = psp_np_fw_load(psp);
 381         if (ret)
 382                 goto failed_mem;
 383
 384         return 0;
 385
 386 failed_mem:
 387         amdgpu_bo_free_kernel(&psp->cmd_buf_bo,
 388                               &psp->cmd_buf_mc_addr,
 389                               (void **)&psp->cmd_buf_mem);
 390 failed_mem1:
 391         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 392                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 393 failed_mem2:
 394         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 395                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 396 failed:
 397         kfree(psp->cmd);
 398         psp->cmd = NULL;
 399         return ret;
 400 }
 401
 402 static int psp_hw_init(void *handle)
 403 {
 404         int ret;
 405         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 406
 407
 408         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 409                 return 0;
 410
 411         mutex_lock(&adev->firmware.mutex);
 412         /*
 413          * This sequence is just used on hw_init only once, no need on
 414          * resume.
 415          */
 416         ret = amdgpu_ucode_init_bo(adev);
 417         if (ret)
 418                 goto failed;
 419
 420         ret = psp_load_fw(adev);
 421         if (ret) {
 422                 DRM_ERROR("PSP firmware loading failed\n");
 423                 goto failed;
 424         }
 425
 426         mutex_unlock(&adev->firmware.mutex);
 427         return 0;
 428
 429 failed:
 430         adev->firmware.load_type = AMDGPU_FW_LOAD_DIRECT;
 431         mutex_unlock(&adev->firmware.mutex);
 432         return -EINVAL;
 433 }
 434
 435 static int psp_hw_fini(void *handle)
 436 {
 437         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 438         struct psp_context *psp = &adev->psp;
 439
 440         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 441                 return 0;
 442
 443         amdgpu_ucode_fini_bo(adev);
 444
 445         psp_ring_destroy(psp, PSP_RING_TYPE__KM);
 446
 447         amdgpu_bo_free_kernel(&psp->tmr_bo, &psp->tmr_mc_addr, &psp->tmr_buf);
 448         amdgpu_bo_free_kernel(&psp->fw_pri_bo,
 449                               &psp->fw_pri_mc_addr, &psp->fw_pri_buf);
 450         amdgpu_bo_free_kernel(&psp->fence_buf_bo,
 451                               &psp->fence_buf_mc_addr, &psp->fence_buf);
 452         amdgpu_bo_free_kernel(&psp->asd_shared_bo, &psp->asd_shared_mc_addr,
 453                               &psp->asd_shared_buf);
 454         amdgpu_bo_free_kernel(&psp->cmd_buf_bo, &psp->cmd_buf_mc_addr,
 455                               (void **)&psp->cmd_buf_mem);
 456
 457         kfree(psp->cmd);
 458         psp->cmd = NULL;
 459
 460         return 0;
 461 }
 462
 463 static int psp_suspend(void *handle)
 464 {
 465         int ret;
 466         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 467         struct psp_context *psp = &adev->psp;
 468
 469         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 470                 return 0;
 471
 472         ret = psp_ring_stop(psp, PSP_RING_TYPE__KM);
 473         if (ret) {
 474                 DRM_ERROR("PSP ring stop failed\n");
 475                 return ret;
 476         }
 477
 478         return 0;
 479 }
 480
 481 static int psp_resume(void *handle)
 482 {
 483         int ret;
 484         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
 485         struct psp_context *psp = &adev->psp;
 486
 487         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 488                 return 0;
 489
 490         DRM_INFO("PSP is resuming...\n");
 491
 492         mutex_lock(&adev->firmware.mutex);
 493
 494         ret = psp_hw_start(psp);
 495         if (ret)
 496                 goto failed;
 497
 498         ret = psp_np_fw_load(psp);
 499         if (ret)
 500                 goto failed;
 501
 502         mutex_unlock(&adev->firmware.mutex);
 503
 504         return 0;
 505
 506 failed:
 507         DRM_ERROR("PSP resume failed\n");
 508         mutex_unlock(&adev->firmware.mutex);
 509         return ret;
 510 }
 511
 512 int psp_gpu_reset(struct amdgpu_device *adev)
 513 {
 514         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
 515                 return 0;
 516
 517         return psp_mode1_reset(&adev->psp);
 518 }
 519
 520 static bool psp_check_fw_loading_status(struct amdgpu_device *adev,
 521                                         enum AMDGPU_UCODE_ID ucode_type)
 522 {
 523         struct amdgpu_firmware_info *ucode = NULL;
 524
 525         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) {
 526                 DRM_INFO("firmware is not loaded by PSP\n");
 527                 return true;
 528         }
 529
 530         if (!adev->firmware.fw_size)
 531                 return false;
 532
 533         ucode = &adev->firmware.ucode[ucode_type];
 534         if (!ucode->fw || !ucode->ucode_size)
 535                 return false;
 536
 537         return psp_compare_sram_data(&adev->psp, ucode, ucode_type);
 538 }
 539
 540 static int psp_set_clockgating_state(void *handle,
 541                                      enum amd_clockgating_state state)
 542 {
 543         return 0;
 544 }
 545
 546 static int psp_set_powergating_state(void *handle,
 547                                      enum amd_powergating_state state)
 548 {
 549         return 0;
 550 }
 551
 552 const struct amd_ip_funcs psp_ip_funcs = {
 553         .name = "psp",
 554         .early_init = psp_early_init,
 555         .late_init = NULL,
 556         .sw_init = psp_sw_init,
 557         .sw_fini = psp_sw_fini,
 558         .hw_init = psp_hw_init,
 559         .hw_fini = psp_hw_fini,
 560         .suspend = psp_suspend,
 561         .resume = psp_resume,
 562         .is_idle = NULL,
 563         .check_soft_reset = NULL,
 564         .wait_for_idle = NULL,
 565         .soft_reset = NULL,
 566         .set_clockgating_state = psp_set_clockgating_state,
 567         .set_powergating_state = psp_set_powergating_state,
 568 };
 569
 570 static const struct amdgpu_psp_funcs psp_funcs = {
 571         .check_fw_loading_status = psp_check_fw_loading_status,
 572 };
 573
 574 static void psp_set_funcs(struct amdgpu_device *adev)
 575 {
 576         if (NULL == adev->firmware.funcs)
 577                 adev->firmware.funcs = &psp_funcs;
 578 }
 579
 580 const struct amdgpu_ip_block_version psp_v3_1_ip_block =
 581 {
 582         .type = AMD_IP_BLOCK_TYPE_PSP,
 583         .major = 3,
 584         .minor = 1,
 585         .rev = 0,
 586         .funcs = &psp_ip_funcs,
 587 };
 588
 589 const struct amdgpu_ip_block_version psp_v10_0_ip_block =
 590 {
 591         .type = AMD_IP_BLOCK_TYPE_PSP,
 592         .major = 10,
 593         .minor = 0,
 594         .rev = 0,
 595         .funcs = &psp_ip_funcs,
 596 };