drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

   1 /*
   2  * Copyright 2021 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23 #include <linux/delay.h>
  24 #include <linux/kernel.h>
  25 #include <linux/firmware.h>
  26 #include <linux/module.h>
  27 #include <linux/pci.h>
  28 #include "amdgpu.h"
  29 #include "amdgpu_gfx.h"
  30 #include "amdgpu_psp.h"
  31 #include "amdgpu_smu.h"
  32 #include "amdgpu_atomfirmware.h"
  33 #include "imu_v11_0.h"
  34 #include "soc21.h"
  35 #include "nvd.h"
  36
  37 #include "gc/gc_11_0_0_offset.h"
  38 #include "gc/gc_11_0_0_sh_mask.h"
  39 #include "smuio/smuio_13_0_6_offset.h"
  40 #include "smuio/smuio_13_0_6_sh_mask.h"
  41 #include "navi10_enum.h"
  42 #include "ivsrcid/gfx/irqsrcs_gfx_11_0_0.h"
  43
  44 #include "soc15.h"
  45 #include "soc15d.h"
  46 #include "clearstate_gfx11.h"
  47 #include "v11_structs.h"
  48 #include "gfx_v11_0.h"
  49 #include "gfx_v11_0_3.h"
  50 #include "nbio_v4_3.h"
  51 #include "mes_v11_0.h"
  52
  53 #define GFX11_NUM_GFX_RINGS             1
  54 #define GFX11_MEC_HPD_SIZE      2048
  55
  56 #define RLCG_UCODE_LOADING_START_ADDRESS        0x00002000L
  57 #define RLC_PG_DELAY_3_DEFAULT_GC_11_0_1        0x1388
  58
  59 #define regCGTT_WD_CLK_CTRL             0x5086
  60 #define regCGTT_WD_CLK_CTRL_BASE_IDX    1
  61 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1   0x4e7e
  62 #define regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1_BASE_IDX  1
  63 #define regPC_CONFIG_CNTL_1             0x194d
  64 #define regPC_CONFIG_CNTL_1_BASE_IDX    1
  65
  66 MODULE_FIRMWARE("amdgpu/gc_11_0_0_pfp.bin");
  67 MODULE_FIRMWARE("amdgpu/gc_11_0_0_me.bin");
  68 MODULE_FIRMWARE("amdgpu/gc_11_0_0_mec.bin");
  69 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc.bin");
  70 MODULE_FIRMWARE("amdgpu/gc_11_0_0_rlc_1.bin");
  71 MODULE_FIRMWARE("amdgpu/gc_11_0_0_toc.bin");
  72 MODULE_FIRMWARE("amdgpu/gc_11_0_1_pfp.bin");
  73 MODULE_FIRMWARE("amdgpu/gc_11_0_1_me.bin");
  74 MODULE_FIRMWARE("amdgpu/gc_11_0_1_mec.bin");
  75 MODULE_FIRMWARE("amdgpu/gc_11_0_1_rlc.bin");
  76 MODULE_FIRMWARE("amdgpu/gc_11_0_2_pfp.bin");
  77 MODULE_FIRMWARE("amdgpu/gc_11_0_2_me.bin");
  78 MODULE_FIRMWARE("amdgpu/gc_11_0_2_mec.bin");
  79 MODULE_FIRMWARE("amdgpu/gc_11_0_2_rlc.bin");
  80 MODULE_FIRMWARE("amdgpu/gc_11_0_3_pfp.bin");
  81 MODULE_FIRMWARE("amdgpu/gc_11_0_3_me.bin");
  82 MODULE_FIRMWARE("amdgpu/gc_11_0_3_mec.bin");
  83 MODULE_FIRMWARE("amdgpu/gc_11_0_3_rlc.bin");
  84 MODULE_FIRMWARE("amdgpu/gc_11_0_4_pfp.bin");
  85 MODULE_FIRMWARE("amdgpu/gc_11_0_4_me.bin");
  86 MODULE_FIRMWARE("amdgpu/gc_11_0_4_mec.bin");
  87 MODULE_FIRMWARE("amdgpu/gc_11_0_4_rlc.bin");
  88 MODULE_FIRMWARE("amdgpu/gc_11_5_0_pfp.bin");
  89 MODULE_FIRMWARE("amdgpu/gc_11_5_0_me.bin");
  90 MODULE_FIRMWARE("amdgpu/gc_11_5_0_mec.bin");
  91 MODULE_FIRMWARE("amdgpu/gc_11_5_0_rlc.bin");
  92
  93 static const struct soc15_reg_golden golden_settings_gc_11_0[] = {
  94         SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL, 0x20000000, 0x20000000)
  95 };
  96
  97 static const struct soc15_reg_golden golden_settings_gc_11_0_1[] =
  98 {
  99         SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_GS_NGG_CLK_CTRL, 0x9fff8fff, 0x00000010),
 100         SOC15_REG_GOLDEN_VALUE(GC, 0, regCGTT_WD_CLK_CTRL, 0xffff8fff, 0x00000010),
 101         SOC15_REG_GOLDEN_VALUE(GC, 0, regCPF_GCR_CNTL, 0x0007ffff, 0x0000c200),
 102         SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xffff001b, 0x00f01988),
 103         SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf0ffffff, 0x00880007),
 104         SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_ENHANCE_3, 0xfffffffd, 0x00000008),
 105         SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_SC_VRS_SURFACE_CNTL_1, 0xfff891ff, 0x55480100),
 106         SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000),
 107         SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xfcffffff, 0x0000000a)
 108 };
 109
 110 static const struct soc15_reg_golden golden_settings_gc_11_5_0[] = {
 111         SOC15_REG_GOLDEN_VALUE(GC, 0, regDB_DEBUG5, 0xffffffff, 0x00000800),
 112         SOC15_REG_GOLDEN_VALUE(GC, 0, regGB_ADDR_CONFIG, 0x0c1807ff, 0x00000242),
 113         SOC15_REG_GOLDEN_VALUE(GC, 0, regGCR_GENERAL_CNTL, 0x1ff1ffff, 0x00000500),
 114         SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2A_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
 115         SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_ADDR_MATCH_MASK, 0xffffffff, 0xfffffff3),
 116         SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL, 0xffffffff, 0xf37fff3f),
 117         SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL3, 0xfffffffb, 0x00f40188),
 118         SOC15_REG_GOLDEN_VALUE(GC, 0, regGL2C_CTRL4, 0xf0ffffff, 0x8000b007),
 119         SOC15_REG_GOLDEN_VALUE(GC, 0, regPA_CL_ENHANCE, 0xf1ffffff, 0x00880007),
 120         SOC15_REG_GOLDEN_VALUE(GC, 0, regPC_CONFIG_CNTL_1, 0xffffffff, 0x00010000),
 121         SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL_AUX, 0xf7f7ffff, 0x01030000),
 122         SOC15_REG_GOLDEN_VALUE(GC, 0, regTA_CNTL2, 0x007f0000, 0x00000000),
 123         SOC15_REG_GOLDEN_VALUE(GC, 0, regTCP_CNTL2, 0xffcfffff, 0x0000200a),
 124         SOC15_REG_GOLDEN_VALUE(GC, 0, regUTCL1_CTRL_2, 0xffffffff, 0x0000048f)
 125 };
 126
 127 #define DEFAULT_SH_MEM_CONFIG \
 128         ((SH_MEM_ADDRESS_MODE_64 << SH_MEM_CONFIG__ADDRESS_MODE__SHIFT) | \
 129          (SH_MEM_ALIGNMENT_MODE_UNALIGNED << SH_MEM_CONFIG__ALIGNMENT_MODE__SHIFT) | \
 130          (3 << SH_MEM_CONFIG__INITIAL_INST_PREFETCH__SHIFT))
 131
 132 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev);
 133 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev);
 134 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev);
 135 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev);
 136 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev);
 137 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev);
 138 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev);
 139 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev,
 140                                  struct amdgpu_cu_info *cu_info);
 141 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev);
 142 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
 143                                    u32 sh_num, u32 instance, int xcc_id);
 144 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev);
 145
 146 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume);
 147 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start, bool secure);
 148 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
 149                                      uint32_t val);
 150 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev);
 151 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
 152                                            uint16_t pasid, uint32_t flush_type,
 153                                            bool all_hub, uint8_t dst_sel);
 154 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id);
 155 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id);
 156 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev,
 157                                       bool enable);
 158
 159 static void gfx11_kiq_set_resources(struct amdgpu_ring *kiq_ring, uint64_t queue_mask)
 160 {
 161         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_SET_RESOURCES, 6));
 162         amdgpu_ring_write(kiq_ring, PACKET3_SET_RESOURCES_VMID_MASK(0) |
 163                           PACKET3_SET_RESOURCES_UNMAP_LATENTY(0xa) | /* unmap_latency: 0xa (~ 1s) */
 164                           PACKET3_SET_RESOURCES_QUEUE_TYPE(0)); /* vmid_mask:0 queue_type:0 (KIQ) */
 165         amdgpu_ring_write(kiq_ring, lower_32_bits(queue_mask)); /* queue mask lo */
 166         amdgpu_ring_write(kiq_ring, upper_32_bits(queue_mask)); /* queue mask hi */
 167         amdgpu_ring_write(kiq_ring, 0); /* gws mask lo */
 168         amdgpu_ring_write(kiq_ring, 0); /* gws mask hi */
 169         amdgpu_ring_write(kiq_ring, 0); /* oac mask */
 170         amdgpu_ring_write(kiq_ring, 0); /* gds heap base:0, gds heap size:0 */
 171 }
 172
 173 static void gfx11_kiq_map_queues(struct amdgpu_ring *kiq_ring,
 174                                  struct amdgpu_ring *ring)
 175 {
 176         uint64_t mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
 177         uint64_t wptr_addr = ring->wptr_gpu_addr;
 178         uint32_t me = 0, eng_sel = 0;
 179
 180         switch (ring->funcs->type) {
 181         case AMDGPU_RING_TYPE_COMPUTE:
 182                 me = 1;
 183                 eng_sel = 0;
 184                 break;
 185         case AMDGPU_RING_TYPE_GFX:
 186                 me = 0;
 187                 eng_sel = 4;
 188                 break;
 189         case AMDGPU_RING_TYPE_MES:
 190                 me = 2;
 191                 eng_sel = 5;
 192                 break;
 193         default:
 194                 WARN_ON(1);
 195         }
 196
 197         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_MAP_QUEUES, 5));
 198         /* Q_sel:0, vmid:0, vidmem: 1, engine:0, num_Q:1*/
 199         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 200                           PACKET3_MAP_QUEUES_QUEUE_SEL(0) | /* Queue_Sel */
 201                           PACKET3_MAP_QUEUES_VMID(0) | /* VMID */
 202                           PACKET3_MAP_QUEUES_QUEUE(ring->queue) |
 203                           PACKET3_MAP_QUEUES_PIPE(ring->pipe) |
 204                           PACKET3_MAP_QUEUES_ME((me)) |
 205                           PACKET3_MAP_QUEUES_QUEUE_TYPE(0) | /*queue_type: normal compute queue */
 206                           PACKET3_MAP_QUEUES_ALLOC_FORMAT(0) | /* alloc format: all_on_one_pipe */
 207                           PACKET3_MAP_QUEUES_ENGINE_SEL(eng_sel) |
 208                           PACKET3_MAP_QUEUES_NUM_QUEUES(1)); /* num_queues: must be 1 */
 209         amdgpu_ring_write(kiq_ring, PACKET3_MAP_QUEUES_DOORBELL_OFFSET(ring->doorbell_index));
 210         amdgpu_ring_write(kiq_ring, lower_32_bits(mqd_addr));
 211         amdgpu_ring_write(kiq_ring, upper_32_bits(mqd_addr));
 212         amdgpu_ring_write(kiq_ring, lower_32_bits(wptr_addr));
 213         amdgpu_ring_write(kiq_ring, upper_32_bits(wptr_addr));
 214 }
 215
 216 static void gfx11_kiq_unmap_queues(struct amdgpu_ring *kiq_ring,
 217                                    struct amdgpu_ring *ring,
 218                                    enum amdgpu_unmap_queues_action action,
 219                                    u64 gpu_addr, u64 seq)
 220 {
 221         struct amdgpu_device *adev = kiq_ring->adev;
 222         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 223
 224         if (adev->enable_mes && !adev->gfx.kiq[0].ring.sched.ready) {
 225                 amdgpu_mes_unmap_legacy_queue(adev, ring, action, gpu_addr, seq);
 226                 return;
 227         }
 228
 229         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_UNMAP_QUEUES, 4));
 230         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 231                           PACKET3_UNMAP_QUEUES_ACTION(action) |
 232                           PACKET3_UNMAP_QUEUES_QUEUE_SEL(0) |
 233                           PACKET3_UNMAP_QUEUES_ENGINE_SEL(eng_sel) |
 234                           PACKET3_UNMAP_QUEUES_NUM_QUEUES(1));
 235         amdgpu_ring_write(kiq_ring,
 236                   PACKET3_UNMAP_QUEUES_DOORBELL_OFFSET0(ring->doorbell_index));
 237
 238         if (action == PREEMPT_QUEUES_NO_UNMAP) {
 239                 amdgpu_ring_write(kiq_ring, lower_32_bits(gpu_addr));
 240                 amdgpu_ring_write(kiq_ring, upper_32_bits(gpu_addr));
 241                 amdgpu_ring_write(kiq_ring, seq);
 242         } else {
 243                 amdgpu_ring_write(kiq_ring, 0);
 244                 amdgpu_ring_write(kiq_ring, 0);
 245                 amdgpu_ring_write(kiq_ring, 0);
 246         }
 247 }
 248
 249 static void gfx11_kiq_query_status(struct amdgpu_ring *kiq_ring,
 250                                    struct amdgpu_ring *ring,
 251                                    u64 addr,
 252                                    u64 seq)
 253 {
 254         uint32_t eng_sel = ring->funcs->type == AMDGPU_RING_TYPE_GFX ? 4 : 0;
 255
 256         amdgpu_ring_write(kiq_ring, PACKET3(PACKET3_QUERY_STATUS, 5));
 257         amdgpu_ring_write(kiq_ring,
 258                           PACKET3_QUERY_STATUS_CONTEXT_ID(0) |
 259                           PACKET3_QUERY_STATUS_INTERRUPT_SEL(0) |
 260                           PACKET3_QUERY_STATUS_COMMAND(2));
 261         amdgpu_ring_write(kiq_ring, /* Q_sel: 0, vmid: 0, engine: 0, num_Q: 1 */
 262                           PACKET3_QUERY_STATUS_DOORBELL_OFFSET(ring->doorbell_index) |
 263                           PACKET3_QUERY_STATUS_ENG_SEL(eng_sel));
 264         amdgpu_ring_write(kiq_ring, lower_32_bits(addr));
 265         amdgpu_ring_write(kiq_ring, upper_32_bits(addr));
 266         amdgpu_ring_write(kiq_ring, lower_32_bits(seq));
 267         amdgpu_ring_write(kiq_ring, upper_32_bits(seq));
 268 }
 269
 270 static void gfx11_kiq_invalidate_tlbs(struct amdgpu_ring *kiq_ring,
 271                                 uint16_t pasid, uint32_t flush_type,
 272                                 bool all_hub)
 273 {
 274         gfx_v11_0_ring_invalidate_tlbs(kiq_ring, pasid, flush_type, all_hub, 1);
 275 }
 276
 277 static const struct kiq_pm4_funcs gfx_v11_0_kiq_pm4_funcs = {
 278         .kiq_set_resources = gfx11_kiq_set_resources,
 279         .kiq_map_queues = gfx11_kiq_map_queues,
 280         .kiq_unmap_queues = gfx11_kiq_unmap_queues,
 281         .kiq_query_status = gfx11_kiq_query_status,
 282         .kiq_invalidate_tlbs = gfx11_kiq_invalidate_tlbs,
 283         .set_resources_size = 8,
 284         .map_queues_size = 7,
 285         .unmap_queues_size = 6,
 286         .query_status_size = 7,
 287         .invalidate_tlbs_size = 2,
 288 };
 289
 290 static void gfx_v11_0_set_kiq_pm4_funcs(struct amdgpu_device *adev)
 291 {
 292         adev->gfx.kiq[0].pmf = &gfx_v11_0_kiq_pm4_funcs;
 293 }
 294
 295 static void gfx_v11_0_init_golden_registers(struct amdgpu_device *adev)
 296 {
 297         if (amdgpu_sriov_vf(adev))
 298                 return;
 299
 300         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 301         case IP_VERSION(11, 0, 1):
 302         case IP_VERSION(11, 0, 4):
 303                 soc15_program_register_sequence(adev,
 304                                                 golden_settings_gc_11_0_1,
 305                                                 (const u32)ARRAY_SIZE(golden_settings_gc_11_0_1));
 306                 break;
 307         case IP_VERSION(11, 5, 0):
 308                 soc15_program_register_sequence(adev,
 309                                                 golden_settings_gc_11_5_0,
 310                                                 (const u32)ARRAY_SIZE(golden_settings_gc_11_5_0));
 311                 break;
 312         default:
 313                 break;
 314         }
 315         soc15_program_register_sequence(adev,
 316                                         golden_settings_gc_11_0,
 317                                         (const u32)ARRAY_SIZE(golden_settings_gc_11_0));
 318
 319 }
 320
 321 static void gfx_v11_0_write_data_to_reg(struct amdgpu_ring *ring, int eng_sel,
 322                                        bool wc, uint32_t reg, uint32_t val)
 323 {
 324         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
 325         amdgpu_ring_write(ring, WRITE_DATA_ENGINE_SEL(eng_sel) |
 326                           WRITE_DATA_DST_SEL(0) | (wc ? WR_CONFIRM : 0));
 327         amdgpu_ring_write(ring, reg);
 328         amdgpu_ring_write(ring, 0);
 329         amdgpu_ring_write(ring, val);
 330 }
 331
 332 static void gfx_v11_0_wait_reg_mem(struct amdgpu_ring *ring, int eng_sel,
 333                                   int mem_space, int opt, uint32_t addr0,
 334                                   uint32_t addr1, uint32_t ref, uint32_t mask,
 335                                   uint32_t inv)
 336 {
 337         amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));
 338         amdgpu_ring_write(ring,
 339                           /* memory (1) or register (0) */
 340                           (WAIT_REG_MEM_MEM_SPACE(mem_space) |
 341                            WAIT_REG_MEM_OPERATION(opt) | /* wait */
 342                            WAIT_REG_MEM_FUNCTION(3) |  /* equal */
 343                            WAIT_REG_MEM_ENGINE(eng_sel)));
 344
 345         if (mem_space)
 346                 BUG_ON(addr0 & 0x3); /* Dword align */
 347         amdgpu_ring_write(ring, addr0);
 348         amdgpu_ring_write(ring, addr1);
 349         amdgpu_ring_write(ring, ref);
 350         amdgpu_ring_write(ring, mask);
 351         amdgpu_ring_write(ring, inv); /* poll interval */
 352 }
 353
 354 static int gfx_v11_0_ring_test_ring(struct amdgpu_ring *ring)
 355 {
 356         struct amdgpu_device *adev = ring->adev;
 357         uint32_t scratch = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
 358         uint32_t tmp = 0;
 359         unsigned i;
 360         int r;
 361
 362         WREG32(scratch, 0xCAFEDEAD);
 363         r = amdgpu_ring_alloc(ring, 5);
 364         if (r) {
 365                 DRM_ERROR("amdgpu: cp failed to lock ring %d (%d).\n",
 366                           ring->idx, r);
 367                 return r;
 368         }
 369
 370         if (ring->funcs->type == AMDGPU_RING_TYPE_KIQ) {
 371                 gfx_v11_0_ring_emit_wreg(ring, scratch, 0xDEADBEEF);
 372         } else {
 373                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_UCONFIG_REG, 1));
 374                 amdgpu_ring_write(ring, scratch -
 375                                   PACKET3_SET_UCONFIG_REG_START);
 376                 amdgpu_ring_write(ring, 0xDEADBEEF);
 377         }
 378         amdgpu_ring_commit(ring);
 379
 380         for (i = 0; i < adev->usec_timeout; i++) {
 381                 tmp = RREG32(scratch);
 382                 if (tmp == 0xDEADBEEF)
 383                         break;
 384                 if (amdgpu_emu_mode == 1)
 385                         msleep(1);
 386                 else
 387                         udelay(1);
 388         }
 389
 390         if (i >= adev->usec_timeout)
 391                 r = -ETIMEDOUT;
 392         return r;
 393 }
 394
 395 static int gfx_v11_0_ring_test_ib(struct amdgpu_ring *ring, long timeout)
 396 {
 397         struct amdgpu_device *adev = ring->adev;
 398         struct amdgpu_ib ib;
 399         struct dma_fence *f = NULL;
 400         unsigned index;
 401         uint64_t gpu_addr;
 402         volatile uint32_t *cpu_ptr;
 403         long r;
 404
 405         /* MES KIQ fw hasn't indirect buffer support for now */
 406         if (adev->enable_mes_kiq &&
 407             ring->funcs->type == AMDGPU_RING_TYPE_KIQ)
 408                 return 0;
 409
 410         memset(&ib, 0, sizeof(ib));
 411
 412         if (ring->is_mes_queue) {
 413                 uint32_t padding, offset;
 414
 415                 offset = amdgpu_mes_ctx_get_offs(ring, AMDGPU_MES_CTX_IB_OFFS);
 416                 padding = amdgpu_mes_ctx_get_offs(ring,
 417                                                   AMDGPU_MES_CTX_PADDING_OFFS);
 418
 419                 ib.gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
 420                 ib.ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
 421
 422                 gpu_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, padding);
 423                 cpu_ptr = amdgpu_mes_ctx_get_offs_cpu_addr(ring, padding);
 424                 *cpu_ptr = cpu_to_le32(0xCAFEDEAD);
 425         } else {
 426                 r = amdgpu_device_wb_get(adev, &index);
 427                 if (r)
 428                         return r;
 429
 430                 gpu_addr = adev->wb.gpu_addr + (index * 4);
 431                 adev->wb.wb[index] = cpu_to_le32(0xCAFEDEAD);
 432                 cpu_ptr = &adev->wb.wb[index];
 433
 434                 r = amdgpu_ib_get(adev, NULL, 20, AMDGPU_IB_POOL_DIRECT, &ib);
 435                 if (r) {
 436                         DRM_ERROR("amdgpu: failed to get ib (%ld).\n", r);
 437                         goto err1;
 438                 }
 439         }
 440
 441         ib.ptr[0] = PACKET3(PACKET3_WRITE_DATA, 3);
 442         ib.ptr[1] = WRITE_DATA_DST_SEL(5) | WR_CONFIRM;
 443         ib.ptr[2] = lower_32_bits(gpu_addr);
 444         ib.ptr[3] = upper_32_bits(gpu_addr);
 445         ib.ptr[4] = 0xDEADBEEF;
 446         ib.length_dw = 5;
 447
 448         r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
 449         if (r)
 450                 goto err2;
 451
 452         r = dma_fence_wait_timeout(f, false, timeout);
 453         if (r == 0) {
 454                 r = -ETIMEDOUT;
 455                 goto err2;
 456         } else if (r < 0) {
 457                 goto err2;
 458         }
 459
 460         if (le32_to_cpu(*cpu_ptr) == 0xDEADBEEF)
 461                 r = 0;
 462         else
 463                 r = -EINVAL;
 464 err2:
 465         if (!ring->is_mes_queue)
 466                 amdgpu_ib_free(adev, &ib, NULL);
 467         dma_fence_put(f);
 468 err1:
 469         if (!ring->is_mes_queue)
 470                 amdgpu_device_wb_free(adev, index);
 471         return r;
 472 }
 473
 474 static void gfx_v11_0_free_microcode(struct amdgpu_device *adev)
 475 {
 476         amdgpu_ucode_release(&adev->gfx.pfp_fw);
 477         amdgpu_ucode_release(&adev->gfx.me_fw);
 478         amdgpu_ucode_release(&adev->gfx.rlc_fw);
 479         amdgpu_ucode_release(&adev->gfx.mec_fw);
 480
 481         kfree(adev->gfx.rlc.register_list_format);
 482 }
 483
 484 static int gfx_v11_0_init_toc_microcode(struct amdgpu_device *adev, const char *ucode_prefix)
 485 {
 486         const struct psp_firmware_header_v1_0 *toc_hdr;
 487         int err = 0;
 488         char fw_name[40];
 489
 490         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_toc.bin", ucode_prefix);
 491         err = amdgpu_ucode_request(adev, &adev->psp.toc_fw, fw_name);
 492         if (err)
 493                 goto out;
 494
 495         toc_hdr = (const struct psp_firmware_header_v1_0 *)adev->psp.toc_fw->data;
 496         adev->psp.toc.fw_version = le32_to_cpu(toc_hdr->header.ucode_version);
 497         adev->psp.toc.feature_version = le32_to_cpu(toc_hdr->sos.fw_version);
 498         adev->psp.toc.size_bytes = le32_to_cpu(toc_hdr->header.ucode_size_bytes);
 499         adev->psp.toc.start_addr = (uint8_t *)toc_hdr +
 500                                 le32_to_cpu(toc_hdr->header.ucode_array_offset_bytes);
 501         return 0;
 502 out:
 503         amdgpu_ucode_release(&adev->psp.toc_fw);
 504         return err;
 505 }
 506
 507 static void gfx_v11_0_check_fw_cp_gfx_shadow(struct amdgpu_device *adev)
 508 {
 509         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 510         case IP_VERSION(11, 0, 0):
 511         case IP_VERSION(11, 0, 2):
 512         case IP_VERSION(11, 0, 3):
 513                 if ((adev->gfx.me_fw_version >= 1505) &&
 514                     (adev->gfx.pfp_fw_version >= 1600) &&
 515                     (adev->gfx.mec_fw_version >= 512)) {
 516                         if (amdgpu_sriov_vf(adev))
 517                                 adev->gfx.cp_gfx_shadow = true;
 518                         else
 519                                 adev->gfx.cp_gfx_shadow = false;
 520                 }
 521                 break;
 522         default:
 523                 adev->gfx.cp_gfx_shadow = false;
 524                 break;
 525         }
 526 }
 527
 528 static int gfx_v11_0_init_microcode(struct amdgpu_device *adev)
 529 {
 530         char fw_name[40];
 531         char ucode_prefix[30];
 532         int err;
 533         const struct rlc_firmware_header_v2_0 *rlc_hdr;
 534         uint16_t version_major;
 535         uint16_t version_minor;
 536
 537         DRM_DEBUG("\n");
 538
 539         amdgpu_ucode_ip_version_decode(adev, GC_HWIP, ucode_prefix, sizeof(ucode_prefix));
 540
 541         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_pfp.bin", ucode_prefix);
 542         err = amdgpu_ucode_request(adev, &adev->gfx.pfp_fw, fw_name);
 543         if (err)
 544                 goto out;
 545         /* check pfp fw hdr version to decide if enable rs64 for gfx11.*/
 546         adev->gfx.rs64_enable = amdgpu_ucode_hdr_version(
 547                                 (union amdgpu_firmware_header *)
 548                                 adev->gfx.pfp_fw->data, 2, 0);
 549         if (adev->gfx.rs64_enable) {
 550                 dev_info(adev->dev, "CP RS64 enable\n");
 551                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP);
 552                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P0_STACK);
 553                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_PFP_P1_STACK);
 554         } else {
 555                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_PFP);
 556         }
 557
 558         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_me.bin", ucode_prefix);
 559         err = amdgpu_ucode_request(adev, &adev->gfx.me_fw, fw_name);
 560         if (err)
 561                 goto out;
 562         if (adev->gfx.rs64_enable) {
 563                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME);
 564                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P0_STACK);
 565                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_ME_P1_STACK);
 566         } else {
 567                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_ME);
 568         }
 569
 570         if (!amdgpu_sriov_vf(adev)) {
 571                 if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 0) &&
 572                     adev->pdev->revision == 0xCE)
 573                         snprintf(fw_name, sizeof(fw_name), "amdgpu/gc_11_0_0_rlc_1.bin");
 574                 else
 575                         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_rlc.bin", ucode_prefix);
 576                 err = amdgpu_ucode_request(adev, &adev->gfx.rlc_fw, fw_name);
 577                 if (err)
 578                         goto out;
 579                 rlc_hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
 580                 version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
 581                 version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
 582                 err = amdgpu_gfx_rlc_init_microcode(adev, version_major, version_minor);
 583                 if (err)
 584                         goto out;
 585         }
 586
 587         snprintf(fw_name, sizeof(fw_name), "amdgpu/%s_mec.bin", ucode_prefix);
 588         err = amdgpu_ucode_request(adev, &adev->gfx.mec_fw, fw_name);
 589         if (err)
 590                 goto out;
 591         if (adev->gfx.rs64_enable) {
 592                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC);
 593                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P0_STACK);
 594                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P1_STACK);
 595                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P2_STACK);
 596                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_RS64_MEC_P3_STACK);
 597         } else {
 598                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1);
 599                 amdgpu_gfx_cp_init_microcode(adev, AMDGPU_UCODE_ID_CP_MEC1_JT);
 600         }
 601
 602         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
 603                 err = gfx_v11_0_init_toc_microcode(adev, ucode_prefix);
 604
 605         /* only one MEC for gfx 11.0.0. */
 606         adev->gfx.mec2_fw = NULL;
 607
 608         gfx_v11_0_check_fw_cp_gfx_shadow(adev);
 609
 610         if (adev->gfx.imu.funcs && adev->gfx.imu.funcs->init_microcode) {
 611                 err = adev->gfx.imu.funcs->init_microcode(adev);
 612                 if (err)
 613                         DRM_ERROR("Failed to init imu firmware!\n");
 614                 return err;
 615         }
 616
 617 out:
 618         if (err) {
 619                 amdgpu_ucode_release(&adev->gfx.pfp_fw);
 620                 amdgpu_ucode_release(&adev->gfx.me_fw);
 621                 amdgpu_ucode_release(&adev->gfx.rlc_fw);
 622                 amdgpu_ucode_release(&adev->gfx.mec_fw);
 623         }
 624
 625         return err;
 626 }
 627
 628 static u32 gfx_v11_0_get_csb_size(struct amdgpu_device *adev)
 629 {
 630         u32 count = 0;
 631         const struct cs_section_def *sect = NULL;
 632         const struct cs_extent_def *ext = NULL;
 633
 634         /* begin clear state */
 635         count += 2;
 636         /* context control state */
 637         count += 3;
 638
 639         for (sect = gfx11_cs_data; sect->section != NULL; ++sect) {
 640                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 641                         if (sect->id == SECT_CONTEXT)
 642                                 count += 2 + ext->reg_count;
 643                         else
 644                                 return 0;
 645                 }
 646         }
 647
 648         /* set PA_SC_TILE_STEERING_OVERRIDE */
 649         count += 3;
 650         /* end clear state */
 651         count += 2;
 652         /* clear state */
 653         count += 2;
 654
 655         return count;
 656 }
 657
 658 static void gfx_v11_0_get_csb_buffer(struct amdgpu_device *adev,
 659                                     volatile u32 *buffer)
 660 {
 661         u32 count = 0, i;
 662         const struct cs_section_def *sect = NULL;
 663         const struct cs_extent_def *ext = NULL;
 664         int ctx_reg_offset;
 665
 666         if (adev->gfx.rlc.cs_data == NULL)
 667                 return;
 668         if (buffer == NULL)
 669                 return;
 670
 671         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 672         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
 673
 674         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CONTEXT_CONTROL, 1));
 675         buffer[count++] = cpu_to_le32(0x80000000);
 676         buffer[count++] = cpu_to_le32(0x80000000);
 677
 678         for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {
 679                 for (ext = sect->section; ext->extent != NULL; ++ext) {
 680                         if (sect->id == SECT_CONTEXT) {
 681                                 buffer[count++] =
 682                                         cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, ext->reg_count));
 683                                 buffer[count++] = cpu_to_le32(ext->reg_index -
 684                                                 PACKET3_SET_CONTEXT_REG_START);
 685                                 for (i = 0; i < ext->reg_count; i++)
 686                                         buffer[count++] = cpu_to_le32(ext->extent[i]);
 687                         } else {
 688                                 return;
 689                         }
 690                 }
 691         }
 692
 693         ctx_reg_offset =
 694                 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
 695         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_SET_CONTEXT_REG, 1));
 696         buffer[count++] = cpu_to_le32(ctx_reg_offset);
 697         buffer[count++] = cpu_to_le32(adev->gfx.config.pa_sc_tile_steering_override);
 698
 699         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_PREAMBLE_CNTL, 0));
 700         buffer[count++] = cpu_to_le32(PACKET3_PREAMBLE_END_CLEAR_STATE);
 701
 702         buffer[count++] = cpu_to_le32(PACKET3(PACKET3_CLEAR_STATE, 0));
 703         buffer[count++] = cpu_to_le32(0);
 704 }
 705
 706 static void gfx_v11_0_rlc_fini(struct amdgpu_device *adev)
 707 {
 708         /* clear state block */
 709         amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,
 710                         &adev->gfx.rlc.clear_state_gpu_addr,
 711                         (void **)&adev->gfx.rlc.cs_ptr);
 712
 713         /* jump table block */
 714         amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,
 715                         &adev->gfx.rlc.cp_table_gpu_addr,
 716                         (void **)&adev->gfx.rlc.cp_table_ptr);
 717 }
 718
 719 static void gfx_v11_0_init_rlcg_reg_access_ctrl(struct amdgpu_device *adev)
 720 {
 721         struct amdgpu_rlcg_reg_access_ctrl *reg_access_ctrl;
 722
 723         reg_access_ctrl = &adev->gfx.rlc.reg_access_ctrl[0];
 724         reg_access_ctrl->scratch_reg0 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG0);
 725         reg_access_ctrl->scratch_reg1 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG1);
 726         reg_access_ctrl->scratch_reg2 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG2);
 727         reg_access_ctrl->scratch_reg3 = SOC15_REG_OFFSET(GC, 0, regSCRATCH_REG3);
 728         reg_access_ctrl->grbm_cntl = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_CNTL);
 729         reg_access_ctrl->grbm_idx = SOC15_REG_OFFSET(GC, 0, regGRBM_GFX_INDEX);
 730         reg_access_ctrl->spare_int = SOC15_REG_OFFSET(GC, 0, regRLC_SPARE_INT_0);
 731         adev->gfx.rlc.rlcg_reg_access_supported = true;
 732 }
 733
 734 static int gfx_v11_0_rlc_init(struct amdgpu_device *adev)
 735 {
 736         const struct cs_section_def *cs_data;
 737         int r;
 738
 739         adev->gfx.rlc.cs_data = gfx11_cs_data;
 740
 741         cs_data = adev->gfx.rlc.cs_data;
 742
 743         if (cs_data) {
 744                 /* init clear state block */
 745                 r = amdgpu_gfx_rlc_init_csb(adev);
 746                 if (r)
 747                         return r;
 748         }
 749
 750         /* init spm vmid with 0xf */
 751         if (adev->gfx.rlc.funcs->update_spm_vmid)
 752                 adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);
 753
 754         return 0;
 755 }
 756
 757 static void gfx_v11_0_mec_fini(struct amdgpu_device *adev)
 758 {
 759         amdgpu_bo_free_kernel(&adev->gfx.mec.hpd_eop_obj, NULL, NULL);
 760         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_obj, NULL, NULL);
 761         amdgpu_bo_free_kernel(&adev->gfx.mec.mec_fw_data_obj, NULL, NULL);
 762 }
 763
 764 static void gfx_v11_0_me_init(struct amdgpu_device *adev)
 765 {
 766         bitmap_zero(adev->gfx.me.queue_bitmap, AMDGPU_MAX_GFX_QUEUES);
 767
 768         amdgpu_gfx_graphics_queue_acquire(adev);
 769 }
 770
 771 static int gfx_v11_0_mec_init(struct amdgpu_device *adev)
 772 {
 773         int r;
 774         u32 *hpd;
 775         size_t mec_hpd_size;
 776
 777         bitmap_zero(adev->gfx.mec_bitmap[0].queue_bitmap, AMDGPU_MAX_COMPUTE_QUEUES);
 778
 779         /* take ownership of the relevant compute queues */
 780         amdgpu_gfx_compute_queue_acquire(adev);
 781         mec_hpd_size = adev->gfx.num_compute_rings * GFX11_MEC_HPD_SIZE;
 782
 783         if (mec_hpd_size) {
 784                 r = amdgpu_bo_create_reserved(adev, mec_hpd_size, PAGE_SIZE,
 785                                               AMDGPU_GEM_DOMAIN_GTT,
 786                                               &adev->gfx.mec.hpd_eop_obj,
 787                                               &adev->gfx.mec.hpd_eop_gpu_addr,
 788                                               (void **)&hpd);
 789                 if (r) {
 790                         dev_warn(adev->dev, "(%d) create HDP EOP bo failed\n", r);
 791                         gfx_v11_0_mec_fini(adev);
 792                         return r;
 793                 }
 794
 795                 memset(hpd, 0, mec_hpd_size);
 796
 797                 amdgpu_bo_kunmap(adev->gfx.mec.hpd_eop_obj);
 798                 amdgpu_bo_unreserve(adev->gfx.mec.hpd_eop_obj);
 799         }
 800
 801         return 0;
 802 }
 803
 804 static uint32_t wave_read_ind(struct amdgpu_device *adev, uint32_t wave, uint32_t address)
 805 {
 806         WREG32_SOC15(GC, 0, regSQ_IND_INDEX,
 807                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
 808                 (address << SQ_IND_INDEX__INDEX__SHIFT));
 809         return RREG32_SOC15(GC, 0, regSQ_IND_DATA);
 810 }
 811
 812 static void wave_read_regs(struct amdgpu_device *adev, uint32_t wave,
 813                            uint32_t thread, uint32_t regno,
 814                            uint32_t num, uint32_t *out)
 815 {
 816         WREG32_SOC15(GC, 0, regSQ_IND_INDEX,
 817                 (wave << SQ_IND_INDEX__WAVE_ID__SHIFT) |
 818                 (regno << SQ_IND_INDEX__INDEX__SHIFT) |
 819                 (thread << SQ_IND_INDEX__WORKITEM_ID__SHIFT) |
 820                 (SQ_IND_INDEX__AUTO_INCR_MASK));
 821         while (num--)
 822                 *(out++) = RREG32_SOC15(GC, 0, regSQ_IND_DATA);
 823 }
 824
 825 static void gfx_v11_0_read_wave_data(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd, uint32_t wave, uint32_t *dst, int *no_fields)
 826 {
 827         /* in gfx11 the SIMD_ID is specified as part of the INSTANCE
 828          * field when performing a select_se_sh so it should be
 829          * zero here */
 830         WARN_ON(simd != 0);
 831
 832         /* type 3 wave data */
 833         dst[(*no_fields)++] = 3;
 834         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_STATUS);
 835         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_LO);
 836         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_PC_HI);
 837         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_LO);
 838         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_EXEC_HI);
 839         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID1);
 840         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_HW_ID2);
 841         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_GPR_ALLOC);
 842         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_LDS_ALLOC);
 843         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_TRAPSTS);
 844         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS);
 845         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_STS2);
 846         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_IB_DBG1);
 847         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_M0);
 848         dst[(*no_fields)++] = wave_read_ind(adev, wave, ixSQ_WAVE_MODE);
 849 }
 850
 851 static void gfx_v11_0_read_wave_sgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
 852                                      uint32_t wave, uint32_t start,
 853                                      uint32_t size, uint32_t *dst)
 854 {
 855         WARN_ON(simd != 0);
 856
 857         wave_read_regs(
 858                 adev, wave, 0, start + SQIND_WAVE_SGPRS_OFFSET, size,
 859                 dst);
 860 }
 861
 862 static void gfx_v11_0_read_wave_vgprs(struct amdgpu_device *adev, uint32_t xcc_id, uint32_t simd,
 863                                       uint32_t wave, uint32_t thread,
 864                                       uint32_t start, uint32_t size,
 865                                       uint32_t *dst)
 866 {
 867         wave_read_regs(
 868                 adev, wave, thread,
 869                 start + SQIND_WAVE_VGPRS_OFFSET, size, dst);
 870 }
 871
 872 static void gfx_v11_0_select_me_pipe_q(struct amdgpu_device *adev,
 873                                         u32 me, u32 pipe, u32 q, u32 vm, u32 xcc_id)
 874 {
 875         soc21_grbm_select(adev, me, pipe, q, vm);
 876 }
 877
 878 /* all sizes are in bytes */
 879 #define MQD_SHADOW_BASE_SIZE      73728
 880 #define MQD_SHADOW_BASE_ALIGNMENT 256
 881 #define MQD_FWWORKAREA_SIZE       484
 882 #define MQD_FWWORKAREA_ALIGNMENT  256
 883
 884 static int gfx_v11_0_get_gfx_shadow_info(struct amdgpu_device *adev,
 885                                          struct amdgpu_gfx_shadow_info *shadow_info)
 886 {
 887         if (adev->gfx.cp_gfx_shadow) {
 888                 shadow_info->shadow_size = MQD_SHADOW_BASE_SIZE;
 889                 shadow_info->shadow_alignment = MQD_SHADOW_BASE_ALIGNMENT;
 890                 shadow_info->csa_size = MQD_FWWORKAREA_SIZE;
 891                 shadow_info->csa_alignment = MQD_FWWORKAREA_ALIGNMENT;
 892                 return 0;
 893         } else {
 894                 memset(shadow_info, 0, sizeof(struct amdgpu_gfx_shadow_info));
 895                 return -ENOTSUPP;
 896         }
 897 }
 898
 899 static const struct amdgpu_gfx_funcs gfx_v11_0_gfx_funcs = {
 900         .get_gpu_clock_counter = &gfx_v11_0_get_gpu_clock_counter,
 901         .select_se_sh = &gfx_v11_0_select_se_sh,
 902         .read_wave_data = &gfx_v11_0_read_wave_data,
 903         .read_wave_sgprs = &gfx_v11_0_read_wave_sgprs,
 904         .read_wave_vgprs = &gfx_v11_0_read_wave_vgprs,
 905         .select_me_pipe_q = &gfx_v11_0_select_me_pipe_q,
 906         .update_perfmon_mgcg = &gfx_v11_0_update_perf_clk,
 907         .get_gfx_shadow_info = &gfx_v11_0_get_gfx_shadow_info,
 908 };
 909
 910 static int gfx_v11_0_gpu_early_init(struct amdgpu_device *adev)
 911 {
 912         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
 913         case IP_VERSION(11, 0, 0):
 914         case IP_VERSION(11, 0, 2):
 915                 adev->gfx.config.max_hw_contexts = 8;
 916                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
 917                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
 918                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
 919                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
 920                 break;
 921         case IP_VERSION(11, 0, 3):
 922                 adev->gfx.ras = &gfx_v11_0_3_ras;
 923                 adev->gfx.config.max_hw_contexts = 8;
 924                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
 925                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
 926                 adev->gfx.config.sc_hiz_tile_fifo_size = 0;
 927                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x4C0;
 928                 break;
 929         case IP_VERSION(11, 0, 1):
 930         case IP_VERSION(11, 0, 4):
 931         case IP_VERSION(11, 5, 0):
 932                 adev->gfx.config.max_hw_contexts = 8;
 933                 adev->gfx.config.sc_prim_fifo_size_frontend = 0x20;
 934                 adev->gfx.config.sc_prim_fifo_size_backend = 0x100;
 935                 adev->gfx.config.sc_hiz_tile_fifo_size = 0x80;
 936                 adev->gfx.config.sc_earlyz_tile_fifo_size = 0x300;
 937                 break;
 938         default:
 939                 BUG();
 940                 break;
 941         }
 942
 943         return 0;
 944 }
 945
 946 static int gfx_v11_0_gfx_ring_init(struct amdgpu_device *adev, int ring_id,
 947                                    int me, int pipe, int queue)
 948 {
 949         int r;
 950         struct amdgpu_ring *ring;
 951         unsigned int irq_type;
 952
 953         ring = &adev->gfx.gfx_ring[ring_id];
 954
 955         ring->me = me;
 956         ring->pipe = pipe;
 957         ring->queue = queue;
 958
 959         ring->ring_obj = NULL;
 960         ring->use_doorbell = true;
 961
 962         if (!ring_id)
 963                 ring->doorbell_index = adev->doorbell_index.gfx_ring0 << 1;
 964         else
 965                 ring->doorbell_index = adev->doorbell_index.gfx_ring1 << 1;
 966         ring->vm_hub = AMDGPU_GFXHUB(0);
 967         sprintf(ring->name, "gfx_%d.%d.%d", ring->me, ring->pipe, ring->queue);
 968
 969         irq_type = AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP + ring->pipe;
 970         r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
 971                              AMDGPU_RING_PRIO_DEFAULT, NULL);
 972         if (r)
 973                 return r;
 974         return 0;
 975 }
 976
 977 static int gfx_v11_0_compute_ring_init(struct amdgpu_device *adev, int ring_id,
 978                                        int mec, int pipe, int queue)
 979 {
 980         int r;
 981         unsigned irq_type;
 982         struct amdgpu_ring *ring;
 983         unsigned int hw_prio;
 984
 985         ring = &adev->gfx.compute_ring[ring_id];
 986
 987         /* mec0 is me1 */
 988         ring->me = mec + 1;
 989         ring->pipe = pipe;
 990         ring->queue = queue;
 991
 992         ring->ring_obj = NULL;
 993         ring->use_doorbell = true;
 994         ring->doorbell_index = (adev->doorbell_index.mec_ring0 + ring_id) << 1;
 995         ring->eop_gpu_addr = adev->gfx.mec.hpd_eop_gpu_addr
 996                                 + (ring_id * GFX11_MEC_HPD_SIZE);
 997         ring->vm_hub = AMDGPU_GFXHUB(0);
 998         sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
 999
1000         irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP
1001                 + ((ring->me - 1) * adev->gfx.mec.num_pipe_per_mec)
1002                 + ring->pipe;
1003         hw_prio = amdgpu_gfx_is_high_priority_compute_queue(adev, ring) ?
1004                         AMDGPU_GFX_PIPE_PRIO_HIGH : AMDGPU_GFX_PIPE_PRIO_NORMAL;
1005         /* type-2 packets are deprecated on MEC, use type-3 instead */
1006         r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type,
1007                              hw_prio, NULL);
1008         if (r)
1009                 return r;
1010
1011         return 0;
1012 }
1013
1014 static struct {
1015         SOC21_FIRMWARE_ID       id;
1016         unsigned int            offset;
1017         unsigned int            size;
1018 } rlc_autoload_info[SOC21_FIRMWARE_ID_MAX];
1019
1020 static void gfx_v11_0_parse_rlc_toc(struct amdgpu_device *adev, void *rlc_toc)
1021 {
1022         RLC_TABLE_OF_CONTENT *ucode = rlc_toc;
1023
1024         while (ucode && (ucode->id > SOC21_FIRMWARE_ID_INVALID) &&
1025                         (ucode->id < SOC21_FIRMWARE_ID_MAX)) {
1026                 rlc_autoload_info[ucode->id].id = ucode->id;
1027                 rlc_autoload_info[ucode->id].offset = ucode->offset * 4;
1028                 rlc_autoload_info[ucode->id].size = ucode->size * 4;
1029
1030                 ucode++;
1031         }
1032 }
1033
1034 static uint32_t gfx_v11_0_calc_toc_total_size(struct amdgpu_device *adev)
1035 {
1036         uint32_t total_size = 0;
1037         SOC21_FIRMWARE_ID id;
1038
1039         gfx_v11_0_parse_rlc_toc(adev, adev->psp.toc.start_addr);
1040
1041         for (id = SOC21_FIRMWARE_ID_RLC_G_UCODE; id < SOC21_FIRMWARE_ID_MAX; id++)
1042                 total_size += rlc_autoload_info[id].size;
1043
1044         /* In case the offset in rlc toc ucode is aligned */
1045         if (total_size < rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset)
1046                 total_size = rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].offset +
1047                         rlc_autoload_info[SOC21_FIRMWARE_ID_MAX-1].size;
1048
1049         return total_size;
1050 }
1051
1052 static int gfx_v11_0_rlc_autoload_buffer_init(struct amdgpu_device *adev)
1053 {
1054         int r;
1055         uint32_t total_size;
1056
1057         total_size = gfx_v11_0_calc_toc_total_size(adev);
1058
1059         r = amdgpu_bo_create_reserved(adev, total_size, 64 * 1024,
1060                                       AMDGPU_GEM_DOMAIN_VRAM |
1061                                       AMDGPU_GEM_DOMAIN_GTT,
1062                                       &adev->gfx.rlc.rlc_autoload_bo,
1063                                       &adev->gfx.rlc.rlc_autoload_gpu_addr,
1064                                       (void **)&adev->gfx.rlc.rlc_autoload_ptr);
1065
1066         if (r) {
1067                 dev_err(adev->dev, "(%d) failed to create fw autoload bo\n", r);
1068                 return r;
1069         }
1070
1071         return 0;
1072 }
1073
1074 static void gfx_v11_0_rlc_backdoor_autoload_copy_ucode(struct amdgpu_device *adev,
1075                                               SOC21_FIRMWARE_ID id,
1076                                               const void *fw_data,
1077                                               uint32_t fw_size,
1078                                               uint32_t *fw_autoload_mask)
1079 {
1080         uint32_t toc_offset;
1081         uint32_t toc_fw_size;
1082         char *ptr = adev->gfx.rlc.rlc_autoload_ptr;
1083
1084         if (id <= SOC21_FIRMWARE_ID_INVALID || id >= SOC21_FIRMWARE_ID_MAX)
1085                 return;
1086
1087         toc_offset = rlc_autoload_info[id].offset;
1088         toc_fw_size = rlc_autoload_info[id].size;
1089
1090         if (fw_size == 0)
1091                 fw_size = toc_fw_size;
1092
1093         if (fw_size > toc_fw_size)
1094                 fw_size = toc_fw_size;
1095
1096         memcpy(ptr + toc_offset, fw_data, fw_size);
1097
1098         if (fw_size < toc_fw_size)
1099                 memset(ptr + toc_offset + fw_size, 0, toc_fw_size - fw_size);
1100
1101         if ((id != SOC21_FIRMWARE_ID_RS64_PFP) && (id != SOC21_FIRMWARE_ID_RS64_ME))
1102                 *(uint64_t *)fw_autoload_mask |= 1ULL << id;
1103 }
1104
1105 static void gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(struct amdgpu_device *adev,
1106                                                         uint32_t *fw_autoload_mask)
1107 {
1108         void *data;
1109         uint32_t size;
1110         uint64_t *toc_ptr;
1111
1112         *(uint64_t *)fw_autoload_mask |= 0x1;
1113
1114         DRM_DEBUG("rlc autoload enabled fw: 0x%llx\n", *(uint64_t *)fw_autoload_mask);
1115
1116         data = adev->psp.toc.start_addr;
1117         size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_TOC].size;
1118
1119         toc_ptr = (uint64_t *)data + size / 8 - 1;
1120         *toc_ptr = *(uint64_t *)fw_autoload_mask;
1121
1122         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_TOC,
1123                                         data, size, fw_autoload_mask);
1124 }
1125
1126 static void gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(struct amdgpu_device *adev,
1127                                                         uint32_t *fw_autoload_mask)
1128 {
1129         const __le32 *fw_data;
1130         uint32_t fw_size;
1131         const struct gfx_firmware_header_v1_0 *cp_hdr;
1132         const struct gfx_firmware_header_v2_0 *cpv2_hdr;
1133         const struct rlc_firmware_header_v2_0 *rlc_hdr;
1134         const struct rlc_firmware_header_v2_2 *rlcv22_hdr;
1135         uint16_t version_major, version_minor;
1136
1137         if (adev->gfx.rs64_enable) {
1138                 /* pfp ucode */
1139                 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1140                         adev->gfx.pfp_fw->data;
1141                 /* instruction */
1142                 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1143                         le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1144                 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1145                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP,
1146                                                 fw_data, fw_size, fw_autoload_mask);
1147                 /* data */
1148                 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1149                         le32_to_cpu(cpv2_hdr->data_offset_bytes));
1150                 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1151                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK,
1152                                                 fw_data, fw_size, fw_autoload_mask);
1153                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_PFP_P1_STACK,
1154                                                 fw_data, fw_size, fw_autoload_mask);
1155                 /* me ucode */
1156                 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1157                         adev->gfx.me_fw->data;
1158                 /* instruction */
1159                 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1160                         le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1161                 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1162                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME,
1163                                                 fw_data, fw_size, fw_autoload_mask);
1164                 /* data */
1165                 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1166                         le32_to_cpu(cpv2_hdr->data_offset_bytes));
1167                 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1168                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P0_STACK,
1169                                                 fw_data, fw_size, fw_autoload_mask);
1170                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_ME_P1_STACK,
1171                                                 fw_data, fw_size, fw_autoload_mask);
1172                 /* mec ucode */
1173                 cpv2_hdr = (const struct gfx_firmware_header_v2_0 *)
1174                         adev->gfx.mec_fw->data;
1175                 /* instruction */
1176                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1177                         le32_to_cpu(cpv2_hdr->ucode_offset_bytes));
1178                 fw_size = le32_to_cpu(cpv2_hdr->ucode_size_bytes);
1179                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC,
1180                                                 fw_data, fw_size, fw_autoload_mask);
1181                 /* data */
1182                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1183                         le32_to_cpu(cpv2_hdr->data_offset_bytes));
1184                 fw_size = le32_to_cpu(cpv2_hdr->data_size_bytes);
1185                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK,
1186                                                 fw_data, fw_size, fw_autoload_mask);
1187                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P1_STACK,
1188                                                 fw_data, fw_size, fw_autoload_mask);
1189                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P2_STACK,
1190                                                 fw_data, fw_size, fw_autoload_mask);
1191                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RS64_MEC_P3_STACK,
1192                                                 fw_data, fw_size, fw_autoload_mask);
1193         } else {
1194                 /* pfp ucode */
1195                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1196                         adev->gfx.pfp_fw->data;
1197                 fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
1198                                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
1199                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1200                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_PFP,
1201                                                 fw_data, fw_size, fw_autoload_mask);
1202
1203                 /* me ucode */
1204                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1205                         adev->gfx.me_fw->data;
1206                 fw_data = (const __le32 *)(adev->gfx.me_fw->data +
1207                                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
1208                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes);
1209                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_ME,
1210                                                 fw_data, fw_size, fw_autoload_mask);
1211
1212                 /* mec ucode */
1213                 cp_hdr = (const struct gfx_firmware_header_v1_0 *)
1214                         adev->gfx.mec_fw->data;
1215                 fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
1216                                 le32_to_cpu(cp_hdr->header.ucode_array_offset_bytes));
1217                 fw_size = le32_to_cpu(cp_hdr->header.ucode_size_bytes) -
1218                         cp_hdr->jt_size * 4;
1219                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_CP_MEC,
1220                                                 fw_data, fw_size, fw_autoload_mask);
1221         }
1222
1223         /* rlc ucode */
1224         rlc_hdr = (const struct rlc_firmware_header_v2_0 *)
1225                 adev->gfx.rlc_fw->data;
1226         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1227                         le32_to_cpu(rlc_hdr->header.ucode_array_offset_bytes));
1228         fw_size = le32_to_cpu(rlc_hdr->header.ucode_size_bytes);
1229         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLC_G_UCODE,
1230                                         fw_data, fw_size, fw_autoload_mask);
1231
1232         version_major = le16_to_cpu(rlc_hdr->header.header_version_major);
1233         version_minor = le16_to_cpu(rlc_hdr->header.header_version_minor);
1234         if (version_major == 2) {
1235                 if (version_minor >= 2) {
1236                         rlcv22_hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
1237
1238                         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1239                                         le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_offset_bytes));
1240                         fw_size = le32_to_cpu(rlcv22_hdr->rlc_iram_ucode_size_bytes);
1241                         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_UCODE,
1242                                         fw_data, fw_size, fw_autoload_mask);
1243
1244                         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1245                                         le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_offset_bytes));
1246                         fw_size = le32_to_cpu(rlcv22_hdr->rlc_dram_ucode_size_bytes);
1247                         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev, SOC21_FIRMWARE_ID_RLX6_DRAM_BOOT,
1248                                         fw_data, fw_size, fw_autoload_mask);
1249                 }
1250         }
1251 }
1252
1253 static void gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(struct amdgpu_device *adev,
1254                                                         uint32_t *fw_autoload_mask)
1255 {
1256         const __le32 *fw_data;
1257         uint32_t fw_size;
1258         const struct sdma_firmware_header_v2_0 *sdma_hdr;
1259
1260         sdma_hdr = (const struct sdma_firmware_header_v2_0 *)
1261                 adev->sdma.instance[0].fw->data;
1262         fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data +
1263                         le32_to_cpu(sdma_hdr->header.ucode_array_offset_bytes));
1264         fw_size = le32_to_cpu(sdma_hdr->ctx_ucode_size_bytes);
1265
1266         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev,
1267                         SOC21_FIRMWARE_ID_SDMA_UCODE_TH0, fw_data, fw_size, fw_autoload_mask);
1268
1269         fw_data = (const __le32 *) (adev->sdma.instance[0].fw->data +
1270                         le32_to_cpu(sdma_hdr->ctl_ucode_offset));
1271         fw_size = le32_to_cpu(sdma_hdr->ctl_ucode_size_bytes);
1272
1273         gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev,
1274                         SOC21_FIRMWARE_ID_SDMA_UCODE_TH1, fw_data, fw_size, fw_autoload_mask);
1275 }
1276
1277 static void gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(struct amdgpu_device *adev,
1278                                                         uint32_t *fw_autoload_mask)
1279 {
1280         const __le32 *fw_data;
1281         unsigned fw_size;
1282         const struct mes_firmware_header_v1_0 *mes_hdr;
1283         int pipe, ucode_id, data_id;
1284
1285         for (pipe = 0; pipe < 2; pipe++) {
1286                 if (pipe==0) {
1287                         ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P0;
1288                         data_id  = SOC21_FIRMWARE_ID_RS64_MES_P0_STACK;
1289                 } else {
1290                         ucode_id = SOC21_FIRMWARE_ID_RS64_MES_P1;
1291                         data_id  = SOC21_FIRMWARE_ID_RS64_MES_P1_STACK;
1292                 }
1293
1294                 mes_hdr = (const struct mes_firmware_header_v1_0 *)
1295                         adev->mes.fw[pipe]->data;
1296
1297                 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
1298                                 le32_to_cpu(mes_hdr->mes_ucode_offset_bytes));
1299                 fw_size = le32_to_cpu(mes_hdr->mes_ucode_size_bytes);
1300
1301                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev,
1302                                 ucode_id, fw_data, fw_size, fw_autoload_mask);
1303
1304                 fw_data = (const __le32 *)(adev->mes.fw[pipe]->data +
1305                                 le32_to_cpu(mes_hdr->mes_ucode_data_offset_bytes));
1306                 fw_size = le32_to_cpu(mes_hdr->mes_ucode_data_size_bytes);
1307
1308                 gfx_v11_0_rlc_backdoor_autoload_copy_ucode(adev,
1309                                 data_id, fw_data, fw_size, fw_autoload_mask);
1310         }
1311 }
1312
1313 static int gfx_v11_0_rlc_backdoor_autoload_enable(struct amdgpu_device *adev)
1314 {
1315         uint32_t rlc_g_offset, rlc_g_size;
1316         uint64_t gpu_addr;
1317         uint32_t autoload_fw_id[2];
1318
1319         memset(autoload_fw_id, 0, sizeof(uint32_t) * 2);
1320
1321         /* RLC autoload sequence 2: copy ucode */
1322         gfx_v11_0_rlc_backdoor_autoload_copy_sdma_ucode(adev, autoload_fw_id);
1323         gfx_v11_0_rlc_backdoor_autoload_copy_gfx_ucode(adev, autoload_fw_id);
1324         gfx_v11_0_rlc_backdoor_autoload_copy_mes_ucode(adev, autoload_fw_id);
1325         gfx_v11_0_rlc_backdoor_autoload_copy_toc_ucode(adev, autoload_fw_id);
1326
1327         rlc_g_offset = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].offset;
1328         rlc_g_size = rlc_autoload_info[SOC21_FIRMWARE_ID_RLC_G_UCODE].size;
1329         gpu_addr = adev->gfx.rlc.rlc_autoload_gpu_addr + rlc_g_offset;
1330
1331         WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_HI, upper_32_bits(gpu_addr));
1332         WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_ADDR_LO, lower_32_bits(gpu_addr));
1333
1334         WREG32_SOC15(GC, 0, regGFX_IMU_RLC_BOOTLOADER_SIZE, rlc_g_size);
1335
1336         /* RLC autoload sequence 3: load IMU fw */
1337         if (adev->gfx.imu.funcs->load_microcode)
1338                 adev->gfx.imu.funcs->load_microcode(adev);
1339         /* RLC autoload sequence 4 init IMU fw */
1340         if (adev->gfx.imu.funcs->setup_imu)
1341                 adev->gfx.imu.funcs->setup_imu(adev);
1342         if (adev->gfx.imu.funcs->start_imu)
1343                 adev->gfx.imu.funcs->start_imu(adev);
1344
1345         /* RLC autoload sequence 5 disable gpa mode */
1346         gfx_v11_0_disable_gpa_mode(adev);
1347
1348         return 0;
1349 }
1350
1351 static int gfx_v11_0_sw_init(void *handle)
1352 {
1353         int i, j, k, r, ring_id = 0;
1354         struct amdgpu_kiq *kiq;
1355         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1356
1357         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
1358         case IP_VERSION(11, 0, 0):
1359         case IP_VERSION(11, 0, 2):
1360         case IP_VERSION(11, 0, 3):
1361                 adev->gfx.me.num_me = 1;
1362                 adev->gfx.me.num_pipe_per_me = 1;
1363                 adev->gfx.me.num_queue_per_pipe = 1;
1364                 adev->gfx.mec.num_mec = 2;
1365                 adev->gfx.mec.num_pipe_per_mec = 4;
1366                 adev->gfx.mec.num_queue_per_pipe = 4;
1367                 break;
1368         case IP_VERSION(11, 0, 1):
1369         case IP_VERSION(11, 0, 4):
1370         case IP_VERSION(11, 5, 0):
1371                 adev->gfx.me.num_me = 1;
1372                 adev->gfx.me.num_pipe_per_me = 1;
1373                 adev->gfx.me.num_queue_per_pipe = 1;
1374                 adev->gfx.mec.num_mec = 1;
1375                 adev->gfx.mec.num_pipe_per_mec = 4;
1376                 adev->gfx.mec.num_queue_per_pipe = 4;
1377                 break;
1378         default:
1379                 adev->gfx.me.num_me = 1;
1380                 adev->gfx.me.num_pipe_per_me = 1;
1381                 adev->gfx.me.num_queue_per_pipe = 1;
1382                 adev->gfx.mec.num_mec = 1;
1383                 adev->gfx.mec.num_pipe_per_mec = 4;
1384                 adev->gfx.mec.num_queue_per_pipe = 8;
1385                 break;
1386         }
1387
1388         /* Enable CG flag in one VF mode for enabling RLC safe mode enter/exit */
1389         if (amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 0, 3) &&
1390             amdgpu_sriov_is_pp_one_vf(adev))
1391                 adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG;
1392
1393         /* EOP Event */
1394         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1395                               GFX_11_0_0__SRCID__CP_EOP_INTERRUPT,
1396                               &adev->gfx.eop_irq);
1397         if (r)
1398                 return r;
1399
1400         /* Privileged reg */
1401         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1402                               GFX_11_0_0__SRCID__CP_PRIV_REG_FAULT,
1403                               &adev->gfx.priv_reg_irq);
1404         if (r)
1405                 return r;
1406
1407         /* Privileged inst */
1408         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GRBM_CP,
1409                               GFX_11_0_0__SRCID__CP_PRIV_INSTR_FAULT,
1410                               &adev->gfx.priv_inst_irq);
1411         if (r)
1412                 return r;
1413
1414         /* FED error */
1415         r = amdgpu_irq_add_id(adev, SOC21_IH_CLIENTID_GFX,
1416                                   GFX_11_0_0__SRCID__RLC_GC_FED_INTERRUPT,
1417                                   &adev->gfx.rlc_gc_fed_irq);
1418         if (r)
1419                 return r;
1420
1421         adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
1422
1423         gfx_v11_0_me_init(adev);
1424
1425         r = gfx_v11_0_rlc_init(adev);
1426         if (r) {
1427                 DRM_ERROR("Failed to init rlc BOs!\n");
1428                 return r;
1429         }
1430
1431         r = gfx_v11_0_mec_init(adev);
1432         if (r) {
1433                 DRM_ERROR("Failed to init MEC BOs!\n");
1434                 return r;
1435         }
1436
1437         /* set up the gfx ring */
1438         for (i = 0; i < adev->gfx.me.num_me; i++) {
1439                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
1440                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
1441                                 if (!amdgpu_gfx_is_me_queue_enabled(adev, i, k, j))
1442                                         continue;
1443
1444                                 r = gfx_v11_0_gfx_ring_init(adev, ring_id,
1445                                                             i, k, j);
1446                                 if (r)
1447                                         return r;
1448                                 ring_id++;
1449                         }
1450                 }
1451         }
1452
1453         ring_id = 0;
1454         /* set up the compute queues - allocate horizontally across pipes */
1455         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
1456                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
1457                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
1458                                 if (!amdgpu_gfx_is_mec_queue_enabled(adev, 0, i,
1459                                                                      k, j))
1460                                         continue;
1461
1462                                 r = gfx_v11_0_compute_ring_init(adev, ring_id,
1463                                                                 i, k, j);
1464                                 if (r)
1465                                         return r;
1466
1467                                 ring_id++;
1468                         }
1469                 }
1470         }
1471
1472         if (!adev->enable_mes_kiq) {
1473                 r = amdgpu_gfx_kiq_init(adev, GFX11_MEC_HPD_SIZE, 0);
1474                 if (r) {
1475                         DRM_ERROR("Failed to init KIQ BOs!\n");
1476                         return r;
1477                 }
1478
1479                 kiq = &adev->gfx.kiq[0];
1480                 r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq, 0);
1481                 if (r)
1482                         return r;
1483         }
1484
1485         r = amdgpu_gfx_mqd_sw_init(adev, sizeof(struct v11_compute_mqd), 0);
1486         if (r)
1487                 return r;
1488
1489         /* allocate visible FB for rlc auto-loading fw */
1490         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
1491                 r = gfx_v11_0_rlc_autoload_buffer_init(adev);
1492                 if (r)
1493                         return r;
1494         }
1495
1496         r = gfx_v11_0_gpu_early_init(adev);
1497         if (r)
1498                 return r;
1499
1500         if (amdgpu_gfx_ras_sw_init(adev)) {
1501                 dev_err(adev->dev, "Failed to initialize gfx ras block!\n");
1502                 return -EINVAL;
1503         }
1504
1505         return 0;
1506 }
1507
1508 static void gfx_v11_0_pfp_fini(struct amdgpu_device *adev)
1509 {
1510         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_obj,
1511                               &adev->gfx.pfp.pfp_fw_gpu_addr,
1512                               (void **)&adev->gfx.pfp.pfp_fw_ptr);
1513
1514         amdgpu_bo_free_kernel(&adev->gfx.pfp.pfp_fw_data_obj,
1515                               &adev->gfx.pfp.pfp_fw_data_gpu_addr,
1516                               (void **)&adev->gfx.pfp.pfp_fw_data_ptr);
1517 }
1518
1519 static void gfx_v11_0_me_fini(struct amdgpu_device *adev)
1520 {
1521         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_obj,
1522                               &adev->gfx.me.me_fw_gpu_addr,
1523                               (void **)&adev->gfx.me.me_fw_ptr);
1524
1525         amdgpu_bo_free_kernel(&adev->gfx.me.me_fw_data_obj,
1526                                &adev->gfx.me.me_fw_data_gpu_addr,
1527                                (void **)&adev->gfx.me.me_fw_data_ptr);
1528 }
1529
1530 static void gfx_v11_0_rlc_autoload_buffer_fini(struct amdgpu_device *adev)
1531 {
1532         amdgpu_bo_free_kernel(&adev->gfx.rlc.rlc_autoload_bo,
1533                         &adev->gfx.rlc.rlc_autoload_gpu_addr,
1534                         (void **)&adev->gfx.rlc.rlc_autoload_ptr);
1535 }
1536
1537 static int gfx_v11_0_sw_fini(void *handle)
1538 {
1539         int i;
1540         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
1541
1542         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
1543                 amdgpu_ring_fini(&adev->gfx.gfx_ring[i]);
1544         for (i = 0; i < adev->gfx.num_compute_rings; i++)
1545                 amdgpu_ring_fini(&adev->gfx.compute_ring[i]);
1546
1547         amdgpu_gfx_mqd_sw_fini(adev, 0);
1548
1549         if (!adev->enable_mes_kiq) {
1550                 amdgpu_gfx_kiq_free_ring(&adev->gfx.kiq[0].ring);
1551                 amdgpu_gfx_kiq_fini(adev, 0);
1552         }
1553
1554         gfx_v11_0_pfp_fini(adev);
1555         gfx_v11_0_me_fini(adev);
1556         gfx_v11_0_rlc_fini(adev);
1557         gfx_v11_0_mec_fini(adev);
1558
1559         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO)
1560                 gfx_v11_0_rlc_autoload_buffer_fini(adev);
1561
1562         gfx_v11_0_free_microcode(adev);
1563
1564         return 0;
1565 }
1566
1567 static void gfx_v11_0_select_se_sh(struct amdgpu_device *adev, u32 se_num,
1568                                    u32 sh_num, u32 instance, int xcc_id)
1569 {
1570         u32 data;
1571
1572         if (instance == 0xffffffff)
1573                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX,
1574                                      INSTANCE_BROADCAST_WRITES, 1);
1575         else
1576                 data = REG_SET_FIELD(0, GRBM_GFX_INDEX, INSTANCE_INDEX,
1577                                      instance);
1578
1579         if (se_num == 0xffffffff)
1580                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_BROADCAST_WRITES,
1581                                      1);
1582         else
1583                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SE_INDEX, se_num);
1584
1585         if (sh_num == 0xffffffff)
1586                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_BROADCAST_WRITES,
1587                                      1);
1588         else
1589                 data = REG_SET_FIELD(data, GRBM_GFX_INDEX, SA_INDEX, sh_num);
1590
1591         WREG32_SOC15(GC, 0, regGRBM_GFX_INDEX, data);
1592 }
1593
1594 static u32 gfx_v11_0_get_sa_active_bitmap(struct amdgpu_device *adev)
1595 {
1596         u32 gc_disabled_sa_mask, gc_user_disabled_sa_mask, sa_mask;
1597
1598         gc_disabled_sa_mask = RREG32_SOC15(GC, 0, regCC_GC_SA_UNIT_DISABLE);
1599         gc_disabled_sa_mask = REG_GET_FIELD(gc_disabled_sa_mask,
1600                                            CC_GC_SA_UNIT_DISABLE,
1601                                            SA_DISABLE);
1602         gc_user_disabled_sa_mask = RREG32_SOC15(GC, 0, regGC_USER_SA_UNIT_DISABLE);
1603         gc_user_disabled_sa_mask = REG_GET_FIELD(gc_user_disabled_sa_mask,
1604                                                  GC_USER_SA_UNIT_DISABLE,
1605                                                  SA_DISABLE);
1606         sa_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_sh_per_se *
1607                                             adev->gfx.config.max_shader_engines);
1608
1609         return sa_mask & (~(gc_disabled_sa_mask | gc_user_disabled_sa_mask));
1610 }
1611
1612 static u32 gfx_v11_0_get_rb_active_bitmap(struct amdgpu_device *adev)
1613 {
1614         u32 gc_disabled_rb_mask, gc_user_disabled_rb_mask;
1615         u32 rb_mask;
1616
1617         gc_disabled_rb_mask = RREG32_SOC15(GC, 0, regCC_RB_BACKEND_DISABLE);
1618         gc_disabled_rb_mask = REG_GET_FIELD(gc_disabled_rb_mask,
1619                                             CC_RB_BACKEND_DISABLE,
1620                                             BACKEND_DISABLE);
1621         gc_user_disabled_rb_mask = RREG32_SOC15(GC, 0, regGC_USER_RB_BACKEND_DISABLE);
1622         gc_user_disabled_rb_mask = REG_GET_FIELD(gc_user_disabled_rb_mask,
1623                                                  GC_USER_RB_BACKEND_DISABLE,
1624                                                  BACKEND_DISABLE);
1625         rb_mask = amdgpu_gfx_create_bitmask(adev->gfx.config.max_backends_per_se *
1626                                             adev->gfx.config.max_shader_engines);
1627
1628         return rb_mask & (~(gc_disabled_rb_mask | gc_user_disabled_rb_mask));
1629 }
1630
1631 static void gfx_v11_0_setup_rb(struct amdgpu_device *adev)
1632 {
1633         u32 rb_bitmap_width_per_sa;
1634         u32 max_sa;
1635         u32 active_sa_bitmap;
1636         u32 global_active_rb_bitmap;
1637         u32 active_rb_bitmap = 0;
1638         u32 i;
1639
1640         /* query sa bitmap from SA_UNIT_DISABLE registers */
1641         active_sa_bitmap = gfx_v11_0_get_sa_active_bitmap(adev);
1642         /* query rb bitmap from RB_BACKEND_DISABLE registers */
1643         global_active_rb_bitmap = gfx_v11_0_get_rb_active_bitmap(adev);
1644
1645         /* generate active rb bitmap according to active sa bitmap */
1646         max_sa = adev->gfx.config.max_shader_engines *
1647                  adev->gfx.config.max_sh_per_se;
1648         rb_bitmap_width_per_sa = adev->gfx.config.max_backends_per_se /
1649                                  adev->gfx.config.max_sh_per_se;
1650         for (i = 0; i < max_sa; i++) {
1651                 if (active_sa_bitmap & (1 << i))
1652                         active_rb_bitmap |= (0x3 << (i * rb_bitmap_width_per_sa));
1653         }
1654
1655         active_rb_bitmap |= global_active_rb_bitmap;
1656         adev->gfx.config.backend_enable_mask = active_rb_bitmap;
1657         adev->gfx.config.num_rbs = hweight32(active_rb_bitmap);
1658 }
1659
1660 #define DEFAULT_SH_MEM_BASES    (0x6000)
1661 #define LDS_APP_BASE           0x1
1662 #define SCRATCH_APP_BASE       0x2
1663
1664 static void gfx_v11_0_init_compute_vmid(struct amdgpu_device *adev)
1665 {
1666         int i;
1667         uint32_t sh_mem_bases;
1668         uint32_t data;
1669
1670         /*
1671          * Configure apertures:
1672          * LDS:         0x60000000'00000000 - 0x60000001'00000000 (4GB)
1673          * Scratch:     0x60000001'00000000 - 0x60000002'00000000 (4GB)
1674          * GPUVM:       0x60010000'00000000 - 0x60020000'00000000 (1TB)
1675          */
1676         sh_mem_bases = (LDS_APP_BASE << SH_MEM_BASES__SHARED_BASE__SHIFT) |
1677                         SCRATCH_APP_BASE;
1678
1679         mutex_lock(&adev->srbm_mutex);
1680         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
1681                 soc21_grbm_select(adev, 0, 0, 0, i);
1682                 /* CP and shaders */
1683                 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1684                 WREG32_SOC15(GC, 0, regSH_MEM_BASES, sh_mem_bases);
1685
1686                 /* Enable trap for each kfd vmid. */
1687                 data = RREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL);
1688                 data = REG_SET_FIELD(data, SPI_GDBG_PER_VMID_CNTL, TRAP_EN, 1);
1689                 WREG32_SOC15(GC, 0, regSPI_GDBG_PER_VMID_CNTL, data);
1690         }
1691         soc21_grbm_select(adev, 0, 0, 0, 0);
1692         mutex_unlock(&adev->srbm_mutex);
1693
1694         /* Initialize all compute VMIDs to have no GDS, GWS, or OA
1695            acccess. These should be enabled by FW for target VMIDs. */
1696         for (i = adev->vm_manager.first_kfd_vmid; i < AMDGPU_NUM_VMID; i++) {
1697                 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * i, 0);
1698                 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * i, 0);
1699                 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, i, 0);
1700                 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, i, 0);
1701         }
1702 }
1703
1704 static void gfx_v11_0_init_gds_vmid(struct amdgpu_device *adev)
1705 {
1706         int vmid;
1707
1708         /*
1709          * Initialize all compute and user-gfx VMIDs to have no GDS, GWS, or OA
1710          * access. Compute VMIDs should be enabled by FW for target VMIDs,
1711          * the driver can enable them for graphics. VMID0 should maintain
1712          * access so that HWS firmware can save/restore entries.
1713          */
1714         for (vmid = 1; vmid < 16; vmid++) {
1715                 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_BASE, 2 * vmid, 0);
1716                 WREG32_SOC15_OFFSET(GC, 0, regGDS_VMID0_SIZE, 2 * vmid, 0);
1717                 WREG32_SOC15_OFFSET(GC, 0, regGDS_GWS_VMID0, vmid, 0);
1718                 WREG32_SOC15_OFFSET(GC, 0, regGDS_OA_VMID0, vmid, 0);
1719         }
1720 }
1721
1722 static void gfx_v11_0_tcp_harvest(struct amdgpu_device *adev)
1723 {
1724         /* TODO: harvest feature to be added later. */
1725 }
1726
1727 static void gfx_v11_0_get_tcc_info(struct amdgpu_device *adev)
1728 {
1729         /* TCCs are global (not instanced). */
1730         uint32_t tcc_disable = RREG32_SOC15(GC, 0, regCGTS_TCC_DISABLE) |
1731                                RREG32_SOC15(GC, 0, regCGTS_USER_TCC_DISABLE);
1732
1733         adev->gfx.config.tcc_disabled_mask =
1734                 REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, TCC_DISABLE) |
1735                 (REG_GET_FIELD(tcc_disable, CGTS_TCC_DISABLE, HI_TCC_DISABLE) << 16);
1736 }
1737
1738 static void gfx_v11_0_constants_init(struct amdgpu_device *adev)
1739 {
1740         u32 tmp;
1741         int i;
1742
1743         if (!amdgpu_sriov_vf(adev))
1744                 WREG32_FIELD15_PREREG(GC, 0, GRBM_CNTL, READ_TIMEOUT, 0xff);
1745
1746         gfx_v11_0_setup_rb(adev);
1747         gfx_v11_0_get_cu_info(adev, &adev->gfx.cu_info);
1748         gfx_v11_0_get_tcc_info(adev);
1749         adev->gfx.config.pa_sc_tile_steering_override = 0;
1750
1751         /* Set whether texture coordinate truncation is conformant. */
1752         tmp = RREG32_SOC15(GC, 0, regTA_CNTL2);
1753         adev->gfx.config.ta_cntl2_truncate_coord_mode =
1754                 REG_GET_FIELD(tmp, TA_CNTL2, TRUNCATE_COORD_MODE);
1755
1756         /* XXX SH_MEM regs */
1757         /* where to put LDS, scratch, GPUVM in FSA64 space */
1758         mutex_lock(&adev->srbm_mutex);
1759         for (i = 0; i < adev->vm_manager.id_mgr[AMDGPU_GFXHUB(0)].num_ids; i++) {
1760                 soc21_grbm_select(adev, 0, 0, 0, i);
1761                 /* CP and shaders */
1762                 WREG32_SOC15(GC, 0, regSH_MEM_CONFIG, DEFAULT_SH_MEM_CONFIG);
1763                 if (i != 0) {
1764                         tmp = REG_SET_FIELD(0, SH_MEM_BASES, PRIVATE_BASE,
1765                                 (adev->gmc.private_aperture_start >> 48));
1766                         tmp = REG_SET_FIELD(tmp, SH_MEM_BASES, SHARED_BASE,
1767                                 (adev->gmc.shared_aperture_start >> 48));
1768                         WREG32_SOC15(GC, 0, regSH_MEM_BASES, tmp);
1769                 }
1770         }
1771         soc21_grbm_select(adev, 0, 0, 0, 0);
1772
1773         mutex_unlock(&adev->srbm_mutex);
1774
1775         gfx_v11_0_init_compute_vmid(adev);
1776         gfx_v11_0_init_gds_vmid(adev);
1777 }
1778
1779 static void gfx_v11_0_enable_gui_idle_interrupt(struct amdgpu_device *adev,
1780                                                bool enable)
1781 {
1782         u32 tmp;
1783
1784         if (amdgpu_sriov_vf(adev))
1785                 return;
1786
1787         tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0);
1788
1789         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_BUSY_INT_ENABLE,
1790                             enable ? 1 : 0);
1791         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CNTX_EMPTY_INT_ENABLE,
1792                             enable ? 1 : 0);
1793         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, CMP_BUSY_INT_ENABLE,
1794                             enable ? 1 : 0);
1795         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL_RING0, GFX_IDLE_INT_ENABLE,
1796                             enable ? 1 : 0);
1797
1798         WREG32_SOC15(GC, 0, regCP_INT_CNTL_RING0, tmp);
1799 }
1800
1801 static int gfx_v11_0_init_csb(struct amdgpu_device *adev)
1802 {
1803         adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);
1804
1805         WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_HI,
1806                         adev->gfx.rlc.clear_state_gpu_addr >> 32);
1807         WREG32_SOC15(GC, 0, regRLC_CSIB_ADDR_LO,
1808                         adev->gfx.rlc.clear_state_gpu_addr & 0xfffffffc);
1809         WREG32_SOC15(GC, 0, regRLC_CSIB_LENGTH, adev->gfx.rlc.clear_state_size);
1810
1811         return 0;
1812 }
1813
1814 static void gfx_v11_0_rlc_stop(struct amdgpu_device *adev)
1815 {
1816         u32 tmp = RREG32_SOC15(GC, 0, regRLC_CNTL);
1817
1818         tmp = REG_SET_FIELD(tmp, RLC_CNTL, RLC_ENABLE_F32, 0);
1819         WREG32_SOC15(GC, 0, regRLC_CNTL, tmp);
1820 }
1821
1822 static void gfx_v11_0_rlc_reset(struct amdgpu_device *adev)
1823 {
1824         WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 1);
1825         udelay(50);
1826         WREG32_FIELD15_PREREG(GC, 0, GRBM_SOFT_RESET, SOFT_RESET_RLC, 0);
1827         udelay(50);
1828 }
1829
1830 static void gfx_v11_0_rlc_smu_handshake_cntl(struct amdgpu_device *adev,
1831                                              bool enable)
1832 {
1833         uint32_t rlc_pg_cntl;
1834
1835         rlc_pg_cntl = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);
1836
1837         if (!enable) {
1838                 /* RLC_PG_CNTL[23] = 0 (default)
1839                  * RLC will wait for handshake acks with SMU
1840                  * GFXOFF will be enabled
1841                  * RLC_PG_CNTL[23] = 1
1842                  * RLC will not issue any message to SMU
1843                  * hence no handshake between SMU & RLC
1844                  * GFXOFF will be disabled
1845                  */
1846                 rlc_pg_cntl |= RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK;
1847         } else
1848                 rlc_pg_cntl &= ~RLC_PG_CNTL__SMU_HANDSHAKE_DISABLE_MASK;
1849         WREG32_SOC15(GC, 0, regRLC_PG_CNTL, rlc_pg_cntl);
1850 }
1851
1852 static void gfx_v11_0_rlc_start(struct amdgpu_device *adev)
1853 {
1854         /* TODO: enable rlc & smu handshake until smu
1855          * and gfxoff feature works as expected */
1856         if (!(amdgpu_pp_feature_mask & PP_GFXOFF_MASK))
1857                 gfx_v11_0_rlc_smu_handshake_cntl(adev, false);
1858
1859         WREG32_FIELD15_PREREG(GC, 0, RLC_CNTL, RLC_ENABLE_F32, 1);
1860         udelay(50);
1861 }
1862
1863 static void gfx_v11_0_rlc_enable_srm(struct amdgpu_device *adev)
1864 {
1865         uint32_t tmp;
1866
1867         /* enable Save Restore Machine */
1868         tmp = RREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL));
1869         tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
1870         tmp |= RLC_SRM_CNTL__SRM_ENABLE_MASK;
1871         WREG32(SOC15_REG_OFFSET(GC, 0, regRLC_SRM_CNTL), tmp);
1872 }
1873
1874 static void gfx_v11_0_load_rlcg_microcode(struct amdgpu_device *adev)
1875 {
1876         const struct rlc_firmware_header_v2_0 *hdr;
1877         const __le32 *fw_data;
1878         unsigned i, fw_size;
1879
1880         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1881         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1882                            le32_to_cpu(hdr->header.ucode_array_offset_bytes));
1883         fw_size = le32_to_cpu(hdr->header.ucode_size_bytes) / 4;
1884
1885         WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR,
1886                      RLCG_UCODE_LOADING_START_ADDRESS);
1887
1888         for (i = 0; i < fw_size; i++)
1889                 WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_DATA,
1890                              le32_to_cpup(fw_data++));
1891
1892         WREG32_SOC15(GC, 0, regRLC_GPM_UCODE_ADDR, adev->gfx.rlc_fw_version);
1893 }
1894
1895 static void gfx_v11_0_load_rlc_iram_dram_microcode(struct amdgpu_device *adev)
1896 {
1897         const struct rlc_firmware_header_v2_2 *hdr;
1898         const __le32 *fw_data;
1899         unsigned i, fw_size;
1900         u32 tmp;
1901
1902         hdr = (const struct rlc_firmware_header_v2_2 *)adev->gfx.rlc_fw->data;
1903
1904         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1905                         le32_to_cpu(hdr->rlc_iram_ucode_offset_bytes));
1906         fw_size = le32_to_cpu(hdr->rlc_iram_ucode_size_bytes) / 4;
1907
1908         WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, 0);
1909
1910         for (i = 0; i < fw_size; i++) {
1911                 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
1912                         msleep(1);
1913                 WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_DATA,
1914                                 le32_to_cpup(fw_data++));
1915         }
1916
1917         WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version);
1918
1919         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1920                         le32_to_cpu(hdr->rlc_dram_ucode_offset_bytes));
1921         fw_size = le32_to_cpu(hdr->rlc_dram_ucode_size_bytes) / 4;
1922
1923         WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_ADDR, 0);
1924         for (i = 0; i < fw_size; i++) {
1925                 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
1926                         msleep(1);
1927                 WREG32_SOC15(GC, 0, regRLC_LX6_DRAM_DATA,
1928                                 le32_to_cpup(fw_data++));
1929         }
1930
1931         WREG32_SOC15(GC, 0, regRLC_LX6_IRAM_ADDR, adev->gfx.rlc_fw_version);
1932
1933         tmp = RREG32_SOC15(GC, 0, regRLC_LX6_CNTL);
1934         tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, PDEBUG_ENABLE, 1);
1935         tmp = REG_SET_FIELD(tmp, RLC_LX6_CNTL, BRESET, 0);
1936         WREG32_SOC15(GC, 0, regRLC_LX6_CNTL, tmp);
1937 }
1938
1939 static void gfx_v11_0_load_rlcp_rlcv_microcode(struct amdgpu_device *adev)
1940 {
1941         const struct rlc_firmware_header_v2_3 *hdr;
1942         const __le32 *fw_data;
1943         unsigned i, fw_size;
1944         u32 tmp;
1945
1946         hdr = (const struct rlc_firmware_header_v2_3 *)adev->gfx.rlc_fw->data;
1947
1948         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1949                         le32_to_cpu(hdr->rlcp_ucode_offset_bytes));
1950         fw_size = le32_to_cpu(hdr->rlcp_ucode_size_bytes) / 4;
1951
1952         WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, 0);
1953
1954         for (i = 0; i < fw_size; i++) {
1955                 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
1956                         msleep(1);
1957                 WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_DATA,
1958                                 le32_to_cpup(fw_data++));
1959         }
1960
1961         WREG32_SOC15(GC, 0, regRLC_PACE_UCODE_ADDR, adev->gfx.rlc_fw_version);
1962
1963         tmp = RREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE);
1964         tmp = REG_SET_FIELD(tmp, RLC_GPM_THREAD_ENABLE, THREAD1_ENABLE, 1);
1965         WREG32_SOC15(GC, 0, regRLC_GPM_THREAD_ENABLE, tmp);
1966
1967         fw_data = (const __le32 *)(adev->gfx.rlc_fw->data +
1968                         le32_to_cpu(hdr->rlcv_ucode_offset_bytes));
1969         fw_size = le32_to_cpu(hdr->rlcv_ucode_size_bytes) / 4;
1970
1971         WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, 0);
1972
1973         for (i = 0; i < fw_size; i++) {
1974                 if ((amdgpu_emu_mode == 1) && (i % 100 == 99))
1975                         msleep(1);
1976                 WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_DATA,
1977                                 le32_to_cpup(fw_data++));
1978         }
1979
1980         WREG32_SOC15(GC, 0, regRLC_GPU_IOV_UCODE_ADDR, adev->gfx.rlc_fw_version);
1981
1982         tmp = RREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL);
1983         tmp = REG_SET_FIELD(tmp, RLC_GPU_IOV_F32_CNTL, ENABLE, 1);
1984         WREG32_SOC15(GC, 0, regRLC_GPU_IOV_F32_CNTL, tmp);
1985 }
1986
1987 static int gfx_v11_0_rlc_load_microcode(struct amdgpu_device *adev)
1988 {
1989         const struct rlc_firmware_header_v2_0 *hdr;
1990         uint16_t version_major;
1991         uint16_t version_minor;
1992
1993         if (!adev->gfx.rlc_fw)
1994                 return -EINVAL;
1995
1996         hdr = (const struct rlc_firmware_header_v2_0 *)adev->gfx.rlc_fw->data;
1997         amdgpu_ucode_print_rlc_hdr(&hdr->header);
1998
1999         version_major = le16_to_cpu(hdr->header.header_version_major);
2000         version_minor = le16_to_cpu(hdr->header.header_version_minor);
2001
2002         if (version_major == 2) {
2003                 gfx_v11_0_load_rlcg_microcode(adev);
2004                 if (amdgpu_dpm == 1) {
2005                         if (version_minor >= 2)
2006                                 gfx_v11_0_load_rlc_iram_dram_microcode(adev);
2007                         if (version_minor == 3)
2008                                 gfx_v11_0_load_rlcp_rlcv_microcode(adev);
2009                 }
2010
2011                 return 0;
2012         }
2013
2014         return -EINVAL;
2015 }
2016
2017 static int gfx_v11_0_rlc_resume(struct amdgpu_device *adev)
2018 {
2019         int r;
2020
2021         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
2022                 gfx_v11_0_init_csb(adev);
2023
2024                 if (!amdgpu_sriov_vf(adev)) /* enable RLC SRM */
2025                         gfx_v11_0_rlc_enable_srm(adev);
2026         } else {
2027                 if (amdgpu_sriov_vf(adev)) {
2028                         gfx_v11_0_init_csb(adev);
2029                         return 0;
2030                 }
2031
2032                 adev->gfx.rlc.funcs->stop(adev);
2033
2034                 /* disable CG */
2035                 WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, 0);
2036
2037                 /* disable PG */
2038                 WREG32_SOC15(GC, 0, regRLC_PG_CNTL, 0);
2039
2040                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
2041                         /* legacy rlc firmware loading */
2042                         r = gfx_v11_0_rlc_load_microcode(adev);
2043                         if (r)
2044                                 return r;
2045                 }
2046
2047                 gfx_v11_0_init_csb(adev);
2048
2049                 adev->gfx.rlc.funcs->start(adev);
2050         }
2051         return 0;
2052 }
2053
2054 static int gfx_v11_0_config_me_cache(struct amdgpu_device *adev, uint64_t addr)
2055 {
2056         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2057         uint32_t tmp;
2058         int i;
2059
2060         /* Trigger an invalidation of the L1 instruction caches */
2061         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2062         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2063         WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);
2064
2065         /* Wait for invalidation complete */
2066         for (i = 0; i < usec_timeout; i++) {
2067                 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2068                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2069                                         INVALIDATE_CACHE_COMPLETE))
2070                         break;
2071                 udelay(1);
2072         }
2073
2074         if (i >= usec_timeout) {
2075                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2076                 return -EINVAL;
2077         }
2078
2079         if (amdgpu_emu_mode == 1)
2080                 adev->hdp.funcs->flush_hdp(adev, NULL);
2081
2082         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
2083         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
2084         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
2085         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
2086         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2087         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);
2088
2089         /* Program me ucode address into intruction cache address register */
2090         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
2091                         lower_32_bits(addr) & 0xFFFFF000);
2092         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,
2093                         upper_32_bits(addr));
2094
2095         return 0;
2096 }
2097
2098 static int gfx_v11_0_config_pfp_cache(struct amdgpu_device *adev, uint64_t addr)
2099 {
2100         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2101         uint32_t tmp;
2102         int i;
2103
2104         /* Trigger an invalidation of the L1 instruction caches */
2105         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2106         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2107         WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);
2108
2109         /* Wait for invalidation complete */
2110         for (i = 0; i < usec_timeout; i++) {
2111                 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2112                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2113                                         INVALIDATE_CACHE_COMPLETE))
2114                         break;
2115                 udelay(1);
2116         }
2117
2118         if (i >= usec_timeout) {
2119                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2120                 return -EINVAL;
2121         }
2122
2123         if (amdgpu_emu_mode == 1)
2124                 adev->hdp.funcs->flush_hdp(adev, NULL);
2125
2126         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
2127         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2128         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2129         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2130         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2131         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);
2132
2133         /* Program pfp ucode address into intruction cache address register */
2134         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
2135                         lower_32_bits(addr) & 0xFFFFF000);
2136         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,
2137                         upper_32_bits(addr));
2138
2139         return 0;
2140 }
2141
2142 static int gfx_v11_0_config_mec_cache(struct amdgpu_device *adev, uint64_t addr)
2143 {
2144         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2145         uint32_t tmp;
2146         int i;
2147
2148         /* Trigger an invalidation of the L1 instruction caches */
2149         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2150         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2151
2152         WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);
2153
2154         /* Wait for invalidation complete */
2155         for (i = 0; i < usec_timeout; i++) {
2156                 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2157                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2158                                         INVALIDATE_CACHE_COMPLETE))
2159                         break;
2160                 udelay(1);
2161         }
2162
2163         if (i >= usec_timeout) {
2164                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2165                 return -EINVAL;
2166         }
2167
2168         if (amdgpu_emu_mode == 1)
2169                 adev->hdp.funcs->flush_hdp(adev, NULL);
2170
2171         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
2172         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2173         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
2174         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, ADDRESS_CLAMP, 1);
2175         WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);
2176
2177         /* Program mec1 ucode address into intruction cache address register */
2178         WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO,
2179                         lower_32_bits(addr) & 0xFFFFF000);
2180         WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,
2181                         upper_32_bits(addr));
2182
2183         return 0;
2184 }
2185
2186 static int gfx_v11_0_config_pfp_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2)
2187 {
2188         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2189         uint32_t tmp;
2190         unsigned i, pipe_id;
2191         const struct gfx_firmware_header_v2_0 *pfp_hdr;
2192
2193         pfp_hdr = (const struct gfx_firmware_header_v2_0 *)
2194                 adev->gfx.pfp_fw->data;
2195
2196         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
2197                 lower_32_bits(addr));
2198         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,
2199                 upper_32_bits(addr));
2200
2201         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
2202         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2203         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2204         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2205         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);
2206
2207         /*
2208          * Programming any of the CP_PFP_IC_BASE registers
2209          * forces invalidation of the ME L1 I$. Wait for the
2210          * invalidation complete
2211          */
2212         for (i = 0; i < usec_timeout; i++) {
2213                 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2214                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2215                         INVALIDATE_CACHE_COMPLETE))
2216                         break;
2217                 udelay(1);
2218         }
2219
2220         if (i >= usec_timeout) {
2221                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2222                 return -EINVAL;
2223         }
2224
2225         /* Prime the L1 instruction caches */
2226         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2227         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1);
2228         WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);
2229         /* Waiting for cache primed*/
2230         for (i = 0; i < usec_timeout; i++) {
2231                 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2232                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2233                         ICACHE_PRIMED))
2234                         break;
2235                 udelay(1);
2236         }
2237
2238         if (i >= usec_timeout) {
2239                 dev_err(adev->dev, "failed to prime instruction cache\n");
2240                 return -EINVAL;
2241         }
2242
2243         mutex_lock(&adev->srbm_mutex);
2244         for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2245                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2246                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
2247                         (pfp_hdr->ucode_start_addr_hi << 30) |
2248                         (pfp_hdr->ucode_start_addr_lo >> 2));
2249                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
2250                         pfp_hdr->ucode_start_addr_hi >> 2);
2251
2252                 /*
2253                  * Program CP_ME_CNTL to reset given PIPE to take
2254                  * effect of CP_PFP_PRGRM_CNTR_START.
2255                  */
2256                 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2257                 if (pipe_id == 0)
2258                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2259                                         PFP_PIPE0_RESET, 1);
2260                 else
2261                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2262                                         PFP_PIPE1_RESET, 1);
2263                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2264
2265                 /* Clear pfp pipe0 reset bit. */
2266                 if (pipe_id == 0)
2267                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2268                                         PFP_PIPE0_RESET, 0);
2269                 else
2270                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2271                                         PFP_PIPE1_RESET, 0);
2272                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2273
2274                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO,
2275                         lower_32_bits(addr2));
2276                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI,
2277                         upper_32_bits(addr2));
2278         }
2279         soc21_grbm_select(adev, 0, 0, 0, 0);
2280         mutex_unlock(&adev->srbm_mutex);
2281
2282         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2283         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2284         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
2285         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2286
2287         /* Invalidate the data caches */
2288         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2289         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2290         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2291
2292         for (i = 0; i < usec_timeout; i++) {
2293                 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2294                 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
2295                         INVALIDATE_DCACHE_COMPLETE))
2296                         break;
2297                 udelay(1);
2298         }
2299
2300         if (i >= usec_timeout) {
2301                 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
2302                 return -EINVAL;
2303         }
2304
2305         return 0;
2306 }
2307
2308 static int gfx_v11_0_config_me_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2)
2309 {
2310         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2311         uint32_t tmp;
2312         unsigned i, pipe_id;
2313         const struct gfx_firmware_header_v2_0 *me_hdr;
2314
2315         me_hdr = (const struct gfx_firmware_header_v2_0 *)
2316                 adev->gfx.me_fw->data;
2317
2318         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
2319                 lower_32_bits(addr));
2320         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,
2321                 upper_32_bits(addr));
2322
2323         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
2324         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
2325         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
2326         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
2327         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);
2328
2329         /*
2330          * Programming any of the CP_ME_IC_BASE registers
2331          * forces invalidation of the ME L1 I$. Wait for the
2332          * invalidation complete
2333          */
2334         for (i = 0; i < usec_timeout; i++) {
2335                 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2336                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2337                         INVALIDATE_CACHE_COMPLETE))
2338                         break;
2339                 udelay(1);
2340         }
2341
2342         if (i >= usec_timeout) {
2343                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2344                 return -EINVAL;
2345         }
2346
2347         /* Prime the instruction caches */
2348         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2349         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1);
2350         WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);
2351
2352         /* Waiting for instruction cache primed*/
2353         for (i = 0; i < usec_timeout; i++) {
2354                 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
2355                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
2356                         ICACHE_PRIMED))
2357                         break;
2358                 udelay(1);
2359         }
2360
2361         if (i >= usec_timeout) {
2362                 dev_err(adev->dev, "failed to prime instruction cache\n");
2363                 return -EINVAL;
2364         }
2365
2366         mutex_lock(&adev->srbm_mutex);
2367         for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2368                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2369                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
2370                         (me_hdr->ucode_start_addr_hi << 30) |
2371                         (me_hdr->ucode_start_addr_lo >> 2) );
2372                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
2373                         me_hdr->ucode_start_addr_hi>>2);
2374
2375                 /*
2376                  * Program CP_ME_CNTL to reset given PIPE to take
2377                  * effect of CP_PFP_PRGRM_CNTR_START.
2378                  */
2379                 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2380                 if (pipe_id == 0)
2381                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2382                                         ME_PIPE0_RESET, 1);
2383                 else
2384                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2385                                         ME_PIPE1_RESET, 1);
2386                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2387
2388                 /* Clear pfp pipe0 reset bit. */
2389                 if (pipe_id == 0)
2390                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2391                                         ME_PIPE0_RESET, 0);
2392                 else
2393                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2394                                         ME_PIPE1_RESET, 0);
2395                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2396
2397                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO,
2398                         lower_32_bits(addr2));
2399                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI,
2400                         upper_32_bits(addr2));
2401         }
2402         soc21_grbm_select(adev, 0, 0, 0, 0);
2403         mutex_unlock(&adev->srbm_mutex);
2404
2405         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2406         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2407         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
2408         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2409
2410         /* Invalidate the data caches */
2411         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2412         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2413         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2414
2415         for (i = 0; i < usec_timeout; i++) {
2416                 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2417                 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
2418                         INVALIDATE_DCACHE_COMPLETE))
2419                         break;
2420                 udelay(1);
2421         }
2422
2423         if (i >= usec_timeout) {
2424                 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
2425                 return -EINVAL;
2426         }
2427
2428         return 0;
2429 }
2430
2431 static int gfx_v11_0_config_mec_cache_rs64(struct amdgpu_device *adev, uint64_t addr, uint64_t addr2)
2432 {
2433         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2434         uint32_t tmp;
2435         unsigned i;
2436         const struct gfx_firmware_header_v2_0 *mec_hdr;
2437
2438         mec_hdr = (const struct gfx_firmware_header_v2_0 *)
2439                 adev->gfx.mec_fw->data;
2440
2441         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
2442         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
2443         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
2444         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
2445         WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);
2446
2447         tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);
2448         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);
2449         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);
2450         WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp);
2451
2452         mutex_lock(&adev->srbm_mutex);
2453         for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
2454                 soc21_grbm_select(adev, 1, i, 0, 0);
2455
2456                 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, addr2);
2457                 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI,
2458                      upper_32_bits(addr2));
2459
2460                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
2461                                         mec_hdr->ucode_start_addr_lo >> 2 |
2462                                         mec_hdr->ucode_start_addr_hi << 30);
2463                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
2464                                         mec_hdr->ucode_start_addr_hi >> 2);
2465
2466                 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, addr);
2467                 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,
2468                      upper_32_bits(addr));
2469         }
2470         mutex_unlock(&adev->srbm_mutex);
2471         soc21_grbm_select(adev, 0, 0, 0, 0);
2472
2473         /* Trigger an invalidation of the L1 instruction caches */
2474         tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
2475         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2476         WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp);
2477
2478         /* Wait for invalidation complete */
2479         for (i = 0; i < usec_timeout; i++) {
2480                 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
2481                 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL,
2482                                        INVALIDATE_DCACHE_COMPLETE))
2483                         break;
2484                 udelay(1);
2485         }
2486
2487         if (i >= usec_timeout) {
2488                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2489                 return -EINVAL;
2490         }
2491
2492         /* Trigger an invalidation of the L1 instruction caches */
2493         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2494         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
2495         WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);
2496
2497         /* Wait for invalidation complete */
2498         for (i = 0; i < usec_timeout; i++) {
2499                 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
2500                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
2501                                        INVALIDATE_CACHE_COMPLETE))
2502                         break;
2503                 udelay(1);
2504         }
2505
2506         if (i >= usec_timeout) {
2507                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2508                 return -EINVAL;
2509         }
2510
2511         return 0;
2512 }
2513
2514 static void gfx_v11_0_config_gfx_rs64(struct amdgpu_device *adev)
2515 {
2516         const struct gfx_firmware_header_v2_0 *pfp_hdr;
2517         const struct gfx_firmware_header_v2_0 *me_hdr;
2518         const struct gfx_firmware_header_v2_0 *mec_hdr;
2519         uint32_t pipe_id, tmp;
2520
2521         mec_hdr = (const struct gfx_firmware_header_v2_0 *)
2522                 adev->gfx.mec_fw->data;
2523         me_hdr = (const struct gfx_firmware_header_v2_0 *)
2524                 adev->gfx.me_fw->data;
2525         pfp_hdr = (const struct gfx_firmware_header_v2_0 *)
2526                 adev->gfx.pfp_fw->data;
2527
2528         /* config pfp program start addr */
2529         for (pipe_id = 0; pipe_id < 2; pipe_id++) {
2530                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2531                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
2532                         (pfp_hdr->ucode_start_addr_hi << 30) |
2533                         (pfp_hdr->ucode_start_addr_lo >> 2));
2534                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
2535                         pfp_hdr->ucode_start_addr_hi >> 2);
2536         }
2537         soc21_grbm_select(adev, 0, 0, 0, 0);
2538
2539         /* reset pfp pipe */
2540         tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2541         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 1);
2542         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 1);
2543         WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2544
2545         /* clear pfp pipe reset */
2546         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE0_RESET, 0);
2547         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_PIPE1_RESET, 0);
2548         WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2549
2550         /* config me program start addr */
2551         for (pipe_id = 0; pipe_id < 2; pipe_id++) {
2552                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2553                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
2554                         (me_hdr->ucode_start_addr_hi << 30) |
2555                         (me_hdr->ucode_start_addr_lo >> 2) );
2556                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
2557                         me_hdr->ucode_start_addr_hi>>2);
2558         }
2559         soc21_grbm_select(adev, 0, 0, 0, 0);
2560
2561         /* reset me pipe */
2562         tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2563         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 1);
2564         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 1);
2565         WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2566
2567         /* clear me pipe reset */
2568         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE0_RESET, 0);
2569         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_PIPE1_RESET, 0);
2570         WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2571
2572         /* config mec program start addr */
2573         for (pipe_id = 0; pipe_id < 4; pipe_id++) {
2574                 soc21_grbm_select(adev, 1, pipe_id, 0, 0);
2575                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
2576                                         mec_hdr->ucode_start_addr_lo >> 2 |
2577                                         mec_hdr->ucode_start_addr_hi << 30);
2578                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
2579                                         mec_hdr->ucode_start_addr_hi >> 2);
2580         }
2581         soc21_grbm_select(adev, 0, 0, 0, 0);
2582
2583         /* reset mec pipe */
2584         tmp = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
2585         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 1);
2586         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 1);
2587         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 1);
2588         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 1);
2589         WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
2590
2591         /* clear mec pipe reset */
2592         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET, 0);
2593         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET, 0);
2594         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET, 0);
2595         tmp = REG_SET_FIELD(tmp, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET, 0);
2596         WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, tmp);
2597 }
2598
2599 static int gfx_v11_0_wait_for_rlc_autoload_complete(struct amdgpu_device *adev)
2600 {
2601         uint32_t cp_status;
2602         uint32_t bootload_status;
2603         int i, r;
2604         uint64_t addr, addr2;
2605
2606         for (i = 0; i < adev->usec_timeout; i++) {
2607                 cp_status = RREG32_SOC15(GC, 0, regCP_STAT);
2608
2609                 if (amdgpu_ip_version(adev, GC_HWIP, 0) ==
2610                             IP_VERSION(11, 0, 1) ||
2611                     amdgpu_ip_version(adev, GC_HWIP, 0) ==
2612                             IP_VERSION(11, 0, 4) ||
2613                     amdgpu_ip_version(adev, GC_HWIP, 0) == IP_VERSION(11, 5, 0))
2614                         bootload_status = RREG32_SOC15(GC, 0,
2615                                         regRLC_RLCS_BOOTLOAD_STATUS_gc_11_0_1);
2616                 else
2617                         bootload_status = RREG32_SOC15(GC, 0, regRLC_RLCS_BOOTLOAD_STATUS);
2618
2619                 if ((cp_status == 0) &&
2620                     (REG_GET_FIELD(bootload_status,
2621                         RLC_RLCS_BOOTLOAD_STATUS, BOOTLOAD_COMPLETE) == 1)) {
2622                         break;
2623                 }
2624                 udelay(1);
2625         }
2626
2627         if (i >= adev->usec_timeout) {
2628                 dev_err(adev->dev, "rlc autoload: gc ucode autoload timeout\n");
2629                 return -ETIMEDOUT;
2630         }
2631
2632         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
2633                 if (adev->gfx.rs64_enable) {
2634                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2635                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME].offset;
2636                         addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr +
2637                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_ME_P0_STACK].offset;
2638                         r = gfx_v11_0_config_me_cache_rs64(adev, addr, addr2);
2639                         if (r)
2640                                 return r;
2641                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2642                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP].offset;
2643                         addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr +
2644                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_PFP_P0_STACK].offset;
2645                         r = gfx_v11_0_config_pfp_cache_rs64(adev, addr, addr2);
2646                         if (r)
2647                                 return r;
2648                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2649                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC].offset;
2650                         addr2 = adev->gfx.rlc.rlc_autoload_gpu_addr +
2651                                 rlc_autoload_info[SOC21_FIRMWARE_ID_RS64_MEC_P0_STACK].offset;
2652                         r = gfx_v11_0_config_mec_cache_rs64(adev, addr, addr2);
2653                         if (r)
2654                                 return r;
2655                 } else {
2656                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2657                                 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_ME].offset;
2658                         r = gfx_v11_0_config_me_cache(adev, addr);
2659                         if (r)
2660                                 return r;
2661                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2662                                 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_PFP].offset;
2663                         r = gfx_v11_0_config_pfp_cache(adev, addr);
2664                         if (r)
2665                                 return r;
2666                         addr = adev->gfx.rlc.rlc_autoload_gpu_addr +
2667                                 rlc_autoload_info[SOC21_FIRMWARE_ID_CP_MEC].offset;
2668                         r = gfx_v11_0_config_mec_cache(adev, addr);
2669                         if (r)
2670                                 return r;
2671                 }
2672         }
2673
2674         return 0;
2675 }
2676
2677 static int gfx_v11_0_cp_gfx_enable(struct amdgpu_device *adev, bool enable)
2678 {
2679         int i;
2680         u32 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2681
2682         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, enable ? 0 : 1);
2683         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, enable ? 0 : 1);
2684         WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2685
2686         for (i = 0; i < adev->usec_timeout; i++) {
2687                 if (RREG32_SOC15(GC, 0, regCP_STAT) == 0)
2688                         break;
2689                 udelay(1);
2690         }
2691
2692         if (i >= adev->usec_timeout)
2693                 DRM_ERROR("failed to %s cp gfx\n", enable ? "unhalt" : "halt");
2694
2695         return 0;
2696 }
2697
2698 static int gfx_v11_0_cp_gfx_load_pfp_microcode(struct amdgpu_device *adev)
2699 {
2700         int r;
2701         const struct gfx_firmware_header_v1_0 *pfp_hdr;
2702         const __le32 *fw_data;
2703         unsigned i, fw_size;
2704
2705         pfp_hdr = (const struct gfx_firmware_header_v1_0 *)
2706                 adev->gfx.pfp_fw->data;
2707
2708         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2709
2710         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2711                 le32_to_cpu(pfp_hdr->header.ucode_array_offset_bytes));
2712         fw_size = le32_to_cpu(pfp_hdr->header.ucode_size_bytes);
2713
2714         r = amdgpu_bo_create_reserved(adev, pfp_hdr->header.ucode_size_bytes,
2715                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2716                                       &adev->gfx.pfp.pfp_fw_obj,
2717                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
2718                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
2719         if (r) {
2720                 dev_err(adev->dev, "(%d) failed to create pfp fw bo\n", r);
2721                 gfx_v11_0_pfp_fini(adev);
2722                 return r;
2723         }
2724
2725         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_data, fw_size);
2726
2727         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
2728         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
2729
2730         gfx_v11_0_config_pfp_cache(adev, adev->gfx.pfp.pfp_fw_gpu_addr);
2731
2732         WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, 0);
2733
2734         for (i = 0; i < pfp_hdr->jt_size; i++)
2735                 WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_DATA,
2736                              le32_to_cpup(fw_data + pfp_hdr->jt_offset + i));
2737
2738         WREG32_SOC15(GC, 0, regCP_HYP_PFP_UCODE_ADDR, adev->gfx.pfp_fw_version);
2739
2740         return 0;
2741 }
2742
2743 static int gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(struct amdgpu_device *adev)
2744 {
2745         int r;
2746         const struct gfx_firmware_header_v2_0 *pfp_hdr;
2747         const __le32 *fw_ucode, *fw_data;
2748         unsigned i, pipe_id, fw_ucode_size, fw_data_size;
2749         uint32_t tmp;
2750         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2751
2752         pfp_hdr = (const struct gfx_firmware_header_v2_0 *)
2753                 adev->gfx.pfp_fw->data;
2754
2755         amdgpu_ucode_print_gfx_hdr(&pfp_hdr->header);
2756
2757         /* instruction */
2758         fw_ucode = (const __le32 *)(adev->gfx.pfp_fw->data +
2759                 le32_to_cpu(pfp_hdr->ucode_offset_bytes));
2760         fw_ucode_size = le32_to_cpu(pfp_hdr->ucode_size_bytes);
2761         /* data */
2762         fw_data = (const __le32 *)(adev->gfx.pfp_fw->data +
2763                 le32_to_cpu(pfp_hdr->data_offset_bytes));
2764         fw_data_size = le32_to_cpu(pfp_hdr->data_size_bytes);
2765
2766         /* 64kb align */
2767         r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
2768                                       64 * 1024,
2769                                       AMDGPU_GEM_DOMAIN_VRAM |
2770                                       AMDGPU_GEM_DOMAIN_GTT,
2771                                       &adev->gfx.pfp.pfp_fw_obj,
2772                                       &adev->gfx.pfp.pfp_fw_gpu_addr,
2773                                       (void **)&adev->gfx.pfp.pfp_fw_ptr);
2774         if (r) {
2775                 dev_err(adev->dev, "(%d) failed to create pfp ucode fw bo\n", r);
2776                 gfx_v11_0_pfp_fini(adev);
2777                 return r;
2778         }
2779
2780         r = amdgpu_bo_create_reserved(adev, fw_data_size,
2781                                       64 * 1024,
2782                                       AMDGPU_GEM_DOMAIN_VRAM |
2783                                       AMDGPU_GEM_DOMAIN_GTT,
2784                                       &adev->gfx.pfp.pfp_fw_data_obj,
2785                                       &adev->gfx.pfp.pfp_fw_data_gpu_addr,
2786                                       (void **)&adev->gfx.pfp.pfp_fw_data_ptr);
2787         if (r) {
2788                 dev_err(adev->dev, "(%d) failed to create pfp data fw bo\n", r);
2789                 gfx_v11_0_pfp_fini(adev);
2790                 return r;
2791         }
2792
2793         memcpy(adev->gfx.pfp.pfp_fw_ptr, fw_ucode, fw_ucode_size);
2794         memcpy(adev->gfx.pfp.pfp_fw_data_ptr, fw_data, fw_data_size);
2795
2796         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_obj);
2797         amdgpu_bo_kunmap(adev->gfx.pfp.pfp_fw_data_obj);
2798         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_obj);
2799         amdgpu_bo_unreserve(adev->gfx.pfp.pfp_fw_data_obj);
2800
2801         if (amdgpu_emu_mode == 1)
2802                 adev->hdp.funcs->flush_hdp(adev, NULL);
2803
2804         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_LO,
2805                 lower_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2806         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_HI,
2807                 upper_32_bits(adev->gfx.pfp.pfp_fw_gpu_addr));
2808
2809         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL);
2810         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, VMID, 0);
2811         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, CACHE_POLICY, 0);
2812         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_BASE_CNTL, EXE_DISABLE, 0);
2813         WREG32_SOC15(GC, 0, regCP_PFP_IC_BASE_CNTL, tmp);
2814
2815         /*
2816          * Programming any of the CP_PFP_IC_BASE registers
2817          * forces invalidation of the ME L1 I$. Wait for the
2818          * invalidation complete
2819          */
2820         for (i = 0; i < usec_timeout; i++) {
2821                 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2822                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2823                         INVALIDATE_CACHE_COMPLETE))
2824                         break;
2825                 udelay(1);
2826         }
2827
2828         if (i >= usec_timeout) {
2829                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
2830                 return -EINVAL;
2831         }
2832
2833         /* Prime the L1 instruction caches */
2834         tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2835         tmp = REG_SET_FIELD(tmp, CP_PFP_IC_OP_CNTL, PRIME_ICACHE, 1);
2836         WREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL, tmp);
2837         /* Waiting for cache primed*/
2838         for (i = 0; i < usec_timeout; i++) {
2839                 tmp = RREG32_SOC15(GC, 0, regCP_PFP_IC_OP_CNTL);
2840                 if (1 == REG_GET_FIELD(tmp, CP_PFP_IC_OP_CNTL,
2841                         ICACHE_PRIMED))
2842                         break;
2843                 udelay(1);
2844         }
2845
2846         if (i >= usec_timeout) {
2847                 dev_err(adev->dev, "failed to prime instruction cache\n");
2848                 return -EINVAL;
2849         }
2850
2851         mutex_lock(&adev->srbm_mutex);
2852         for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
2853                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
2854                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START,
2855                         (pfp_hdr->ucode_start_addr_hi << 30) |
2856                         (pfp_hdr->ucode_start_addr_lo >> 2) );
2857                 WREG32_SOC15(GC, 0, regCP_PFP_PRGRM_CNTR_START_HI,
2858                         pfp_hdr->ucode_start_addr_hi>>2);
2859
2860                 /*
2861                  * Program CP_ME_CNTL to reset given PIPE to take
2862                  * effect of CP_PFP_PRGRM_CNTR_START.
2863                  */
2864                 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
2865                 if (pipe_id == 0)
2866                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2867                                         PFP_PIPE0_RESET, 1);
2868                 else
2869                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2870                                         PFP_PIPE1_RESET, 1);
2871                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2872
2873                 /* Clear pfp pipe0 reset bit. */
2874                 if (pipe_id == 0)
2875                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2876                                         PFP_PIPE0_RESET, 0);
2877                 else
2878                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
2879                                         PFP_PIPE1_RESET, 0);
2880                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
2881
2882                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_LO,
2883                         lower_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr));
2884                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE0_HI,
2885                         upper_32_bits(adev->gfx.pfp.pfp_fw_data_gpu_addr));
2886         }
2887         soc21_grbm_select(adev, 0, 0, 0, 0);
2888         mutex_unlock(&adev->srbm_mutex);
2889
2890         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
2891         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
2892         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
2893         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
2894
2895         /* Invalidate the data caches */
2896         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2897         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
2898         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
2899
2900         for (i = 0; i < usec_timeout; i++) {
2901                 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
2902                 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
2903                         INVALIDATE_DCACHE_COMPLETE))
2904                         break;
2905                 udelay(1);
2906         }
2907
2908         if (i >= usec_timeout) {
2909                 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
2910                 return -EINVAL;
2911         }
2912
2913         return 0;
2914 }
2915
2916 static int gfx_v11_0_cp_gfx_load_me_microcode(struct amdgpu_device *adev)
2917 {
2918         int r;
2919         const struct gfx_firmware_header_v1_0 *me_hdr;
2920         const __le32 *fw_data;
2921         unsigned i, fw_size;
2922
2923         me_hdr = (const struct gfx_firmware_header_v1_0 *)
2924                 adev->gfx.me_fw->data;
2925
2926         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2927
2928         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2929                 le32_to_cpu(me_hdr->header.ucode_array_offset_bytes));
2930         fw_size = le32_to_cpu(me_hdr->header.ucode_size_bytes);
2931
2932         r = amdgpu_bo_create_reserved(adev, me_hdr->header.ucode_size_bytes,
2933                                       PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
2934                                       &adev->gfx.me.me_fw_obj,
2935                                       &adev->gfx.me.me_fw_gpu_addr,
2936                                       (void **)&adev->gfx.me.me_fw_ptr);
2937         if (r) {
2938                 dev_err(adev->dev, "(%d) failed to create me fw bo\n", r);
2939                 gfx_v11_0_me_fini(adev);
2940                 return r;
2941         }
2942
2943         memcpy(adev->gfx.me.me_fw_ptr, fw_data, fw_size);
2944
2945         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
2946         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
2947
2948         gfx_v11_0_config_me_cache(adev, adev->gfx.me.me_fw_gpu_addr);
2949
2950         WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, 0);
2951
2952         for (i = 0; i < me_hdr->jt_size; i++)
2953                 WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_DATA,
2954                              le32_to_cpup(fw_data + me_hdr->jt_offset + i));
2955
2956         WREG32_SOC15(GC, 0, regCP_HYP_ME_UCODE_ADDR, adev->gfx.me_fw_version);
2957
2958         return 0;
2959 }
2960
2961 static int gfx_v11_0_cp_gfx_load_me_microcode_rs64(struct amdgpu_device *adev)
2962 {
2963         int r;
2964         const struct gfx_firmware_header_v2_0 *me_hdr;
2965         const __le32 *fw_ucode, *fw_data;
2966         unsigned i, pipe_id, fw_ucode_size, fw_data_size;
2967         uint32_t tmp;
2968         uint32_t usec_timeout = 50000;  /* wait for 50ms */
2969
2970         me_hdr = (const struct gfx_firmware_header_v2_0 *)
2971                 adev->gfx.me_fw->data;
2972
2973         amdgpu_ucode_print_gfx_hdr(&me_hdr->header);
2974
2975         /* instruction */
2976         fw_ucode = (const __le32 *)(adev->gfx.me_fw->data +
2977                 le32_to_cpu(me_hdr->ucode_offset_bytes));
2978         fw_ucode_size = le32_to_cpu(me_hdr->ucode_size_bytes);
2979         /* data */
2980         fw_data = (const __le32 *)(adev->gfx.me_fw->data +
2981                 le32_to_cpu(me_hdr->data_offset_bytes));
2982         fw_data_size = le32_to_cpu(me_hdr->data_size_bytes);
2983
2984         /* 64kb align*/
2985         r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
2986                                       64 * 1024,
2987                                       AMDGPU_GEM_DOMAIN_VRAM |
2988                                       AMDGPU_GEM_DOMAIN_GTT,
2989                                       &adev->gfx.me.me_fw_obj,
2990                                       &adev->gfx.me.me_fw_gpu_addr,
2991                                       (void **)&adev->gfx.me.me_fw_ptr);
2992         if (r) {
2993                 dev_err(adev->dev, "(%d) failed to create me ucode bo\n", r);
2994                 gfx_v11_0_me_fini(adev);
2995                 return r;
2996         }
2997
2998         r = amdgpu_bo_create_reserved(adev, fw_data_size,
2999                                       64 * 1024,
3000                                       AMDGPU_GEM_DOMAIN_VRAM |
3001                                       AMDGPU_GEM_DOMAIN_GTT,
3002                                       &adev->gfx.me.me_fw_data_obj,
3003                                       &adev->gfx.me.me_fw_data_gpu_addr,
3004                                       (void **)&adev->gfx.me.me_fw_data_ptr);
3005         if (r) {
3006                 dev_err(adev->dev, "(%d) failed to create me data bo\n", r);
3007                 gfx_v11_0_pfp_fini(adev);
3008                 return r;
3009         }
3010
3011         memcpy(adev->gfx.me.me_fw_ptr, fw_ucode, fw_ucode_size);
3012         memcpy(adev->gfx.me.me_fw_data_ptr, fw_data, fw_data_size);
3013
3014         amdgpu_bo_kunmap(adev->gfx.me.me_fw_obj);
3015         amdgpu_bo_kunmap(adev->gfx.me.me_fw_data_obj);
3016         amdgpu_bo_unreserve(adev->gfx.me.me_fw_obj);
3017         amdgpu_bo_unreserve(adev->gfx.me.me_fw_data_obj);
3018
3019         if (amdgpu_emu_mode == 1)
3020                 adev->hdp.funcs->flush_hdp(adev, NULL);
3021
3022         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_LO,
3023                 lower_32_bits(adev->gfx.me.me_fw_gpu_addr));
3024         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_HI,
3025                 upper_32_bits(adev->gfx.me.me_fw_gpu_addr));
3026
3027         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL);
3028         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, VMID, 0);
3029         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, CACHE_POLICY, 0);
3030         tmp = REG_SET_FIELD(tmp, CP_ME_IC_BASE_CNTL, EXE_DISABLE, 0);
3031         WREG32_SOC15(GC, 0, regCP_ME_IC_BASE_CNTL, tmp);
3032
3033         /*
3034          * Programming any of the CP_ME_IC_BASE registers
3035          * forces invalidation of the ME L1 I$. Wait for the
3036          * invalidation complete
3037          */
3038         for (i = 0; i < usec_timeout; i++) {
3039                 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
3040                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
3041                         INVALIDATE_CACHE_COMPLETE))
3042                         break;
3043                 udelay(1);
3044         }
3045
3046         if (i >= usec_timeout) {
3047                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
3048                 return -EINVAL;
3049         }
3050
3051         /* Prime the instruction caches */
3052         tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
3053         tmp = REG_SET_FIELD(tmp, CP_ME_IC_OP_CNTL, PRIME_ICACHE, 1);
3054         WREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL, tmp);
3055
3056         /* Waiting for instruction cache primed*/
3057         for (i = 0; i < usec_timeout; i++) {
3058                 tmp = RREG32_SOC15(GC, 0, regCP_ME_IC_OP_CNTL);
3059                 if (1 == REG_GET_FIELD(tmp, CP_ME_IC_OP_CNTL,
3060                         ICACHE_PRIMED))
3061                         break;
3062                 udelay(1);
3063         }
3064
3065         if (i >= usec_timeout) {
3066                 dev_err(adev->dev, "failed to prime instruction cache\n");
3067                 return -EINVAL;
3068         }
3069
3070         mutex_lock(&adev->srbm_mutex);
3071         for (pipe_id = 0; pipe_id < adev->gfx.me.num_pipe_per_me; pipe_id++) {
3072                 soc21_grbm_select(adev, 0, pipe_id, 0, 0);
3073                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START,
3074                         (me_hdr->ucode_start_addr_hi << 30) |
3075                         (me_hdr->ucode_start_addr_lo >> 2) );
3076                 WREG32_SOC15(GC, 0, regCP_ME_PRGRM_CNTR_START_HI,
3077                         me_hdr->ucode_start_addr_hi>>2);
3078
3079                 /*
3080                  * Program CP_ME_CNTL to reset given PIPE to take
3081                  * effect of CP_PFP_PRGRM_CNTR_START.
3082                  */
3083                 tmp = RREG32_SOC15(GC, 0, regCP_ME_CNTL);
3084                 if (pipe_id == 0)
3085                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
3086                                         ME_PIPE0_RESET, 1);
3087                 else
3088                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
3089                                         ME_PIPE1_RESET, 1);
3090                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
3091
3092                 /* Clear pfp pipe0 reset bit. */
3093                 if (pipe_id == 0)
3094                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
3095                                         ME_PIPE0_RESET, 0);
3096                 else
3097                         tmp = REG_SET_FIELD(tmp, CP_ME_CNTL,
3098                                         ME_PIPE1_RESET, 0);
3099                 WREG32_SOC15(GC, 0, regCP_ME_CNTL, tmp);
3100
3101                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_LO,
3102                         lower_32_bits(adev->gfx.me.me_fw_data_gpu_addr));
3103                 WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE1_HI,
3104                         upper_32_bits(adev->gfx.me.me_fw_data_gpu_addr));
3105         }
3106         soc21_grbm_select(adev, 0, 0, 0, 0);
3107         mutex_unlock(&adev->srbm_mutex);
3108
3109         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL);
3110         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, VMID, 0);
3111         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_BASE_CNTL, CACHE_POLICY, 0);
3112         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_BASE_CNTL, tmp);
3113
3114         /* Invalidate the data caches */
3115         tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
3116         tmp = REG_SET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
3117         WREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL, tmp);
3118
3119         for (i = 0; i < usec_timeout; i++) {
3120                 tmp = RREG32_SOC15(GC, 0, regCP_GFX_RS64_DC_OP_CNTL);
3121                 if (1 == REG_GET_FIELD(tmp, CP_GFX_RS64_DC_OP_CNTL,
3122                         INVALIDATE_DCACHE_COMPLETE))
3123                         break;
3124                 udelay(1);
3125         }
3126
3127         if (i >= usec_timeout) {
3128                 dev_err(adev->dev, "failed to invalidate RS64 data cache\n");
3129                 return -EINVAL;
3130         }
3131
3132         return 0;
3133 }
3134
3135 static int gfx_v11_0_cp_gfx_load_microcode(struct amdgpu_device *adev)
3136 {
3137         int r;
3138
3139         if (!adev->gfx.me_fw || !adev->gfx.pfp_fw)
3140                 return -EINVAL;
3141
3142         gfx_v11_0_cp_gfx_enable(adev, false);
3143
3144         if (adev->gfx.rs64_enable)
3145                 r = gfx_v11_0_cp_gfx_load_pfp_microcode_rs64(adev);
3146         else
3147                 r = gfx_v11_0_cp_gfx_load_pfp_microcode(adev);
3148         if (r) {
3149                 dev_err(adev->dev, "(%d) failed to load pfp fw\n", r);
3150                 return r;
3151         }
3152
3153         if (adev->gfx.rs64_enable)
3154                 r = gfx_v11_0_cp_gfx_load_me_microcode_rs64(adev);
3155         else
3156                 r = gfx_v11_0_cp_gfx_load_me_microcode(adev);
3157         if (r) {
3158                 dev_err(adev->dev, "(%d) failed to load me fw\n", r);
3159                 return r;
3160         }
3161
3162         return 0;
3163 }
3164
3165 static int gfx_v11_0_cp_gfx_start(struct amdgpu_device *adev)
3166 {
3167         struct amdgpu_ring *ring;
3168         const struct cs_section_def *sect = NULL;
3169         const struct cs_extent_def *ext = NULL;
3170         int r, i;
3171         int ctx_reg_offset;
3172
3173         /* init the CP */
3174         WREG32_SOC15(GC, 0, regCP_MAX_CONTEXT,
3175                      adev->gfx.config.max_hw_contexts - 1);
3176         WREG32_SOC15(GC, 0, regCP_DEVICE_ID, 1);
3177
3178         if (!amdgpu_async_gfx_ring)
3179                 gfx_v11_0_cp_gfx_enable(adev, true);
3180
3181         ring = &adev->gfx.gfx_ring[0];
3182         r = amdgpu_ring_alloc(ring, gfx_v11_0_get_csb_size(adev));
3183         if (r) {
3184                 DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
3185                 return r;
3186         }
3187
3188         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3189         amdgpu_ring_write(ring, PACKET3_PREAMBLE_BEGIN_CLEAR_STATE);
3190
3191         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
3192         amdgpu_ring_write(ring, 0x80000000);
3193         amdgpu_ring_write(ring, 0x80000000);
3194
3195         for (sect = gfx11_cs_data; sect->section != NULL; ++sect) {
3196                 for (ext = sect->section; ext->extent != NULL; ++ext) {
3197                         if (sect->id == SECT_CONTEXT) {
3198                                 amdgpu_ring_write(ring,
3199                                                   PACKET3(PACKET3_SET_CONTEXT_REG,
3200                                                           ext->reg_count));
3201                                 amdgpu_ring_write(ring, ext->reg_index -
3202                                                   PACKET3_SET_CONTEXT_REG_START);
3203                                 for (i = 0; i < ext->reg_count; i++)
3204                                         amdgpu_ring_write(ring, ext->extent[i]);
3205                         }
3206                 }
3207         }
3208
3209         ctx_reg_offset =
3210                 SOC15_REG_OFFSET(GC, 0, regPA_SC_TILE_STEERING_OVERRIDE) - PACKET3_SET_CONTEXT_REG_START;
3211         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONTEXT_REG, 1));
3212         amdgpu_ring_write(ring, ctx_reg_offset);
3213         amdgpu_ring_write(ring, adev->gfx.config.pa_sc_tile_steering_override);
3214
3215         amdgpu_ring_write(ring, PACKET3(PACKET3_PREAMBLE_CNTL, 0));
3216         amdgpu_ring_write(ring, PACKET3_PREAMBLE_END_CLEAR_STATE);
3217
3218         amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
3219         amdgpu_ring_write(ring, 0);
3220
3221         amdgpu_ring_commit(ring);
3222
3223         /* submit cs packet to copy state 0 to next available state */
3224         if (adev->gfx.num_gfx_rings > 1) {
3225                 /* maximum supported gfx ring is 2 */
3226                 ring = &adev->gfx.gfx_ring[1];
3227                 r = amdgpu_ring_alloc(ring, 2);
3228                 if (r) {
3229                         DRM_ERROR("amdgpu: cp failed to lock ring (%d).\n", r);
3230                         return r;
3231                 }
3232
3233                 amdgpu_ring_write(ring, PACKET3(PACKET3_CLEAR_STATE, 0));
3234                 amdgpu_ring_write(ring, 0);
3235
3236                 amdgpu_ring_commit(ring);
3237         }
3238         return 0;
3239 }
3240
3241 static void gfx_v11_0_cp_gfx_switch_pipe(struct amdgpu_device *adev,
3242                                          CP_PIPE_ID pipe)
3243 {
3244         u32 tmp;
3245
3246         tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);
3247         tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, pipe);
3248
3249         WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);
3250 }
3251
3252 static void gfx_v11_0_cp_gfx_set_doorbell(struct amdgpu_device *adev,
3253                                           struct amdgpu_ring *ring)
3254 {
3255         u32 tmp;
3256
3257         tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);
3258         if (ring->use_doorbell) {
3259                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3260                                     DOORBELL_OFFSET, ring->doorbell_index);
3261                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3262                                     DOORBELL_EN, 1);
3263         } else {
3264                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3265                                     DOORBELL_EN, 0);
3266         }
3267         WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL, tmp);
3268
3269         tmp = REG_SET_FIELD(0, CP_RB_DOORBELL_RANGE_LOWER,
3270                             DOORBELL_RANGE_LOWER, ring->doorbell_index);
3271         WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER, tmp);
3272
3273         WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER,
3274                      CP_RB_DOORBELL_RANGE_UPPER__DOORBELL_RANGE_UPPER_MASK);
3275 }
3276
3277 static int gfx_v11_0_cp_gfx_resume(struct amdgpu_device *adev)
3278 {
3279         struct amdgpu_ring *ring;
3280         u32 tmp;
3281         u32 rb_bufsz;
3282         u64 rb_addr, rptr_addr, wptr_gpu_addr;
3283
3284         /* Set the write pointer delay */
3285         WREG32_SOC15(GC, 0, regCP_RB_WPTR_DELAY, 0);
3286
3287         /* set the RB to use vmid 0 */
3288         WREG32_SOC15(GC, 0, regCP_RB_VMID, 0);
3289
3290         /* Init gfx ring 0 for pipe 0 */
3291         mutex_lock(&adev->srbm_mutex);
3292         gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
3293
3294         /* Set ring buffer size */
3295         ring = &adev->gfx.gfx_ring[0];
3296         rb_bufsz = order_base_2(ring->ring_size / 8);
3297         tmp = REG_SET_FIELD(0, CP_RB0_CNTL, RB_BUFSZ, rb_bufsz);
3298         tmp = REG_SET_FIELD(tmp, CP_RB0_CNTL, RB_BLKSZ, rb_bufsz - 2);
3299         WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);
3300
3301         /* Initialize the ring buffer's write pointers */
3302         ring->wptr = 0;
3303         WREG32_SOC15(GC, 0, regCP_RB0_WPTR, lower_32_bits(ring->wptr));
3304         WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI, upper_32_bits(ring->wptr));
3305
3306         /* set the wb address wether it's enabled or not */
3307         rptr_addr = ring->rptr_gpu_addr;
3308         WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR, lower_32_bits(rptr_addr));
3309         WREG32_SOC15(GC, 0, regCP_RB0_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
3310                      CP_RB_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
3311
3312         wptr_gpu_addr = ring->wptr_gpu_addr;
3313         WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO,
3314                      lower_32_bits(wptr_gpu_addr));
3315         WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI,
3316                      upper_32_bits(wptr_gpu_addr));
3317
3318         mdelay(1);
3319         WREG32_SOC15(GC, 0, regCP_RB0_CNTL, tmp);
3320
3321         rb_addr = ring->gpu_addr >> 8;
3322         WREG32_SOC15(GC, 0, regCP_RB0_BASE, rb_addr);
3323         WREG32_SOC15(GC, 0, regCP_RB0_BASE_HI, upper_32_bits(rb_addr));
3324
3325         WREG32_SOC15(GC, 0, regCP_RB_ACTIVE, 1);
3326
3327         gfx_v11_0_cp_gfx_set_doorbell(adev, ring);
3328         mutex_unlock(&adev->srbm_mutex);
3329
3330         /* Init gfx ring 1 for pipe 1 */
3331         if (adev->gfx.num_gfx_rings > 1) {
3332                 mutex_lock(&adev->srbm_mutex);
3333                 gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID1);
3334                 /* maximum supported gfx ring is 2 */
3335                 ring = &adev->gfx.gfx_ring[1];
3336                 rb_bufsz = order_base_2(ring->ring_size / 8);
3337                 tmp = REG_SET_FIELD(0, CP_RB1_CNTL, RB_BUFSZ, rb_bufsz);
3338                 tmp = REG_SET_FIELD(tmp, CP_RB1_CNTL, RB_BLKSZ, rb_bufsz - 2);
3339                 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp);
3340                 /* Initialize the ring buffer's write pointers */
3341                 ring->wptr = 0;
3342                 WREG32_SOC15(GC, 0, regCP_RB1_WPTR, lower_32_bits(ring->wptr));
3343                 WREG32_SOC15(GC, 0, regCP_RB1_WPTR_HI, upper_32_bits(ring->wptr));
3344                 /* Set the wb address wether it's enabled or not */
3345                 rptr_addr = ring->rptr_gpu_addr;
3346                 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR, lower_32_bits(rptr_addr));
3347                 WREG32_SOC15(GC, 0, regCP_RB1_RPTR_ADDR_HI, upper_32_bits(rptr_addr) &
3348                              CP_RB1_RPTR_ADDR_HI__RB_RPTR_ADDR_HI_MASK);
3349                 wptr_gpu_addr = ring->wptr_gpu_addr;
3350                 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_LO,
3351                              lower_32_bits(wptr_gpu_addr));
3352                 WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_ADDR_HI,
3353                              upper_32_bits(wptr_gpu_addr));
3354
3355                 mdelay(1);
3356                 WREG32_SOC15(GC, 0, regCP_RB1_CNTL, tmp);
3357
3358                 rb_addr = ring->gpu_addr >> 8;
3359                 WREG32_SOC15(GC, 0, regCP_RB1_BASE, rb_addr);
3360                 WREG32_SOC15(GC, 0, regCP_RB1_BASE_HI, upper_32_bits(rb_addr));
3361                 WREG32_SOC15(GC, 0, regCP_RB1_ACTIVE, 1);
3362
3363                 gfx_v11_0_cp_gfx_set_doorbell(adev, ring);
3364                 mutex_unlock(&adev->srbm_mutex);
3365         }
3366         /* Switch to pipe 0 */
3367         mutex_lock(&adev->srbm_mutex);
3368         gfx_v11_0_cp_gfx_switch_pipe(adev, PIPE_ID0);
3369         mutex_unlock(&adev->srbm_mutex);
3370
3371         /* start the ring */
3372         gfx_v11_0_cp_gfx_start(adev);
3373
3374         return 0;
3375 }
3376
3377 static void gfx_v11_0_cp_compute_enable(struct amdgpu_device *adev, bool enable)
3378 {
3379         u32 data;
3380
3381         if (adev->gfx.rs64_enable) {
3382                 data = RREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL);
3383                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_INVALIDATE_ICACHE,
3384                                                          enable ? 0 : 1);
3385                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_RESET,
3386                                                          enable ? 0 : 1);
3387                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_RESET,
3388                                                          enable ? 0 : 1);
3389                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_RESET,
3390                                                          enable ? 0 : 1);
3391                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_RESET,
3392                                                          enable ? 0 : 1);
3393                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE0_ACTIVE,
3394                                                          enable ? 1 : 0);
3395                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE1_ACTIVE,
3396                                                          enable ? 1 : 0);
3397                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE2_ACTIVE,
3398                                                          enable ? 1 : 0);
3399                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_PIPE3_ACTIVE,
3400                                                          enable ? 1 : 0);
3401                 data = REG_SET_FIELD(data, CP_MEC_RS64_CNTL, MEC_HALT,
3402                                                          enable ? 0 : 1);
3403                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, data);
3404         } else {
3405                 data = RREG32_SOC15(GC, 0, regCP_MEC_CNTL);
3406
3407                 if (enable) {
3408                         data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 0);
3409                         if (!adev->enable_mes_kiq)
3410                                 data = REG_SET_FIELD(data, CP_MEC_CNTL,
3411                                                      MEC_ME2_HALT, 0);
3412                 } else {
3413                         data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME1_HALT, 1);
3414                         data = REG_SET_FIELD(data, CP_MEC_CNTL, MEC_ME2_HALT, 1);
3415                 }
3416                 WREG32_SOC15(GC, 0, regCP_MEC_CNTL, data);
3417         }
3418
3419         udelay(50);
3420 }
3421
3422 static int gfx_v11_0_cp_compute_load_microcode(struct amdgpu_device *adev)
3423 {
3424         const struct gfx_firmware_header_v1_0 *mec_hdr;
3425         const __le32 *fw_data;
3426         unsigned i, fw_size;
3427         u32 *fw = NULL;
3428         int r;
3429
3430         if (!adev->gfx.mec_fw)
3431                 return -EINVAL;
3432
3433         gfx_v11_0_cp_compute_enable(adev, false);
3434
3435         mec_hdr = (const struct gfx_firmware_header_v1_0 *)adev->gfx.mec_fw->data;
3436         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
3437
3438         fw_data = (const __le32 *)
3439                 (adev->gfx.mec_fw->data +
3440                  le32_to_cpu(mec_hdr->header.ucode_array_offset_bytes));
3441         fw_size = le32_to_cpu(mec_hdr->header.ucode_size_bytes);
3442
3443         r = amdgpu_bo_create_reserved(adev, mec_hdr->header.ucode_size_bytes,
3444                                           PAGE_SIZE, AMDGPU_GEM_DOMAIN_GTT,
3445                                           &adev->gfx.mec.mec_fw_obj,
3446                                           &adev->gfx.mec.mec_fw_gpu_addr,
3447                                           (void **)&fw);
3448         if (r) {
3449                 dev_err(adev->dev, "(%d) failed to create mec fw bo\n", r);
3450                 gfx_v11_0_mec_fini(adev);
3451                 return r;
3452         }
3453
3454         memcpy(fw, fw_data, fw_size);
3455
3456         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
3457         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
3458
3459         gfx_v11_0_config_mec_cache(adev, adev->gfx.mec.mec_fw_gpu_addr);
3460
3461         /* MEC1 */
3462         WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, 0);
3463
3464         for (i = 0; i < mec_hdr->jt_size; i++)
3465                 WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_DATA,
3466                              le32_to_cpup(fw_data + mec_hdr->jt_offset + i));
3467
3468         WREG32_SOC15(GC, 0, regCP_MEC_ME1_UCODE_ADDR, adev->gfx.mec_fw_version);
3469
3470         return 0;
3471 }
3472
3473 static int gfx_v11_0_cp_compute_load_microcode_rs64(struct amdgpu_device *adev)
3474 {
3475         const struct gfx_firmware_header_v2_0 *mec_hdr;
3476         const __le32 *fw_ucode, *fw_data;
3477         u32 tmp, fw_ucode_size, fw_data_size;
3478         u32 i, usec_timeout = 50000; /* Wait for 50 ms */
3479         u32 *fw_ucode_ptr, *fw_data_ptr;
3480         int r;
3481
3482         if (!adev->gfx.mec_fw)
3483                 return -EINVAL;
3484
3485         gfx_v11_0_cp_compute_enable(adev, false);
3486
3487         mec_hdr = (const struct gfx_firmware_header_v2_0 *)adev->gfx.mec_fw->data;
3488         amdgpu_ucode_print_gfx_hdr(&mec_hdr->header);
3489
3490         fw_ucode = (const __le32 *) (adev->gfx.mec_fw->data +
3491                                 le32_to_cpu(mec_hdr->ucode_offset_bytes));
3492         fw_ucode_size = le32_to_cpu(mec_hdr->ucode_size_bytes);
3493
3494         fw_data = (const __le32 *) (adev->gfx.mec_fw->data +
3495                                 le32_to_cpu(mec_hdr->data_offset_bytes));
3496         fw_data_size = le32_to_cpu(mec_hdr->data_size_bytes);
3497
3498         r = amdgpu_bo_create_reserved(adev, fw_ucode_size,
3499                                       64 * 1024,
3500                                       AMDGPU_GEM_DOMAIN_VRAM |
3501                                       AMDGPU_GEM_DOMAIN_GTT,
3502                                       &adev->gfx.mec.mec_fw_obj,
3503                                       &adev->gfx.mec.mec_fw_gpu_addr,
3504                                       (void **)&fw_ucode_ptr);
3505         if (r) {
3506                 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r);
3507                 gfx_v11_0_mec_fini(adev);
3508                 return r;
3509         }
3510
3511         r = amdgpu_bo_create_reserved(adev, fw_data_size,
3512                                       64 * 1024,
3513                                       AMDGPU_GEM_DOMAIN_VRAM |
3514                                       AMDGPU_GEM_DOMAIN_GTT,
3515                                       &adev->gfx.mec.mec_fw_data_obj,
3516                                       &adev->gfx.mec.mec_fw_data_gpu_addr,
3517                                       (void **)&fw_data_ptr);
3518         if (r) {
3519                 dev_err(adev->dev, "(%d) failed to create mec fw ucode bo\n", r);
3520                 gfx_v11_0_mec_fini(adev);
3521                 return r;
3522         }
3523
3524         memcpy(fw_ucode_ptr, fw_ucode, fw_ucode_size);
3525         memcpy(fw_data_ptr, fw_data, fw_data_size);
3526
3527         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_obj);
3528         amdgpu_bo_kunmap(adev->gfx.mec.mec_fw_data_obj);
3529         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_obj);
3530         amdgpu_bo_unreserve(adev->gfx.mec.mec_fw_data_obj);
3531
3532         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL);
3533         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, VMID, 0);
3534         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, EXE_DISABLE, 0);
3535         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_BASE_CNTL, CACHE_POLICY, 0);
3536         WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_CNTL, tmp);
3537
3538         tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL);
3539         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, VMID, 0);
3540         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_BASE_CNTL, CACHE_POLICY, 0);
3541         WREG32_SOC15(GC, 0, regCP_MEC_DC_BASE_CNTL, tmp);
3542
3543         mutex_lock(&adev->srbm_mutex);
3544         for (i = 0; i < adev->gfx.mec.num_pipe_per_mec; i++) {
3545                 soc21_grbm_select(adev, 1, i, 0, 0);
3546
3547                 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_LO, adev->gfx.mec.mec_fw_data_gpu_addr);
3548                 WREG32_SOC15(GC, 0, regCP_MEC_MDBASE_HI,
3549                      upper_32_bits(adev->gfx.mec.mec_fw_data_gpu_addr));
3550
3551                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START,
3552                                         mec_hdr->ucode_start_addr_lo >> 2 |
3553                                         mec_hdr->ucode_start_addr_hi << 30);
3554                 WREG32_SOC15(GC, 0, regCP_MEC_RS64_PRGRM_CNTR_START_HI,
3555                                         mec_hdr->ucode_start_addr_hi >> 2);
3556
3557                 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_LO, adev->gfx.mec.mec_fw_gpu_addr);
3558                 WREG32_SOC15(GC, 0, regCP_CPC_IC_BASE_HI,
3559                      upper_32_bits(adev->gfx.mec.mec_fw_gpu_addr));
3560         }
3561         mutex_unlock(&adev->srbm_mutex);
3562         soc21_grbm_select(adev, 0, 0, 0, 0);
3563
3564         /* Trigger an invalidation of the L1 instruction caches */
3565         tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
3566         tmp = REG_SET_FIELD(tmp, CP_MEC_DC_OP_CNTL, INVALIDATE_DCACHE, 1);
3567         WREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL, tmp);
3568
3569         /* Wait for invalidation complete */
3570         for (i = 0; i < usec_timeout; i++) {
3571                 tmp = RREG32_SOC15(GC, 0, regCP_MEC_DC_OP_CNTL);
3572                 if (1 == REG_GET_FIELD(tmp, CP_MEC_DC_OP_CNTL,
3573                                        INVALIDATE_DCACHE_COMPLETE))
3574                         break;
3575                 udelay(1);
3576         }
3577
3578         if (i >= usec_timeout) {
3579                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
3580                 return -EINVAL;
3581         }
3582
3583         /* Trigger an invalidation of the L1 instruction caches */
3584         tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
3585         tmp = REG_SET_FIELD(tmp, CP_CPC_IC_OP_CNTL, INVALIDATE_CACHE, 1);
3586         WREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL, tmp);
3587
3588         /* Wait for invalidation complete */
3589         for (i = 0; i < usec_timeout; i++) {
3590                 tmp = RREG32_SOC15(GC, 0, regCP_CPC_IC_OP_CNTL);
3591                 if (1 == REG_GET_FIELD(tmp, CP_CPC_IC_OP_CNTL,
3592                                        INVALIDATE_CACHE_COMPLETE))
3593                         break;
3594                 udelay(1);
3595         }
3596
3597         if (i >= usec_timeout) {
3598                 dev_err(adev->dev, "failed to invalidate instruction cache\n");
3599                 return -EINVAL;
3600         }
3601
3602         return 0;
3603 }
3604
3605 static void gfx_v11_0_kiq_setting(struct amdgpu_ring *ring)
3606 {
3607         uint32_t tmp;
3608         struct amdgpu_device *adev = ring->adev;
3609
3610         /* tell RLC which is KIQ queue */
3611         tmp = RREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS);
3612         tmp &= 0xffffff00;
3613         tmp |= (ring->me << 5) | (ring->pipe << 3) | (ring->queue);
3614         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
3615         tmp |= 0x80;
3616         WREG32_SOC15(GC, 0, regRLC_CP_SCHEDULERS, tmp);
3617 }
3618
3619 static void gfx_v11_0_cp_set_doorbell_range(struct amdgpu_device *adev)
3620 {
3621         /* set graphics engine doorbell range */
3622         WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_LOWER,
3623                      (adev->doorbell_index.gfx_ring0 * 2) << 2);
3624         WREG32_SOC15(GC, 0, regCP_RB_DOORBELL_RANGE_UPPER,
3625                      (adev->doorbell_index.gfx_userqueue_end * 2) << 2);
3626
3627         /* set compute engine doorbell range */
3628         WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,
3629                      (adev->doorbell_index.kiq * 2) << 2);
3630         WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,
3631                      (adev->doorbell_index.userqueue_end * 2) << 2);
3632 }
3633
3634 static int gfx_v11_0_gfx_mqd_init(struct amdgpu_device *adev, void *m,
3635                                   struct amdgpu_mqd_prop *prop)
3636 {
3637         struct v11_gfx_mqd *mqd = m;
3638         uint64_t hqd_gpu_addr, wb_gpu_addr;
3639         uint32_t tmp;
3640         uint32_t rb_bufsz;
3641
3642         /* set up gfx hqd wptr */
3643         mqd->cp_gfx_hqd_wptr = 0;
3644         mqd->cp_gfx_hqd_wptr_hi = 0;
3645
3646         /* set the pointer to the MQD */
3647         mqd->cp_mqd_base_addr = prop->mqd_gpu_addr & 0xfffffffc;
3648         mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
3649
3650         /* set up mqd control */
3651         tmp = RREG32_SOC15(GC, 0, regCP_GFX_MQD_CONTROL);
3652         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, VMID, 0);
3653         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, PRIV_STATE, 1);
3654         tmp = REG_SET_FIELD(tmp, CP_GFX_MQD_CONTROL, CACHE_POLICY, 0);
3655         mqd->cp_gfx_mqd_control = tmp;
3656
3657         /* set up gfx_hqd_vimd with 0x0 to indicate the ring buffer's vmid */
3658         tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_VMID);
3659         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_VMID, VMID, 0);
3660         mqd->cp_gfx_hqd_vmid = 0;
3661
3662         /* set up default queue priority level
3663          * 0x0 = low priority, 0x1 = high priority */
3664         tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUEUE_PRIORITY);
3665         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUEUE_PRIORITY, PRIORITY_LEVEL, 0);
3666         mqd->cp_gfx_hqd_queue_priority = tmp;
3667
3668         /* set up time quantum */
3669         tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_QUANTUM);
3670         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_QUANTUM, QUANTUM_EN, 1);
3671         mqd->cp_gfx_hqd_quantum = tmp;
3672
3673         /* set up gfx hqd base. this is similar as CP_RB_BASE */
3674         hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
3675         mqd->cp_gfx_hqd_base = hqd_gpu_addr;
3676         mqd->cp_gfx_hqd_base_hi = upper_32_bits(hqd_gpu_addr);
3677
3678         /* set up hqd_rptr_addr/_hi, similar as CP_RB_RPTR */
3679         wb_gpu_addr = prop->rptr_gpu_addr;
3680         mqd->cp_gfx_hqd_rptr_addr = wb_gpu_addr & 0xfffffffc;
3681         mqd->cp_gfx_hqd_rptr_addr_hi =
3682                 upper_32_bits(wb_gpu_addr) & 0xffff;
3683
3684         /* set up rb_wptr_poll addr */
3685         wb_gpu_addr = prop->wptr_gpu_addr;
3686         mqd->cp_rb_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3687         mqd->cp_rb_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3688
3689         /* set up the gfx_hqd_control, similar as CP_RB0_CNTL */
3690         rb_bufsz = order_base_2(prop->queue_size / 4) - 1;
3691         tmp = RREG32_SOC15(GC, 0, regCP_GFX_HQD_CNTL);
3692         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BUFSZ, rb_bufsz);
3693         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, RB_BLKSZ, rb_bufsz - 2);
3694 #ifdef __BIG_ENDIAN
3695         tmp = REG_SET_FIELD(tmp, CP_GFX_HQD_CNTL, BUF_SWAP, 1);
3696 #endif
3697         mqd->cp_gfx_hqd_cntl = tmp;
3698
3699         /* set up cp_doorbell_control */
3700         tmp = RREG32_SOC15(GC, 0, regCP_RB_DOORBELL_CONTROL);
3701         if (prop->use_doorbell) {
3702                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3703                                     DOORBELL_OFFSET, prop->doorbell_index);
3704                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3705                                     DOORBELL_EN, 1);
3706         } else
3707                 tmp = REG_SET_FIELD(tmp, CP_RB_DOORBELL_CONTROL,
3708                                     DOORBELL_EN, 0);
3709         mqd->cp_rb_doorbell_control = tmp;
3710
3711         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3712         mqd->cp_gfx_hqd_rptr = RREG32_SOC15(GC, 0, regCP_GFX_HQD_RPTR);
3713
3714         /* active the queue */
3715         mqd->cp_gfx_hqd_active = 1;
3716
3717         return 0;
3718 }
3719
3720 static int gfx_v11_0_gfx_init_queue(struct amdgpu_ring *ring)
3721 {
3722         struct amdgpu_device *adev = ring->adev;
3723         struct v11_gfx_mqd *mqd = ring->mqd_ptr;
3724         int mqd_idx = ring - &adev->gfx.gfx_ring[0];
3725
3726         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
3727                 memset((void *)mqd, 0, sizeof(*mqd));
3728                 mutex_lock(&adev->srbm_mutex);
3729                 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
3730                 amdgpu_ring_init_mqd(ring);
3731                 soc21_grbm_select(adev, 0, 0, 0, 0);
3732                 mutex_unlock(&adev->srbm_mutex);
3733                 if (adev->gfx.me.mqd_backup[mqd_idx])
3734                         memcpy_fromio(adev->gfx.me.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
3735         } else {
3736                 /* restore mqd with the backup copy */
3737                 if (adev->gfx.me.mqd_backup[mqd_idx])
3738                         memcpy_toio(mqd, adev->gfx.me.mqd_backup[mqd_idx], sizeof(*mqd));
3739                 /* reset the ring */
3740                 ring->wptr = 0;
3741                 *ring->wptr_cpu_addr = 0;
3742                 amdgpu_ring_clear_ring(ring);
3743         }
3744
3745         return 0;
3746 }
3747
3748 static int gfx_v11_0_cp_async_gfx_ring_resume(struct amdgpu_device *adev)
3749 {
3750         int r, i;
3751         struct amdgpu_ring *ring;
3752
3753         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
3754                 ring = &adev->gfx.gfx_ring[i];
3755
3756                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
3757                 if (unlikely(r != 0))
3758                         return r;
3759
3760                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
3761                 if (!r) {
3762                         r = gfx_v11_0_gfx_init_queue(ring);
3763                         amdgpu_bo_kunmap(ring->mqd_obj);
3764                         ring->mqd_ptr = NULL;
3765                 }
3766                 amdgpu_bo_unreserve(ring->mqd_obj);
3767                 if (r)
3768                         return r;
3769         }
3770
3771         r = amdgpu_gfx_enable_kgq(adev, 0);
3772         if (r)
3773                 return r;
3774
3775         return gfx_v11_0_cp_gfx_start(adev);
3776 }
3777
3778 static int gfx_v11_0_compute_mqd_init(struct amdgpu_device *adev, void *m,
3779                                       struct amdgpu_mqd_prop *prop)
3780 {
3781         struct v11_compute_mqd *mqd = m;
3782         uint64_t hqd_gpu_addr, wb_gpu_addr, eop_base_addr;
3783         uint32_t tmp;
3784
3785         mqd->header = 0xC0310800;
3786         mqd->compute_pipelinestat_enable = 0x00000001;
3787         mqd->compute_static_thread_mgmt_se0 = 0xffffffff;
3788         mqd->compute_static_thread_mgmt_se1 = 0xffffffff;
3789         mqd->compute_static_thread_mgmt_se2 = 0xffffffff;
3790         mqd->compute_static_thread_mgmt_se3 = 0xffffffff;
3791         mqd->compute_misc_reserved = 0x00000007;
3792
3793         eop_base_addr = prop->eop_gpu_addr >> 8;
3794         mqd->cp_hqd_eop_base_addr_lo = eop_base_addr;
3795         mqd->cp_hqd_eop_base_addr_hi = upper_32_bits(eop_base_addr);
3796
3797         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3798         tmp = RREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL);
3799         tmp = REG_SET_FIELD(tmp, CP_HQD_EOP_CONTROL, EOP_SIZE,
3800                         (order_base_2(GFX11_MEC_HPD_SIZE / 4) - 1));
3801
3802         mqd->cp_hqd_eop_control = tmp;
3803
3804         /* enable doorbell? */
3805         tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
3806
3807         if (prop->use_doorbell) {
3808                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3809                                     DOORBELL_OFFSET, prop->doorbell_index);
3810                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3811                                     DOORBELL_EN, 1);
3812                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3813                                     DOORBELL_SOURCE, 0);
3814                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3815                                     DOORBELL_HIT, 0);
3816         } else {
3817                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3818                                     DOORBELL_EN, 0);
3819         }
3820
3821         mqd->cp_hqd_pq_doorbell_control = tmp;
3822
3823         /* disable the queue if it's active */
3824         mqd->cp_hqd_dequeue_request = 0;
3825         mqd->cp_hqd_pq_rptr = 0;
3826         mqd->cp_hqd_pq_wptr_lo = 0;
3827         mqd->cp_hqd_pq_wptr_hi = 0;
3828
3829         /* set the pointer to the MQD */
3830         mqd->cp_mqd_base_addr_lo = prop->mqd_gpu_addr & 0xfffffffc;
3831         mqd->cp_mqd_base_addr_hi = upper_32_bits(prop->mqd_gpu_addr);
3832
3833         /* set MQD vmid to 0 */
3834         tmp = RREG32_SOC15(GC, 0, regCP_MQD_CONTROL);
3835         tmp = REG_SET_FIELD(tmp, CP_MQD_CONTROL, VMID, 0);
3836         mqd->cp_mqd_control = tmp;
3837
3838         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3839         hqd_gpu_addr = prop->hqd_base_gpu_addr >> 8;
3840         mqd->cp_hqd_pq_base_lo = hqd_gpu_addr;
3841         mqd->cp_hqd_pq_base_hi = upper_32_bits(hqd_gpu_addr);
3842
3843         /* set up the HQD, this is similar to CP_RB0_CNTL */
3844         tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL);
3845         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, QUEUE_SIZE,
3846                             (order_base_2(prop->queue_size / 4) - 1));
3847         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, RPTR_BLOCK_SIZE,
3848                             (order_base_2(AMDGPU_GPU_PAGE_SIZE / 4) - 1));
3849         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, UNORD_DISPATCH, 0);
3850         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, TUNNEL_DISPATCH, 0);
3851         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, PRIV_STATE, 1);
3852         tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_CONTROL, KMD_QUEUE, 1);
3853         mqd->cp_hqd_pq_control = tmp;
3854
3855         /* set the wb address whether it's enabled or not */
3856         wb_gpu_addr = prop->rptr_gpu_addr;
3857         mqd->cp_hqd_pq_rptr_report_addr_lo = wb_gpu_addr & 0xfffffffc;
3858         mqd->cp_hqd_pq_rptr_report_addr_hi =
3859                 upper_32_bits(wb_gpu_addr) & 0xffff;
3860
3861         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3862         wb_gpu_addr = prop->wptr_gpu_addr;
3863         mqd->cp_hqd_pq_wptr_poll_addr_lo = wb_gpu_addr & 0xfffffffc;
3864         mqd->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits(wb_gpu_addr) & 0xffff;
3865
3866         tmp = 0;
3867         /* enable the doorbell if requested */
3868         if (prop->use_doorbell) {
3869                 tmp = RREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL);
3870                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3871                                 DOORBELL_OFFSET, prop->doorbell_index);
3872
3873                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3874                                     DOORBELL_EN, 1);
3875                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3876                                     DOORBELL_SOURCE, 0);
3877                 tmp = REG_SET_FIELD(tmp, CP_HQD_PQ_DOORBELL_CONTROL,
3878                                     DOORBELL_HIT, 0);
3879         }
3880
3881         mqd->cp_hqd_pq_doorbell_control = tmp;
3882
3883         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3884         mqd->cp_hqd_pq_rptr = RREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR);
3885
3886         /* set the vmid for the queue */
3887         mqd->cp_hqd_vmid = 0;
3888
3889         tmp = RREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE);
3890         tmp = REG_SET_FIELD(tmp, CP_HQD_PERSISTENT_STATE, PRELOAD_SIZE, 0x55);
3891         mqd->cp_hqd_persistent_state = tmp;
3892
3893         /* set MIN_IB_AVAIL_SIZE */
3894         tmp = RREG32_SOC15(GC, 0, regCP_HQD_IB_CONTROL);
3895         tmp = REG_SET_FIELD(tmp, CP_HQD_IB_CONTROL, MIN_IB_AVAIL_SIZE, 3);
3896         mqd->cp_hqd_ib_control = tmp;
3897
3898         /* set static priority for a compute queue/ring */
3899         mqd->cp_hqd_pipe_priority = prop->hqd_pipe_priority;
3900         mqd->cp_hqd_queue_priority = prop->hqd_queue_priority;
3901
3902         mqd->cp_hqd_active = prop->hqd_active;
3903
3904         return 0;
3905 }
3906
3907 static int gfx_v11_0_kiq_init_register(struct amdgpu_ring *ring)
3908 {
3909         struct amdgpu_device *adev = ring->adev;
3910         struct v11_compute_mqd *mqd = ring->mqd_ptr;
3911         int j;
3912
3913         /* inactivate the queue */
3914         if (amdgpu_sriov_vf(adev))
3915                 WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE, 0);
3916
3917         /* disable wptr polling */
3918         WREG32_FIELD15_PREREG(GC, 0, CP_PQ_WPTR_POLL_CNTL, EN, 0);
3919
3920         /* write the EOP addr */
3921         WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR,
3922                mqd->cp_hqd_eop_base_addr_lo);
3923         WREG32_SOC15(GC, 0, regCP_HQD_EOP_BASE_ADDR_HI,
3924                mqd->cp_hqd_eop_base_addr_hi);
3925
3926         /* set the EOP size, register value is 2^(EOP_SIZE+1) dwords */
3927         WREG32_SOC15(GC, 0, regCP_HQD_EOP_CONTROL,
3928                mqd->cp_hqd_eop_control);
3929
3930         /* enable doorbell? */
3931         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
3932                mqd->cp_hqd_pq_doorbell_control);
3933
3934         /* disable the queue if it's active */
3935         if (RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1) {
3936                 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 1);
3937                 for (j = 0; j < adev->usec_timeout; j++) {
3938                         if (!(RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) & 1))
3939                                 break;
3940                         udelay(1);
3941                 }
3942                 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST,
3943                        mqd->cp_hqd_dequeue_request);
3944                 WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR,
3945                        mqd->cp_hqd_pq_rptr);
3946                 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO,
3947                        mqd->cp_hqd_pq_wptr_lo);
3948                 WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,
3949                        mqd->cp_hqd_pq_wptr_hi);
3950         }
3951
3952         /* set the pointer to the MQD */
3953         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR,
3954                mqd->cp_mqd_base_addr_lo);
3955         WREG32_SOC15(GC, 0, regCP_MQD_BASE_ADDR_HI,
3956                mqd->cp_mqd_base_addr_hi);
3957
3958         /* set MQD vmid to 0 */
3959         WREG32_SOC15(GC, 0, regCP_MQD_CONTROL,
3960                mqd->cp_mqd_control);
3961
3962         /* set the pointer to the HQD, this is similar CP_RB0_BASE/_HI */
3963         WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE,
3964                mqd->cp_hqd_pq_base_lo);
3965         WREG32_SOC15(GC, 0, regCP_HQD_PQ_BASE_HI,
3966                mqd->cp_hqd_pq_base_hi);
3967
3968         /* set up the HQD, this is similar to CP_RB0_CNTL */
3969         WREG32_SOC15(GC, 0, regCP_HQD_PQ_CONTROL,
3970                mqd->cp_hqd_pq_control);
3971
3972         /* set the wb address whether it's enabled or not */
3973         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR,
3974                 mqd->cp_hqd_pq_rptr_report_addr_lo);
3975         WREG32_SOC15(GC, 0, regCP_HQD_PQ_RPTR_REPORT_ADDR_HI,
3976                 mqd->cp_hqd_pq_rptr_report_addr_hi);
3977
3978         /* only used if CP_PQ_WPTR_POLL_CNTL.CP_PQ_WPTR_POLL_CNTL__EN_MASK=1 */
3979         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR,
3980                mqd->cp_hqd_pq_wptr_poll_addr_lo);
3981         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_POLL_ADDR_HI,
3982                mqd->cp_hqd_pq_wptr_poll_addr_hi);
3983
3984         /* enable the doorbell if requested */
3985         if (ring->use_doorbell) {
3986                 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_LOWER,
3987                         (adev->doorbell_index.kiq * 2) << 2);
3988                 WREG32_SOC15(GC, 0, regCP_MEC_DOORBELL_RANGE_UPPER,
3989                         (adev->doorbell_index.userqueue_end * 2) << 2);
3990         }
3991
3992         WREG32_SOC15(GC, 0, regCP_HQD_PQ_DOORBELL_CONTROL,
3993                mqd->cp_hqd_pq_doorbell_control);
3994
3995         /* reset read and write pointers, similar to CP_RB0_WPTR/_RPTR */
3996         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_LO,
3997                mqd->cp_hqd_pq_wptr_lo);
3998         WREG32_SOC15(GC, 0, regCP_HQD_PQ_WPTR_HI,
3999                mqd->cp_hqd_pq_wptr_hi);
4000
4001         /* set the vmid for the queue */
4002         WREG32_SOC15(GC, 0, regCP_HQD_VMID, mqd->cp_hqd_vmid);
4003
4004         WREG32_SOC15(GC, 0, regCP_HQD_PERSISTENT_STATE,
4005                mqd->cp_hqd_persistent_state);
4006
4007         /* activate the queue */
4008         WREG32_SOC15(GC, 0, regCP_HQD_ACTIVE,
4009                mqd->cp_hqd_active);
4010
4011         if (ring->use_doorbell)
4012                 WREG32_FIELD15_PREREG(GC, 0, CP_PQ_STATUS, DOORBELL_ENABLE, 1);
4013
4014         return 0;
4015 }
4016
4017 static int gfx_v11_0_kiq_init_queue(struct amdgpu_ring *ring)
4018 {
4019         struct amdgpu_device *adev = ring->adev;
4020         struct v11_compute_mqd *mqd = ring->mqd_ptr;
4021
4022         gfx_v11_0_kiq_setting(ring);
4023
4024         if (amdgpu_in_reset(adev)) { /* for GPU_RESET case */
4025                 /* reset MQD to a clean status */
4026                 if (adev->gfx.kiq[0].mqd_backup)
4027                         memcpy_toio(mqd, adev->gfx.kiq[0].mqd_backup, sizeof(*mqd));
4028
4029                 /* reset ring buffer */
4030                 ring->wptr = 0;
4031                 amdgpu_ring_clear_ring(ring);
4032
4033                 mutex_lock(&adev->srbm_mutex);
4034                 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4035                 gfx_v11_0_kiq_init_register(ring);
4036                 soc21_grbm_select(adev, 0, 0, 0, 0);
4037                 mutex_unlock(&adev->srbm_mutex);
4038         } else {
4039                 memset((void *)mqd, 0, sizeof(*mqd));
4040                 if (amdgpu_sriov_vf(adev) && adev->in_suspend)
4041                         amdgpu_ring_clear_ring(ring);
4042                 mutex_lock(&adev->srbm_mutex);
4043                 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4044                 amdgpu_ring_init_mqd(ring);
4045                 gfx_v11_0_kiq_init_register(ring);
4046                 soc21_grbm_select(adev, 0, 0, 0, 0);
4047                 mutex_unlock(&adev->srbm_mutex);
4048
4049                 if (adev->gfx.kiq[0].mqd_backup)
4050                         memcpy_fromio(adev->gfx.kiq[0].mqd_backup, mqd, sizeof(*mqd));
4051         }
4052
4053         return 0;
4054 }
4055
4056 static int gfx_v11_0_kcq_init_queue(struct amdgpu_ring *ring)
4057 {
4058         struct amdgpu_device *adev = ring->adev;
4059         struct v11_compute_mqd *mqd = ring->mqd_ptr;
4060         int mqd_idx = ring - &adev->gfx.compute_ring[0];
4061
4062         if (!amdgpu_in_reset(adev) && !adev->in_suspend) {
4063                 memset((void *)mqd, 0, sizeof(*mqd));
4064                 mutex_lock(&adev->srbm_mutex);
4065                 soc21_grbm_select(adev, ring->me, ring->pipe, ring->queue, 0);
4066                 amdgpu_ring_init_mqd(ring);
4067                 soc21_grbm_select(adev, 0, 0, 0, 0);
4068                 mutex_unlock(&adev->srbm_mutex);
4069
4070                 if (adev->gfx.mec.mqd_backup[mqd_idx])
4071                         memcpy_fromio(adev->gfx.mec.mqd_backup[mqd_idx], mqd, sizeof(*mqd));
4072         } else {
4073                 /* restore MQD to a clean status */
4074                 if (adev->gfx.mec.mqd_backup[mqd_idx])
4075                         memcpy_toio(mqd, adev->gfx.mec.mqd_backup[mqd_idx], sizeof(*mqd));
4076                 /* reset ring buffer */
4077                 ring->wptr = 0;
4078                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr, 0);
4079                 amdgpu_ring_clear_ring(ring);
4080         }
4081
4082         return 0;
4083 }
4084
4085 static int gfx_v11_0_kiq_resume(struct amdgpu_device *adev)
4086 {
4087         struct amdgpu_ring *ring;
4088         int r;
4089
4090         ring = &adev->gfx.kiq[0].ring;
4091
4092         r = amdgpu_bo_reserve(ring->mqd_obj, false);
4093         if (unlikely(r != 0))
4094                 return r;
4095
4096         r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
4097         if (unlikely(r != 0)) {
4098                 amdgpu_bo_unreserve(ring->mqd_obj);
4099                 return r;
4100         }
4101
4102         gfx_v11_0_kiq_init_queue(ring);
4103         amdgpu_bo_kunmap(ring->mqd_obj);
4104         ring->mqd_ptr = NULL;
4105         amdgpu_bo_unreserve(ring->mqd_obj);
4106         ring->sched.ready = true;
4107         return 0;
4108 }
4109
4110 static int gfx_v11_0_kcq_resume(struct amdgpu_device *adev)
4111 {
4112         struct amdgpu_ring *ring = NULL;
4113         int r = 0, i;
4114
4115         if (!amdgpu_async_gfx_ring)
4116                 gfx_v11_0_cp_compute_enable(adev, true);
4117
4118         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4119                 ring = &adev->gfx.compute_ring[i];
4120
4121                 r = amdgpu_bo_reserve(ring->mqd_obj, false);
4122                 if (unlikely(r != 0))
4123                         goto done;
4124                 r = amdgpu_bo_kmap(ring->mqd_obj, (void **)&ring->mqd_ptr);
4125                 if (!r) {
4126                         r = gfx_v11_0_kcq_init_queue(ring);
4127                         amdgpu_bo_kunmap(ring->mqd_obj);
4128                         ring->mqd_ptr = NULL;
4129                 }
4130                 amdgpu_bo_unreserve(ring->mqd_obj);
4131                 if (r)
4132                         goto done;
4133         }
4134
4135         r = amdgpu_gfx_enable_kcq(adev, 0);
4136 done:
4137         return r;
4138 }
4139
4140 static int gfx_v11_0_cp_resume(struct amdgpu_device *adev)
4141 {
4142         int r, i;
4143         struct amdgpu_ring *ring;
4144
4145         if (!(adev->flags & AMD_IS_APU))
4146                 gfx_v11_0_enable_gui_idle_interrupt(adev, false);
4147
4148         if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4149                 /* legacy firmware loading */
4150                 r = gfx_v11_0_cp_gfx_load_microcode(adev);
4151                 if (r)
4152                         return r;
4153
4154                 if (adev->gfx.rs64_enable)
4155                         r = gfx_v11_0_cp_compute_load_microcode_rs64(adev);
4156                 else
4157                         r = gfx_v11_0_cp_compute_load_microcode(adev);
4158                 if (r)
4159                         return r;
4160         }
4161
4162         gfx_v11_0_cp_set_doorbell_range(adev);
4163
4164         if (amdgpu_async_gfx_ring) {
4165                 gfx_v11_0_cp_compute_enable(adev, true);
4166                 gfx_v11_0_cp_gfx_enable(adev, true);
4167         }
4168
4169         if (adev->enable_mes_kiq && adev->mes.kiq_hw_init)
4170                 r = amdgpu_mes_kiq_hw_init(adev);
4171         else
4172                 r = gfx_v11_0_kiq_resume(adev);
4173         if (r)
4174                 return r;
4175
4176         r = gfx_v11_0_kcq_resume(adev);
4177         if (r)
4178                 return r;
4179
4180         if (!amdgpu_async_gfx_ring) {
4181                 r = gfx_v11_0_cp_gfx_resume(adev);
4182                 if (r)
4183                         return r;
4184         } else {
4185                 r = gfx_v11_0_cp_async_gfx_ring_resume(adev);
4186                 if (r)
4187                         return r;
4188         }
4189
4190         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4191                 ring = &adev->gfx.gfx_ring[i];
4192                 r = amdgpu_ring_test_helper(ring);
4193                 if (r)
4194                         return r;
4195         }
4196
4197         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4198                 ring = &adev->gfx.compute_ring[i];
4199                 r = amdgpu_ring_test_helper(ring);
4200                 if (r)
4201                         return r;
4202         }
4203
4204         return 0;
4205 }
4206
4207 static void gfx_v11_0_cp_enable(struct amdgpu_device *adev, bool enable)
4208 {
4209         gfx_v11_0_cp_gfx_enable(adev, enable);
4210         gfx_v11_0_cp_compute_enable(adev, enable);
4211 }
4212
4213 static int gfx_v11_0_gfxhub_enable(struct amdgpu_device *adev)
4214 {
4215         int r;
4216         bool value;
4217
4218         r = adev->gfxhub.funcs->gart_enable(adev);
4219         if (r)
4220                 return r;
4221
4222         adev->hdp.funcs->flush_hdp(adev, NULL);
4223
4224         value = (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS) ?
4225                 false : true;
4226
4227         adev->gfxhub.funcs->set_fault_enable_default(adev, value);
4228         amdgpu_gmc_flush_gpu_tlb(adev, 0, AMDGPU_GFXHUB(0), 0);
4229
4230         return 0;
4231 }
4232
4233 static void gfx_v11_0_select_cp_fw_arch(struct amdgpu_device *adev)
4234 {
4235         u32 tmp;
4236
4237         /* select RS64 */
4238         if (adev->gfx.rs64_enable) {
4239                 tmp = RREG32_SOC15(GC, 0, regCP_GFX_CNTL);
4240                 tmp = REG_SET_FIELD(tmp, CP_GFX_CNTL, ENGINE_SEL, 1);
4241                 WREG32_SOC15(GC, 0, regCP_GFX_CNTL, tmp);
4242
4243                 tmp = RREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL);
4244                 tmp = REG_SET_FIELD(tmp, CP_MEC_ISA_CNTL, ISA_MODE, 1);
4245                 WREG32_SOC15(GC, 0, regCP_MEC_ISA_CNTL, tmp);
4246         }
4247
4248         if (amdgpu_emu_mode == 1)
4249                 msleep(100);
4250 }
4251
4252 static int get_gb_addr_config(struct amdgpu_device * adev)
4253 {
4254         u32 gb_addr_config;
4255
4256         gb_addr_config = RREG32_SOC15(GC, 0, regGB_ADDR_CONFIG);
4257         if (gb_addr_config == 0)
4258                 return -EINVAL;
4259
4260         adev->gfx.config.gb_addr_config_fields.num_pkrs =
4261                 1 << REG_GET_FIELD(gb_addr_config, GB_ADDR_CONFIG, NUM_PKRS);
4262
4263         adev->gfx.config.gb_addr_config = gb_addr_config;
4264
4265         adev->gfx.config.gb_addr_config_fields.num_pipes = 1 <<
4266                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4267                                       GB_ADDR_CONFIG, NUM_PIPES);
4268
4269         adev->gfx.config.max_tile_pipes =
4270                 adev->gfx.config.gb_addr_config_fields.num_pipes;
4271
4272         adev->gfx.config.gb_addr_config_fields.max_compress_frags = 1 <<
4273                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4274                                       GB_ADDR_CONFIG, MAX_COMPRESSED_FRAGS);
4275         adev->gfx.config.gb_addr_config_fields.num_rb_per_se = 1 <<
4276                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4277                                       GB_ADDR_CONFIG, NUM_RB_PER_SE);
4278         adev->gfx.config.gb_addr_config_fields.num_se = 1 <<
4279                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4280                                       GB_ADDR_CONFIG, NUM_SHADER_ENGINES);
4281         adev->gfx.config.gb_addr_config_fields.pipe_interleave_size = 1 << (8 +
4282                         REG_GET_FIELD(adev->gfx.config.gb_addr_config,
4283                                       GB_ADDR_CONFIG, PIPE_INTERLEAVE_SIZE));
4284
4285         return 0;
4286 }
4287
4288 static void gfx_v11_0_disable_gpa_mode(struct amdgpu_device *adev)
4289 {
4290         uint32_t data;
4291
4292         data = RREG32_SOC15(GC, 0, regCPC_PSP_DEBUG);
4293         data |= CPC_PSP_DEBUG__GPA_OVERRIDE_MASK;
4294         WREG32_SOC15(GC, 0, regCPC_PSP_DEBUG, data);
4295
4296         data = RREG32_SOC15(GC, 0, regCPG_PSP_DEBUG);
4297         data |= CPG_PSP_DEBUG__GPA_OVERRIDE_MASK;
4298         WREG32_SOC15(GC, 0, regCPG_PSP_DEBUG, data);
4299 }
4300
4301 static int gfx_v11_0_hw_init(void *handle)
4302 {
4303         int r;
4304         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4305
4306         if (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) {
4307                 if (adev->gfx.imu.funcs) {
4308                         /* RLC autoload sequence 1: Program rlc ram */
4309                         if (adev->gfx.imu.funcs->program_rlc_ram)
4310                                 adev->gfx.imu.funcs->program_rlc_ram(adev);
4311                 }
4312                 /* rlc autoload firmware */
4313                 r = gfx_v11_0_rlc_backdoor_autoload_enable(adev);
4314                 if (r)
4315                         return r;
4316         } else {
4317                 if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
4318                         if (adev->gfx.imu.funcs && (amdgpu_dpm > 0)) {
4319                                 if (adev->gfx.imu.funcs->load_microcode)
4320                                         adev->gfx.imu.funcs->load_microcode(adev);
4321                                 if (adev->gfx.imu.funcs->setup_imu)
4322                                         adev->gfx.imu.funcs->setup_imu(adev);
4323                                 if (adev->gfx.imu.funcs->start_imu)
4324                                         adev->gfx.imu.funcs->start_imu(adev);
4325                         }
4326
4327                         /* disable gpa mode in backdoor loading */
4328                         gfx_v11_0_disable_gpa_mode(adev);
4329                 }
4330         }
4331
4332         if ((adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO) ||
4333             (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)) {
4334                 r = gfx_v11_0_wait_for_rlc_autoload_complete(adev);
4335                 if (r) {
4336                         dev_err(adev->dev, "(%d) failed to wait rlc autoload complete\n", r);
4337                         return r;
4338                 }
4339         }
4340
4341         adev->gfx.is_poweron = true;
4342
4343         if(get_gb_addr_config(adev))
4344                 DRM_WARN("Invalid gb_addr_config !\n");
4345
4346         if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP &&
4347             adev->gfx.rs64_enable)
4348                 gfx_v11_0_config_gfx_rs64(adev);
4349
4350         r = gfx_v11_0_gfxhub_enable(adev);
4351         if (r)
4352                 return r;
4353
4354         if (!amdgpu_emu_mode)
4355                 gfx_v11_0_init_golden_registers(adev);
4356
4357         if ((adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) ||
4358             (adev->firmware.load_type == AMDGPU_FW_LOAD_RLC_BACKDOOR_AUTO && amdgpu_dpm == 1)) {
4359                 /**
4360                  * For gfx 11, rlc firmware loading relies on smu firmware is
4361                  * loaded firstly, so in direct type, it has to load smc ucode
4362                  * here before rlc.
4363                  */
4364                 if (!(adev->flags & AMD_IS_APU)) {
4365                         r = amdgpu_pm_load_smu_firmware(adev, NULL);
4366                         if (r)
4367                                 return r;
4368                 }
4369         }
4370
4371         gfx_v11_0_constants_init(adev);
4372
4373         if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP)
4374                 gfx_v11_0_select_cp_fw_arch(adev);
4375
4376         if (adev->nbio.funcs->gc_doorbell_init)
4377                 adev->nbio.funcs->gc_doorbell_init(adev);
4378
4379         r = gfx_v11_0_rlc_resume(adev);
4380         if (r)
4381                 return r;
4382
4383         /*
4384          * init golden registers and rlc resume may override some registers,
4385          * reconfig them here
4386          */
4387         gfx_v11_0_tcp_harvest(adev);
4388
4389         r = gfx_v11_0_cp_resume(adev);
4390         if (r)
4391                 return r;
4392
4393         /* get IMU version from HW if it's not set */
4394         if (!adev->gfx.imu_fw_version)
4395                 adev->gfx.imu_fw_version = RREG32_SOC15(GC, 0, regGFX_IMU_SCRATCH_0);
4396
4397         return r;
4398 }
4399
4400 static int gfx_v11_0_hw_fini(void *handle)
4401 {
4402         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4403
4404         amdgpu_irq_put(adev, &adev->gfx.priv_reg_irq, 0);
4405         amdgpu_irq_put(adev, &adev->gfx.priv_inst_irq, 0);
4406
4407         if (!adev->no_hw_access) {
4408                 if (amdgpu_async_gfx_ring) {
4409                         if (amdgpu_gfx_disable_kgq(adev, 0))
4410                                 DRM_ERROR("KGQ disable failed\n");
4411                 }
4412
4413                 if (amdgpu_gfx_disable_kcq(adev, 0))
4414                         DRM_ERROR("KCQ disable failed\n");
4415
4416                 amdgpu_mes_kiq_hw_fini(adev);
4417         }
4418
4419         if (amdgpu_sriov_vf(adev))
4420                 /* Remove the steps disabling CPG and clearing KIQ position,
4421                  * so that CP could perform IDLE-SAVE during switch. Those
4422                  * steps are necessary to avoid a DMAR error in gfx9 but it is
4423                  * not reproduced on gfx11.
4424                  */
4425                 return 0;
4426
4427         gfx_v11_0_cp_enable(adev, false);
4428         gfx_v11_0_enable_gui_idle_interrupt(adev, false);
4429
4430         adev->gfxhub.funcs->gart_disable(adev);
4431
4432         adev->gfx.is_poweron = false;
4433
4434         return 0;
4435 }
4436
4437 static int gfx_v11_0_suspend(void *handle)
4438 {
4439         return gfx_v11_0_hw_fini(handle);
4440 }
4441
4442 static int gfx_v11_0_resume(void *handle)
4443 {
4444         return gfx_v11_0_hw_init(handle);
4445 }
4446
4447 static bool gfx_v11_0_is_idle(void *handle)
4448 {
4449         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4450
4451         if (REG_GET_FIELD(RREG32_SOC15(GC, 0, regGRBM_STATUS),
4452                                 GRBM_STATUS, GUI_ACTIVE))
4453                 return false;
4454         else
4455                 return true;
4456 }
4457
4458 static int gfx_v11_0_wait_for_idle(void *handle)
4459 {
4460         unsigned i;
4461         u32 tmp;
4462         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4463
4464         for (i = 0; i < adev->usec_timeout; i++) {
4465                 /* read MC_STATUS */
4466                 tmp = RREG32_SOC15(GC, 0, regGRBM_STATUS) &
4467                         GRBM_STATUS__GUI_ACTIVE_MASK;
4468
4469                 if (!REG_GET_FIELD(tmp, GRBM_STATUS, GUI_ACTIVE))
4470                         return 0;
4471                 udelay(1);
4472         }
4473         return -ETIMEDOUT;
4474 }
4475
4476 static int gfx_v11_0_soft_reset(void *handle)
4477 {
4478         u32 grbm_soft_reset = 0;
4479         u32 tmp;
4480         int i, j, k;
4481         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4482
4483         tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL);
4484         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 0);
4485         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 0);
4486         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 0);
4487         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 0);
4488         WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp);
4489
4490         gfx_v11_0_set_safe_mode(adev, 0);
4491
4492         for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
4493                 for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
4494                         for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
4495                                 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);
4496                                 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i);
4497                                 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j);
4498                                 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k);
4499                                 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);
4500
4501                                 WREG32_SOC15(GC, 0, regCP_HQD_DEQUEUE_REQUEST, 0x2);
4502                                 WREG32_SOC15(GC, 0, regSPI_COMPUTE_QUEUE_RESET, 0x1);
4503                         }
4504                 }
4505         }
4506         for (i = 0; i < adev->gfx.me.num_me; ++i) {
4507                 for (j = 0; j < adev->gfx.me.num_queue_per_pipe; j++) {
4508                         for (k = 0; k < adev->gfx.me.num_pipe_per_me; k++) {
4509                                 tmp = RREG32_SOC15(GC, 0, regGRBM_GFX_CNTL);
4510                                 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, MEID, i);
4511                                 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, QUEUEID, j);
4512                                 tmp = REG_SET_FIELD(tmp, GRBM_GFX_CNTL, PIPEID, k);
4513                                 WREG32_SOC15(GC, 0, regGRBM_GFX_CNTL, tmp);
4514
4515                                 WREG32_SOC15(GC, 0, regCP_GFX_HQD_DEQUEUE_REQUEST, 0x1);
4516                         }
4517                 }
4518         }
4519
4520         WREG32_SOC15(GC, 0, regCP_VMID_RESET, 0xfffffffe);
4521
4522         // Read CP_VMID_RESET register three times.
4523         // to get sufficient time for GFX_HQD_ACTIVE reach 0
4524         RREG32_SOC15(GC, 0, regCP_VMID_RESET);
4525         RREG32_SOC15(GC, 0, regCP_VMID_RESET);
4526         RREG32_SOC15(GC, 0, regCP_VMID_RESET);
4527
4528         for (i = 0; i < adev->usec_timeout; i++) {
4529                 if (!RREG32_SOC15(GC, 0, regCP_HQD_ACTIVE) &&
4530                     !RREG32_SOC15(GC, 0, regCP_GFX_HQD_ACTIVE))
4531                         break;
4532                 udelay(1);
4533         }
4534         if (i >= adev->usec_timeout) {
4535                 printk("Failed to wait all pipes clean\n");
4536                 return -EINVAL;
4537         }
4538
4539         /**********  trigger soft reset  ***********/
4540         grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
4541         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4542                                         SOFT_RESET_CP, 1);
4543         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4544                                         SOFT_RESET_GFX, 1);
4545         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4546                                         SOFT_RESET_CPF, 1);
4547         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4548                                         SOFT_RESET_CPC, 1);
4549         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4550                                         SOFT_RESET_CPG, 1);
4551         WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset);
4552         /**********  exit soft reset  ***********/
4553         grbm_soft_reset = RREG32_SOC15(GC, 0, regGRBM_SOFT_RESET);
4554         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4555                                         SOFT_RESET_CP, 0);
4556         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4557                                         SOFT_RESET_GFX, 0);
4558         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4559                                         SOFT_RESET_CPF, 0);
4560         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4561                                         SOFT_RESET_CPC, 0);
4562         grbm_soft_reset = REG_SET_FIELD(grbm_soft_reset, GRBM_SOFT_RESET,
4563                                         SOFT_RESET_CPG, 0);
4564         WREG32_SOC15(GC, 0, regGRBM_SOFT_RESET, grbm_soft_reset);
4565
4566         tmp = RREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL);
4567         tmp = REG_SET_FIELD(tmp, CP_SOFT_RESET_CNTL, CMP_HQD_REG_RESET, 0x1);
4568         WREG32_SOC15(GC, 0, regCP_SOFT_RESET_CNTL, tmp);
4569
4570         WREG32_SOC15(GC, 0, regCP_ME_CNTL, 0x0);
4571         WREG32_SOC15(GC, 0, regCP_MEC_RS64_CNTL, 0x0);
4572
4573         for (i = 0; i < adev->usec_timeout; i++) {
4574                 if (!RREG32_SOC15(GC, 0, regCP_VMID_RESET))
4575                         break;
4576                 udelay(1);
4577         }
4578         if (i >= adev->usec_timeout) {
4579                 printk("Failed to wait CP_VMID_RESET to 0\n");
4580                 return -EINVAL;
4581         }
4582
4583         tmp = RREG32_SOC15(GC, 0, regCP_INT_CNTL);
4584         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1);
4585         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1);
4586         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1);
4587         tmp = REG_SET_FIELD(tmp, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);
4588         WREG32_SOC15(GC, 0, regCP_INT_CNTL, tmp);
4589
4590         gfx_v11_0_unset_safe_mode(adev, 0);
4591
4592         return gfx_v11_0_cp_resume(adev);
4593 }
4594
4595 static bool gfx_v11_0_check_soft_reset(void *handle)
4596 {
4597         int i, r;
4598         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4599         struct amdgpu_ring *ring;
4600         long tmo = msecs_to_jiffies(1000);
4601
4602         for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
4603                 ring = &adev->gfx.gfx_ring[i];
4604                 r = amdgpu_ring_test_ib(ring, tmo);
4605                 if (r)
4606                         return true;
4607         }
4608
4609         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
4610                 ring = &adev->gfx.compute_ring[i];
4611                 r = amdgpu_ring_test_ib(ring, tmo);
4612                 if (r)
4613                         return true;
4614         }
4615
4616         return false;
4617 }
4618
4619 static int gfx_v11_0_post_soft_reset(void *handle)
4620 {
4621         /**
4622          * GFX soft reset will impact MES, need resume MES when do GFX soft reset
4623          */
4624         return amdgpu_mes_resume((struct amdgpu_device *)handle);
4625 }
4626
4627 static uint64_t gfx_v11_0_get_gpu_clock_counter(struct amdgpu_device *adev)
4628 {
4629         uint64_t clock;
4630         uint64_t clock_counter_lo, clock_counter_hi_pre, clock_counter_hi_after;
4631
4632         if (amdgpu_sriov_vf(adev)) {
4633                 amdgpu_gfx_off_ctrl(adev, false);
4634                 mutex_lock(&adev->gfx.gpu_clock_mutex);
4635                 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI);
4636                 clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO);
4637                 clock_counter_hi_after = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_HI);
4638                 if (clock_counter_hi_pre != clock_counter_hi_after)
4639                         clock_counter_lo = (uint64_t)RREG32_SOC15(GC, 0, regCP_MES_MTIME_LO);
4640                 mutex_unlock(&adev->gfx.gpu_clock_mutex);
4641                 amdgpu_gfx_off_ctrl(adev, true);
4642         } else {
4643                 preempt_disable();
4644                 clock_counter_hi_pre = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);
4645                 clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);
4646                 clock_counter_hi_after = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_UPPER);
4647                 if (clock_counter_hi_pre != clock_counter_hi_after)
4648                         clock_counter_lo = (uint64_t)RREG32_SOC15(SMUIO, 0, regGOLDEN_TSC_COUNT_LOWER);
4649                 preempt_enable();
4650         }
4651         clock = clock_counter_lo | (clock_counter_hi_after << 32ULL);
4652
4653         return clock;
4654 }
4655
4656 static void gfx_v11_0_ring_emit_gds_switch(struct amdgpu_ring *ring,
4657                                            uint32_t vmid,
4658                                            uint32_t gds_base, uint32_t gds_size,
4659                                            uint32_t gws_base, uint32_t gws_size,
4660                                            uint32_t oa_base, uint32_t oa_size)
4661 {
4662         struct amdgpu_device *adev = ring->adev;
4663
4664         /* GDS Base */
4665         gfx_v11_0_write_data_to_reg(ring, 0, false,
4666                                     SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_BASE) + 2 * vmid,
4667                                     gds_base);
4668
4669         /* GDS Size */
4670         gfx_v11_0_write_data_to_reg(ring, 0, false,
4671                                     SOC15_REG_OFFSET(GC, 0, regGDS_VMID0_SIZE) + 2 * vmid,
4672                                     gds_size);
4673
4674         /* GWS */
4675         gfx_v11_0_write_data_to_reg(ring, 0, false,
4676                                     SOC15_REG_OFFSET(GC, 0, regGDS_GWS_VMID0) + vmid,
4677                                     gws_size << GDS_GWS_VMID0__SIZE__SHIFT | gws_base);
4678
4679         /* OA */
4680         gfx_v11_0_write_data_to_reg(ring, 0, false,
4681                                     SOC15_REG_OFFSET(GC, 0, regGDS_OA_VMID0) + vmid,
4682                                     (1 << (oa_size + oa_base)) - (1 << oa_base));
4683 }
4684
4685 static int gfx_v11_0_early_init(void *handle)
4686 {
4687         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4688
4689         adev->gfx.funcs = &gfx_v11_0_gfx_funcs;
4690
4691         adev->gfx.num_gfx_rings = GFX11_NUM_GFX_RINGS;
4692         adev->gfx.num_compute_rings = min(amdgpu_gfx_get_num_kcq(adev),
4693                                           AMDGPU_MAX_COMPUTE_RINGS);
4694
4695         gfx_v11_0_set_kiq_pm4_funcs(adev);
4696         gfx_v11_0_set_ring_funcs(adev);
4697         gfx_v11_0_set_irq_funcs(adev);
4698         gfx_v11_0_set_gds_init(adev);
4699         gfx_v11_0_set_rlc_funcs(adev);
4700         gfx_v11_0_set_mqd_funcs(adev);
4701         gfx_v11_0_set_imu_funcs(adev);
4702
4703         gfx_v11_0_init_rlcg_reg_access_ctrl(adev);
4704
4705         return gfx_v11_0_init_microcode(adev);
4706 }
4707
4708 static int gfx_v11_0_late_init(void *handle)
4709 {
4710         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
4711         int r;
4712
4713         r = amdgpu_irq_get(adev, &adev->gfx.priv_reg_irq, 0);
4714         if (r)
4715                 return r;
4716
4717         r = amdgpu_irq_get(adev, &adev->gfx.priv_inst_irq, 0);
4718         if (r)
4719                 return r;
4720
4721         return 0;
4722 }
4723
4724 static bool gfx_v11_0_is_rlc_enabled(struct amdgpu_device *adev)
4725 {
4726         uint32_t rlc_cntl;
4727
4728         /* if RLC is not enabled, do nothing */
4729         rlc_cntl = RREG32_SOC15(GC, 0, regRLC_CNTL);
4730         return (REG_GET_FIELD(rlc_cntl, RLC_CNTL, RLC_ENABLE_F32)) ? true : false;
4731 }
4732
4733 static void gfx_v11_0_set_safe_mode(struct amdgpu_device *adev, int xcc_id)
4734 {
4735         uint32_t data;
4736         unsigned i;
4737
4738         data = RLC_SAFE_MODE__CMD_MASK;
4739         data |= (1 << RLC_SAFE_MODE__MESSAGE__SHIFT);
4740
4741         WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, data);
4742
4743         /* wait for RLC_SAFE_MODE */
4744         for (i = 0; i < adev->usec_timeout; i++) {
4745                 if (!REG_GET_FIELD(RREG32_SOC15(GC, 0, regRLC_SAFE_MODE),
4746                                    RLC_SAFE_MODE, CMD))
4747                         break;
4748                 udelay(1);
4749         }
4750 }
4751
4752 static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev, int xcc_id)
4753 {
4754         WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK);
4755 }
4756
4757 static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev,
4758                                       bool enable)
4759 {
4760         uint32_t def, data;
4761
4762         if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK))
4763                 return;
4764
4765         def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4766
4767         if (enable)
4768                 data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK;
4769         else
4770                 data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK;
4771
4772         if (def != data)
4773                 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4774 }
4775
4776 static void gfx_v11_0_update_sram_fgcg(struct amdgpu_device *adev,
4777                                        bool enable)
4778 {
4779         uint32_t def, data;
4780
4781         if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
4782                 return;
4783
4784         def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4785
4786         if (enable)
4787                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
4788         else
4789                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
4790
4791         if (def != data)
4792                 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4793 }
4794
4795 static void gfx_v11_0_update_repeater_fgcg(struct amdgpu_device *adev,
4796                                            bool enable)
4797 {
4798         uint32_t def, data;
4799
4800         if (!(adev->cg_flags & AMD_CG_SUPPORT_REPEATER_FGCG))
4801                 return;
4802
4803         def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4804
4805         if (enable)
4806                 data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK;
4807         else
4808                 data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK;
4809
4810         if (def != data)
4811                 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4812 }
4813
4814 static void gfx_v11_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
4815                                                        bool enable)
4816 {
4817         uint32_t data, def;
4818
4819         if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
4820                 return;
4821
4822         /* It is disabled by HW by default */
4823         if (enable) {
4824                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
4825                         /* 1 - RLC_CGTT_MGCG_OVERRIDE */
4826                         def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4827
4828                         data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4829                                   RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4830                                   RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK);
4831
4832                         if (def != data)
4833                                 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4834                 }
4835         } else {
4836                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
4837                         def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4838
4839                         data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
4840                                  RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
4841                                  RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK);
4842
4843                         if (def != data)
4844                                 WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4845                 }
4846         }
4847 }
4848
4849 static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
4850                                                        bool enable)
4851 {
4852         uint32_t def, data;
4853
4854         if (!(adev->cg_flags &
4855               (AMD_CG_SUPPORT_GFX_CGCG |
4856               AMD_CG_SUPPORT_GFX_CGLS |
4857               AMD_CG_SUPPORT_GFX_3D_CGCG |
4858               AMD_CG_SUPPORT_GFX_3D_CGLS)))
4859                 return;
4860
4861         if (enable) {
4862                 def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
4863
4864                 /* unset CGCG override */
4865                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
4866                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGCG_OVERRIDE_MASK;
4867                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4868                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_CGLS_OVERRIDE_MASK;
4869                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG ||
4870                     adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
4871                         data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_GFX3D_CG_OVERRIDE_MASK;
4872
4873                 /* update CGCG override bits */
4874                 if (def != data)
4875                         WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
4876
4877                 /* enable cgcg FSM(0x0000363F) */
4878                 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
4879
4880                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG) {
4881                         data &= ~RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD_MASK;
4882                         data |= (0x36 << RLC_CGCG_CGLS_CTRL__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4883                                  RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4884                 }
4885
4886                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS) {
4887                         data &= ~RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY_MASK;
4888                         data |= (0x000F << RLC_CGCG_CGLS_CTRL__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4889                                  RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4890                 }
4891
4892                 if (def != data)
4893                         WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);
4894
4895                 /* Program RLC_CGCG_CGLS_CTRL_3D */
4896                 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
4897
4898                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG) {
4899                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD_MASK;
4900                         data |= (0x36 << RLC_CGCG_CGLS_CTRL_3D__CGCG_GFX_IDLE_THRESHOLD__SHIFT) |
4901                                  RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
4902                 }
4903
4904                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS) {
4905                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY_MASK;
4906                         data |= (0xf << RLC_CGCG_CGLS_CTRL_3D__CGLS_REP_COMPANSAT_DELAY__SHIFT) |
4907                                  RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
4908                 }
4909
4910                 if (def != data)
4911                         WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);
4912
4913                 /* set IDLE_POLL_COUNT(0x00900100) */
4914                 def = data = RREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL);
4915
4916                 data &= ~(CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY_MASK | CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK);
4917                 data |= (0x0100 << CP_RB_WPTR_POLL_CNTL__POLL_FREQUENCY__SHIFT) |
4918                         (0x0090 << CP_RB_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT);
4919
4920                 if (def != data)
4921                         WREG32_SOC15(GC, 0, regCP_RB_WPTR_POLL_CNTL, data);
4922
4923                 data = RREG32_SOC15(GC, 0, regCP_INT_CNTL);
4924                 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_BUSY_INT_ENABLE, 1);
4925                 data = REG_SET_FIELD(data, CP_INT_CNTL, CNTX_EMPTY_INT_ENABLE, 1);
4926                 data = REG_SET_FIELD(data, CP_INT_CNTL, CMP_BUSY_INT_ENABLE, 1);
4927                 data = REG_SET_FIELD(data, CP_INT_CNTL, GFX_IDLE_INT_ENABLE, 1);
4928                 WREG32_SOC15(GC, 0, regCP_INT_CNTL, data);
4929
4930                 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);
4931                 data = REG_SET_FIELD(data, SDMA0_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);
4932                 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);
4933
4934                 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */
4935                 if (adev->sdma.num_instances > 1) {
4936                         data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
4937                         data = REG_SET_FIELD(data, SDMA1_RLC_CGCG_CTRL, CGCG_INT_ENABLE, 1);
4938                         WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
4939                 }
4940         } else {
4941                 /* Program RLC_CGCG_CGLS_CTRL */
4942                 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
4943
4944                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGCG)
4945                         data &= ~RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK;
4946
4947                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_CGLS)
4948                         data &= ~RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK;
4949
4950                 if (def != data)
4951                         WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL, data);
4952
4953                 /* Program RLC_CGCG_CGLS_CTRL_3D */
4954                 def = data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
4955
4956                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGCG)
4957                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK;
4958                 if (adev->cg_flags & AMD_CG_SUPPORT_GFX_3D_CGLS)
4959                         data &= ~RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK;
4960
4961                 if (def != data)
4962                         WREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D, data);
4963
4964                 data = RREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL);
4965                 data &= ~SDMA0_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;
4966                 WREG32_SOC15(GC, 0, regSDMA0_RLC_CGCG_CTRL, data);
4967
4968                 /* Some ASICs only have one SDMA instance, not need to configure SDMA1 */
4969                 if (adev->sdma.num_instances > 1) {
4970                         data = RREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL);
4971                         data &= ~SDMA1_RLC_CGCG_CTRL__CGCG_INT_ENABLE_MASK;
4972                         WREG32_SOC15(GC, 0, regSDMA1_RLC_CGCG_CTRL, data);
4973                 }
4974         }
4975 }
4976
4977 static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev,
4978                                             bool enable)
4979 {
4980         amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
4981
4982         gfx_v11_0_update_coarse_grain_clock_gating(adev, enable);
4983
4984         gfx_v11_0_update_medium_grain_clock_gating(adev, enable);
4985
4986         gfx_v11_0_update_repeater_fgcg(adev, enable);
4987
4988         gfx_v11_0_update_sram_fgcg(adev, enable);
4989
4990         gfx_v11_0_update_perf_clk(adev, enable);
4991
4992         if (adev->cg_flags &
4993             (AMD_CG_SUPPORT_GFX_MGCG |
4994              AMD_CG_SUPPORT_GFX_CGLS |
4995              AMD_CG_SUPPORT_GFX_CGCG |
4996              AMD_CG_SUPPORT_GFX_3D_CGCG |
4997              AMD_CG_SUPPORT_GFX_3D_CGLS))
4998                 gfx_v11_0_enable_gui_idle_interrupt(adev, enable);
4999
5000         amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
5001
5002         return 0;
5003 }
5004
5005 static void gfx_v11_0_update_spm_vmid(struct amdgpu_device *adev, unsigned vmid)
5006 {
5007         u32 data;
5008
5009         amdgpu_gfx_off_ctrl(adev, false);
5010
5011         data = RREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL);
5012
5013         data &= ~RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK;
5014         data |= (vmid & RLC_SPM_MC_CNTL__RLC_SPM_VMID_MASK) << RLC_SPM_MC_CNTL__RLC_SPM_VMID__SHIFT;
5015
5016         WREG32_SOC15_NO_KIQ(GC, 0, regRLC_SPM_MC_CNTL, data);
5017
5018         amdgpu_gfx_off_ctrl(adev, true);
5019 }
5020
5021 static const struct amdgpu_rlc_funcs gfx_v11_0_rlc_funcs = {
5022         .is_rlc_enabled = gfx_v11_0_is_rlc_enabled,
5023         .set_safe_mode = gfx_v11_0_set_safe_mode,
5024         .unset_safe_mode = gfx_v11_0_unset_safe_mode,
5025         .init = gfx_v11_0_rlc_init,
5026         .get_csb_size = gfx_v11_0_get_csb_size,
5027         .get_csb_buffer = gfx_v11_0_get_csb_buffer,
5028         .resume = gfx_v11_0_rlc_resume,
5029         .stop = gfx_v11_0_rlc_stop,
5030         .reset = gfx_v11_0_rlc_reset,
5031         .start = gfx_v11_0_rlc_start,
5032         .update_spm_vmid = gfx_v11_0_update_spm_vmid,
5033 };
5034
5035 static void gfx_v11_cntl_power_gating(struct amdgpu_device *adev, bool enable)
5036 {
5037         u32 data = RREG32_SOC15(GC, 0, regRLC_PG_CNTL);
5038
5039         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG))
5040                 data |= RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
5041         else
5042                 data &= ~RLC_PG_CNTL__GFX_POWER_GATING_ENABLE_MASK;
5043
5044         WREG32_SOC15(GC, 0, regRLC_PG_CNTL, data);
5045
5046         // Program RLC_PG_DELAY3 for CGPG hysteresis
5047         if (enable && (adev->pg_flags & AMD_PG_SUPPORT_GFX_PG)) {
5048                 switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
5049                 case IP_VERSION(11, 0, 1):
5050                 case IP_VERSION(11, 0, 4):
5051                 case IP_VERSION(11, 5, 0):
5052                         WREG32_SOC15(GC, 0, regRLC_PG_DELAY_3, RLC_PG_DELAY_3_DEFAULT_GC_11_0_1);
5053                         break;
5054                 default:
5055                         break;
5056                 }
5057         }
5058 }
5059
5060 static void gfx_v11_cntl_pg(struct amdgpu_device *adev, bool enable)
5061 {
5062         amdgpu_gfx_rlc_enter_safe_mode(adev, 0);
5063
5064         gfx_v11_cntl_power_gating(adev, enable);
5065
5066         amdgpu_gfx_rlc_exit_safe_mode(adev, 0);
5067 }
5068
5069 static int gfx_v11_0_set_powergating_state(void *handle,
5070                                            enum amd_powergating_state state)
5071 {
5072         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5073         bool enable = (state == AMD_PG_STATE_GATE);
5074
5075         if (amdgpu_sriov_vf(adev))
5076                 return 0;
5077
5078         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
5079         case IP_VERSION(11, 0, 0):
5080         case IP_VERSION(11, 0, 2):
5081         case IP_VERSION(11, 0, 3):
5082                 amdgpu_gfx_off_ctrl(adev, enable);
5083                 break;
5084         case IP_VERSION(11, 0, 1):
5085         case IP_VERSION(11, 0, 4):
5086         case IP_VERSION(11, 5, 0):
5087                 if (!enable)
5088                         amdgpu_gfx_off_ctrl(adev, false);
5089
5090                 gfx_v11_cntl_pg(adev, enable);
5091
5092                 if (enable)
5093                         amdgpu_gfx_off_ctrl(adev, true);
5094
5095                 break;
5096         default:
5097                 break;
5098         }
5099
5100         return 0;
5101 }
5102
5103 static int gfx_v11_0_set_clockgating_state(void *handle,
5104                                           enum amd_clockgating_state state)
5105 {
5106         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5107
5108         if (amdgpu_sriov_vf(adev))
5109                 return 0;
5110
5111         switch (amdgpu_ip_version(adev, GC_HWIP, 0)) {
5112         case IP_VERSION(11, 0, 0):
5113         case IP_VERSION(11, 0, 1):
5114         case IP_VERSION(11, 0, 2):
5115         case IP_VERSION(11, 0, 3):
5116         case IP_VERSION(11, 0, 4):
5117         case IP_VERSION(11, 5, 0):
5118                 gfx_v11_0_update_gfx_clock_gating(adev,
5119                                 state ==  AMD_CG_STATE_GATE);
5120                 break;
5121         default:
5122                 break;
5123         }
5124
5125         return 0;
5126 }
5127
5128 static void gfx_v11_0_get_clockgating_state(void *handle, u64 *flags)
5129 {
5130         struct amdgpu_device *adev = (struct amdgpu_device *)handle;
5131         int data;
5132
5133         /* AMD_CG_SUPPORT_GFX_MGCG */
5134         data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
5135         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
5136                 *flags |= AMD_CG_SUPPORT_GFX_MGCG;
5137
5138         /* AMD_CG_SUPPORT_REPEATER_FGCG */
5139         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK))
5140                 *flags |= AMD_CG_SUPPORT_REPEATER_FGCG;
5141
5142         /* AMD_CG_SUPPORT_GFX_FGCG */
5143         if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
5144                 *flags |= AMD_CG_SUPPORT_GFX_FGCG;
5145
5146         /* AMD_CG_SUPPORT_GFX_PERF_CLK */
5147         if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK))
5148                 *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK;
5149
5150         /* AMD_CG_SUPPORT_GFX_CGCG */
5151         data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
5152         if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
5153                 *flags |= AMD_CG_SUPPORT_GFX_CGCG;
5154
5155         /* AMD_CG_SUPPORT_GFX_CGLS */
5156         if (data & RLC_CGCG_CGLS_CTRL__CGLS_EN_MASK)
5157                 *flags |= AMD_CG_SUPPORT_GFX_CGLS;
5158
5159         /* AMD_CG_SUPPORT_GFX_3D_CGCG */
5160         data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL_3D);
5161         if (data & RLC_CGCG_CGLS_CTRL_3D__CGCG_EN_MASK)
5162                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGCG;
5163
5164         /* AMD_CG_SUPPORT_GFX_3D_CGLS */
5165         if (data & RLC_CGCG_CGLS_CTRL_3D__CGLS_EN_MASK)
5166                 *flags |= AMD_CG_SUPPORT_GFX_3D_CGLS;
5167 }
5168
5169 static u64 gfx_v11_0_ring_get_rptr_gfx(struct amdgpu_ring *ring)
5170 {
5171         /* gfx11 is 32bit rptr*/
5172         return *(uint32_t *)ring->rptr_cpu_addr;
5173 }
5174
5175 static u64 gfx_v11_0_ring_get_wptr_gfx(struct amdgpu_ring *ring)
5176 {
5177         struct amdgpu_device *adev = ring->adev;
5178         u64 wptr;
5179
5180         /* XXX check if swapping is necessary on BE */
5181         if (ring->use_doorbell) {
5182                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
5183         } else {
5184                 wptr = RREG32_SOC15(GC, 0, regCP_RB0_WPTR);
5185                 wptr += (u64)RREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI) << 32;
5186         }
5187
5188         return wptr;
5189 }
5190
5191 static void gfx_v11_0_ring_set_wptr_gfx(struct amdgpu_ring *ring)
5192 {
5193         struct amdgpu_device *adev = ring->adev;
5194
5195         if (ring->use_doorbell) {
5196                 /* XXX check if swapping is necessary on BE */
5197                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
5198                              ring->wptr);
5199                 WDOORBELL64(ring->doorbell_index, ring->wptr);
5200         } else {
5201                 WREG32_SOC15(GC, 0, regCP_RB0_WPTR,
5202                              lower_32_bits(ring->wptr));
5203                 WREG32_SOC15(GC, 0, regCP_RB0_WPTR_HI,
5204                              upper_32_bits(ring->wptr));
5205         }
5206 }
5207
5208 static u64 gfx_v11_0_ring_get_rptr_compute(struct amdgpu_ring *ring)
5209 {
5210         /* gfx11 hardware is 32bit rptr */
5211         return *(uint32_t *)ring->rptr_cpu_addr;
5212 }
5213
5214 static u64 gfx_v11_0_ring_get_wptr_compute(struct amdgpu_ring *ring)
5215 {
5216         u64 wptr;
5217
5218         /* XXX check if swapping is necessary on BE */
5219         if (ring->use_doorbell)
5220                 wptr = atomic64_read((atomic64_t *)ring->wptr_cpu_addr);
5221         else
5222                 BUG();
5223         return wptr;
5224 }
5225
5226 static void gfx_v11_0_ring_set_wptr_compute(struct amdgpu_ring *ring)
5227 {
5228         struct amdgpu_device *adev = ring->adev;
5229
5230         /* XXX check if swapping is necessary on BE */
5231         if (ring->use_doorbell) {
5232                 atomic64_set((atomic64_t *)ring->wptr_cpu_addr,
5233                              ring->wptr);
5234                 WDOORBELL64(ring->doorbell_index, ring->wptr);
5235         } else {
5236                 BUG(); /* only DOORBELL method supported on gfx11 now */
5237         }
5238 }
5239
5240 static void gfx_v11_0_ring_emit_hdp_flush(struct amdgpu_ring *ring)
5241 {
5242         struct amdgpu_device *adev = ring->adev;
5243         u32 ref_and_mask, reg_mem_engine;
5244         const struct nbio_hdp_flush_reg *nbio_hf_reg = adev->nbio.hdp_flush_reg;
5245
5246         if (ring->funcs->type == AMDGPU_RING_TYPE_COMPUTE) {
5247                 switch (ring->me) {
5248                 case 1:
5249                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp2 << ring->pipe;
5250                         break;
5251                 case 2:
5252                         ref_and_mask = nbio_hf_reg->ref_and_mask_cp6 << ring->pipe;
5253                         break;
5254                 default:
5255                         return;
5256                 }
5257                 reg_mem_engine = 0;
5258         } else {
5259                 ref_and_mask = nbio_hf_reg->ref_and_mask_cp0;
5260                 reg_mem_engine = 1; /* pfp */
5261         }
5262
5263         gfx_v11_0_wait_reg_mem(ring, reg_mem_engine, 0, 1,
5264                                adev->nbio.funcs->get_hdp_flush_req_offset(adev),
5265                                adev->nbio.funcs->get_hdp_flush_done_offset(adev),
5266                                ref_and_mask, ref_and_mask, 0x20);
5267 }
5268
5269 static void gfx_v11_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
5270                                        struct amdgpu_job *job,
5271                                        struct amdgpu_ib *ib,
5272                                        uint32_t flags)
5273 {
5274         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
5275         u32 header, control = 0;
5276
5277         BUG_ON(ib->flags & AMDGPU_IB_FLAG_CE);
5278
5279         header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
5280
5281         control |= ib->length_dw | (vmid << 24);
5282
5283         if (ring->adev->gfx.mcbp && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
5284                 control |= INDIRECT_BUFFER_PRE_ENB(1);
5285
5286                 if (flags & AMDGPU_IB_PREEMPTED)
5287                         control |= INDIRECT_BUFFER_PRE_RESUME(1);
5288
5289                 if (vmid)
5290                         gfx_v11_0_ring_emit_de_meta(ring,
5291                                     (!amdgpu_sriov_vf(ring->adev) && flags & AMDGPU_IB_PREEMPTED) ? true : false);
5292         }
5293
5294         if (ring->is_mes_queue)
5295                 /* inherit vmid from mqd */
5296                 control |= 0x400000;
5297
5298         amdgpu_ring_write(ring, header);
5299         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
5300         amdgpu_ring_write(ring,
5301 #ifdef __BIG_ENDIAN
5302                 (2 << 0) |
5303 #endif
5304                 lower_32_bits(ib->gpu_addr));
5305         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
5306         amdgpu_ring_write(ring, control);
5307 }
5308
5309 static void gfx_v11_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
5310                                            struct amdgpu_job *job,
5311                                            struct amdgpu_ib *ib,
5312                                            uint32_t flags)
5313 {
5314         unsigned vmid = AMDGPU_JOB_GET_VMID(job);
5315         u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
5316
5317         if (ring->is_mes_queue)
5318                 /* inherit vmid from mqd */
5319                 control |= 0x40000000;
5320
5321         /* Currently, there is a high possibility to get wave ID mismatch
5322          * between ME and GDS, leading to a hw deadlock, because ME generates
5323          * different wave IDs than the GDS expects. This situation happens
5324          * randomly when at least 5 compute pipes use GDS ordered append.
5325          * The wave IDs generated by ME are also wrong after suspend/resume.
5326          * Those are probably bugs somewhere else in the kernel driver.
5327          *
5328          * Writing GDS_COMPUTE_MAX_WAVE_ID resets wave ID counters in ME and
5329          * GDS to 0 for this ring (me/pipe).
5330          */
5331         if (ib->flags & AMDGPU_IB_FLAG_RESET_GDS_MAX_WAVE_ID) {
5332                 amdgpu_ring_write(ring, PACKET3(PACKET3_SET_CONFIG_REG, 1));
5333                 amdgpu_ring_write(ring, regGDS_COMPUTE_MAX_WAVE_ID);
5334                 amdgpu_ring_write(ring, ring->adev->gds.gds_compute_max_wave_id);
5335         }
5336
5337         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
5338         BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
5339         amdgpu_ring_write(ring,
5340 #ifdef __BIG_ENDIAN
5341                                 (2 << 0) |
5342 #endif
5343                                 lower_32_bits(ib->gpu_addr));
5344         amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
5345         amdgpu_ring_write(ring, control);
5346 }
5347
5348 static void gfx_v11_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
5349                                      u64 seq, unsigned flags)
5350 {
5351         bool write64bit = flags & AMDGPU_FENCE_FLAG_64BIT;
5352         bool int_sel = flags & AMDGPU_FENCE_FLAG_INT;
5353
5354         /* RELEASE_MEM - flush caches, send int */
5355         amdgpu_ring_write(ring, PACKET3(PACKET3_RELEASE_MEM, 6));
5356         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_GCR_SEQ |
5357                                  PACKET3_RELEASE_MEM_GCR_GL2_WB |
5358                                  PACKET3_RELEASE_MEM_GCR_GL2_INV |
5359                                  PACKET3_RELEASE_MEM_GCR_GL2_US |
5360                                  PACKET3_RELEASE_MEM_GCR_GL1_INV |
5361                                  PACKET3_RELEASE_MEM_GCR_GLV_INV |
5362                                  PACKET3_RELEASE_MEM_GCR_GLM_INV |
5363                                  PACKET3_RELEASE_MEM_GCR_GLM_WB |
5364                                  PACKET3_RELEASE_MEM_CACHE_POLICY(3) |
5365                                  PACKET3_RELEASE_MEM_EVENT_TYPE(CACHE_FLUSH_AND_INV_TS_EVENT) |
5366                                  PACKET3_RELEASE_MEM_EVENT_INDEX(5)));
5367         amdgpu_ring_write(ring, (PACKET3_RELEASE_MEM_DATA_SEL(write64bit ? 2 : 1) |
5368                                  PACKET3_RELEASE_MEM_INT_SEL(int_sel ? 2 : 0)));
5369
5370         /*
5371          * the address should be Qword aligned if 64bit write, Dword
5372          * aligned if only send 32bit data low (discard data high)
5373          */
5374         if (write64bit)
5375                 BUG_ON(addr & 0x7);
5376         else
5377                 BUG_ON(addr & 0x3);
5378         amdgpu_ring_write(ring, lower_32_bits(addr));
5379         amdgpu_ring_write(ring, upper_32_bits(addr));
5380         amdgpu_ring_write(ring, lower_32_bits(seq));
5381         amdgpu_ring_write(ring, upper_32_bits(seq));
5382         amdgpu_ring_write(ring, ring->is_mes_queue ?
5383                          (ring->hw_queue_id | AMDGPU_FENCE_MES_QUEUE_FLAG) : 0);
5384 }
5385
5386 static void gfx_v11_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
5387 {
5388         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
5389         uint32_t seq = ring->fence_drv.sync_seq;
5390         uint64_t addr = ring->fence_drv.gpu_addr;
5391
5392         gfx_v11_0_wait_reg_mem(ring, usepfp, 1, 0, lower_32_bits(addr),
5393                                upper_32_bits(addr), seq, 0xffffffff, 4);
5394 }
5395
5396 static void gfx_v11_0_ring_invalidate_tlbs(struct amdgpu_ring *ring,
5397                                    uint16_t pasid, uint32_t flush_type,
5398                                    bool all_hub, uint8_t dst_sel)
5399 {
5400         amdgpu_ring_write(ring, PACKET3(PACKET3_INVALIDATE_TLBS, 0));
5401         amdgpu_ring_write(ring,
5402                           PACKET3_INVALIDATE_TLBS_DST_SEL(dst_sel) |
5403                           PACKET3_INVALIDATE_TLBS_ALL_HUB(all_hub) |
5404                           PACKET3_INVALIDATE_TLBS_PASID(pasid) |
5405                           PACKET3_INVALIDATE_TLBS_FLUSH_TYPE(flush_type));
5406 }
5407
5408 static void gfx_v11_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
5409                                          unsigned vmid, uint64_t pd_addr)
5410 {
5411         if (ring->is_mes_queue)
5412                 gfx_v11_0_ring_invalidate_tlbs(ring, 0, 0, false, 0);
5413         else
5414                 amdgpu_gmc_emit_flush_gpu_tlb(ring, vmid, pd_addr);
5415
5416         /* compute doesn't have PFP */
5417         if (ring->funcs->type == AMDGPU_RING_TYPE_GFX) {
5418                 /* sync PFP to ME, otherwise we might get invalid PFP reads */
5419                 amdgpu_ring_write(ring, PACKET3(PACKET3_PFP_SYNC_ME, 0));
5420                 amdgpu_ring_write(ring, 0x0);
5421         }
5422 }
5423
5424 static void gfx_v11_0_ring_emit_fence_kiq(struct amdgpu_ring *ring, u64 addr,
5425                                           u64 seq, unsigned int flags)
5426 {
5427         struct amdgpu_device *adev = ring->adev;
5428
5429         /* we only allocate 32bit for each seq wb address */
5430         BUG_ON(flags & AMDGPU_FENCE_FLAG_64BIT);
5431
5432         /* write fence seq to the "addr" */
5433         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5434         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5435                                  WRITE_DATA_DST_SEL(5) | WR_CONFIRM));
5436         amdgpu_ring_write(ring, lower_32_bits(addr));
5437         amdgpu_ring_write(ring, upper_32_bits(addr));
5438         amdgpu_ring_write(ring, lower_32_bits(seq));
5439
5440         if (flags & AMDGPU_FENCE_FLAG_INT) {
5441                 /* set register to trigger INT */
5442                 amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5443                 amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(0) |
5444                                          WRITE_DATA_DST_SEL(0) | WR_CONFIRM));
5445                 amdgpu_ring_write(ring, SOC15_REG_OFFSET(GC, 0, regCPC_INT_STATUS));
5446                 amdgpu_ring_write(ring, 0);
5447                 amdgpu_ring_write(ring, 0x20000000); /* src_id is 178 */
5448         }
5449 }
5450
5451 static void gfx_v11_0_ring_emit_cntxcntl(struct amdgpu_ring *ring,
5452                                          uint32_t flags)
5453 {
5454         uint32_t dw2 = 0;
5455
5456         dw2 |= 0x80000000; /* set load_enable otherwise this package is just NOPs */
5457         if (flags & AMDGPU_HAVE_CTX_SWITCH) {
5458                 /* set load_global_config & load_global_uconfig */
5459                 dw2 |= 0x8001;
5460                 /* set load_cs_sh_regs */
5461                 dw2 |= 0x01000000;
5462                 /* set load_per_context_state & load_gfx_sh_regs for GFX */
5463                 dw2 |= 0x10002;
5464         }
5465
5466         amdgpu_ring_write(ring, PACKET3(PACKET3_CONTEXT_CONTROL, 1));
5467         amdgpu_ring_write(ring, dw2);
5468         amdgpu_ring_write(ring, 0);
5469 }
5470
5471 static void gfx_v11_0_ring_emit_gfx_shadow(struct amdgpu_ring *ring,
5472                                            u64 shadow_va, u64 csa_va,
5473                                            u64 gds_va, bool init_shadow,
5474                                            int vmid)
5475 {
5476         struct amdgpu_device *adev = ring->adev;
5477
5478         if (!adev->gfx.cp_gfx_shadow)
5479                 return;
5480
5481         amdgpu_ring_write(ring, PACKET3(PACKET3_SET_Q_PREEMPTION_MODE, 7));
5482         amdgpu_ring_write(ring, lower_32_bits(shadow_va));
5483         amdgpu_ring_write(ring, upper_32_bits(shadow_va));
5484         amdgpu_ring_write(ring, lower_32_bits(gds_va));
5485         amdgpu_ring_write(ring, upper_32_bits(gds_va));
5486         amdgpu_ring_write(ring, lower_32_bits(csa_va));
5487         amdgpu_ring_write(ring, upper_32_bits(csa_va));
5488         amdgpu_ring_write(ring, shadow_va ?
5489                           PACKET3_SET_Q_PREEMPTION_MODE_IB_VMID(vmid) : 0);
5490         amdgpu_ring_write(ring, init_shadow ?
5491                           PACKET3_SET_Q_PREEMPTION_MODE_INIT_SHADOW_MEM : 0);
5492 }
5493
5494 static unsigned gfx_v11_0_ring_emit_init_cond_exec(struct amdgpu_ring *ring)
5495 {
5496         unsigned ret;
5497
5498         amdgpu_ring_write(ring, PACKET3(PACKET3_COND_EXEC, 3));
5499         amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr));
5500         amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr));
5501         amdgpu_ring_write(ring, 0); /* discard following DWs if *cond_exec_gpu_addr==0 */
5502         ret = ring->wptr & ring->buf_mask;
5503         amdgpu_ring_write(ring, 0x55aa55aa); /* patch dummy value later */
5504
5505         return ret;
5506 }
5507
5508 static void gfx_v11_0_ring_emit_patch_cond_exec(struct amdgpu_ring *ring, unsigned offset)
5509 {
5510         unsigned cur;
5511         BUG_ON(offset > ring->buf_mask);
5512         BUG_ON(ring->ring[offset] != 0x55aa55aa);
5513
5514         cur = (ring->wptr - 1) & ring->buf_mask;
5515         if (likely(cur > offset))
5516                 ring->ring[offset] = cur - offset;
5517         else
5518                 ring->ring[offset] = (ring->buf_mask + 1) - offset + cur;
5519 }
5520
5521 static int gfx_v11_0_ring_preempt_ib(struct amdgpu_ring *ring)
5522 {
5523         int i, r = 0;
5524         struct amdgpu_device *adev = ring->adev;
5525         struct amdgpu_kiq *kiq = &adev->gfx.kiq[0];
5526         struct amdgpu_ring *kiq_ring = &kiq->ring;
5527         unsigned long flags;
5528
5529         if (!kiq->pmf || !kiq->pmf->kiq_unmap_queues)
5530                 return -EINVAL;
5531
5532         spin_lock_irqsave(&kiq->ring_lock, flags);
5533
5534         if (amdgpu_ring_alloc(kiq_ring, kiq->pmf->unmap_queues_size)) {
5535                 spin_unlock_irqrestore(&kiq->ring_lock, flags);
5536                 return -ENOMEM;
5537         }
5538
5539         /* assert preemption condition */
5540         amdgpu_ring_set_preempt_cond_exec(ring, false);
5541
5542         /* assert IB preemption, emit the trailing fence */
5543         kiq->pmf->kiq_unmap_queues(kiq_ring, ring, PREEMPT_QUEUES_NO_UNMAP,
5544                                    ring->trail_fence_gpu_addr,
5545                                    ++ring->trail_seq);
5546         amdgpu_ring_commit(kiq_ring);
5547
5548         spin_unlock_irqrestore(&kiq->ring_lock, flags);
5549
5550         /* poll the trailing fence */
5551         for (i = 0; i < adev->usec_timeout; i++) {
5552                 if (ring->trail_seq ==
5553                     le32_to_cpu(*(ring->trail_fence_cpu_addr)))
5554                         break;
5555                 udelay(1);
5556         }
5557
5558         if (i >= adev->usec_timeout) {
5559                 r = -EINVAL;
5560                 DRM_ERROR("ring %d failed to preempt ib\n", ring->idx);
5561         }
5562
5563         /* deassert preemption condition */
5564         amdgpu_ring_set_preempt_cond_exec(ring, true);
5565         return r;
5566 }
5567
5568 static void gfx_v11_0_ring_emit_de_meta(struct amdgpu_ring *ring, bool resume)
5569 {
5570         struct amdgpu_device *adev = ring->adev;
5571         struct v10_de_ib_state de_payload = {0};
5572         uint64_t offset, gds_addr, de_payload_gpu_addr;
5573         void *de_payload_cpu_addr;
5574         int cnt;
5575
5576         if (ring->is_mes_queue) {
5577                 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
5578                                   gfx[0].gfx_meta_data) +
5579                         offsetof(struct v10_gfx_meta_data, de_payload);
5580                 de_payload_gpu_addr =
5581                         amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
5582                 de_payload_cpu_addr =
5583                         amdgpu_mes_ctx_get_offs_cpu_addr(ring, offset);
5584
5585                 offset = offsetof(struct amdgpu_mes_ctx_meta_data,
5586                                   gfx[0].gds_backup) +
5587                         offsetof(struct v10_gfx_meta_data, de_payload);
5588                 gds_addr = amdgpu_mes_ctx_get_offs_gpu_addr(ring, offset);
5589         } else {
5590                 offset = offsetof(struct v10_gfx_meta_data, de_payload);
5591                 de_payload_gpu_addr = amdgpu_csa_vaddr(ring->adev) + offset;
5592                 de_payload_cpu_addr = adev->virt.csa_cpu_addr + offset;
5593
5594                 gds_addr = ALIGN(amdgpu_csa_vaddr(ring->adev) +
5595                                  AMDGPU_CSA_SIZE - adev->gds.gds_size,
5596                                  PAGE_SIZE);
5597         }
5598
5599         de_payload.gds_backup_addrlo = lower_32_bits(gds_addr);
5600         de_payload.gds_backup_addrhi = upper_32_bits(gds_addr);
5601
5602         cnt = (sizeof(de_payload) >> 2) + 4 - 2;
5603         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, cnt));
5604         amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
5605                                  WRITE_DATA_DST_SEL(8) |
5606                                  WR_CONFIRM) |
5607                                  WRITE_DATA_CACHE_POLICY(0));
5608         amdgpu_ring_write(ring, lower_32_bits(de_payload_gpu_addr));
5609         amdgpu_ring_write(ring, upper_32_bits(de_payload_gpu_addr));
5610
5611         if (resume)
5612                 amdgpu_ring_write_multiple(ring, de_payload_cpu_addr,
5613                                            sizeof(de_payload) >> 2);
5614         else
5615                 amdgpu_ring_write_multiple(ring, (void *)&de_payload,
5616                                            sizeof(de_payload) >> 2);
5617 }
5618
5619 static void gfx_v11_0_ring_emit_frame_cntl(struct amdgpu_ring *ring, bool start,
5620                                     bool secure)
5621 {
5622         uint32_t v = secure ? FRAME_TMZ : 0;
5623
5624         amdgpu_ring_write(ring, PACKET3(PACKET3_FRAME_CONTROL, 0));
5625         amdgpu_ring_write(ring, v | FRAME_CMD(start ? 0 : 1));
5626 }
5627
5628 static void gfx_v11_0_ring_emit_rreg(struct amdgpu_ring *ring, uint32_t reg,
5629                                      uint32_t reg_val_offs)
5630 {
5631         struct amdgpu_device *adev = ring->adev;
5632
5633         amdgpu_ring_write(ring, PACKET3(PACKET3_COPY_DATA, 4));
5634         amdgpu_ring_write(ring, 0 |     /* src: register*/
5635                                 (5 << 8) |      /* dst: memory */
5636                                 (1 << 20));     /* write confirm */
5637         amdgpu_ring_write(ring, reg);
5638         amdgpu_ring_write(ring, 0);
5639         amdgpu_ring_write(ring, lower_32_bits(adev->wb.gpu_addr +
5640                                 reg_val_offs * 4));
5641         amdgpu_ring_write(ring, upper_32_bits(adev->wb.gpu_addr +
5642                                 reg_val_offs * 4));
5643 }
5644
5645 static void gfx_v11_0_ring_emit_wreg(struct amdgpu_ring *ring, uint32_t reg,
5646                                    uint32_t val)
5647 {
5648         uint32_t cmd = 0;
5649
5650         switch (ring->funcs->type) {
5651         case AMDGPU_RING_TYPE_GFX:
5652                 cmd = WRITE_DATA_ENGINE_SEL(1) | WR_CONFIRM;
5653                 break;
5654         case AMDGPU_RING_TYPE_KIQ:
5655                 cmd = (1 << 16); /* no inc addr */
5656                 break;
5657         default:
5658                 cmd = WR_CONFIRM;
5659                 break;
5660         }
5661         amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
5662         amdgpu_ring_write(ring, cmd);
5663         amdgpu_ring_write(ring, reg);
5664         amdgpu_ring_write(ring, 0);
5665         amdgpu_ring_write(ring, val);
5666 }
5667
5668 static void gfx_v11_0_ring_emit_reg_wait(struct amdgpu_ring *ring, uint32_t reg,
5669                                         uint32_t val, uint32_t mask)
5670 {
5671         gfx_v11_0_wait_reg_mem(ring, 0, 0, 0, reg, 0, val, mask, 0x20);
5672 }
5673
5674 static void gfx_v11_0_ring_emit_reg_write_reg_wait(struct amdgpu_ring *ring,
5675                                                    uint32_t reg0, uint32_t reg1,
5676                                                    uint32_t ref, uint32_t mask)
5677 {
5678         int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
5679
5680         gfx_v11_0_wait_reg_mem(ring, usepfp, 0, 1, reg0, reg1,
5681                                ref, mask, 0x20);
5682 }
5683
5684 static void gfx_v11_0_ring_soft_recovery(struct amdgpu_ring *ring,
5685                                          unsigned vmid)
5686 {
5687         struct amdgpu_device *adev = ring->adev;
5688         uint32_t value = 0;
5689
5690         value = REG_SET_FIELD(value, SQ_CMD, CMD, 0x03);
5691         value = REG_SET_FIELD(value, SQ_CMD, MODE, 0x01);
5692         value = REG_SET_FIELD(value, SQ_CMD, CHECK_VMID, 1);
5693         value = REG_SET_FIELD(value, SQ_CMD, VM_ID, vmid);
5694         WREG32_SOC15(GC, 0, regSQ_CMD, value);
5695 }
5696
5697 static void
5698 gfx_v11_0_set_gfx_eop_interrupt_state(struct amdgpu_device *adev,
5699                                       uint32_t me, uint32_t pipe,
5700                                       enum amdgpu_interrupt_state state)
5701 {
5702         uint32_t cp_int_cntl, cp_int_cntl_reg;
5703
5704         if (!me) {
5705                 switch (pipe) {
5706                 case 0:
5707                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING0);
5708                         break;
5709                 case 1:
5710                         cp_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_INT_CNTL_RING1);
5711                         break;
5712                 default:
5713                         DRM_DEBUG("invalid pipe %d\n", pipe);
5714                         return;
5715                 }
5716         } else {
5717                 DRM_DEBUG("invalid me %d\n", me);
5718                 return;
5719         }
5720
5721         switch (state) {
5722         case AMDGPU_IRQ_STATE_DISABLE:
5723                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
5724                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
5725                                             TIME_STAMP_INT_ENABLE, 0);
5726                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
5727                                             GENERIC0_INT_ENABLE, 0);
5728                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
5729                 break;
5730         case AMDGPU_IRQ_STATE_ENABLE:
5731                 cp_int_cntl = RREG32_SOC15_IP(GC, cp_int_cntl_reg);
5732                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
5733                                             TIME_STAMP_INT_ENABLE, 1);
5734                 cp_int_cntl = REG_SET_FIELD(cp_int_cntl, CP_INT_CNTL_RING0,
5735                                             GENERIC0_INT_ENABLE, 1);
5736                 WREG32_SOC15_IP(GC, cp_int_cntl_reg, cp_int_cntl);
5737                 break;
5738         default:
5739                 break;
5740         }
5741 }
5742
5743 static void gfx_v11_0_set_compute_eop_interrupt_state(struct amdgpu_device *adev,
5744                                                      int me, int pipe,
5745                                                      enum amdgpu_interrupt_state state)
5746 {
5747         u32 mec_int_cntl, mec_int_cntl_reg;
5748
5749         /*
5750          * amdgpu controls only the first MEC. That's why this function only
5751          * handles the setting of interrupts for this specific MEC. All other
5752          * pipes' interrupts are set by amdkfd.
5753          */
5754
5755         if (me == 1) {
5756                 switch (pipe) {
5757                 case 0:
5758                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
5759                         break;
5760                 case 1:
5761                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE1_INT_CNTL);
5762                         break;
5763                 case 2:
5764                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE2_INT_CNTL);
5765                         break;
5766                 case 3:
5767                         mec_int_cntl_reg = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE3_INT_CNTL);
5768                         break;
5769                 default:
5770                         DRM_DEBUG("invalid pipe %d\n", pipe);
5771                         return;
5772                 }
5773         } else {
5774                 DRM_DEBUG("invalid me %d\n", me);
5775                 return;
5776         }
5777
5778         switch (state) {
5779         case AMDGPU_IRQ_STATE_DISABLE:
5780                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
5781                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5782                                              TIME_STAMP_INT_ENABLE, 0);
5783                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5784                                              GENERIC0_INT_ENABLE, 0);
5785                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
5786                 break;
5787         case AMDGPU_IRQ_STATE_ENABLE:
5788                 mec_int_cntl = RREG32_SOC15_IP(GC, mec_int_cntl_reg);
5789                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5790                                              TIME_STAMP_INT_ENABLE, 1);
5791                 mec_int_cntl = REG_SET_FIELD(mec_int_cntl, CP_ME1_PIPE0_INT_CNTL,
5792                                              GENERIC0_INT_ENABLE, 1);
5793                 WREG32_SOC15_IP(GC, mec_int_cntl_reg, mec_int_cntl);
5794                 break;
5795         default:
5796                 break;
5797         }
5798 }
5799
5800 static int gfx_v11_0_set_eop_interrupt_state(struct amdgpu_device *adev,
5801                                             struct amdgpu_irq_src *src,
5802                                             unsigned type,
5803                                             enum amdgpu_interrupt_state state)
5804 {
5805         switch (type) {
5806         case AMDGPU_CP_IRQ_GFX_ME0_PIPE0_EOP:
5807                 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 0, state);
5808                 break;
5809         case AMDGPU_CP_IRQ_GFX_ME0_PIPE1_EOP:
5810                 gfx_v11_0_set_gfx_eop_interrupt_state(adev, 0, 1, state);
5811                 break;
5812         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP:
5813                 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 0, state);
5814                 break;
5815         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE1_EOP:
5816                 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 1, state);
5817                 break;
5818         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE2_EOP:
5819                 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 2, state);
5820                 break;
5821         case AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE3_EOP:
5822                 gfx_v11_0_set_compute_eop_interrupt_state(adev, 1, 3, state);
5823                 break;
5824         default:
5825                 break;
5826         }
5827         return 0;
5828 }
5829
5830 static int gfx_v11_0_eop_irq(struct amdgpu_device *adev,
5831                              struct amdgpu_irq_src *source,
5832                              struct amdgpu_iv_entry *entry)
5833 {
5834         int i;
5835         u8 me_id, pipe_id, queue_id;
5836         struct amdgpu_ring *ring;
5837         uint32_t mes_queue_id = entry->src_data[0];
5838
5839         DRM_DEBUG("IH: CP EOP\n");
5840
5841         if (adev->enable_mes && (mes_queue_id & AMDGPU_FENCE_MES_QUEUE_FLAG)) {
5842                 struct amdgpu_mes_queue *queue;
5843
5844                 mes_queue_id &= AMDGPU_FENCE_MES_QUEUE_ID_MASK;
5845
5846                 spin_lock(&adev->mes.queue_id_lock);
5847                 queue = idr_find(&adev->mes.queue_id_idr, mes_queue_id);
5848                 if (queue) {
5849                         DRM_DEBUG("process mes queue id = %d\n", mes_queue_id);
5850                         amdgpu_fence_process(queue->ring);
5851                 }
5852                 spin_unlock(&adev->mes.queue_id_lock);
5853         } else {
5854                 me_id = (entry->ring_id & 0x0c) >> 2;
5855                 pipe_id = (entry->ring_id & 0x03) >> 0;
5856                 queue_id = (entry->ring_id & 0x70) >> 4;
5857
5858                 switch (me_id) {
5859                 case 0:
5860                         if (pipe_id == 0)
5861                                 amdgpu_fence_process(&adev->gfx.gfx_ring[0]);
5862                         else
5863                                 amdgpu_fence_process(&adev->gfx.gfx_ring[1]);
5864                         break;
5865                 case 1:
5866                 case 2:
5867                         for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5868                                 ring = &adev->gfx.compute_ring[i];
5869                                 /* Per-queue interrupt is supported for MEC starting from VI.
5870                                  * The interrupt can only be enabled/disabled per pipe instead
5871                                  * of per queue.
5872                                  */
5873                                 if ((ring->me == me_id) &&
5874                                     (ring->pipe == pipe_id) &&
5875                                     (ring->queue == queue_id))
5876                                         amdgpu_fence_process(ring);
5877                         }
5878                         break;
5879                 }
5880         }
5881
5882         return 0;
5883 }
5884
5885 static int gfx_v11_0_set_priv_reg_fault_state(struct amdgpu_device *adev,
5886                                               struct amdgpu_irq_src *source,
5887                                               unsigned type,
5888                                               enum amdgpu_interrupt_state state)
5889 {
5890         switch (state) {
5891         case AMDGPU_IRQ_STATE_DISABLE:
5892         case AMDGPU_IRQ_STATE_ENABLE:
5893                 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0,
5894                                PRIV_REG_INT_ENABLE,
5895                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
5896                 break;
5897         default:
5898                 break;
5899         }
5900
5901         return 0;
5902 }
5903
5904 static int gfx_v11_0_set_priv_inst_fault_state(struct amdgpu_device *adev,
5905                                                struct amdgpu_irq_src *source,
5906                                                unsigned type,
5907                                                enum amdgpu_interrupt_state state)
5908 {
5909         switch (state) {
5910         case AMDGPU_IRQ_STATE_DISABLE:
5911         case AMDGPU_IRQ_STATE_ENABLE:
5912                 WREG32_FIELD15_PREREG(GC, 0, CP_INT_CNTL_RING0,
5913                                PRIV_INSTR_INT_ENABLE,
5914                                state == AMDGPU_IRQ_STATE_ENABLE ? 1 : 0);
5915                 break;
5916         default:
5917                 break;
5918         }
5919
5920         return 0;
5921 }
5922
5923 static void gfx_v11_0_handle_priv_fault(struct amdgpu_device *adev,
5924                                         struct amdgpu_iv_entry *entry)
5925 {
5926         u8 me_id, pipe_id, queue_id;
5927         struct amdgpu_ring *ring;
5928         int i;
5929
5930         me_id = (entry->ring_id & 0x0c) >> 2;
5931         pipe_id = (entry->ring_id & 0x03) >> 0;
5932         queue_id = (entry->ring_id & 0x70) >> 4;
5933
5934         switch (me_id) {
5935         case 0:
5936                 for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
5937                         ring = &adev->gfx.gfx_ring[i];
5938                         /* we only enabled 1 gfx queue per pipe for now */
5939                         if (ring->me == me_id && ring->pipe == pipe_id)
5940                                 drm_sched_fault(&ring->sched);
5941                 }
5942                 break;
5943         case 1:
5944         case 2:
5945                 for (i = 0; i < adev->gfx.num_compute_rings; i++) {
5946                         ring = &adev->gfx.compute_ring[i];
5947                         if (ring->me == me_id && ring->pipe == pipe_id &&
5948                             ring->queue == queue_id)
5949                                 drm_sched_fault(&ring->sched);
5950                 }
5951                 break;
5952         default:
5953                 BUG();
5954                 break;
5955         }
5956 }
5957
5958 static int gfx_v11_0_priv_reg_irq(struct amdgpu_device *adev,
5959                                   struct amdgpu_irq_src *source,
5960                                   struct amdgpu_iv_entry *entry)
5961 {
5962         DRM_ERROR("Illegal register access in command stream\n");
5963         gfx_v11_0_handle_priv_fault(adev, entry);
5964         return 0;
5965 }
5966
5967 static int gfx_v11_0_priv_inst_irq(struct amdgpu_device *adev,
5968                                    struct amdgpu_irq_src *source,
5969                                    struct amdgpu_iv_entry *entry)
5970 {
5971         DRM_ERROR("Illegal instruction in command stream\n");
5972         gfx_v11_0_handle_priv_fault(adev, entry);
5973         return 0;
5974 }
5975
5976 static int gfx_v11_0_rlc_gc_fed_irq(struct amdgpu_device *adev,
5977                                   struct amdgpu_irq_src *source,
5978                                   struct amdgpu_iv_entry *entry)
5979 {
5980         if (adev->gfx.ras && adev->gfx.ras->rlc_gc_fed_irq)
5981                 return adev->gfx.ras->rlc_gc_fed_irq(adev, source, entry);
5982
5983         return 0;
5984 }
5985
5986 #if 0
5987 static int gfx_v11_0_kiq_set_interrupt_state(struct amdgpu_device *adev,
5988                                              struct amdgpu_irq_src *src,
5989                                              unsigned int type,
5990                                              enum amdgpu_interrupt_state state)
5991 {
5992         uint32_t tmp, target;
5993         struct amdgpu_ring *ring = &(adev->gfx.kiq[0].ring);
5994
5995         target = SOC15_REG_OFFSET(GC, 0, regCP_ME1_PIPE0_INT_CNTL);
5996         target += ring->pipe;
5997
5998         switch (type) {
5999         case AMDGPU_CP_KIQ_IRQ_DRIVER0:
6000                 if (state == AMDGPU_IRQ_STATE_DISABLE) {
6001                         tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);
6002                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
6003                                             GENERIC2_INT_ENABLE, 0);
6004                         WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp);
6005
6006                         tmp = RREG32_SOC15_IP(GC, target);
6007                         tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL,
6008                                             GENERIC2_INT_ENABLE, 0);
6009                         WREG32_SOC15_IP(GC, target, tmp);
6010                 } else {
6011                         tmp = RREG32_SOC15(GC, 0, regCPC_INT_CNTL);
6012                         tmp = REG_SET_FIELD(tmp, CPC_INT_CNTL,
6013                                             GENERIC2_INT_ENABLE, 1);
6014                         WREG32_SOC15(GC, 0, regCPC_INT_CNTL, tmp);
6015
6016                         tmp = RREG32_SOC15_IP(GC, target);
6017                         tmp = REG_SET_FIELD(tmp, CP_ME1_PIPE0_INT_CNTL,
6018                                             GENERIC2_INT_ENABLE, 1);
6019                         WREG32_SOC15_IP(GC, target, tmp);
6020                 }
6021                 break;
6022         default:
6023                 BUG(); /* kiq only support GENERIC2_INT now */
6024                 break;
6025         }
6026         return 0;
6027 }
6028 #endif
6029
6030 static void gfx_v11_0_emit_mem_sync(struct amdgpu_ring *ring)
6031 {
6032         const unsigned int gcr_cntl =
6033                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_INV(1) |
6034                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL2_WB(1) |
6035                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_INV(1) |
6036                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLM_WB(1) |
6037                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GL1_INV(1) |
6038                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLV_INV(1) |
6039                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLK_INV(1) |
6040                         PACKET3_ACQUIRE_MEM_GCR_CNTL_GLI_INV(1);
6041
6042         /* ACQUIRE_MEM - make one or more surfaces valid for use by the subsequent operations */
6043         amdgpu_ring_write(ring, PACKET3(PACKET3_ACQUIRE_MEM, 6));
6044         amdgpu_ring_write(ring, 0); /* CP_COHER_CNTL */
6045         amdgpu_ring_write(ring, 0xffffffff);  /* CP_COHER_SIZE */
6046         amdgpu_ring_write(ring, 0xffffff);  /* CP_COHER_SIZE_HI */
6047         amdgpu_ring_write(ring, 0); /* CP_COHER_BASE */
6048         amdgpu_ring_write(ring, 0);  /* CP_COHER_BASE_HI */
6049         amdgpu_ring_write(ring, 0x0000000A); /* POLL_INTERVAL */
6050         amdgpu_ring_write(ring, gcr_cntl); /* GCR_CNTL */
6051 }
6052
6053 static const struct amd_ip_funcs gfx_v11_0_ip_funcs = {
6054         .name = "gfx_v11_0",
6055         .early_init = gfx_v11_0_early_init,
6056         .late_init = gfx_v11_0_late_init,
6057         .sw_init = gfx_v11_0_sw_init,
6058         .sw_fini = gfx_v11_0_sw_fini,
6059         .hw_init = gfx_v11_0_hw_init,
6060         .hw_fini = gfx_v11_0_hw_fini,
6061         .suspend = gfx_v11_0_suspend,
6062         .resume = gfx_v11_0_resume,
6063         .is_idle = gfx_v11_0_is_idle,
6064         .wait_for_idle = gfx_v11_0_wait_for_idle,
6065         .soft_reset = gfx_v11_0_soft_reset,
6066         .check_soft_reset = gfx_v11_0_check_soft_reset,
6067         .post_soft_reset = gfx_v11_0_post_soft_reset,
6068         .set_clockgating_state = gfx_v11_0_set_clockgating_state,
6069         .set_powergating_state = gfx_v11_0_set_powergating_state,
6070         .get_clockgating_state = gfx_v11_0_get_clockgating_state,
6071 };
6072
6073 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_gfx = {
6074         .type = AMDGPU_RING_TYPE_GFX,
6075         .align_mask = 0xff,
6076         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6077         .support_64bit_ptrs = true,
6078         .secure_submission_supported = true,
6079         .get_rptr = gfx_v11_0_ring_get_rptr_gfx,
6080         .get_wptr = gfx_v11_0_ring_get_wptr_gfx,
6081         .set_wptr = gfx_v11_0_ring_set_wptr_gfx,
6082         .emit_frame_size = /* totally 242 maximum if 16 IBs */
6083                 5 + /* COND_EXEC */
6084                 9 + /* SET_Q_PREEMPTION_MODE */
6085                 7 + /* PIPELINE_SYNC */
6086                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
6087                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6088                 2 + /* VM_FLUSH */
6089                 8 + /* FENCE for VM_FLUSH */
6090                 20 + /* GDS switch */
6091                 5 + /* COND_EXEC */
6092                 7 + /* HDP_flush */
6093                 4 + /* VGT_flush */
6094                 31 + /* DE_META */
6095                 3 + /* CNTX_CTRL */
6096                 5 + /* HDP_INVL */
6097                 8 + 8 + /* FENCE x2 */
6098                 8, /* gfx_v11_0_emit_mem_sync */
6099         .emit_ib_size = 4, /* gfx_v11_0_ring_emit_ib_gfx */
6100         .emit_ib = gfx_v11_0_ring_emit_ib_gfx,
6101         .emit_fence = gfx_v11_0_ring_emit_fence,
6102         .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync,
6103         .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush,
6104         .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch,
6105         .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush,
6106         .test_ring = gfx_v11_0_ring_test_ring,
6107         .test_ib = gfx_v11_0_ring_test_ib,
6108         .insert_nop = amdgpu_ring_insert_nop,
6109         .pad_ib = amdgpu_ring_generic_pad_ib,
6110         .emit_cntxcntl = gfx_v11_0_ring_emit_cntxcntl,
6111         .emit_gfx_shadow = gfx_v11_0_ring_emit_gfx_shadow,
6112         .init_cond_exec = gfx_v11_0_ring_emit_init_cond_exec,
6113         .patch_cond_exec = gfx_v11_0_ring_emit_patch_cond_exec,
6114         .preempt_ib = gfx_v11_0_ring_preempt_ib,
6115         .emit_frame_cntl = gfx_v11_0_ring_emit_frame_cntl,
6116         .emit_wreg = gfx_v11_0_ring_emit_wreg,
6117         .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait,
6118         .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait,
6119         .soft_recovery = gfx_v11_0_ring_soft_recovery,
6120         .emit_mem_sync = gfx_v11_0_emit_mem_sync,
6121 };
6122
6123 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_compute = {
6124         .type = AMDGPU_RING_TYPE_COMPUTE,
6125         .align_mask = 0xff,
6126         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6127         .support_64bit_ptrs = true,
6128         .get_rptr = gfx_v11_0_ring_get_rptr_compute,
6129         .get_wptr = gfx_v11_0_ring_get_wptr_compute,
6130         .set_wptr = gfx_v11_0_ring_set_wptr_compute,
6131         .emit_frame_size =
6132                 20 + /* gfx_v11_0_ring_emit_gds_switch */
6133                 7 + /* gfx_v11_0_ring_emit_hdp_flush */
6134                 5 + /* hdp invalidate */
6135                 7 + /* gfx_v11_0_ring_emit_pipeline_sync */
6136                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
6137                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6138                 2 + /* gfx_v11_0_ring_emit_vm_flush */
6139                 8 + 8 + 8 + /* gfx_v11_0_ring_emit_fence x3 for user fence, vm fence */
6140                 8, /* gfx_v11_0_emit_mem_sync */
6141         .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */
6142         .emit_ib = gfx_v11_0_ring_emit_ib_compute,
6143         .emit_fence = gfx_v11_0_ring_emit_fence,
6144         .emit_pipeline_sync = gfx_v11_0_ring_emit_pipeline_sync,
6145         .emit_vm_flush = gfx_v11_0_ring_emit_vm_flush,
6146         .emit_gds_switch = gfx_v11_0_ring_emit_gds_switch,
6147         .emit_hdp_flush = gfx_v11_0_ring_emit_hdp_flush,
6148         .test_ring = gfx_v11_0_ring_test_ring,
6149         .test_ib = gfx_v11_0_ring_test_ib,
6150         .insert_nop = amdgpu_ring_insert_nop,
6151         .pad_ib = amdgpu_ring_generic_pad_ib,
6152         .emit_wreg = gfx_v11_0_ring_emit_wreg,
6153         .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait,
6154         .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait,
6155         .emit_mem_sync = gfx_v11_0_emit_mem_sync,
6156 };
6157
6158 static const struct amdgpu_ring_funcs gfx_v11_0_ring_funcs_kiq = {
6159         .type = AMDGPU_RING_TYPE_KIQ,
6160         .align_mask = 0xff,
6161         .nop = PACKET3(PACKET3_NOP, 0x3FFF),
6162         .support_64bit_ptrs = true,
6163         .get_rptr = gfx_v11_0_ring_get_rptr_compute,
6164         .get_wptr = gfx_v11_0_ring_get_wptr_compute,
6165         .set_wptr = gfx_v11_0_ring_set_wptr_compute,
6166         .emit_frame_size =
6167                 20 + /* gfx_v11_0_ring_emit_gds_switch */
6168                 7 + /* gfx_v11_0_ring_emit_hdp_flush */
6169                 5 + /*hdp invalidate */
6170                 7 + /* gfx_v11_0_ring_emit_pipeline_sync */
6171                 SOC15_FLUSH_GPU_TLB_NUM_WREG * 5 +
6172                 SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT * 7 +
6173                 2 + /* gfx_v11_0_ring_emit_vm_flush */
6174                 8 + 8 + 8, /* gfx_v11_0_ring_emit_fence_kiq x3 for user fence, vm fence */
6175         .emit_ib_size = 7, /* gfx_v11_0_ring_emit_ib_compute */
6176         .emit_ib = gfx_v11_0_ring_emit_ib_compute,
6177         .emit_fence = gfx_v11_0_ring_emit_fence_kiq,
6178         .test_ring = gfx_v11_0_ring_test_ring,
6179         .test_ib = gfx_v11_0_ring_test_ib,
6180         .insert_nop = amdgpu_ring_insert_nop,
6181         .pad_ib = amdgpu_ring_generic_pad_ib,
6182         .emit_rreg = gfx_v11_0_ring_emit_rreg,
6183         .emit_wreg = gfx_v11_0_ring_emit_wreg,
6184         .emit_reg_wait = gfx_v11_0_ring_emit_reg_wait,
6185         .emit_reg_write_reg_wait = gfx_v11_0_ring_emit_reg_write_reg_wait,
6186 };
6187
6188 static void gfx_v11_0_set_ring_funcs(struct amdgpu_device *adev)
6189 {
6190         int i;
6191
6192         adev->gfx.kiq[0].ring.funcs = &gfx_v11_0_ring_funcs_kiq;
6193
6194         for (i = 0; i < adev->gfx.num_gfx_rings; i++)
6195                 adev->gfx.gfx_ring[i].funcs = &gfx_v11_0_ring_funcs_gfx;
6196
6197         for (i = 0; i < adev->gfx.num_compute_rings; i++)
6198                 adev->gfx.compute_ring[i].funcs = &gfx_v11_0_ring_funcs_compute;
6199 }
6200
6201 static const struct amdgpu_irq_src_funcs gfx_v11_0_eop_irq_funcs = {
6202         .set = gfx_v11_0_set_eop_interrupt_state,
6203         .process = gfx_v11_0_eop_irq,
6204 };
6205
6206 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_reg_irq_funcs = {
6207         .set = gfx_v11_0_set_priv_reg_fault_state,
6208         .process = gfx_v11_0_priv_reg_irq,
6209 };
6210
6211 static const struct amdgpu_irq_src_funcs gfx_v11_0_priv_inst_irq_funcs = {
6212         .set = gfx_v11_0_set_priv_inst_fault_state,
6213         .process = gfx_v11_0_priv_inst_irq,
6214 };
6215
6216 static const struct amdgpu_irq_src_funcs gfx_v11_0_rlc_gc_fed_irq_funcs = {
6217         .process = gfx_v11_0_rlc_gc_fed_irq,
6218 };
6219
6220 static void gfx_v11_0_set_irq_funcs(struct amdgpu_device *adev)
6221 {
6222         adev->gfx.eop_irq.num_types = AMDGPU_CP_IRQ_LAST;
6223         adev->gfx.eop_irq.funcs = &gfx_v11_0_eop_irq_funcs;
6224
6225         adev->gfx.priv_reg_irq.num_types = 1;
6226         adev->gfx.priv_reg_irq.funcs = &gfx_v11_0_priv_reg_irq_funcs;
6227
6228         adev->gfx.priv_inst_irq.num_types = 1;
6229         adev->gfx.priv_inst_irq.funcs = &gfx_v11_0_priv_inst_irq_funcs;
6230
6231         adev->gfx.rlc_gc_fed_irq.num_types = 1; /* 0x80 FED error */
6232         adev->gfx.rlc_gc_fed_irq.funcs = &gfx_v11_0_rlc_gc_fed_irq_funcs;
6233
6234 }
6235
6236 static void gfx_v11_0_set_imu_funcs(struct amdgpu_device *adev)
6237 {
6238         if (adev->flags & AMD_IS_APU)
6239                 adev->gfx.imu.mode = MISSION_MODE;
6240         else
6241                 adev->gfx.imu.mode = DEBUG_MODE;
6242
6243         adev->gfx.imu.funcs = &gfx_v11_0_imu_funcs;
6244 }
6245
6246 static void gfx_v11_0_set_rlc_funcs(struct amdgpu_device *adev)
6247 {
6248         adev->gfx.rlc.funcs = &gfx_v11_0_rlc_funcs;
6249 }
6250
6251 static void gfx_v11_0_set_gds_init(struct amdgpu_device *adev)
6252 {
6253         unsigned total_cu = adev->gfx.config.max_cu_per_sh *
6254                             adev->gfx.config.max_sh_per_se *
6255                             adev->gfx.config.max_shader_engines;
6256
6257         adev->gds.gds_size = 0x1000;
6258         adev->gds.gds_compute_max_wave_id = total_cu * 32 - 1;
6259         adev->gds.gws_size = 64;
6260         adev->gds.oa_size = 16;
6261 }
6262
6263 static void gfx_v11_0_set_mqd_funcs(struct amdgpu_device *adev)
6264 {
6265         /* set gfx eng mqd */
6266         adev->mqds[AMDGPU_HW_IP_GFX].mqd_size =
6267                 sizeof(struct v11_gfx_mqd);
6268         adev->mqds[AMDGPU_HW_IP_GFX].init_mqd =
6269                 gfx_v11_0_gfx_mqd_init;
6270         /* set compute eng mqd */
6271         adev->mqds[AMDGPU_HW_IP_COMPUTE].mqd_size =
6272                 sizeof(struct v11_compute_mqd);
6273         adev->mqds[AMDGPU_HW_IP_COMPUTE].init_mqd =
6274                 gfx_v11_0_compute_mqd_init;
6275 }
6276
6277 static void gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(struct amdgpu_device *adev,
6278                                                           u32 bitmap)
6279 {
6280         u32 data;
6281
6282         if (!bitmap)
6283                 return;
6284
6285         data = bitmap << GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
6286         data &= GC_USER_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
6287
6288         WREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG, data);
6289 }
6290
6291 static u32 gfx_v11_0_get_wgp_active_bitmap_per_sh(struct amdgpu_device *adev)
6292 {
6293         u32 data, wgp_bitmask;
6294         data = RREG32_SOC15(GC, 0, regCC_GC_SHADER_ARRAY_CONFIG);
6295         data |= RREG32_SOC15(GC, 0, regGC_USER_SHADER_ARRAY_CONFIG);
6296
6297         data &= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS_MASK;
6298         data >>= CC_GC_SHADER_ARRAY_CONFIG__INACTIVE_WGPS__SHIFT;
6299
6300         wgp_bitmask =
6301                 amdgpu_gfx_create_bitmask(adev->gfx.config.max_cu_per_sh >> 1);
6302
6303         return (~data) & wgp_bitmask;
6304 }
6305
6306 static u32 gfx_v11_0_get_cu_active_bitmap_per_sh(struct amdgpu_device *adev)
6307 {
6308         u32 wgp_idx, wgp_active_bitmap;
6309         u32 cu_bitmap_per_wgp, cu_active_bitmap;
6310
6311         wgp_active_bitmap = gfx_v11_0_get_wgp_active_bitmap_per_sh(adev);
6312         cu_active_bitmap = 0;
6313
6314         for (wgp_idx = 0; wgp_idx < 16; wgp_idx++) {
6315                 /* if there is one WGP enabled, it means 2 CUs will be enabled */
6316                 cu_bitmap_per_wgp = 3 << (2 * wgp_idx);
6317                 if (wgp_active_bitmap & (1 << wgp_idx))
6318                         cu_active_bitmap |= cu_bitmap_per_wgp;
6319         }
6320
6321         return cu_active_bitmap;
6322 }
6323
6324 static int gfx_v11_0_get_cu_info(struct amdgpu_device *adev,
6325                                  struct amdgpu_cu_info *cu_info)
6326 {
6327         int i, j, k, counter, active_cu_number = 0;
6328         u32 mask, bitmap;
6329         unsigned disable_masks[8 * 2];
6330
6331         if (!adev || !cu_info)
6332                 return -EINVAL;
6333
6334         amdgpu_gfx_parse_disable_cu(disable_masks, 8, 2);
6335
6336         mutex_lock(&adev->grbm_idx_mutex);
6337         for (i = 0; i < adev->gfx.config.max_shader_engines; i++) {
6338                 for (j = 0; j < adev->gfx.config.max_sh_per_se; j++) {
6339                         mask = 1;
6340                         counter = 0;
6341                         gfx_v11_0_select_se_sh(adev, i, j, 0xffffffff, 0);
6342                         if (i < 8 && j < 2)
6343                                 gfx_v11_0_set_user_wgp_inactive_bitmap_per_sh(
6344                                         adev, disable_masks[i * 2 + j]);
6345                         bitmap = gfx_v11_0_get_cu_active_bitmap_per_sh(adev);
6346
6347                         /**
6348                          * GFX11 could support more than 4 SEs, while the bitmap
6349                          * in cu_info struct is 4x4 and ioctl interface struct
6350                          * drm_amdgpu_info_device should keep stable.
6351                          * So we use last two columns of bitmap to store cu mask for
6352                          * SEs 4 to 7, the layout of the bitmap is as below:
6353                          *    SE0: {SH0,SH1} --> {bitmap[0][0], bitmap[0][1]}
6354                          *    SE1: {SH0,SH1} --> {bitmap[1][0], bitmap[1][1]}
6355                          *    SE2: {SH0,SH1} --> {bitmap[2][0], bitmap[2][1]}
6356                          *    SE3: {SH0,SH1} --> {bitmap[3][0], bitmap[3][1]}
6357                          *    SE4: {SH0,SH1} --> {bitmap[0][2], bitmap[0][3]}
6358                          *    SE5: {SH0,SH1} --> {bitmap[1][2], bitmap[1][3]}
6359                          *    SE6: {SH0,SH1} --> {bitmap[2][2], bitmap[2][3]}
6360                          *    SE7: {SH0,SH1} --> {bitmap[3][2], bitmap[3][3]}
6361                          */
6362                         cu_info->bitmap[0][i % 4][j + (i / 4) * 2] = bitmap;
6363
6364                         for (k = 0; k < adev->gfx.config.max_cu_per_sh; k++) {
6365                                 if (bitmap & mask)
6366                                         counter++;
6367
6368                                 mask <<= 1;
6369                         }
6370                         active_cu_number += counter;
6371                 }
6372         }
6373         gfx_v11_0_select_se_sh(adev, 0xffffffff, 0xffffffff, 0xffffffff, 0);
6374         mutex_unlock(&adev->grbm_idx_mutex);
6375
6376         cu_info->number = active_cu_number;
6377         cu_info->simd_per_cu = NUM_SIMD_PER_CU;
6378
6379         return 0;
6380 }
6381
6382 const struct amdgpu_ip_block_version gfx_v11_0_ip_block =
6383 {
6384         .type = AMD_IP_BLOCK_TYPE_GFX,
6385         .major = 11,
6386         .minor = 0,
6387         .rev = 0,
6388         .funcs = &gfx_v11_0_ip_funcs,
6389 };