drivers/net/cpmac.c

   1 /*
   2  * Copyright (C) 2006, 2007 Eugene Konev
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with this program; if not, write to the Free Software
  16  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
  17  */
  18
  19 #include <linux/module.h>
  20 #include <linux/init.h>
  21 #include <linux/moduleparam.h>
  22
  23 #include <linux/sched.h>
  24 #include <linux/kernel.h>
  25 #include <linux/slab.h>
  26 #include <linux/errno.h>
  27 #include <linux/types.h>
  28 #include <linux/delay.h>
  29
  30 #include <linux/netdevice.h>
  31 #include <linux/etherdevice.h>
  32 #include <linux/ethtool.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/mii.h>
  35 #include <linux/phy.h>
  36 #include <linux/phy_fixed.h>
  37 #include <linux/platform_device.h>
  38 #include <linux/dma-mapping.h>
  39 #include <asm/gpio.h>
  40 #include <asm/atomic.h>
  41
  42 MODULE_AUTHOR("Eugene Konev <[email protected]>");
  43 MODULE_DESCRIPTION("TI AR7 ethernet driver (CPMAC)");
  44 MODULE_LICENSE("GPL");
  45 MODULE_ALIAS("platform:cpmac");
  46
  47 static int debug_level = 8;
  48 static int dumb_switch;
  49
  50 /* Next 2 are only used in cpmac_probe, so it's pointless to change them */
  51 module_param(debug_level, int, 0444);
  52 module_param(dumb_switch, int, 0444);
  53
  54 MODULE_PARM_DESC(debug_level, "Number of NETIF_MSG bits to enable");
  55 MODULE_PARM_DESC(dumb_switch, "Assume switch is not connected to MDIO bus");
  56
  57 #define CPMAC_VERSION "0.5.1"
  58 /* frame size + 802.1q tag */
  59 #define CPMAC_SKB_SIZE          (ETH_FRAME_LEN + 4)
  60 #define CPMAC_QUEUES    8
  61
  62 /* Ethernet registers */
  63 #define CPMAC_TX_CONTROL                0x0004
  64 #define CPMAC_TX_TEARDOWN               0x0008
  65 #define CPMAC_RX_CONTROL                0x0014
  66 #define CPMAC_RX_TEARDOWN               0x0018
  67 #define CPMAC_MBP                       0x0100
  68 # define MBP_RXPASSCRC                  0x40000000
  69 # define MBP_RXQOS                      0x20000000
  70 # define MBP_RXNOCHAIN                  0x10000000
  71 # define MBP_RXCMF                      0x01000000
  72 # define MBP_RXSHORT                    0x00800000
  73 # define MBP_RXCEF                      0x00400000
  74 # define MBP_RXPROMISC                  0x00200000
  75 # define MBP_PROMISCCHAN(channel)       (((channel) & 0x7) << 16)
  76 # define MBP_RXBCAST                    0x00002000
  77 # define MBP_BCASTCHAN(channel)         (((channel) & 0x7) << 8)
  78 # define MBP_RXMCAST                    0x00000020
  79 # define MBP_MCASTCHAN(channel)         ((channel) & 0x7)
  80 #define CPMAC_UNICAST_ENABLE            0x0104
  81 #define CPMAC_UNICAST_CLEAR             0x0108
  82 #define CPMAC_MAX_LENGTH                0x010c
  83 #define CPMAC_BUFFER_OFFSET             0x0110
  84 #define CPMAC_MAC_CONTROL               0x0160
  85 # define MAC_TXPTYPE                    0x00000200
  86 # define MAC_TXPACE                     0x00000040
  87 # define MAC_MII                        0x00000020
  88 # define MAC_TXFLOW                     0x00000010
  89 # define MAC_RXFLOW                     0x00000008
  90 # define MAC_MTEST                      0x00000004
  91 # define MAC_LOOPBACK                   0x00000002
  92 # define MAC_FDX                        0x00000001
  93 #define CPMAC_MAC_STATUS                0x0164
  94 # define MAC_STATUS_QOS                 0x00000004
  95 # define MAC_STATUS_RXFLOW              0x00000002
  96 # define MAC_STATUS_TXFLOW              0x00000001
  97 #define CPMAC_TX_INT_ENABLE             0x0178
  98 #define CPMAC_TX_INT_CLEAR              0x017c
  99 #define CPMAC_MAC_INT_VECTOR            0x0180
 100 # define MAC_INT_STATUS                 0x00080000
 101 # define MAC_INT_HOST                   0x00040000
 102 # define MAC_INT_RX                     0x00020000
 103 # define MAC_INT_TX                     0x00010000
 104 #define CPMAC_MAC_EOI_VECTOR            0x0184
 105 #define CPMAC_RX_INT_ENABLE             0x0198
 106 #define CPMAC_RX_INT_CLEAR              0x019c
 107 #define CPMAC_MAC_INT_ENABLE            0x01a8
 108 #define CPMAC_MAC_INT_CLEAR             0x01ac
 109 #define CPMAC_MAC_ADDR_LO(channel)      (0x01b0 + (channel) * 4)
 110 #define CPMAC_MAC_ADDR_MID              0x01d0
 111 #define CPMAC_MAC_ADDR_HI               0x01d4
 112 #define CPMAC_MAC_HASH_LO               0x01d8
 113 #define CPMAC_MAC_HASH_HI               0x01dc
 114 #define CPMAC_TX_PTR(channel)           (0x0600 + (channel) * 4)
 115 #define CPMAC_RX_PTR(channel)           (0x0620 + (channel) * 4)
 116 #define CPMAC_TX_ACK(channel)           (0x0640 + (channel) * 4)
 117 #define CPMAC_RX_ACK(channel)           (0x0660 + (channel) * 4)
 118 #define CPMAC_REG_END                   0x0680
 119 /*
 120  * Rx/Tx statistics
 121  * TODO: use some of them to fill stats in cpmac_stats()
 122  */
 123 #define CPMAC_STATS_RX_GOOD             0x0200
 124 #define CPMAC_STATS_RX_BCAST            0x0204
 125 #define CPMAC_STATS_RX_MCAST            0x0208
 126 #define CPMAC_STATS_RX_PAUSE            0x020c
 127 #define CPMAC_STATS_RX_CRC              0x0210
 128 #define CPMAC_STATS_RX_ALIGN            0x0214
 129 #define CPMAC_STATS_RX_OVER             0x0218
 130 #define CPMAC_STATS_RX_JABBER           0x021c
 131 #define CPMAC_STATS_RX_UNDER            0x0220
 132 #define CPMAC_STATS_RX_FRAG             0x0224
 133 #define CPMAC_STATS_RX_FILTER           0x0228
 134 #define CPMAC_STATS_RX_QOSFILTER        0x022c
 135 #define CPMAC_STATS_RX_OCTETS           0x0230
 136
 137 #define CPMAC_STATS_TX_GOOD             0x0234
 138 #define CPMAC_STATS_TX_BCAST            0x0238
 139 #define CPMAC_STATS_TX_MCAST            0x023c
 140 #define CPMAC_STATS_TX_PAUSE            0x0240
 141 #define CPMAC_STATS_TX_DEFER            0x0244
 142 #define CPMAC_STATS_TX_COLLISION        0x0248
 143 #define CPMAC_STATS_TX_SINGLECOLL       0x024c
 144 #define CPMAC_STATS_TX_MULTICOLL        0x0250
 145 #define CPMAC_STATS_TX_EXCESSCOLL       0x0254
 146 #define CPMAC_STATS_TX_LATECOLL         0x0258
 147 #define CPMAC_STATS_TX_UNDERRUN         0x025c
 148 #define CPMAC_STATS_TX_CARRIERSENSE     0x0260
 149 #define CPMAC_STATS_TX_OCTETS           0x0264
 150
 151 #define cpmac_read(base, reg)           (readl((void __iomem *)(base) + (reg)))
 152 #define cpmac_write(base, reg, val)     (writel(val, (void __iomem *)(base) + \
 153                                                 (reg)))
 154
 155 /* MDIO bus */
 156 #define CPMAC_MDIO_VERSION              0x0000
 157 #define CPMAC_MDIO_CONTROL              0x0004
 158 # define MDIOC_IDLE                     0x80000000
 159 # define MDIOC_ENABLE                   0x40000000
 160 # define MDIOC_PREAMBLE                 0x00100000
 161 # define MDIOC_FAULT                    0x00080000
 162 # define MDIOC_FAULTDETECT              0x00040000
 163 # define MDIOC_INTTEST                  0x00020000
 164 # define MDIOC_CLKDIV(div)              ((div) & 0xff)
 165 #define CPMAC_MDIO_ALIVE                0x0008
 166 #define CPMAC_MDIO_LINK                 0x000c
 167 #define CPMAC_MDIO_ACCESS(channel)      (0x0080 + (channel) * 8)
 168 # define MDIO_BUSY                      0x80000000
 169 # define MDIO_WRITE                     0x40000000
 170 # define MDIO_REG(reg)                  (((reg) & 0x1f) << 21)
 171 # define MDIO_PHY(phy)                  (((phy) & 0x1f) << 16)
 172 # define MDIO_DATA(data)                ((data) & 0xffff)
 173 #define CPMAC_MDIO_PHYSEL(channel)      (0x0084 + (channel) * 8)
 174 # define PHYSEL_LINKSEL                 0x00000040
 175 # define PHYSEL_LINKINT                 0x00000020
 176
 177 struct cpmac_desc {
 178         u32 hw_next;
 179         u32 hw_data;
 180         u16 buflen;
 181         u16 bufflags;
 182         u16 datalen;
 183         u16 dataflags;
 184 #define CPMAC_SOP                       0x8000
 185 #define CPMAC_EOP                       0x4000
 186 #define CPMAC_OWN                       0x2000
 187 #define CPMAC_EOQ                       0x1000
 188         struct sk_buff *skb;
 189         struct cpmac_desc *next;
 190         struct cpmac_desc *prev;
 191         dma_addr_t mapping;
 192         dma_addr_t data_mapping;
 193 };
 194
 195 struct cpmac_priv {
 196         spinlock_t lock;
 197         spinlock_t rx_lock;
 198         struct cpmac_desc *rx_head;
 199         int ring_size;
 200         struct cpmac_desc *desc_ring;
 201         dma_addr_t dma_ring;
 202         void __iomem *regs;
 203         struct mii_bus *mii_bus;
 204         struct phy_device *phy;
 205         char phy_name[MII_BUS_ID_SIZE + 3];
 206         int oldlink, oldspeed, oldduplex;
 207         u32 msg_enable;
 208         struct net_device *dev;
 209         struct work_struct reset_work;
 210         struct platform_device *pdev;
 211         struct napi_struct napi;
 212         atomic_t reset_pending;
 213 };
 214
 215 static irqreturn_t cpmac_irq(int, void *);
 216 static void cpmac_hw_start(struct net_device *dev);
 217 static void cpmac_hw_stop(struct net_device *dev);
 218 static int cpmac_stop(struct net_device *dev);
 219 static int cpmac_open(struct net_device *dev);
 220
 221 static void cpmac_dump_regs(struct net_device *dev)
 222 {
 223         int i;
 224         struct cpmac_priv *priv = netdev_priv(dev);
 225         for (i = 0; i < CPMAC_REG_END; i += 4) {
 226                 if (i % 16 == 0) {
 227                         if (i)
 228                                 printk("\n");
 229                         printk(KERN_DEBUG "%s: reg[%p]:", dev->name,
 230                                priv->regs + i);
 231                 }
 232                 printk(" %08x", cpmac_read(priv->regs, i));
 233         }
 234         printk("\n");
 235 }
 236
 237 static void cpmac_dump_desc(struct net_device *dev, struct cpmac_desc *desc)
 238 {
 239         int i;
 240         printk(KERN_DEBUG "%s: desc[%p]:", dev->name, desc);
 241         for (i = 0; i < sizeof(*desc) / 4; i++)
 242                 printk(" %08x", ((u32 *)desc)[i]);
 243         printk("\n");
 244 }
 245
 246 static void cpmac_dump_all_desc(struct net_device *dev)
 247 {
 248         struct cpmac_priv *priv = netdev_priv(dev);
 249         struct cpmac_desc *dump = priv->rx_head;
 250         do {
 251                 cpmac_dump_desc(dev, dump);
 252                 dump = dump->next;
 253         } while (dump != priv->rx_head);
 254 }
 255
 256 static void cpmac_dump_skb(struct net_device *dev, struct sk_buff *skb)
 257 {
 258         int i;
 259         printk(KERN_DEBUG "%s: skb 0x%p, len=%d\n", dev->name, skb, skb->len);
 260         for (i = 0; i < skb->len; i++) {
 261                 if (i % 16 == 0) {
 262                         if (i)
 263                                 printk("\n");
 264                         printk(KERN_DEBUG "%s: data[%p]:", dev->name,
 265                                skb->data + i);
 266                 }
 267                 printk(" %02x", ((u8 *)skb->data)[i]);
 268         }
 269         printk("\n");
 270 }
 271
 272 static int cpmac_mdio_read(struct mii_bus *bus, int phy_id, int reg)
 273 {
 274         u32 val;
 275
 276         while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
 277                 cpu_relax();
 278         cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_REG(reg) |
 279                     MDIO_PHY(phy_id));
 280         while ((val = cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0))) & MDIO_BUSY)
 281                 cpu_relax();
 282         return MDIO_DATA(val);
 283 }
 284
 285 static int cpmac_mdio_write(struct mii_bus *bus, int phy_id,
 286                             int reg, u16 val)
 287 {
 288         while (cpmac_read(bus->priv, CPMAC_MDIO_ACCESS(0)) & MDIO_BUSY)
 289                 cpu_relax();
 290         cpmac_write(bus->priv, CPMAC_MDIO_ACCESS(0), MDIO_BUSY | MDIO_WRITE |
 291                     MDIO_REG(reg) | MDIO_PHY(phy_id) | MDIO_DATA(val));
 292         return 0;
 293 }
 294
 295 static int cpmac_mdio_reset(struct mii_bus *bus)
 296 {
 297         ar7_device_reset(AR7_RESET_BIT_MDIO);
 298         cpmac_write(bus->priv, CPMAC_MDIO_CONTROL, MDIOC_ENABLE |
 299                     MDIOC_CLKDIV(ar7_cpmac_freq() / 2200000 - 1));
 300         return 0;
 301 }
 302
 303 static int mii_irqs[PHY_MAX_ADDR] = { PHY_POLL, };
 304
 305 static struct mii_bus *cpmac_mii;
 306
 307 static int cpmac_config(struct net_device *dev, struct ifmap *map)
 308 {
 309         if (dev->flags & IFF_UP)
 310                 return -EBUSY;
 311
 312         /* Don't allow changing the I/O address */
 313         if (map->base_addr != dev->base_addr)
 314                 return -EOPNOTSUPP;
 315
 316         /* ignore other fields */
 317         return 0;
 318 }
 319
 320 static void cpmac_set_multicast_list(struct net_device *dev)
 321 {
 322         struct dev_mc_list *iter;
 323         u8 tmp;
 324         u32 mbp, bit, hash[2] = { 0, };
 325         struct cpmac_priv *priv = netdev_priv(dev);
 326
 327         mbp = cpmac_read(priv->regs, CPMAC_MBP);
 328         if (dev->flags & IFF_PROMISC) {
 329                 cpmac_write(priv->regs, CPMAC_MBP, (mbp & ~MBP_PROMISCCHAN(0)) |
 330                             MBP_RXPROMISC);
 331         } else {
 332                 cpmac_write(priv->regs, CPMAC_MBP, mbp & ~MBP_RXPROMISC);
 333                 if (dev->flags & IFF_ALLMULTI) {
 334                         /* enable all multicast mode */
 335                         cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, 0xffffffff);
 336                         cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, 0xffffffff);
 337                 } else {
 338                         /*
 339                          * cpmac uses some strange mac address hashing
 340                          * (not crc32)
 341                          */
 342                         netdev_for_each_mc_addr(iter, dev) {
 343                                 bit = 0;
 344                                 tmp = iter->dmi_addr[0];
 345                                 bit  ^= (tmp >> 2) ^ (tmp << 4);
 346                                 tmp = iter->dmi_addr[1];
 347                                 bit  ^= (tmp >> 4) ^ (tmp << 2);
 348                                 tmp = iter->dmi_addr[2];
 349                                 bit  ^= (tmp >> 6) ^ tmp;
 350                                 tmp = iter->dmi_addr[3];
 351                                 bit  ^= (tmp >> 2) ^ (tmp << 4);
 352                                 tmp = iter->dmi_addr[4];
 353                                 bit  ^= (tmp >> 4) ^ (tmp << 2);
 354                                 tmp = iter->dmi_addr[5];
 355                                 bit  ^= (tmp >> 6) ^ tmp;
 356                                 bit &= 0x3f;
 357                                 hash[bit / 32] |= 1 << (bit % 32);
 358                         }
 359
 360                         cpmac_write(priv->regs, CPMAC_MAC_HASH_LO, hash[0]);
 361                         cpmac_write(priv->regs, CPMAC_MAC_HASH_HI, hash[1]);
 362                 }
 363         }
 364 }
 365
 366 static struct sk_buff *cpmac_rx_one(struct cpmac_priv *priv,
 367                                     struct cpmac_desc *desc)
 368 {
 369         struct sk_buff *skb, *result = NULL;
 370
 371         if (unlikely(netif_msg_hw(priv)))
 372                 cpmac_dump_desc(priv->dev, desc);
 373         cpmac_write(priv->regs, CPMAC_RX_ACK(0), (u32)desc->mapping);
 374         if (unlikely(!desc->datalen)) {
 375                 if (netif_msg_rx_err(priv) && net_ratelimit())
 376                         printk(KERN_WARNING "%s: rx: spurious interrupt\n",
 377                                priv->dev->name);
 378                 return NULL;
 379         }
 380
 381         skb = netdev_alloc_skb_ip_align(priv->dev, CPMAC_SKB_SIZE);
 382         if (likely(skb)) {
 383                 skb_put(desc->skb, desc->datalen);
 384                 desc->skb->protocol = eth_type_trans(desc->skb, priv->dev);
 385                 desc->skb->ip_summed = CHECKSUM_NONE;
 386                 priv->dev->stats.rx_packets++;
 387                 priv->dev->stats.rx_bytes += desc->datalen;
 388                 result = desc->skb;
 389                 dma_unmap_single(&priv->dev->dev, desc->data_mapping,
 390                                  CPMAC_SKB_SIZE, DMA_FROM_DEVICE);
 391                 desc->skb = skb;
 392                 desc->data_mapping = dma_map_single(&priv->dev->dev, skb->data,
 393                                                     CPMAC_SKB_SIZE,
 394                                                     DMA_FROM_DEVICE);
 395                 desc->hw_data = (u32)desc->data_mapping;
 396                 if (unlikely(netif_msg_pktdata(priv))) {
 397                         printk(KERN_DEBUG "%s: received packet:\n",
 398                                priv->dev->name);
 399                         cpmac_dump_skb(priv->dev, result);
 400                 }
 401         } else {
 402                 if (netif_msg_rx_err(priv) && net_ratelimit())
 403                         printk(KERN_WARNING
 404                                "%s: low on skbs, dropping packet\n",
 405                                priv->dev->name);
 406                 priv->dev->stats.rx_dropped++;
 407         }
 408
 409         desc->buflen = CPMAC_SKB_SIZE;
 410         desc->dataflags = CPMAC_OWN;
 411
 412         return result;
 413 }
 414
 415 static int cpmac_poll(struct napi_struct *napi, int budget)
 416 {
 417         struct sk_buff *skb;
 418         struct cpmac_desc *desc, *restart;
 419         struct cpmac_priv *priv = container_of(napi, struct cpmac_priv, napi);
 420         int received = 0, processed = 0;
 421
 422         spin_lock(&priv->rx_lock);
 423         if (unlikely(!priv->rx_head)) {
 424                 if (netif_msg_rx_err(priv) && net_ratelimit())
 425                         printk(KERN_WARNING "%s: rx: polling, but no queue\n",
 426                                priv->dev->name);
 427                 spin_unlock(&priv->rx_lock);
 428                 napi_complete(napi);
 429                 return 0;
 430         }
 431
 432         desc = priv->rx_head;
 433         restart = NULL;
 434         while (((desc->dataflags & CPMAC_OWN) == 0) && (received < budget)) {
 435                 processed++;
 436
 437                 if ((desc->dataflags & CPMAC_EOQ) != 0) {
 438                         /* The last update to eoq->hw_next didn't happen
 439                         * soon enough, and the receiver stopped here.
 440                         *Remember this descriptor so we can restart
 441                         * the receiver after freeing some space.
 442                         */
 443                         if (unlikely(restart)) {
 444                                 if (netif_msg_rx_err(priv))
 445                                         printk(KERN_ERR "%s: poll found a"
 446                                                 " duplicate EOQ: %p and %p\n",
 447                                                 priv->dev->name, restart, desc);
 448                                 goto fatal_error;
 449                         }
 450
 451                         restart = desc->next;
 452                 }
 453
 454                 skb = cpmac_rx_one(priv, desc);
 455                 if (likely(skb)) {
 456                         netif_receive_skb(skb);
 457                         received++;
 458                 }
 459                 desc = desc->next;
 460         }
 461
 462         if (desc != priv->rx_head) {
 463                 /* We freed some buffers, but not the whole ring,
 464                  * add what we did free to the rx list */
 465                 desc->prev->hw_next = (u32)0;
 466                 priv->rx_head->prev->hw_next = priv->rx_head->mapping;
 467         }
 468
 469         /* Optimization: If we did not actually process an EOQ (perhaps because
 470          * of quota limits), check to see if the tail of the queue has EOQ set.
 471         * We should immediately restart in that case so that the receiver can
 472         * restart and run in parallel with more packet processing.
 473         * This lets us handle slightly larger bursts before running
 474         * out of ring space (assuming dev->weight < ring_size) */
 475
 476         if (!restart &&
 477              (priv->rx_head->prev->dataflags & (CPMAC_OWN|CPMAC_EOQ))
 478                     == CPMAC_EOQ &&
 479              (priv->rx_head->dataflags & CPMAC_OWN) != 0) {
 480                 /* reset EOQ so the poll loop (above) doesn't try to
 481                 * restart this when it eventually gets to this descriptor.
 482                 */
 483                 priv->rx_head->prev->dataflags &= ~CPMAC_EOQ;
 484                 restart = priv->rx_head;
 485         }
 486
 487         if (restart) {
 488                 priv->dev->stats.rx_errors++;
 489                 priv->dev->stats.rx_fifo_errors++;
 490                 if (netif_msg_rx_err(priv) && net_ratelimit())
 491                         printk(KERN_WARNING "%s: rx dma ring overrun\n",
 492                                priv->dev->name);
 493
 494                 if (unlikely((restart->dataflags & CPMAC_OWN) == 0)) {
 495                         if (netif_msg_drv(priv))
 496                                 printk(KERN_ERR "%s: cpmac_poll is trying to "
 497                                         "restart rx from a descriptor that's "
 498                                         "not free: %p\n",
 499                                         priv->dev->name, restart);
 500                                 goto fatal_error;
 501                 }
 502
 503                 cpmac_write(priv->regs, CPMAC_RX_PTR(0), restart->mapping);
 504         }
 505
 506         priv->rx_head = desc;
 507         spin_unlock(&priv->rx_lock);
 508         if (unlikely(netif_msg_rx_status(priv)))
 509                 printk(KERN_DEBUG "%s: poll processed %d packets\n",
 510                        priv->dev->name, received);
 511         if (processed == 0) {
 512                 /* we ran out of packets to read,
 513                  * revert to interrupt-driven mode */
 514                 napi_complete(napi);
 515                 cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
 516                 return 0;
 517         }
 518
 519         return 1;
 520
 521 fatal_error:
 522         /* Something went horribly wrong.
 523          * Reset hardware to try to recover rather than wedging. */
 524
 525         if (netif_msg_drv(priv)) {
 526                 printk(KERN_ERR "%s: cpmac_poll is confused. "
 527                                 "Resetting hardware\n", priv->dev->name);
 528                 cpmac_dump_all_desc(priv->dev);
 529                 printk(KERN_DEBUG "%s: RX_PTR(0)=0x%08x RX_ACK(0)=0x%08x\n",
 530                         priv->dev->name,
 531                         cpmac_read(priv->regs, CPMAC_RX_PTR(0)),
 532                         cpmac_read(priv->regs, CPMAC_RX_ACK(0)));
 533         }
 534
 535         spin_unlock(&priv->rx_lock);
 536         napi_complete(napi);
 537         netif_tx_stop_all_queues(priv->dev);
 538         napi_disable(&priv->napi);
 539
 540         atomic_inc(&priv->reset_pending);
 541         cpmac_hw_stop(priv->dev);
 542         if (!schedule_work(&priv->reset_work))
 543                 atomic_dec(&priv->reset_pending);
 544         return 0;
 545
 546 }
 547
 548 static int cpmac_start_xmit(struct sk_buff *skb, struct net_device *dev)
 549 {
 550         int queue, len;
 551         struct cpmac_desc *desc;
 552         struct cpmac_priv *priv = netdev_priv(dev);
 553
 554         if (unlikely(atomic_read(&priv->reset_pending)))
 555                 return NETDEV_TX_BUSY;
 556
 557         if (unlikely(skb_padto(skb, ETH_ZLEN)))
 558                 return NETDEV_TX_OK;
 559
 560         len = max(skb->len, ETH_ZLEN);
 561         queue = skb_get_queue_mapping(skb);
 562         netif_stop_subqueue(dev, queue);
 563
 564         desc = &priv->desc_ring[queue];
 565         if (unlikely(desc->dataflags & CPMAC_OWN)) {
 566                 if (netif_msg_tx_err(priv) && net_ratelimit())
 567                         printk(KERN_WARNING "%s: tx dma ring full\n",
 568                                dev->name);
 569                 return NETDEV_TX_BUSY;
 570         }
 571
 572         spin_lock(&priv->lock);
 573         dev->trans_start = jiffies;
 574         spin_unlock(&priv->lock);
 575         desc->dataflags = CPMAC_SOP | CPMAC_EOP | CPMAC_OWN;
 576         desc->skb = skb;
 577         desc->data_mapping = dma_map_single(&dev->dev, skb->data, len,
 578                                             DMA_TO_DEVICE);
 579         desc->hw_data = (u32)desc->data_mapping;
 580         desc->datalen = len;
 581         desc->buflen = len;
 582         if (unlikely(netif_msg_tx_queued(priv)))
 583                 printk(KERN_DEBUG "%s: sending 0x%p, len=%d\n", dev->name, skb,
 584                        skb->len);
 585         if (unlikely(netif_msg_hw(priv)))
 586                 cpmac_dump_desc(dev, desc);
 587         if (unlikely(netif_msg_pktdata(priv)))
 588                 cpmac_dump_skb(dev, skb);
 589         cpmac_write(priv->regs, CPMAC_TX_PTR(queue), (u32)desc->mapping);
 590
 591         return NETDEV_TX_OK;
 592 }
 593
 594 static void cpmac_end_xmit(struct net_device *dev, int queue)
 595 {
 596         struct cpmac_desc *desc;
 597         struct cpmac_priv *priv = netdev_priv(dev);
 598
 599         desc = &priv->desc_ring[queue];
 600         cpmac_write(priv->regs, CPMAC_TX_ACK(queue), (u32)desc->mapping);
 601         if (likely(desc->skb)) {
 602                 spin_lock(&priv->lock);
 603                 dev->stats.tx_packets++;
 604                 dev->stats.tx_bytes += desc->skb->len;
 605                 spin_unlock(&priv->lock);
 606                 dma_unmap_single(&dev->dev, desc->data_mapping, desc->skb->len,
 607                                  DMA_TO_DEVICE);
 608
 609                 if (unlikely(netif_msg_tx_done(priv)))
 610                         printk(KERN_DEBUG "%s: sent 0x%p, len=%d\n", dev->name,
 611                                desc->skb, desc->skb->len);
 612
 613                 dev_kfree_skb_irq(desc->skb);
 614                 desc->skb = NULL;
 615                 if (__netif_subqueue_stopped(dev, queue))
 616                         netif_wake_subqueue(dev, queue);
 617         } else {
 618                 if (netif_msg_tx_err(priv) && net_ratelimit())
 619                         printk(KERN_WARNING
 620                                "%s: end_xmit: spurious interrupt\n", dev->name);
 621                 if (__netif_subqueue_stopped(dev, queue))
 622                         netif_wake_subqueue(dev, queue);
 623         }
 624 }
 625
 626 static void cpmac_hw_stop(struct net_device *dev)
 627 {
 628         int i;
 629         struct cpmac_priv *priv = netdev_priv(dev);
 630         struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
 631
 632         ar7_device_reset(pdata->reset_bit);
 633         cpmac_write(priv->regs, CPMAC_RX_CONTROL,
 634                     cpmac_read(priv->regs, CPMAC_RX_CONTROL) & ~1);
 635         cpmac_write(priv->regs, CPMAC_TX_CONTROL,
 636                     cpmac_read(priv->regs, CPMAC_TX_CONTROL) & ~1);
 637         for (i = 0; i < 8; i++) {
 638                 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
 639                 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
 640         }
 641         cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
 642         cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
 643         cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
 644         cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
 645         cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
 646                     cpmac_read(priv->regs, CPMAC_MAC_CONTROL) & ~MAC_MII);
 647 }
 648
 649 static void cpmac_hw_start(struct net_device *dev)
 650 {
 651         int i;
 652         struct cpmac_priv *priv = netdev_priv(dev);
 653         struct plat_cpmac_data *pdata = priv->pdev->dev.platform_data;
 654
 655         ar7_device_reset(pdata->reset_bit);
 656         for (i = 0; i < 8; i++) {
 657                 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
 658                 cpmac_write(priv->regs, CPMAC_RX_PTR(i), 0);
 659         }
 660         cpmac_write(priv->regs, CPMAC_RX_PTR(0), priv->rx_head->mapping);
 661
 662         cpmac_write(priv->regs, CPMAC_MBP, MBP_RXSHORT | MBP_RXBCAST |
 663                     MBP_RXMCAST);
 664         cpmac_write(priv->regs, CPMAC_BUFFER_OFFSET, 0);
 665         for (i = 0; i < 8; i++)
 666                 cpmac_write(priv->regs, CPMAC_MAC_ADDR_LO(i), dev->dev_addr[5]);
 667         cpmac_write(priv->regs, CPMAC_MAC_ADDR_MID, dev->dev_addr[4]);
 668         cpmac_write(priv->regs, CPMAC_MAC_ADDR_HI, dev->dev_addr[0] |
 669                     (dev->dev_addr[1] << 8) | (dev->dev_addr[2] << 16) |
 670                     (dev->dev_addr[3] << 24));
 671         cpmac_write(priv->regs, CPMAC_MAX_LENGTH, CPMAC_SKB_SIZE);
 672         cpmac_write(priv->regs, CPMAC_UNICAST_CLEAR, 0xff);
 673         cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 0xff);
 674         cpmac_write(priv->regs, CPMAC_TX_INT_CLEAR, 0xff);
 675         cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
 676         cpmac_write(priv->regs, CPMAC_UNICAST_ENABLE, 1);
 677         cpmac_write(priv->regs, CPMAC_RX_INT_ENABLE, 1);
 678         cpmac_write(priv->regs, CPMAC_TX_INT_ENABLE, 0xff);
 679         cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
 680
 681         cpmac_write(priv->regs, CPMAC_RX_CONTROL,
 682                     cpmac_read(priv->regs, CPMAC_RX_CONTROL) | 1);
 683         cpmac_write(priv->regs, CPMAC_TX_CONTROL,
 684                     cpmac_read(priv->regs, CPMAC_TX_CONTROL) | 1);
 685         cpmac_write(priv->regs, CPMAC_MAC_CONTROL,
 686                     cpmac_read(priv->regs, CPMAC_MAC_CONTROL) | MAC_MII |
 687                     MAC_FDX);
 688 }
 689
 690 static void cpmac_clear_rx(struct net_device *dev)
 691 {
 692         struct cpmac_priv *priv = netdev_priv(dev);
 693         struct cpmac_desc *desc;
 694         int i;
 695         if (unlikely(!priv->rx_head))
 696                 return;
 697         desc = priv->rx_head;
 698         for (i = 0; i < priv->ring_size; i++) {
 699                 if ((desc->dataflags & CPMAC_OWN) == 0) {
 700                         if (netif_msg_rx_err(priv) && net_ratelimit())
 701                                 printk(KERN_WARNING "%s: packet dropped\n",
 702                                        dev->name);
 703                         if (unlikely(netif_msg_hw(priv)))
 704                                 cpmac_dump_desc(dev, desc);
 705                         desc->dataflags = CPMAC_OWN;
 706                         dev->stats.rx_dropped++;
 707                 }
 708                 desc->hw_next = desc->next->mapping;
 709                 desc = desc->next;
 710         }
 711         priv->rx_head->prev->hw_next = 0;
 712 }
 713
 714 static void cpmac_clear_tx(struct net_device *dev)
 715 {
 716         struct cpmac_priv *priv = netdev_priv(dev);
 717         int i;
 718         if (unlikely(!priv->desc_ring))
 719                 return;
 720         for (i = 0; i < CPMAC_QUEUES; i++) {
 721                 priv->desc_ring[i].dataflags = 0;
 722                 if (priv->desc_ring[i].skb) {
 723                         dev_kfree_skb_any(priv->desc_ring[i].skb);
 724                         priv->desc_ring[i].skb = NULL;
 725                 }
 726         }
 727 }
 728
 729 static void cpmac_hw_error(struct work_struct *work)
 730 {
 731         struct cpmac_priv *priv =
 732                 container_of(work, struct cpmac_priv, reset_work);
 733
 734         spin_lock(&priv->rx_lock);
 735         cpmac_clear_rx(priv->dev);
 736         spin_unlock(&priv->rx_lock);
 737         cpmac_clear_tx(priv->dev);
 738         cpmac_hw_start(priv->dev);
 739         barrier();
 740         atomic_dec(&priv->reset_pending);
 741
 742         netif_tx_wake_all_queues(priv->dev);
 743         cpmac_write(priv->regs, CPMAC_MAC_INT_ENABLE, 3);
 744 }
 745
 746 static void cpmac_check_status(struct net_device *dev)
 747 {
 748         struct cpmac_priv *priv = netdev_priv(dev);
 749
 750         u32 macstatus = cpmac_read(priv->regs, CPMAC_MAC_STATUS);
 751         int rx_channel = (macstatus >> 8) & 7;
 752         int rx_code = (macstatus >> 12) & 15;
 753         int tx_channel = (macstatus >> 16) & 7;
 754         int tx_code = (macstatus >> 20) & 15;
 755
 756         if (rx_code || tx_code) {
 757                 if (netif_msg_drv(priv) && net_ratelimit()) {
 758                         /* Can't find any documentation on what these
 759                          *error codes actually are. So just log them and hope..
 760                          */
 761                         if (rx_code)
 762                                 printk(KERN_WARNING "%s: host error %d on rx "
 763                                      "channel %d (macstatus %08x), resetting\n",
 764                                      dev->name, rx_code, rx_channel, macstatus);
 765                         if (tx_code)
 766                                 printk(KERN_WARNING "%s: host error %d on tx "
 767                                      "channel %d (macstatus %08x), resetting\n",
 768                                      dev->name, tx_code, tx_channel, macstatus);
 769                 }
 770
 771                 netif_tx_stop_all_queues(dev);
 772                 cpmac_hw_stop(dev);
 773                 if (schedule_work(&priv->reset_work))
 774                         atomic_inc(&priv->reset_pending);
 775                 if (unlikely(netif_msg_hw(priv)))
 776                         cpmac_dump_regs(dev);
 777         }
 778         cpmac_write(priv->regs, CPMAC_MAC_INT_CLEAR, 0xff);
 779 }
 780
 781 static irqreturn_t cpmac_irq(int irq, void *dev_id)
 782 {
 783         struct net_device *dev = dev_id;
 784         struct cpmac_priv *priv;
 785         int queue;
 786         u32 status;
 787
 788         priv = netdev_priv(dev);
 789
 790         status = cpmac_read(priv->regs, CPMAC_MAC_INT_VECTOR);
 791
 792         if (unlikely(netif_msg_intr(priv)))
 793                 printk(KERN_DEBUG "%s: interrupt status: 0x%08x\n", dev->name,
 794                        status);
 795
 796         if (status & MAC_INT_TX)
 797                 cpmac_end_xmit(dev, (status & 7));
 798
 799         if (status & MAC_INT_RX) {
 800                 queue = (status >> 8) & 7;
 801                 if (napi_schedule_prep(&priv->napi)) {
 802                         cpmac_write(priv->regs, CPMAC_RX_INT_CLEAR, 1 << queue);
 803                         __napi_schedule(&priv->napi);
 804                 }
 805         }
 806
 807         cpmac_write(priv->regs, CPMAC_MAC_EOI_VECTOR, 0);
 808
 809         if (unlikely(status & (MAC_INT_HOST | MAC_INT_STATUS)))
 810                 cpmac_check_status(dev);
 811
 812         return IRQ_HANDLED;
 813 }
 814
 815 static void cpmac_tx_timeout(struct net_device *dev)
 816 {
 817         struct cpmac_priv *priv = netdev_priv(dev);
 818
 819         spin_lock(&priv->lock);
 820         dev->stats.tx_errors++;
 821         spin_unlock(&priv->lock);
 822         if (netif_msg_tx_err(priv) && net_ratelimit())
 823                 printk(KERN_WARNING "%s: transmit timeout\n", dev->name);
 824
 825         atomic_inc(&priv->reset_pending);
 826         barrier();
 827         cpmac_clear_tx(dev);
 828         barrier();
 829         atomic_dec(&priv->reset_pending);
 830
 831         netif_tx_wake_all_queues(priv->dev);
 832 }
 833
 834 static int cpmac_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 835 {
 836         struct cpmac_priv *priv = netdev_priv(dev);
 837         if (!(netif_running(dev)))
 838                 return -EINVAL;
 839         if (!priv->phy)
 840                 return -EINVAL;
 841         if ((cmd == SIOCGMIIPHY) || (cmd == SIOCGMIIREG) ||
 842             (cmd == SIOCSMIIREG))
 843                 return phy_mii_ioctl(priv->phy, if_mii(ifr), cmd);
 844
 845         return -EOPNOTSUPP;
 846 }
 847
 848 static int cpmac_get_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 849 {
 850         struct cpmac_priv *priv = netdev_priv(dev);
 851
 852         if (priv->phy)
 853                 return phy_ethtool_gset(priv->phy, cmd);
 854
 855         return -EINVAL;
 856 }
 857
 858 static int cpmac_set_settings(struct net_device *dev, struct ethtool_cmd *cmd)
 859 {
 860         struct cpmac_priv *priv = netdev_priv(dev);
 861
 862         if (!capable(CAP_NET_ADMIN))
 863                 return -EPERM;
 864
 865         if (priv->phy)
 866                 return phy_ethtool_sset(priv->phy, cmd);
 867
 868         return -EINVAL;
 869 }
 870
 871 static void cpmac_get_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
 872 {
 873         struct cpmac_priv *priv = netdev_priv(dev);
 874
 875         ring->rx_max_pending = 1024;
 876         ring->rx_mini_max_pending = 1;
 877         ring->rx_jumbo_max_pending = 1;
 878         ring->tx_max_pending = 1;
 879
 880         ring->rx_pending = priv->ring_size;
 881         ring->rx_mini_pending = 1;
 882         ring->rx_jumbo_pending = 1;
 883         ring->tx_pending = 1;
 884 }
 885
 886 static int cpmac_set_ringparam(struct net_device *dev, struct ethtool_ringparam* ring)
 887 {
 888         struct cpmac_priv *priv = netdev_priv(dev);
 889
 890         if (netif_running(dev))
 891                 return -EBUSY;
 892         priv->ring_size = ring->rx_pending;
 893         return 0;
 894 }
 895
 896 static void cpmac_get_drvinfo(struct net_device *dev,
 897                               struct ethtool_drvinfo *info)
 898 {
 899         strcpy(info->driver, "cpmac");
 900         strcpy(info->version, CPMAC_VERSION);
 901         info->fw_version[0] = '\0';
 902         sprintf(info->bus_info, "%s", "cpmac");
 903         info->regdump_len = 0;
 904 }
 905
 906 static const struct ethtool_ops cpmac_ethtool_ops = {
 907         .get_settings = cpmac_get_settings,
 908         .set_settings = cpmac_set_settings,
 909         .get_drvinfo = cpmac_get_drvinfo,
 910         .get_link = ethtool_op_get_link,
 911         .get_ringparam = cpmac_get_ringparam,
 912         .set_ringparam = cpmac_set_ringparam,
 913 };
 914
 915 static void cpmac_adjust_link(struct net_device *dev)
 916 {
 917         struct cpmac_priv *priv = netdev_priv(dev);
 918         int new_state = 0;
 919
 920         spin_lock(&priv->lock);
 921         if (priv->phy->link) {
 922                 netif_tx_start_all_queues(dev);
 923                 if (priv->phy->duplex != priv->oldduplex) {
 924                         new_state = 1;
 925                         priv->oldduplex = priv->phy->duplex;
 926                 }
 927
 928                 if (priv->phy->speed != priv->oldspeed) {
 929                         new_state = 1;
 930                         priv->oldspeed = priv->phy->speed;
 931                 }
 932
 933                 if (!priv->oldlink) {
 934                         new_state = 1;
 935                         priv->oldlink = 1;
 936                 }
 937         } else if (priv->oldlink) {
 938                 new_state = 1;
 939                 priv->oldlink = 0;
 940                 priv->oldspeed = 0;
 941                 priv->oldduplex = -1;
 942         }
 943
 944         if (new_state && netif_msg_link(priv) && net_ratelimit())
 945                 phy_print_status(priv->phy);
 946
 947         spin_unlock(&priv->lock);
 948 }
 949
 950 static int cpmac_open(struct net_device *dev)
 951 {
 952         int i, size, res;
 953         struct cpmac_priv *priv = netdev_priv(dev);
 954         struct resource *mem;
 955         struct cpmac_desc *desc;
 956         struct sk_buff *skb;
 957
 958         mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
 959         if (!request_mem_region(mem->start, mem->end - mem->start, dev->name)) {
 960                 if (netif_msg_drv(priv))
 961                         printk(KERN_ERR "%s: failed to request registers\n",
 962                                dev->name);
 963                 res = -ENXIO;
 964                 goto fail_reserve;
 965         }
 966
 967         priv->regs = ioremap(mem->start, mem->end - mem->start);
 968         if (!priv->regs) {
 969                 if (netif_msg_drv(priv))
 970                         printk(KERN_ERR "%s: failed to remap registers\n",
 971                                dev->name);
 972                 res = -ENXIO;
 973                 goto fail_remap;
 974         }
 975
 976         size = priv->ring_size + CPMAC_QUEUES;
 977         priv->desc_ring = dma_alloc_coherent(&dev->dev,
 978                                              sizeof(struct cpmac_desc) * size,
 979                                              &priv->dma_ring,
 980                                              GFP_KERNEL);
 981         if (!priv->desc_ring) {
 982                 res = -ENOMEM;
 983                 goto fail_alloc;
 984         }
 985
 986         for (i = 0; i < size; i++)
 987                 priv->desc_ring[i].mapping = priv->dma_ring + sizeof(*desc) * i;
 988
 989         priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
 990         for (i = 0, desc = priv->rx_head; i < priv->ring_size; i++, desc++) {
 991                 skb = netdev_alloc_skb_ip_align(dev, CPMAC_SKB_SIZE);
 992                 if (unlikely(!skb)) {
 993                         res = -ENOMEM;
 994                         goto fail_desc;
 995                 }
 996                 desc->skb = skb;
 997                 desc->data_mapping = dma_map_single(&dev->dev, skb->data,
 998                                                     CPMAC_SKB_SIZE,
 999                                                     DMA_FROM_DEVICE);
1000                 desc->hw_data = (u32)desc->data_mapping;
1001                 desc->buflen = CPMAC_SKB_SIZE;
1002                 desc->dataflags = CPMAC_OWN;
1003                 desc->next = &priv->rx_head[(i + 1) % priv->ring_size];
1004                 desc->next->prev = desc;
1005                 desc->hw_next = (u32)desc->next->mapping;
1006         }
1007
1008         priv->rx_head->prev->hw_next = (u32)0;
1009
1010         if ((res = request_irq(dev->irq, cpmac_irq, IRQF_SHARED,
1011                                dev->name, dev))) {
1012                 if (netif_msg_drv(priv))
1013                         printk(KERN_ERR "%s: failed to obtain irq\n",
1014                                dev->name);
1015                 goto fail_irq;
1016         }
1017
1018         atomic_set(&priv->reset_pending, 0);
1019         INIT_WORK(&priv->reset_work, cpmac_hw_error);
1020         cpmac_hw_start(dev);
1021
1022         napi_enable(&priv->napi);
1023         priv->phy->state = PHY_CHANGELINK;
1024         phy_start(priv->phy);
1025
1026         return 0;
1027
1028 fail_irq:
1029 fail_desc:
1030         for (i = 0; i < priv->ring_size; i++) {
1031                 if (priv->rx_head[i].skb) {
1032                         dma_unmap_single(&dev->dev,
1033                                          priv->rx_head[i].data_mapping,
1034                                          CPMAC_SKB_SIZE,
1035                                          DMA_FROM_DEVICE);
1036                         kfree_skb(priv->rx_head[i].skb);
1037                 }
1038         }
1039 fail_alloc:
1040         kfree(priv->desc_ring);
1041         iounmap(priv->regs);
1042
1043 fail_remap:
1044         release_mem_region(mem->start, mem->end - mem->start);
1045
1046 fail_reserve:
1047         return res;
1048 }
1049
1050 static int cpmac_stop(struct net_device *dev)
1051 {
1052         int i;
1053         struct cpmac_priv *priv = netdev_priv(dev);
1054         struct resource *mem;
1055
1056         netif_tx_stop_all_queues(dev);
1057
1058         cancel_work_sync(&priv->reset_work);
1059         napi_disable(&priv->napi);
1060         phy_stop(priv->phy);
1061
1062         cpmac_hw_stop(dev);
1063
1064         for (i = 0; i < 8; i++)
1065                 cpmac_write(priv->regs, CPMAC_TX_PTR(i), 0);
1066         cpmac_write(priv->regs, CPMAC_RX_PTR(0), 0);
1067         cpmac_write(priv->regs, CPMAC_MBP, 0);
1068
1069         free_irq(dev->irq, dev);
1070         iounmap(priv->regs);
1071         mem = platform_get_resource_byname(priv->pdev, IORESOURCE_MEM, "regs");
1072         release_mem_region(mem->start, mem->end - mem->start);
1073         priv->rx_head = &priv->desc_ring[CPMAC_QUEUES];
1074         for (i = 0; i < priv->ring_size; i++) {
1075                 if (priv->rx_head[i].skb) {
1076                         dma_unmap_single(&dev->dev,
1077                                          priv->rx_head[i].data_mapping,
1078                                          CPMAC_SKB_SIZE,
1079                                          DMA_FROM_DEVICE);
1080                         kfree_skb(priv->rx_head[i].skb);
1081                 }
1082         }
1083
1084         dma_free_coherent(&dev->dev, sizeof(struct cpmac_desc) *
1085                           (CPMAC_QUEUES + priv->ring_size),
1086                           priv->desc_ring, priv->dma_ring);
1087         return 0;
1088 }
1089
1090 static const struct net_device_ops cpmac_netdev_ops = {
1091         .ndo_open               = cpmac_open,
1092         .ndo_stop               = cpmac_stop,
1093         .ndo_start_xmit         = cpmac_start_xmit,
1094         .ndo_tx_timeout         = cpmac_tx_timeout,
1095         .ndo_set_multicast_list = cpmac_set_multicast_list,
1096         .ndo_do_ioctl           = cpmac_ioctl,
1097         .ndo_set_config         = cpmac_config,
1098         .ndo_change_mtu         = eth_change_mtu,
1099         .ndo_validate_addr      = eth_validate_addr,
1100         .ndo_set_mac_address    = eth_mac_addr,
1101 };
1102
1103 static int external_switch;
1104
1105 static int __devinit cpmac_probe(struct platform_device *pdev)
1106 {
1107         int rc, phy_id;
1108         char mdio_bus_id[MII_BUS_ID_SIZE];
1109         struct resource *mem;
1110         struct cpmac_priv *priv;
1111         struct net_device *dev;
1112         struct plat_cpmac_data *pdata;
1113
1114         pdata = pdev->dev.platform_data;
1115
1116         if (external_switch || dumb_switch) {
1117                 strncpy(mdio_bus_id, "0", MII_BUS_ID_SIZE); /* fixed phys bus */
1118                 phy_id = pdev->id;
1119         } else {
1120                 for (phy_id = 0; phy_id < PHY_MAX_ADDR; phy_id++) {
1121                         if (!(pdata->phy_mask & (1 << phy_id)))
1122                                 continue;
1123                         if (!cpmac_mii->phy_map[phy_id])
1124                                 continue;
1125                         strncpy(mdio_bus_id, cpmac_mii->id, MII_BUS_ID_SIZE);
1126                         break;
1127                 }
1128         }
1129
1130         if (phy_id == PHY_MAX_ADDR) {
1131                 dev_err(&pdev->dev, "no PHY present\n");
1132                 return -ENODEV;
1133         }
1134
1135         dev = alloc_etherdev_mq(sizeof(*priv), CPMAC_QUEUES);
1136
1137         if (!dev) {
1138                 printk(KERN_ERR "cpmac: Unable to allocate net_device\n");
1139                 return -ENOMEM;
1140         }
1141
1142         platform_set_drvdata(pdev, dev);
1143         priv = netdev_priv(dev);
1144
1145         priv->pdev = pdev;
1146         mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "regs");
1147         if (!mem) {
1148                 rc = -ENODEV;
1149                 goto fail;
1150         }
1151
1152         dev->irq = platform_get_irq_byname(pdev, "irq");
1153
1154         dev->netdev_ops = &cpmac_netdev_ops;
1155         dev->ethtool_ops = &cpmac_ethtool_ops;
1156
1157         netif_napi_add(dev, &priv->napi, cpmac_poll, 64);
1158
1159         spin_lock_init(&priv->lock);
1160         spin_lock_init(&priv->rx_lock);
1161         priv->dev = dev;
1162         priv->ring_size = 64;
1163         priv->msg_enable = netif_msg_init(debug_level, 0xff);
1164         memcpy(dev->dev_addr, pdata->dev_addr, sizeof(pdata->dev_addr));
1165
1166         snprintf(priv->phy_name, MII_BUS_ID_SIZE, PHY_ID_FMT, mdio_bus_id, phy_id);
1167
1168         priv->phy = phy_connect(dev, priv->phy_name, &cpmac_adjust_link, 0,
1169                                                 PHY_INTERFACE_MODE_MII);
1170
1171         if (IS_ERR(priv->phy)) {
1172                 if (netif_msg_drv(priv))
1173                         printk(KERN_ERR "%s: Could not attach to PHY\n",
1174                                dev->name);
1175                 return PTR_ERR(priv->phy);
1176         }
1177
1178         if ((rc = register_netdev(dev))) {
1179                 printk(KERN_ERR "cpmac: error %i registering device %s\n", rc,
1180                        dev->name);
1181                 goto fail;
1182         }
1183
1184         if (netif_msg_probe(priv)) {
1185                 printk(KERN_INFO
1186                        "cpmac: device %s (regs: %p, irq: %d, phy: %s, "
1187                        "mac: %pM)\n", dev->name, (void *)mem->start, dev->irq,
1188                        priv->phy_name, dev->dev_addr);
1189         }
1190         return 0;
1191
1192 fail:
1193         free_netdev(dev);
1194         return rc;
1195 }
1196
1197 static int __devexit cpmac_remove(struct platform_device *pdev)
1198 {
1199         struct net_device *dev = platform_get_drvdata(pdev);
1200         unregister_netdev(dev);
1201         free_netdev(dev);
1202         return 0;
1203 }
1204
1205 static struct platform_driver cpmac_driver = {
1206         .driver.name = "cpmac",
1207         .driver.owner = THIS_MODULE,
1208         .probe = cpmac_probe,
1209         .remove = __devexit_p(cpmac_remove),
1210 };
1211
1212 int __devinit cpmac_init(void)
1213 {
1214         u32 mask;
1215         int i, res;
1216
1217         cpmac_mii = mdiobus_alloc();
1218         if (cpmac_mii == NULL)
1219                 return -ENOMEM;
1220
1221         cpmac_mii->name = "cpmac-mii";
1222         cpmac_mii->read = cpmac_mdio_read;
1223         cpmac_mii->write = cpmac_mdio_write;
1224         cpmac_mii->reset = cpmac_mdio_reset;
1225         cpmac_mii->irq = mii_irqs;
1226
1227         cpmac_mii->priv = ioremap(AR7_REGS_MDIO, 256);
1228
1229         if (!cpmac_mii->priv) {
1230                 printk(KERN_ERR "Can't ioremap mdio registers\n");
1231                 res = -ENXIO;
1232                 goto fail_alloc;
1233         }
1234
1235 #warning FIXME: unhardcode gpio&reset bits
1236         ar7_gpio_disable(26);
1237         ar7_gpio_disable(27);
1238         ar7_device_reset(AR7_RESET_BIT_CPMAC_LO);
1239         ar7_device_reset(AR7_RESET_BIT_CPMAC_HI);
1240         ar7_device_reset(AR7_RESET_BIT_EPHY);
1241
1242         cpmac_mii->reset(cpmac_mii);
1243
1244         for (i = 0; i < 300; i++)
1245                 if ((mask = cpmac_read(cpmac_mii->priv, CPMAC_MDIO_ALIVE)))
1246                         break;
1247                 else
1248                         msleep(10);
1249
1250         mask &= 0x7fffffff;
1251         if (mask & (mask - 1)) {
1252                 external_switch = 1;
1253                 mask = 0;
1254         }
1255
1256         cpmac_mii->phy_mask = ~(mask | 0x80000000);
1257         snprintf(cpmac_mii->id, MII_BUS_ID_SIZE, "1");
1258
1259         res = mdiobus_register(cpmac_mii);
1260         if (res)
1261                 goto fail_mii;
1262
1263         res = platform_driver_register(&cpmac_driver);
1264         if (res)
1265                 goto fail_cpmac;
1266
1267         return 0;
1268
1269 fail_cpmac:
1270         mdiobus_unregister(cpmac_mii);
1271
1272 fail_mii:
1273         iounmap(cpmac_mii->priv);
1274
1275 fail_alloc:
1276         mdiobus_free(cpmac_mii);
1277
1278         return res;
1279 }
1280
1281 void __devexit cpmac_exit(void)
1282 {
1283         platform_driver_unregister(&cpmac_driver);
1284         mdiobus_unregister(cpmac_mii);
1285         mdiobus_free(cpmac_mii);
1286         iounmap(cpmac_mii->priv);
1287 }
1288
1289 module_init(cpmac_init);
1290 module_exit(cpmac_exit);